2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
26 #include "ecore_sriov.h"
27 #include "ecore_mcp.h"
29 #define ECORE_MAX_SGES_NUM 16
30 #define CRC32_POLY 0x1edc6f41
32 struct ecore_l2_info {
34 unsigned long **pp_qid_usage;
36 /* The lock is meant to synchronize access to the qid usage */
40 enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn)
42 struct ecore_l2_info *p_l2_info;
43 unsigned long **pp_qids;
46 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
49 p_l2_info = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_l2_info));
52 p_hwfn->p_l2_info = p_l2_info;
54 if (IS_PF(p_hwfn->p_dev)) {
55 p_l2_info->queues = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
59 ecore_vf_get_num_rxqs(p_hwfn, &rx);
60 ecore_vf_get_num_txqs(p_hwfn, &tx);
62 p_l2_info->queues = (u32)OSAL_MAX_T(u8, rx, tx);
65 pp_qids = OSAL_VZALLOC(p_hwfn->p_dev,
66 sizeof(unsigned long *) *
68 if (pp_qids == OSAL_NULL)
70 p_l2_info->pp_qid_usage = pp_qids;
72 for (i = 0; i < p_l2_info->queues; i++) {
73 pp_qids[i] = OSAL_VZALLOC(p_hwfn->p_dev,
74 MAX_QUEUES_PER_QZONE / 8);
75 if (pp_qids[i] == OSAL_NULL)
79 #ifdef CONFIG_ECORE_LOCK_ALLOC
80 OSAL_MUTEX_ALLOC(p_hwfn, &p_l2_info->lock);
86 void ecore_l2_setup(struct ecore_hwfn *p_hwfn)
88 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
91 OSAL_MUTEX_INIT(&p_hwfn->p_l2_info->lock);
94 void ecore_l2_free(struct ecore_hwfn *p_hwfn)
98 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
101 if (p_hwfn->p_l2_info == OSAL_NULL)
104 if (p_hwfn->p_l2_info->pp_qid_usage == OSAL_NULL)
107 /* Free until hit first uninitialized entry */
108 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
109 if (p_hwfn->p_l2_info->pp_qid_usage[i] == OSAL_NULL)
111 OSAL_VFREE(p_hwfn->p_dev,
112 p_hwfn->p_l2_info->pp_qid_usage[i]);
115 #ifdef CONFIG_ECORE_LOCK_ALLOC
116 /* Lock is last to initialize, if everything else was */
117 if (i == p_hwfn->p_l2_info->queues)
118 OSAL_MUTEX_DEALLOC(&p_hwfn->p_l2_info->lock);
121 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info->pp_qid_usage);
124 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info);
125 p_hwfn->p_l2_info = OSAL_NULL;
128 /* TODO - we'll need locking around these... */
129 static bool ecore_eth_queue_qid_usage_add(struct ecore_hwfn *p_hwfn,
130 struct ecore_queue_cid *p_cid)
132 struct ecore_l2_info *p_l2_info = p_hwfn->p_l2_info;
133 u16 queue_id = p_cid->rel.queue_id;
137 OSAL_MUTEX_ACQUIRE(&p_l2_info->lock);
139 if (queue_id > p_l2_info->queues) {
140 DP_NOTICE(p_hwfn, true,
141 "Requested to increase usage for qzone %04x out of %08x\n",
142 queue_id, p_l2_info->queues);
147 first = (u8)OSAL_FIND_FIRST_ZERO_BIT(p_l2_info->pp_qid_usage[queue_id],
148 MAX_QUEUES_PER_QZONE);
149 if (first >= MAX_QUEUES_PER_QZONE) {
154 OSAL_SET_BIT(first, p_l2_info->pp_qid_usage[queue_id]);
155 p_cid->qid_usage_idx = first;
158 OSAL_MUTEX_RELEASE(&p_l2_info->lock);
162 static void ecore_eth_queue_qid_usage_del(struct ecore_hwfn *p_hwfn,
163 struct ecore_queue_cid *p_cid)
165 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_l2_info->lock);
167 OSAL_CLEAR_BIT(p_cid->qid_usage_idx,
168 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
170 OSAL_MUTEX_RELEASE(&p_hwfn->p_l2_info->lock);
173 void ecore_eth_queue_cid_release(struct ecore_hwfn *p_hwfn,
174 struct ecore_queue_cid *p_cid)
176 bool b_legacy_vf = !!(p_cid->vf_legacy &
177 ECORE_QCID_LEGACY_VF_CID);
179 /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF.
180 * For legacy vf-queues, the CID doesn't go through here.
182 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
183 _ecore_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
185 /* VFs maintain the index inside queue-zone on their own */
186 if (p_cid->vfid == ECORE_QUEUE_CID_PF)
187 ecore_eth_queue_qid_usage_del(p_hwfn, p_cid);
189 OSAL_VFREE(p_hwfn->p_dev, p_cid);
192 /* The internal is only meant to be directly called by PFs initializeing CIDs
195 static struct ecore_queue_cid *
196 _ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn,
197 u16 opaque_fid, u32 cid,
198 struct ecore_queue_start_common_params *p_params,
200 struct ecore_queue_cid_vf_params *p_vf_params)
202 struct ecore_queue_cid *p_cid;
203 enum _ecore_status_t rc;
205 p_cid = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_cid));
206 if (p_cid == OSAL_NULL)
209 p_cid->opaque_fid = opaque_fid;
211 p_cid->p_owner = p_hwfn;
213 /* Fill in parameters */
214 p_cid->rel.vport_id = p_params->vport_id;
215 p_cid->rel.queue_id = p_params->queue_id;
216 p_cid->rel.stats_id = p_params->stats_id;
217 p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
218 p_cid->b_is_rx = b_is_rx;
219 p_cid->sb_idx = p_params->sb_idx;
221 /* Fill-in bits related to VFs' queues if information was provided */
222 if (p_vf_params != OSAL_NULL) {
223 p_cid->vfid = p_vf_params->vfid;
224 p_cid->vf_qid = p_vf_params->vf_qid;
225 p_cid->vf_legacy = p_vf_params->vf_legacy;
227 p_cid->vfid = ECORE_QUEUE_CID_PF;
230 /* Don't try calculating the absolute indices for VFs */
231 if (IS_VF(p_hwfn->p_dev)) {
232 p_cid->abs = p_cid->rel;
237 /* Calculate the engine-absolute indices of the resources.
238 * This would guarantee they're valid later on.
239 * In some cases [SBs] we already have the right values.
241 rc = ecore_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
242 if (rc != ECORE_SUCCESS)
245 rc = ecore_fw_l2_queue(p_hwfn, p_cid->rel.queue_id,
246 &p_cid->abs.queue_id);
247 if (rc != ECORE_SUCCESS)
250 /* In case of a PF configuring its VF's queues, the stats-id is already
251 * absolute [since there's a single index that's suitable per-VF].
253 if (p_cid->vfid == ECORE_QUEUE_CID_PF) {
254 rc = ecore_fw_vport(p_hwfn, p_cid->rel.stats_id,
255 &p_cid->abs.stats_id);
256 if (rc != ECORE_SUCCESS)
259 p_cid->abs.stats_id = p_cid->rel.stats_id;
263 /* VF-images have provided the qid_usage_idx on their own.
264 * Otherwise, we need to allocate a unique one.
267 if (!ecore_eth_queue_qid_usage_add(p_hwfn, p_cid))
270 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
273 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
274 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
275 p_cid->opaque_fid, p_cid->cid,
276 p_cid->rel.vport_id, p_cid->abs.vport_id,
277 p_cid->rel.queue_id, p_cid->qid_usage_idx,
279 p_cid->rel.stats_id, p_cid->abs.stats_id,
280 p_cid->sb_igu_id, p_cid->sb_idx);
285 OSAL_VFREE(p_hwfn->p_dev, p_cid);
289 struct ecore_queue_cid *
290 ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
291 struct ecore_queue_start_common_params *p_params,
293 struct ecore_queue_cid_vf_params *p_vf_params)
295 struct ecore_queue_cid *p_cid;
296 u8 vfid = ECORE_CXT_PF_CID;
297 bool b_legacy_vf = false;
300 /* In case of legacy VFs, The CID can be derived from the additional
301 * VF parameters - the VF assumes queue X uses CID X, so we can simply
302 * use the vf_qid for this purpose as well.
305 vfid = p_vf_params->vfid;
307 if (p_vf_params->vf_legacy &
308 ECORE_QCID_LEGACY_VF_CID) {
310 cid = p_vf_params->vf_qid;
314 /* Get a unique firmware CID for this queue, in case it's a PF.
315 * VF's don't need a CID as the queue configuration will be done
318 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf) {
319 if (_ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
320 &cid, vfid) != ECORE_SUCCESS) {
321 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
326 p_cid = _ecore_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
327 p_params, b_is_rx, p_vf_params);
328 if ((p_cid == OSAL_NULL) && IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
329 _ecore_cxt_release_cid(p_hwfn, cid, vfid);
334 static struct ecore_queue_cid *
335 ecore_eth_queue_to_cid_pf(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
337 struct ecore_queue_start_common_params *p_params)
339 return ecore_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
344 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
345 struct ecore_sp_vport_start_params *p_params)
347 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
348 struct ecore_spq_entry *p_ent = OSAL_NULL;
349 struct ecore_sp_init_data init_data;
350 struct eth_vport_tpa_param *p_tpa;
351 u16 rx_mode = 0, tx_err = 0;
353 enum _ecore_status_t rc = ECORE_NOTIMPL;
355 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
356 if (rc != ECORE_SUCCESS)
360 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
361 init_data.cid = ecore_spq_get_cid(p_hwfn);
362 init_data.opaque_fid = p_params->opaque_fid;
363 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
365 rc = ecore_sp_init_request(p_hwfn, &p_ent,
366 ETH_RAMROD_VPORT_START,
367 PROTOCOLID_ETH, &init_data);
368 if (rc != ECORE_SUCCESS)
371 p_ramrod = &p_ent->ramrod.vport_start;
372 p_ramrod->vport_id = abs_vport_id;
374 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
375 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
376 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
377 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
378 p_ramrod->untagged = p_params->only_untagged;
379 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
381 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
382 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
384 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
386 /* Handle requests for strict behavior on transmission errors */
387 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE,
388 p_params->b_err_illegal_vlan_mode ?
389 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
390 SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL,
391 p_params->b_err_small_pkt ?
392 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
393 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR,
394 p_params->b_err_anti_spoof ?
395 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
396 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS,
397 p_params->b_err_illegal_inband_mode ?
398 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
399 SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG,
400 p_params->b_err_vlan_insert_with_inband ?
401 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
402 SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION,
403 p_params->b_err_big_pkt ?
404 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
405 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME,
406 p_params->b_err_ctrl_frame ?
407 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
408 p_ramrod->tx_err_behav.values = OSAL_CPU_TO_LE16(tx_err);
410 /* TPA related fields */
411 p_tpa = &p_ramrod->tpa_param;
412 OSAL_MEMSET(p_tpa, 0, sizeof(struct eth_vport_tpa_param));
413 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
415 switch (p_params->tpa_mode) {
416 case ECORE_TPA_MODE_GRO:
417 p_tpa->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
418 p_tpa->tpa_max_size = (u16)-1;
419 p_tpa->tpa_min_size_to_cont = p_params->mtu / 2;
420 p_tpa->tpa_min_size_to_start = p_params->mtu / 2;
421 p_tpa->tpa_ipv4_en_flg = 1;
422 p_tpa->tpa_ipv6_en_flg = 1;
423 p_tpa->tpa_ipv4_tunn_en_flg = 1;
424 p_tpa->tpa_ipv6_tunn_en_flg = 1;
425 p_tpa->tpa_pkt_split_flg = 1;
426 p_tpa->tpa_gro_consistent_flg = 1;
432 p_ramrod->tx_switching_en = p_params->tx_switching;
434 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
435 p_ramrod->tx_switching_en = 0;
438 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
439 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
441 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
442 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_params->concrete_fid);
444 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
448 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
449 struct ecore_sp_vport_start_params *p_params)
451 if (IS_VF(p_hwfn->p_dev))
452 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
454 p_params->remove_inner_vlan,
456 p_params->max_buffers_per_cqe,
457 p_params->only_untagged);
459 return ecore_sp_eth_vport_start(p_hwfn, p_params);
462 static enum _ecore_status_t
463 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
464 struct vport_update_ramrod_data *p_ramrod,
465 struct ecore_rss_params *p_rss)
467 struct eth_vport_rss_config *p_config;
468 u16 capabilities = 0;
470 enum _ecore_status_t rc = ECORE_SUCCESS;
473 p_ramrod->common.update_rss_flg = 0;
476 p_config = &p_ramrod->rss_config;
478 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
479 ETH_RSS_IND_TABLE_ENTRIES_NUM);
481 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
482 if (rc != ECORE_SUCCESS)
485 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
486 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
487 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
488 p_config->update_rss_key = p_rss->update_rss_key;
490 p_config->rss_mode = p_rss->rss_enable ?
491 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
493 p_config->capabilities = 0;
495 SET_FIELD(capabilities,
496 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
497 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
498 SET_FIELD(capabilities,
499 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
500 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
501 SET_FIELD(capabilities,
502 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
503 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
504 SET_FIELD(capabilities,
505 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
506 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
507 SET_FIELD(capabilities,
508 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
509 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
510 SET_FIELD(capabilities,
511 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
512 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
513 p_config->tbl_size = p_rss->rss_table_size_log;
514 p_config->capabilities = OSAL_CPU_TO_LE16(capabilities);
516 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
517 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
518 p_ramrod->common.update_rss_flg,
520 p_config->update_rss_capabilities,
521 p_config->capabilities,
522 p_config->update_rss_ind_table, p_config->update_rss_key);
524 table_size = OSAL_MIN_T(int, ECORE_RSS_IND_TABLE_SIZE,
525 1 << p_config->tbl_size);
526 for (i = 0; i < table_size; i++) {
527 struct ecore_queue_cid *p_queue = p_rss->rss_ind_table[i];
532 p_config->indirection_table[i] =
533 OSAL_CPU_TO_LE16(p_queue->abs.queue_id);
536 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
537 "Configured RSS indirection table [%d entries]:\n",
539 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i += 0x10) {
540 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
541 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
542 OSAL_LE16_TO_CPU(p_config->indirection_table[i]),
543 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 1]),
544 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 2]),
545 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 3]),
546 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 4]),
547 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 5]),
548 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 6]),
549 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 7]),
550 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 8]),
551 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 9]),
552 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 10]),
553 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 11]),
554 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 12]),
555 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 13]),
556 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 14]),
557 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 15]));
560 for (i = 0; i < 10; i++)
561 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
567 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
568 struct vport_update_ramrod_data *p_ramrod,
569 struct ecore_filter_accept_flags accept_flags)
571 p_ramrod->common.update_rx_mode_flg =
572 accept_flags.update_rx_mode_config;
573 p_ramrod->common.update_tx_mode_flg =
574 accept_flags.update_tx_mode_config;
577 /* On B0 emulation we cannot enable Tx, since this would cause writes
578 * to PVFC HW block which isn't implemented in emulation.
580 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
581 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
582 "Non-Asic - prevent Tx mode in vport update\n");
583 p_ramrod->common.update_tx_mode_flg = 0;
587 /* Set Rx mode accept flags */
588 if (p_ramrod->common.update_rx_mode_flg) {
589 u8 accept_filter = accept_flags.rx_accept_filter;
592 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
593 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
594 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
596 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
597 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
599 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
600 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
601 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
603 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
604 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
605 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
607 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
608 !!(accept_filter & ECORE_ACCEPT_BCAST));
610 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
611 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
612 "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n",
613 p_ramrod->common.vport_id, state);
616 /* Set Tx mode accept flags */
617 if (p_ramrod->common.update_tx_mode_flg) {
618 u8 accept_filter = accept_flags.tx_accept_filter;
621 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
622 !!(accept_filter & ECORE_ACCEPT_NONE));
624 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
625 !!(accept_filter & ECORE_ACCEPT_NONE));
627 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
628 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
629 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
631 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
632 !!(accept_filter & ECORE_ACCEPT_BCAST));
634 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
635 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
636 "vport[%02x] p_ramrod->tx_mode.state = 0x%x\n",
637 p_ramrod->common.vport_id, state);
642 ecore_sp_vport_update_sge_tpa(struct vport_update_ramrod_data *p_ramrod,
643 struct ecore_sge_tpa_params *p_params)
645 struct eth_vport_tpa_param *p_tpa;
649 p_ramrod->common.update_tpa_param_flg = 0;
650 p_ramrod->common.update_tpa_en_flg = 0;
651 p_ramrod->common.update_tpa_param_flg = 0;
655 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
656 p_tpa = &p_ramrod->tpa_param;
657 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
658 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
659 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
660 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
662 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
663 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
664 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
665 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
666 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
667 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
668 val = p_params->tpa_max_size;
669 p_tpa->tpa_max_size = OSAL_CPU_TO_LE16(val);
670 val = p_params->tpa_min_size_to_start;
671 p_tpa->tpa_min_size_to_start = OSAL_CPU_TO_LE16(val);
672 val = p_params->tpa_min_size_to_cont;
673 p_tpa->tpa_min_size_to_cont = OSAL_CPU_TO_LE16(val);
677 ecore_sp_update_mcast_bin(struct vport_update_ramrod_data *p_ramrod,
678 struct ecore_sp_vport_update_params *p_params)
682 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
683 sizeof(p_ramrod->approx_mcast.bins));
685 if (!p_params->update_approx_mcast_flg)
688 p_ramrod->common.update_approx_mcast_flg = 1;
689 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
690 u32 *p_bins = (u32 *)p_params->bins;
692 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
697 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
698 struct ecore_sp_vport_update_params *p_params,
699 enum spq_mode comp_mode,
700 struct ecore_spq_comp_cb *p_comp_data)
702 struct ecore_rss_params *p_rss_params = p_params->rss_params;
703 struct vport_update_ramrod_data_cmn *p_cmn;
704 struct ecore_sp_init_data init_data;
705 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
706 struct ecore_spq_entry *p_ent = OSAL_NULL;
707 u8 abs_vport_id = 0, val;
708 enum _ecore_status_t rc = ECORE_NOTIMPL;
710 if (IS_VF(p_hwfn->p_dev)) {
711 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
715 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
716 if (rc != ECORE_SUCCESS)
720 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
721 init_data.cid = ecore_spq_get_cid(p_hwfn);
722 init_data.opaque_fid = p_params->opaque_fid;
723 init_data.comp_mode = comp_mode;
724 init_data.p_comp_data = p_comp_data;
726 rc = ecore_sp_init_request(p_hwfn, &p_ent,
727 ETH_RAMROD_VPORT_UPDATE,
728 PROTOCOLID_ETH, &init_data);
729 if (rc != ECORE_SUCCESS)
732 /* Copy input params to ramrod according to FW struct */
733 p_ramrod = &p_ent->ramrod.vport_update;
734 p_cmn = &p_ramrod->common;
736 p_cmn->vport_id = abs_vport_id;
738 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
739 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
740 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
741 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
743 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
744 val = p_params->update_accept_any_vlan_flg;
745 p_cmn->update_accept_any_vlan_flg = val;
747 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
748 val = p_params->update_inner_vlan_removal_flg;
749 p_cmn->update_inner_vlan_removal_en_flg = val;
751 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
752 val = p_params->update_default_vlan_enable_flg;
753 p_cmn->update_default_vlan_en_flg = val;
755 p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
756 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
758 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
760 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
763 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
764 if (p_ramrod->common.tx_switching_en ||
765 p_ramrod->common.update_tx_switching_en_flg) {
766 DP_NOTICE(p_hwfn, false,
767 "FPGA - why are we seeing tx-switching? Overriding it\n");
768 p_ramrod->common.tx_switching_en = 0;
769 p_ramrod->common.update_tx_switching_en_flg = 1;
772 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
774 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
775 val = p_params->update_anti_spoofing_en_flg;
776 p_ramrod->common.update_anti_spoofing_en_flg = val;
778 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
779 if (rc != ECORE_SUCCESS) {
780 /* Return spq entry which is taken in ecore_sp_init_request()*/
781 ecore_spq_return_entry(p_hwfn, p_ent);
785 /* Update mcast bins for VFs, PF doesn't use this functionality */
786 ecore_sp_update_mcast_bin(p_ramrod, p_params);
788 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
789 ecore_sp_vport_update_sge_tpa(p_ramrod, p_params->sge_tpa_params);
791 p_ramrod->common.update_mtu_flg = 1;
792 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
795 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
798 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
799 u16 opaque_fid, u8 vport_id)
801 struct vport_stop_ramrod_data *p_ramrod;
802 struct ecore_sp_init_data init_data;
803 struct ecore_spq_entry *p_ent;
805 enum _ecore_status_t rc;
807 if (IS_VF(p_hwfn->p_dev))
808 return ecore_vf_pf_vport_stop(p_hwfn);
810 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
811 if (rc != ECORE_SUCCESS)
815 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
816 init_data.cid = ecore_spq_get_cid(p_hwfn);
817 init_data.opaque_fid = opaque_fid;
818 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
820 rc = ecore_sp_init_request(p_hwfn, &p_ent,
821 ETH_RAMROD_VPORT_STOP,
822 PROTOCOLID_ETH, &init_data);
823 if (rc != ECORE_SUCCESS)
826 p_ramrod = &p_ent->ramrod.vport_stop;
827 p_ramrod->vport_id = abs_vport_id;
829 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
832 static enum _ecore_status_t
833 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
834 struct ecore_filter_accept_flags *p_accept_flags)
836 struct ecore_sp_vport_update_params s_params;
838 OSAL_MEMSET(&s_params, 0, sizeof(s_params));
839 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
840 sizeof(struct ecore_filter_accept_flags));
842 return ecore_vf_pf_vport_update(p_hwfn, &s_params);
846 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
848 struct ecore_filter_accept_flags accept_flags,
849 u8 update_accept_any_vlan,
851 enum spq_mode comp_mode,
852 struct ecore_spq_comp_cb *p_comp_data)
854 struct ecore_sp_vport_update_params vport_update_params;
857 /* Prepare and send the vport rx_mode change */
858 OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
859 vport_update_params.vport_id = vport;
860 vport_update_params.accept_flags = accept_flags;
861 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
862 vport_update_params.accept_any_vlan = accept_any_vlan;
864 for_each_hwfn(p_dev, i) {
865 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
867 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
870 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
871 if (rc != ECORE_SUCCESS)
876 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
877 comp_mode, p_comp_data);
878 if (rc != ECORE_SUCCESS) {
879 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
883 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
884 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
885 accept_flags.rx_accept_filter,
886 accept_flags.tx_accept_filter);
888 if (update_accept_any_vlan)
889 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
890 "accept_any_vlan=%d configured\n",
898 ecore_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
899 struct ecore_queue_cid *p_cid,
901 dma_addr_t bd_chain_phys_addr,
902 dma_addr_t cqe_pbl_addr,
905 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
906 struct ecore_spq_entry *p_ent = OSAL_NULL;
907 struct ecore_sp_init_data init_data;
908 enum _ecore_status_t rc = ECORE_NOTIMPL;
910 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
911 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
912 p_cid->opaque_fid, p_cid->cid, p_cid->abs.queue_id,
913 p_cid->abs.vport_id, p_cid->sb_igu_id);
916 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
917 init_data.cid = p_cid->cid;
918 init_data.opaque_fid = p_cid->opaque_fid;
919 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
921 rc = ecore_sp_init_request(p_hwfn, &p_ent,
922 ETH_RAMROD_RX_QUEUE_START,
923 PROTOCOLID_ETH, &init_data);
924 if (rc != ECORE_SUCCESS)
927 p_ramrod = &p_ent->ramrod.rx_queue_start;
929 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id);
930 p_ramrod->sb_index = p_cid->sb_idx;
931 p_ramrod->vport_id = p_cid->abs.vport_id;
932 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
933 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
934 p_ramrod->complete_cqe_flg = 0;
935 p_ramrod->complete_event_flg = 1;
937 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
938 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
940 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
941 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
943 if (p_cid->vfid != ECORE_QUEUE_CID_PF) {
944 bool b_legacy_vf = !!(p_cid->vf_legacy &
945 ECORE_QCID_LEGACY_VF_RX_PROD);
947 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
948 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
949 "Queue%s is meant for VF rxq[%02x]\n",
950 b_legacy_vf ? " [legacy]" : "",
952 p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
955 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
958 static enum _ecore_status_t
959 ecore_eth_pf_rx_queue_start(struct ecore_hwfn *p_hwfn,
960 struct ecore_queue_cid *p_cid,
962 dma_addr_t bd_chain_phys_addr,
963 dma_addr_t cqe_pbl_addr,
965 void OSAL_IOMEM * *pp_prod)
967 u32 init_prod_val = 0;
969 *pp_prod = (u8 OSAL_IOMEM *)
971 GTT_BAR0_MAP_REG_MSDM_RAM +
972 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
974 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
975 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
976 (u32 *)(&init_prod_val));
978 return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid,
981 cqe_pbl_addr, cqe_pbl_size);
985 ecore_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
987 struct ecore_queue_start_common_params *p_params,
989 dma_addr_t bd_chain_phys_addr,
990 dma_addr_t cqe_pbl_addr,
992 struct ecore_rxq_start_ret_params *p_ret_params)
994 struct ecore_queue_cid *p_cid;
995 enum _ecore_status_t rc;
997 /* Allocate a CID for the queue */
998 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
999 if (p_cid == OSAL_NULL)
1002 if (IS_PF(p_hwfn->p_dev))
1003 rc = ecore_eth_pf_rx_queue_start(p_hwfn, p_cid,
1006 cqe_pbl_addr, cqe_pbl_size,
1007 &p_ret_params->p_prod);
1009 rc = ecore_vf_pf_rxq_start(p_hwfn, p_cid,
1014 &p_ret_params->p_prod);
1016 /* Provide the caller with a reference to as handler */
1017 if (rc != ECORE_SUCCESS)
1018 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1020 p_ret_params->p_handle = (void *)p_cid;
1025 enum _ecore_status_t
1026 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
1027 void **pp_rxq_handles,
1029 u8 complete_cqe_flg,
1030 u8 complete_event_flg,
1031 enum spq_mode comp_mode,
1032 struct ecore_spq_comp_cb *p_comp_data)
1034 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
1035 struct ecore_spq_entry *p_ent = OSAL_NULL;
1036 struct ecore_sp_init_data init_data;
1037 struct ecore_queue_cid *p_cid;
1038 enum _ecore_status_t rc = ECORE_NOTIMPL;
1041 if (IS_VF(p_hwfn->p_dev))
1042 return ecore_vf_pf_rxqs_update(p_hwfn,
1043 (struct ecore_queue_cid **)
1047 complete_event_flg);
1049 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1050 init_data.comp_mode = comp_mode;
1051 init_data.p_comp_data = p_comp_data;
1053 for (i = 0; i < num_rxqs; i++) {
1054 p_cid = ((struct ecore_queue_cid **)pp_rxq_handles)[i];
1057 init_data.cid = p_cid->cid;
1058 init_data.opaque_fid = p_cid->opaque_fid;
1060 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1061 ETH_RAMROD_RX_QUEUE_UPDATE,
1062 PROTOCOLID_ETH, &init_data);
1063 if (rc != ECORE_SUCCESS)
1066 p_ramrod = &p_ent->ramrod.rx_queue_update;
1067 p_ramrod->vport_id = p_cid->abs.vport_id;
1069 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1070 p_ramrod->complete_cqe_flg = complete_cqe_flg;
1071 p_ramrod->complete_event_flg = complete_event_flg;
1073 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1074 if (rc != ECORE_SUCCESS)
1081 static enum _ecore_status_t
1082 ecore_eth_pf_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1083 struct ecore_queue_cid *p_cid,
1084 bool b_eq_completion_only,
1085 bool b_cqe_completion)
1087 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
1088 struct ecore_spq_entry *p_ent = OSAL_NULL;
1089 struct ecore_sp_init_data init_data;
1090 enum _ecore_status_t rc;
1092 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1093 init_data.cid = p_cid->cid;
1094 init_data.opaque_fid = p_cid->opaque_fid;
1095 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1097 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1098 ETH_RAMROD_RX_QUEUE_STOP,
1099 PROTOCOLID_ETH, &init_data);
1100 if (rc != ECORE_SUCCESS)
1103 p_ramrod = &p_ent->ramrod.rx_queue_stop;
1104 p_ramrod->vport_id = p_cid->abs.vport_id;
1105 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1107 /* Cleaning the queue requires the completion to arrive there.
1108 * In addition, VFs require the answer to come as eqe to PF.
1110 p_ramrod->complete_cqe_flg = ((p_cid->vfid == ECORE_QUEUE_CID_PF) &&
1111 !b_eq_completion_only) ||
1113 p_ramrod->complete_event_flg = (p_cid->vfid != ECORE_QUEUE_CID_PF) ||
1114 b_eq_completion_only;
1116 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1119 enum _ecore_status_t ecore_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1121 bool eq_completion_only,
1122 bool cqe_completion)
1124 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_rxq;
1125 enum _ecore_status_t rc = ECORE_NOTIMPL;
1127 if (IS_PF(p_hwfn->p_dev))
1128 rc = ecore_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1132 rc = ecore_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1134 if (rc == ECORE_SUCCESS)
1135 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1139 enum _ecore_status_t
1140 ecore_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
1141 struct ecore_queue_cid *p_cid,
1142 dma_addr_t pbl_addr, u16 pbl_size,
1145 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
1146 struct ecore_spq_entry *p_ent = OSAL_NULL;
1147 struct ecore_sp_init_data init_data;
1148 enum _ecore_status_t rc = ECORE_NOTIMPL;
1151 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1152 init_data.cid = p_cid->cid;
1153 init_data.opaque_fid = p_cid->opaque_fid;
1154 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1156 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1157 ETH_RAMROD_TX_QUEUE_START,
1158 PROTOCOLID_ETH, &init_data);
1159 if (rc != ECORE_SUCCESS)
1162 p_ramrod = &p_ent->ramrod.tx_queue_start;
1163 p_ramrod->vport_id = p_cid->abs.vport_id;
1165 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id);
1166 p_ramrod->sb_index = p_cid->sb_idx;
1167 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
1169 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1170 p_ramrod->same_as_last_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1172 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
1173 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
1175 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
1177 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1180 static enum _ecore_status_t
1181 ecore_eth_pf_tx_queue_start(struct ecore_hwfn *p_hwfn,
1182 struct ecore_queue_cid *p_cid,
1184 dma_addr_t pbl_addr, u16 pbl_size,
1185 void OSAL_IOMEM * *pp_doorbell)
1187 enum _ecore_status_t rc;
1189 /* TODO - set tc in the pq_params for multi-cos */
1190 rc = ecore_eth_txq_start_ramrod(p_hwfn, p_cid,
1192 ecore_get_cm_pq_idx_mcos(p_hwfn, tc));
1193 if (rc != ECORE_SUCCESS)
1196 /* Provide the caller with the necessary return values */
1197 *pp_doorbell = (u8 OSAL_IOMEM *)
1199 DB_ADDR(p_cid->cid, DQ_DEMS_LEGACY);
1201 return ECORE_SUCCESS;
1204 enum _ecore_status_t
1205 ecore_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
1206 struct ecore_queue_start_common_params *p_params,
1208 dma_addr_t pbl_addr, u16 pbl_size,
1209 struct ecore_txq_start_ret_params *p_ret_params)
1211 struct ecore_queue_cid *p_cid;
1212 enum _ecore_status_t rc;
1214 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
1215 if (p_cid == OSAL_NULL)
1218 if (IS_PF(p_hwfn->p_dev))
1219 rc = ecore_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1221 &p_ret_params->p_doorbell);
1223 rc = ecore_vf_pf_txq_start(p_hwfn, p_cid,
1225 &p_ret_params->p_doorbell);
1227 if (rc != ECORE_SUCCESS)
1228 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1230 p_ret_params->p_handle = (void *)p_cid;
1235 static enum _ecore_status_t
1236 ecore_eth_pf_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1237 struct ecore_queue_cid *p_cid)
1239 struct ecore_spq_entry *p_ent = OSAL_NULL;
1240 struct ecore_sp_init_data init_data;
1241 enum _ecore_status_t rc;
1243 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1244 init_data.cid = p_cid->cid;
1245 init_data.opaque_fid = p_cid->opaque_fid;
1246 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1248 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1249 ETH_RAMROD_TX_QUEUE_STOP,
1250 PROTOCOLID_ETH, &init_data);
1251 if (rc != ECORE_SUCCESS)
1254 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1257 enum _ecore_status_t ecore_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1260 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
1261 enum _ecore_status_t rc;
1263 if (IS_PF(p_hwfn->p_dev))
1264 rc = ecore_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1266 rc = ecore_vf_pf_txq_stop(p_hwfn, p_cid);
1268 if (rc == ECORE_SUCCESS)
1269 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1273 static enum eth_filter_action
1274 ecore_filter_action(enum ecore_filter_opcode opcode)
1276 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1279 case ECORE_FILTER_ADD:
1280 action = ETH_FILTER_ACTION_ADD;
1282 case ECORE_FILTER_REMOVE:
1283 action = ETH_FILTER_ACTION_REMOVE;
1285 case ECORE_FILTER_FLUSH:
1286 action = ETH_FILTER_ACTION_REMOVE_ALL;
1289 action = MAX_ETH_FILTER_ACTION;
1295 static enum _ecore_status_t
1296 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1298 struct ecore_filter_ucast *p_filter_cmd,
1299 struct vport_filter_update_ramrod_data **pp_ramrod,
1300 struct ecore_spq_entry **pp_ent,
1301 enum spq_mode comp_mode,
1302 struct ecore_spq_comp_cb *p_comp_data)
1304 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1305 struct vport_filter_update_ramrod_data *p_ramrod;
1306 struct eth_filter_cmd *p_first_filter;
1307 struct eth_filter_cmd *p_second_filter;
1308 struct ecore_sp_init_data init_data;
1309 enum eth_filter_action action;
1310 enum _ecore_status_t rc;
1312 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1313 &vport_to_remove_from);
1314 if (rc != ECORE_SUCCESS)
1317 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1319 if (rc != ECORE_SUCCESS)
1323 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1324 init_data.cid = ecore_spq_get_cid(p_hwfn);
1325 init_data.opaque_fid = opaque_fid;
1326 init_data.comp_mode = comp_mode;
1327 init_data.p_comp_data = p_comp_data;
1329 rc = ecore_sp_init_request(p_hwfn, pp_ent,
1330 ETH_RAMROD_FILTERS_UPDATE,
1331 PROTOCOLID_ETH, &init_data);
1332 if (rc != ECORE_SUCCESS)
1335 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1336 p_ramrod = *pp_ramrod;
1337 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1338 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1341 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1342 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1343 "Non-Asic - prevent Tx filters\n");
1344 p_ramrod->filter_cmd_hdr.tx = 0;
1348 switch (p_filter_cmd->opcode) {
1349 case ECORE_FILTER_REPLACE:
1350 case ECORE_FILTER_MOVE:
1351 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1354 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1358 p_first_filter = &p_ramrod->filter_cmds[0];
1359 p_second_filter = &p_ramrod->filter_cmds[1];
1361 switch (p_filter_cmd->type) {
1362 case ECORE_FILTER_MAC:
1363 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1365 case ECORE_FILTER_VLAN:
1366 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1368 case ECORE_FILTER_MAC_VLAN:
1369 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1371 case ECORE_FILTER_INNER_MAC:
1372 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1374 case ECORE_FILTER_INNER_VLAN:
1375 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1377 case ECORE_FILTER_INNER_PAIR:
1378 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1380 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1381 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1383 case ECORE_FILTER_MAC_VNI_PAIR:
1384 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1386 case ECORE_FILTER_VNI:
1387 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1389 case ECORE_FILTER_UNUSED: /* @DPDK */
1390 p_first_filter->type = MAX_ETH_FILTER_TYPE;
1394 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1395 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1396 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1397 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1398 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1399 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1400 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1401 &p_first_filter->mac_mid,
1402 &p_first_filter->mac_lsb,
1403 (u8 *)p_filter_cmd->mac);
1405 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1406 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1407 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1408 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1409 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1411 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1412 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1413 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1414 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1416 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1417 p_second_filter->type = p_first_filter->type;
1418 p_second_filter->mac_msb = p_first_filter->mac_msb;
1419 p_second_filter->mac_mid = p_first_filter->mac_mid;
1420 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1421 p_second_filter->vlan_id = p_first_filter->vlan_id;
1422 p_second_filter->vni = p_first_filter->vni;
1424 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1426 p_first_filter->vport_id = vport_to_remove_from;
1428 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1429 p_second_filter->vport_id = vport_to_add_to;
1430 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1431 p_first_filter->vport_id = vport_to_add_to;
1432 OSAL_MEMCPY(p_second_filter, p_first_filter,
1433 sizeof(*p_second_filter));
1434 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1435 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1437 action = ecore_filter_action(p_filter_cmd->opcode);
1439 if (action == MAX_ETH_FILTER_ACTION) {
1440 DP_NOTICE(p_hwfn, true,
1441 "%d is not supported yet\n",
1442 p_filter_cmd->opcode);
1443 return ECORE_NOTIMPL;
1446 p_first_filter->action = action;
1447 p_first_filter->vport_id =
1448 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1449 vport_to_remove_from : vport_to_add_to;
1452 return ECORE_SUCCESS;
1455 enum _ecore_status_t
1456 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1458 struct ecore_filter_ucast *p_filter_cmd,
1459 enum spq_mode comp_mode,
1460 struct ecore_spq_comp_cb *p_comp_data)
1462 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1463 struct ecore_spq_entry *p_ent = OSAL_NULL;
1464 struct eth_filter_cmd_header *p_header;
1465 enum _ecore_status_t rc;
1467 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1469 comp_mode, p_comp_data);
1470 if (rc != ECORE_SUCCESS) {
1471 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1474 p_header = &p_ramrod->filter_cmd_hdr;
1475 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1477 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1478 if (rc != ECORE_SUCCESS) {
1479 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1483 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1484 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1485 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1486 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1488 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1489 "MOVE" : "REPLACE")),
1490 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1491 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1492 "VLAN" : "MAC & VLAN"),
1493 p_ramrod->filter_cmd_hdr.cmd_cnt,
1494 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1495 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1496 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1497 p_filter_cmd->vport_to_add_to,
1498 p_filter_cmd->vport_to_remove_from,
1499 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1500 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1501 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1502 p_filter_cmd->vlan);
1504 return ECORE_SUCCESS;
1507 /*******************************************************************************
1509 * Calculates crc 32 on a buffer
1510 * Note: crc32_length MUST be aligned to 8
1512 ******************************************************************************/
1513 static u32 ecore_calc_crc32c(u8 *crc32_packet, u32 crc32_length, u32 crc32_seed)
1515 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1516 u8 msb = 0, current_byte = 0;
1518 if ((crc32_packet == OSAL_NULL) ||
1519 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1520 return crc32_result;
1523 for (byte = 0; byte < crc32_length; byte++) {
1524 current_byte = crc32_packet[byte];
1525 for (bit = 0; bit < 8; bit++) {
1526 msb = (u8)(crc32_result >> 31);
1527 crc32_result = crc32_result << 1;
1528 if (msb != (0x1 & (current_byte >> bit))) {
1529 crc32_result = crc32_result ^ CRC32_POLY;
1535 return crc32_result;
1538 static u32 ecore_crc32c_le(u32 seed, u8 *mac)
1540 u32 packet_buf[2] = { 0 };
1542 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1543 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed);
1546 u8 ecore_mcast_bin_from_mac(u8 *mac)
1548 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, mac);
1553 static enum _ecore_status_t
1554 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1555 struct ecore_filter_mcast *p_filter_cmd,
1556 enum spq_mode comp_mode,
1557 struct ecore_spq_comp_cb *p_comp_data)
1559 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1560 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1561 struct ecore_spq_entry *p_ent = OSAL_NULL;
1562 struct ecore_sp_init_data init_data;
1563 u8 abs_vport_id = 0;
1564 enum _ecore_status_t rc;
1567 if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1568 rc = ecore_fw_vport(p_hwfn,
1569 p_filter_cmd->vport_to_add_to,
1572 rc = ecore_fw_vport(p_hwfn,
1573 p_filter_cmd->vport_to_remove_from,
1575 if (rc != ECORE_SUCCESS)
1579 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1580 init_data.cid = ecore_spq_get_cid(p_hwfn);
1581 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1582 init_data.comp_mode = comp_mode;
1583 init_data.p_comp_data = p_comp_data;
1585 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1586 ETH_RAMROD_VPORT_UPDATE,
1587 PROTOCOLID_ETH, &init_data);
1588 if (rc != ECORE_SUCCESS) {
1589 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1593 p_ramrod = &p_ent->ramrod.vport_update;
1594 p_ramrod->common.update_approx_mcast_flg = 1;
1596 /* explicitly clear out the entire vector */
1597 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1598 0, sizeof(p_ramrod->approx_mcast.bins));
1599 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1600 ETH_MULTICAST_MAC_BINS_IN_REGS);
1601 /* filter ADD op is explicit set op and it removes
1602 * any existing filters for the vport.
1604 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1605 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1608 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1609 OSAL_SET_BIT(bit, bins);
1612 /* Convert to correct endianity */
1613 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1614 struct vport_update_ramrod_mcast *p_ramrod_bins;
1615 u32 *p_bins = (u32 *)bins;
1617 p_ramrod_bins = &p_ramrod->approx_mcast;
1618 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1622 p_ramrod->common.vport_id = abs_vport_id;
1624 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1625 if (rc != ECORE_SUCCESS)
1626 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1631 enum _ecore_status_t
1632 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1633 struct ecore_filter_mcast *p_filter_cmd,
1634 enum spq_mode comp_mode,
1635 struct ecore_spq_comp_cb *p_comp_data)
1637 enum _ecore_status_t rc = ECORE_SUCCESS;
1640 /* only ADD and REMOVE operations are supported for multi-cast */
1641 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1642 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1643 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1647 for_each_hwfn(p_dev, i) {
1648 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1651 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1655 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1657 comp_mode, p_comp_data);
1658 if (rc != ECORE_SUCCESS)
1665 enum _ecore_status_t
1666 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1667 struct ecore_filter_ucast *p_filter_cmd,
1668 enum spq_mode comp_mode,
1669 struct ecore_spq_comp_cb *p_comp_data)
1671 enum _ecore_status_t rc = ECORE_SUCCESS;
1674 for_each_hwfn(p_dev, i) {
1675 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1679 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1683 opaque_fid = p_hwfn->hw_info.opaque_fid;
1684 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1687 comp_mode, p_comp_data);
1688 if (rc != ECORE_SUCCESS)
1695 /* Statistics related code */
1696 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1697 u32 *p_addr, u32 *p_len,
1700 if (IS_PF(p_hwfn->p_dev)) {
1701 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1702 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1703 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1705 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1706 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1708 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1709 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1713 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1714 struct ecore_ptt *p_ptt,
1715 struct ecore_eth_stats *p_stats,
1718 struct eth_pstorm_per_queue_stat pstats;
1719 u32 pstats_addr = 0, pstats_len = 0;
1721 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1724 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1725 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1727 p_stats->common.tx_ucast_bytes +=
1728 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1729 p_stats->common.tx_mcast_bytes +=
1730 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1731 p_stats->common.tx_bcast_bytes +=
1732 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1733 p_stats->common.tx_ucast_pkts +=
1734 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1735 p_stats->common.tx_mcast_pkts +=
1736 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1737 p_stats->common.tx_bcast_pkts +=
1738 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1739 p_stats->common.tx_err_drop_pkts +=
1740 HILO_64_REGPAIR(pstats.error_drop_pkts);
1743 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1744 struct ecore_ptt *p_ptt,
1745 struct ecore_eth_stats *p_stats)
1747 struct tstorm_per_port_stat tstats;
1748 u32 tstats_addr, tstats_len;
1750 if (IS_PF(p_hwfn->p_dev)) {
1751 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1752 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1753 tstats_len = sizeof(struct tstorm_per_port_stat);
1755 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1756 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1758 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1759 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1762 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1763 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1765 p_stats->common.mftag_filter_discards +=
1766 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1767 p_stats->common.mac_filter_discards +=
1768 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1771 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1772 u32 *p_addr, u32 *p_len,
1775 if (IS_PF(p_hwfn->p_dev)) {
1776 *p_addr = BAR0_MAP_REG_USDM_RAM +
1777 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1778 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1780 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1781 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1783 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1784 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1788 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1789 struct ecore_ptt *p_ptt,
1790 struct ecore_eth_stats *p_stats,
1793 struct eth_ustorm_per_queue_stat ustats;
1794 u32 ustats_addr = 0, ustats_len = 0;
1796 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1799 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1800 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1802 p_stats->common.rx_ucast_bytes +=
1803 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1804 p_stats->common.rx_mcast_bytes +=
1805 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1806 p_stats->common.rx_bcast_bytes +=
1807 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1808 p_stats->common.rx_ucast_pkts +=
1809 HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1810 p_stats->common.rx_mcast_pkts +=
1811 HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1812 p_stats->common.rx_bcast_pkts +=
1813 HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1816 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1817 u32 *p_addr, u32 *p_len,
1820 if (IS_PF(p_hwfn->p_dev)) {
1821 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1822 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1823 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1825 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1826 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1828 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1829 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1833 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1834 struct ecore_ptt *p_ptt,
1835 struct ecore_eth_stats *p_stats,
1838 struct eth_mstorm_per_queue_stat mstats;
1839 u32 mstats_addr = 0, mstats_len = 0;
1841 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1844 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1845 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1847 p_stats->common.no_buff_discards +=
1848 HILO_64_REGPAIR(mstats.no_buff_discard);
1849 p_stats->common.packet_too_big_discard +=
1850 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1851 p_stats->common.ttl0_discard +=
1852 HILO_64_REGPAIR(mstats.ttl0_discard);
1853 p_stats->common.tpa_coalesced_pkts +=
1854 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1855 p_stats->common.tpa_coalesced_events +=
1856 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1857 p_stats->common.tpa_aborts_num +=
1858 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1859 p_stats->common.tpa_coalesced_bytes +=
1860 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1863 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1864 struct ecore_ptt *p_ptt,
1865 struct ecore_eth_stats *p_stats)
1867 struct ecore_eth_stats_common *p_common = &p_stats->common;
1868 struct port_stats port_stats;
1871 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1873 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1874 p_hwfn->mcp_info->port_addr +
1875 OFFSETOF(struct public_port, stats),
1876 sizeof(port_stats));
1878 p_common->rx_64_byte_packets += port_stats.eth.r64;
1879 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1880 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1881 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1882 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1883 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1884 p_common->rx_crc_errors += port_stats.eth.rfcs;
1885 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1886 p_common->rx_pause_frames += port_stats.eth.rxpf;
1887 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1888 p_common->rx_align_errors += port_stats.eth.raln;
1889 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1890 p_common->rx_oversize_packets += port_stats.eth.rovr;
1891 p_common->rx_jabbers += port_stats.eth.rjbr;
1892 p_common->rx_undersize_packets += port_stats.eth.rund;
1893 p_common->rx_fragments += port_stats.eth.rfrg;
1894 p_common->tx_64_byte_packets += port_stats.eth.t64;
1895 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1896 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1897 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1898 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1899 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1900 p_common->tx_pause_frames += port_stats.eth.txpf;
1901 p_common->tx_pfc_frames += port_stats.eth.txpp;
1902 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1903 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1904 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1905 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1906 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1907 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1908 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1909 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1910 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1911 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
1912 for (j = 0; j < 8; j++) {
1913 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1914 p_common->brb_discards += port_stats.brb.brb_discard[j];
1917 if (ECORE_IS_BB(p_hwfn->p_dev)) {
1918 struct ecore_eth_stats_bb *p_bb = &p_stats->bb;
1920 p_bb->rx_1519_to_1522_byte_packets +=
1921 port_stats.eth.u0.bb0.r1522;
1922 p_bb->rx_1519_to_2047_byte_packets +=
1923 port_stats.eth.u0.bb0.r2047;
1924 p_bb->rx_2048_to_4095_byte_packets +=
1925 port_stats.eth.u0.bb0.r4095;
1926 p_bb->rx_4096_to_9216_byte_packets +=
1927 port_stats.eth.u0.bb0.r9216;
1928 p_bb->rx_9217_to_16383_byte_packets +=
1929 port_stats.eth.u0.bb0.r16383;
1930 p_bb->tx_1519_to_2047_byte_packets +=
1931 port_stats.eth.u1.bb1.t2047;
1932 p_bb->tx_2048_to_4095_byte_packets +=
1933 port_stats.eth.u1.bb1.t4095;
1934 p_bb->tx_4096_to_9216_byte_packets +=
1935 port_stats.eth.u1.bb1.t9216;
1936 p_bb->tx_9217_to_16383_byte_packets +=
1937 port_stats.eth.u1.bb1.t16383;
1938 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1939 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1941 struct ecore_eth_stats_ah *p_ah = &p_stats->ah;
1943 p_ah->rx_1519_to_max_byte_packets +=
1944 port_stats.eth.u0.ah0.r1519_to_max;
1945 p_ah->tx_1519_to_max_byte_packets =
1946 port_stats.eth.u1.ah1.t1519_to_max;
1950 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1951 struct ecore_ptt *p_ptt,
1952 struct ecore_eth_stats *stats,
1953 u16 statistics_bin, bool b_get_port_stats)
1955 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1956 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1957 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats);
1958 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1961 /* Avoid getting PORT stats for emulation. */
1962 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1966 if (b_get_port_stats && p_hwfn->mcp_info)
1967 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1970 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1971 struct ecore_eth_stats *stats)
1976 OSAL_MEMSET(stats, 0, sizeof(*stats));
1978 for_each_hwfn(p_dev, i) {
1979 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1980 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1981 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1982 bool b_get_port_stats;
1985 /* The main vport index is relative first */
1986 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1987 DP_ERR(p_hwfn, "No vport available!\n");
1992 if (IS_PF(p_dev) && !p_ptt) {
1993 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1997 b_get_port_stats = IS_PF(p_dev) && IS_LEAD_HWFN(p_hwfn);
1998 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
2002 if (IS_PF(p_dev) && p_ptt)
2003 ecore_ptt_release(p_hwfn, p_ptt);
2007 void ecore_get_vport_stats(struct ecore_dev *p_dev,
2008 struct ecore_eth_stats *stats)
2013 OSAL_MEMSET(stats, 0, sizeof(*stats));
2017 _ecore_get_vport_stats(p_dev, stats);
2019 if (!p_dev->reset_stats)
2022 /* Reduce the statistics baseline */
2023 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
2024 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
2027 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
2028 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
2032 for_each_hwfn(p_dev, i) {
2033 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2034 struct eth_mstorm_per_queue_stat mstats;
2035 struct eth_ustorm_per_queue_stat ustats;
2036 struct eth_pstorm_per_queue_stat pstats;
2037 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
2038 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
2039 u32 addr = 0, len = 0;
2041 if (IS_PF(p_dev) && !p_ptt) {
2042 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
2046 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
2047 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
2048 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
2050 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
2051 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
2052 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
2054 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
2055 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
2056 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
2059 ecore_ptt_release(p_hwfn, p_ptt);
2062 /* PORT statistics are not necessarily reset, so we need to
2063 * read and create a baseline for future statistics.
2065 if (!p_dev->reset_stats)
2066 DP_INFO(p_dev, "Reset stats not allocated\n");
2068 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
2071 void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
2072 struct ecore_ptt *p_ptt,
2073 struct ecore_arfs_config_params *p_cfg_params)
2075 if (p_cfg_params->arfs_enable) {
2076 ecore_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2080 p_cfg_params->ipv6);
2081 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2082 "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
2083 p_cfg_params->tcp ? "Enable" : "Disable",
2084 p_cfg_params->udp ? "Enable" : "Disable",
2085 p_cfg_params->ipv4 ? "Enable" : "Disable",
2086 p_cfg_params->ipv6 ? "Enable" : "Disable");
2088 ecore_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2090 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n",
2091 p_cfg_params->arfs_enable ? "Enable" : "Disable");
2094 enum _ecore_status_t
2095 ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn,
2096 struct ecore_spq_comp_cb *p_cb,
2097 dma_addr_t p_addr, u16 length,
2098 u16 qid, u8 vport_id,
2101 struct rx_update_gft_filter_data *p_ramrod = OSAL_NULL;
2102 struct ecore_spq_entry *p_ent = OSAL_NULL;
2103 struct ecore_sp_init_data init_data;
2104 u16 abs_rx_q_id = 0;
2105 u8 abs_vport_id = 0;
2106 enum _ecore_status_t rc = ECORE_NOTIMPL;
2108 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
2109 if (rc != ECORE_SUCCESS)
2112 rc = ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
2113 if (rc != ECORE_SUCCESS)
2117 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
2118 init_data.cid = ecore_spq_get_cid(p_hwfn);
2120 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2123 init_data.comp_mode = ECORE_SPQ_MODE_CB;
2124 init_data.p_comp_data = p_cb;
2126 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
2129 rc = ecore_sp_init_request(p_hwfn, &p_ent,
2130 ETH_RAMROD_GFT_UPDATE_FILTER,
2131 PROTOCOLID_ETH, &init_data);
2132 if (rc != ECORE_SUCCESS)
2135 p_ramrod = &p_ent->ramrod.rx_update_gft;
2137 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
2138 p_ramrod->pkt_hdr_length = OSAL_CPU_TO_LE16(length);
2139 p_ramrod->rx_qid_or_action_icid = OSAL_CPU_TO_LE16(abs_rx_q_id);
2140 p_ramrod->vport_id = abs_vport_id;
2141 p_ramrod->filter_type = RFS_FILTER_TYPE;
2142 p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER
2143 : GFT_DELETE_FILTER;
2145 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2146 "V[%0x], Q[%04x] - %s filter from 0x%lx [length %04xb]\n",
2147 abs_vport_id, abs_rx_q_id,
2148 b_is_add ? "Adding" : "Removing",
2149 (unsigned long)p_addr, length);
2151 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
2154 int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn,
2155 struct ecore_ptt *p_ptt,
2156 struct ecore_queue_cid *p_cid,
2159 u32 coalesce, address, is_valid;
2160 struct cau_sb_entry sb_entry;
2162 enum _ecore_status_t rc;
2164 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2165 p_cid->sb_igu_id * sizeof(u64),
2166 (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2167 if (rc != ECORE_SUCCESS) {
2168 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2172 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
2174 address = BAR0_MAP_REG_USDM_RAM +
2175 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2176 coalesce = ecore_rd(p_hwfn, p_ptt, address);
2178 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2182 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2183 *p_rx_coal = (u16)(coalesce << timer_res);
2185 return ECORE_SUCCESS;
2188 int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn,
2189 struct ecore_ptt *p_ptt,
2190 struct ecore_queue_cid *p_cid,
2193 u32 coalesce, address, is_valid;
2194 struct cau_sb_entry sb_entry;
2196 enum _ecore_status_t rc;
2198 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2199 p_cid->sb_igu_id * sizeof(u64),
2200 (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2201 if (rc != ECORE_SUCCESS) {
2202 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2206 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
2208 address = BAR0_MAP_REG_XSDM_RAM +
2209 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2210 coalesce = ecore_rd(p_hwfn, p_ptt, address);
2212 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2216 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2217 *p_tx_coal = (u16)(coalesce << timer_res);
2219 return ECORE_SUCCESS;
2222 enum _ecore_status_t
2223 ecore_get_queue_coalesce(struct ecore_hwfn *p_hwfn, u16 *p_coal,
2226 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)handle;
2227 enum _ecore_status_t rc = ECORE_SUCCESS;
2228 struct ecore_ptt *p_ptt;
2230 if (IS_VF(p_hwfn->p_dev)) {
2231 rc = ecore_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
2232 if (rc != ECORE_SUCCESS)
2233 DP_NOTICE(p_hwfn, false,
2234 "Unable to read queue calescing\n");
2239 p_ptt = ecore_ptt_acquire(p_hwfn);
2243 if (p_cid->b_is_rx) {
2244 rc = ecore_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2245 if (rc != ECORE_SUCCESS)
2248 rc = ecore_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2249 if (rc != ECORE_SUCCESS)
2254 ecore_ptt_release(p_hwfn, p_ptt);