2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
25 #include "ecore_mcp.h"
27 #define ECORE_MAX_SGES_NUM 16
28 #define CRC32_POLY 0x1edc6f41
31 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
32 struct ecore_sp_vport_start_params *p_params)
34 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
35 struct ecore_spq_entry *p_ent = OSAL_NULL;
36 enum _ecore_status_t rc = ECORE_NOTIMPL;
37 struct ecore_sp_init_data init_data;
41 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
42 if (rc != ECORE_SUCCESS)
46 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
47 init_data.cid = ecore_spq_get_cid(p_hwfn);
48 init_data.opaque_fid = p_params->opaque_fid;
49 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
51 rc = ecore_sp_init_request(p_hwfn, &p_ent,
52 ETH_RAMROD_VPORT_START,
53 PROTOCOLID_ETH, &init_data);
54 if (rc != ECORE_SUCCESS)
57 p_ramrod = &p_ent->ramrod.vport_start;
58 p_ramrod->vport_id = abs_vport_id;
60 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
61 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
62 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
63 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
64 p_ramrod->untagged = p_params->only_untagged;
65 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
67 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
68 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
70 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
72 /* TPA related fields */
73 OSAL_MEMSET(&p_ramrod->tpa_param, 0,
74 sizeof(struct eth_vport_tpa_param));
75 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
77 switch (p_params->tpa_mode) {
78 case ECORE_TPA_MODE_GRO:
79 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
80 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
81 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
82 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
83 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
84 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
85 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
86 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
92 p_ramrod->tx_switching_en = p_params->tx_switching;
94 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
95 p_ramrod->tx_switching_en = 0;
98 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
99 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
100 p_params->concrete_fid);
102 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
106 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
107 struct ecore_sp_vport_start_params *p_params)
109 return ecore_sp_eth_vport_start(p_hwfn, p_params);
112 static enum _ecore_status_t
113 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
114 struct vport_update_ramrod_data *p_ramrod,
115 struct ecore_rss_params *p_rss)
117 enum _ecore_status_t rc = ECORE_SUCCESS;
118 struct eth_vport_rss_config *p_config;
119 u16 abs_l2_queue = 0;
123 p_ramrod->common.update_rss_flg = 0;
126 p_config = &p_ramrod->rss_config;
128 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
129 ETH_RSS_IND_TABLE_ENTRIES_NUM);
131 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
132 if (rc != ECORE_SUCCESS)
135 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
136 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
137 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
138 p_config->update_rss_key = p_rss->update_rss_key;
140 p_config->rss_mode = p_rss->rss_enable ?
141 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
143 p_config->capabilities = 0;
145 SET_FIELD(p_config->capabilities,
146 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
147 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
148 SET_FIELD(p_config->capabilities,
149 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
150 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
151 SET_FIELD(p_config->capabilities,
152 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
153 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
154 SET_FIELD(p_config->capabilities,
155 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
156 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
157 SET_FIELD(p_config->capabilities,
158 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
159 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
160 SET_FIELD(p_config->capabilities,
161 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
162 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
163 p_config->tbl_size = p_rss->rss_table_size_log;
164 p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
166 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
167 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
168 p_ramrod->common.update_rss_flg,
170 p_config->update_rss_capabilities,
171 p_config->capabilities,
172 p_config->update_rss_ind_table, p_config->update_rss_key);
174 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
175 rc = ecore_fw_l2_queue(p_hwfn,
176 (u8)p_rss->rss_ind_table[i],
178 if (rc != ECORE_SUCCESS)
181 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
182 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
183 i, p_config->indirection_table[i]);
186 for (i = 0; i < 10; i++)
187 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
193 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
194 struct vport_update_ramrod_data *p_ramrod,
195 struct ecore_filter_accept_flags flags)
197 p_ramrod->common.update_rx_mode_flg = flags.update_rx_mode_config;
198 p_ramrod->common.update_tx_mode_flg = flags.update_tx_mode_config;
201 /* On B0 emulation we cannot enable Tx, since this would cause writes
202 * to PVFC HW block which isn't implemented in emulation.
204 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
205 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
206 "Non-Asic - prevent Tx mode in vport update\n");
207 p_ramrod->common.update_tx_mode_flg = 0;
211 /* Set Rx mode accept flags */
212 if (p_ramrod->common.update_rx_mode_flg) {
213 __le16 *state = &p_ramrod->rx_mode.state;
214 u8 accept_filter = flags.rx_accept_filter;
217 * SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
218 * !!(accept_filter & ECORE_ACCEPT_NONE));
221 * SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL,
222 * (!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) &&
223 * !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
225 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
226 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
227 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
229 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
230 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
232 * SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
233 * !!(accept_filter & ECORE_ACCEPT_NONE));
235 SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
236 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
237 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
239 SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
240 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
241 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
243 SET_FIELD(*state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
244 !!(accept_filter & ECORE_ACCEPT_BCAST));
246 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
247 "p_ramrod->rx_mode.state = 0x%x\n",
248 p_ramrod->rx_mode.state);
251 /* Set Tx mode accept flags */
252 if (p_ramrod->common.update_tx_mode_flg) {
253 __le16 *state = &p_ramrod->tx_mode.state;
254 u8 accept_filter = flags.tx_accept_filter;
256 SET_FIELD(*state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
257 !!(accept_filter & ECORE_ACCEPT_NONE));
259 SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
260 !!(accept_filter & ECORE_ACCEPT_NONE));
262 SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
263 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
264 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
266 SET_FIELD(*state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
267 !!(accept_filter & ECORE_ACCEPT_BCAST));
269 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
270 "p_ramrod->tx_mode.state = 0x%x\n",
271 p_ramrod->tx_mode.state);
276 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
277 struct vport_update_ramrod_data *p_ramrod,
278 struct ecore_sge_tpa_params *p_params)
280 struct eth_vport_tpa_param *p_tpa;
283 p_ramrod->common.update_tpa_param_flg = 0;
284 p_ramrod->common.update_tpa_en_flg = 0;
285 p_ramrod->common.update_tpa_param_flg = 0;
289 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
290 p_tpa = &p_ramrod->tpa_param;
291 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
292 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
293 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
294 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
296 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
297 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
298 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
299 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
300 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
301 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
302 p_tpa->tpa_max_size = p_params->tpa_max_size;
303 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
304 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
308 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
309 struct vport_update_ramrod_data *p_ramrod,
310 struct ecore_sp_vport_update_params *p_params)
314 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
315 sizeof(p_ramrod->approx_mcast.bins));
317 if (!p_params->update_approx_mcast_flg)
320 p_ramrod->common.update_approx_mcast_flg = 1;
321 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
322 u32 *p_bins = (u32 *)p_params->bins;
324 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
329 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
330 struct ecore_sp_vport_update_params *p_params,
331 enum spq_mode comp_mode,
332 struct ecore_spq_comp_cb *p_comp_data)
334 struct ecore_rss_params *p_rss_params = p_params->rss_params;
335 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
336 struct ecore_spq_entry *p_ent = OSAL_NULL;
337 enum _ecore_status_t rc = ECORE_NOTIMPL;
338 struct ecore_sp_init_data init_data;
339 u8 abs_vport_id = 0, val;
342 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
343 if (rc != ECORE_SUCCESS)
347 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
348 init_data.cid = ecore_spq_get_cid(p_hwfn);
349 init_data.opaque_fid = p_params->opaque_fid;
350 init_data.comp_mode = comp_mode;
351 init_data.p_comp_data = p_comp_data;
353 rc = ecore_sp_init_request(p_hwfn, &p_ent,
354 ETH_RAMROD_VPORT_UPDATE,
355 PROTOCOLID_ETH, &init_data);
356 if (rc != ECORE_SUCCESS)
359 /* Copy input params to ramrod according to FW struct */
360 p_ramrod = &p_ent->ramrod.vport_update;
362 p_ramrod->common.vport_id = abs_vport_id;
364 p_ramrod->common.rx_active_flg = p_params->vport_active_rx_flg;
365 p_ramrod->common.tx_active_flg = p_params->vport_active_tx_flg;
366 val = p_params->update_vport_active_rx_flg;
367 p_ramrod->common.update_rx_active_flg = val;
368 val = p_params->update_vport_active_tx_flg;
369 p_ramrod->common.update_tx_active_flg = val;
370 val = p_params->update_inner_vlan_removal_flg;
371 p_ramrod->common.update_inner_vlan_removal_en_flg = val;
372 val = p_params->inner_vlan_removal_flg;
373 p_ramrod->common.inner_vlan_removal_en = val;
374 val = p_params->silent_vlan_removal_flg;
375 p_ramrod->common.silent_vlan_removal_en = val;
376 val = p_params->update_tx_switching_flg;
377 p_ramrod->common.update_tx_switching_en_flg = val;
378 val = p_params->update_default_vlan_enable_flg;
379 p_ramrod->common.update_default_vlan_en_flg = val;
380 p_ramrod->common.default_vlan_en = p_params->default_vlan_enable_flg;
381 val = p_params->update_default_vlan_flg;
382 p_ramrod->common.update_default_vlan_flg = val;
383 wordval = p_params->default_vlan;
384 p_ramrod->common.default_vlan = OSAL_CPU_TO_LE16(wordval);
386 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
389 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
390 if (p_ramrod->common.tx_switching_en ||
391 p_ramrod->common.update_tx_switching_en_flg) {
392 DP_NOTICE(p_hwfn, false,
393 "FPGA - why are we seeing tx-switching? Overriding it\n");
394 p_ramrod->common.tx_switching_en = 0;
395 p_ramrod->common.update_tx_switching_en_flg = 1;
399 val = p_params->update_anti_spoofing_en_flg;
400 p_ramrod->common.update_anti_spoofing_en_flg = val;
401 p_ramrod->common.anti_spoofing_en = p_params->anti_spoofing_en;
402 p_ramrod->common.accept_any_vlan = p_params->accept_any_vlan;
403 val = p_params->update_accept_any_vlan_flg;
404 p_ramrod->common.update_accept_any_vlan_flg = val;
406 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
407 if (rc != ECORE_SUCCESS) {
408 /* Return spq entry which is taken in ecore_sp_init_request() */
409 ecore_spq_return_entry(p_hwfn, p_ent);
413 /* Update mcast bins for VFs, PF doesn't use this functionality */
414 ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
416 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
417 ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
418 p_params->sge_tpa_params);
419 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
422 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
423 u16 opaque_fid, u8 vport_id)
425 struct vport_stop_ramrod_data *p_ramrod;
426 struct ecore_sp_init_data init_data;
427 struct ecore_spq_entry *p_ent;
428 enum _ecore_status_t rc;
431 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
432 if (rc != ECORE_SUCCESS)
436 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
437 init_data.cid = ecore_spq_get_cid(p_hwfn);
438 init_data.opaque_fid = opaque_fid;
439 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
441 rc = ecore_sp_init_request(p_hwfn, &p_ent,
442 ETH_RAMROD_VPORT_STOP,
443 PROTOCOLID_ETH, &init_data);
444 if (rc != ECORE_SUCCESS)
447 p_ramrod = &p_ent->ramrod.vport_stop;
448 p_ramrod->vport_id = abs_vport_id;
450 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
454 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
456 struct ecore_filter_accept_flags accept_flags,
457 u8 update_accept_any_vlan,
459 enum spq_mode comp_mode,
460 struct ecore_spq_comp_cb *p_comp_data)
462 struct ecore_sp_vport_update_params update_params;
465 /* Prepare and send the vport rx_mode change */
466 OSAL_MEMSET(&update_params, 0, sizeof(update_params));
467 update_params.vport_id = vport;
468 update_params.accept_flags = accept_flags;
469 update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
470 update_params.accept_any_vlan = accept_any_vlan;
472 for_each_hwfn(p_dev, i) {
473 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
475 update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
477 rc = ecore_sp_vport_update(p_hwfn, &update_params,
478 comp_mode, p_comp_data);
479 if (rc != ECORE_SUCCESS) {
480 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
484 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
485 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
486 accept_flags.rx_accept_filter,
487 accept_flags.tx_accept_filter);
489 if (update_accept_any_vlan)
490 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
491 "accept_any_vlan=%d configured\n",
498 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
499 struct ecore_hw_cid_data *p_cid_data)
501 if (!p_cid_data->b_cid_allocated)
504 ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
505 p_cid_data->b_cid_allocated = false;
509 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
518 dma_addr_t bd_chain_phys_addr,
519 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
521 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
522 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
523 struct ecore_spq_entry *p_ent = OSAL_NULL;
524 enum _ecore_status_t rc = ECORE_NOTIMPL;
525 struct ecore_sp_init_data init_data;
529 /* Store information for the stop */
531 p_rx_cid->opaque_fid = opaque_fid;
532 p_rx_cid->vport_id = vport_id;
534 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
535 if (rc != ECORE_SUCCESS)
538 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
539 if (rc != ECORE_SUCCESS)
542 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
543 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
544 opaque_fid, cid, rx_queue_id, vport_id, sb);
547 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
549 init_data.opaque_fid = opaque_fid;
550 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
552 rc = ecore_sp_init_request(p_hwfn, &p_ent,
553 ETH_RAMROD_RX_QUEUE_START,
554 PROTOCOLID_ETH, &init_data);
555 if (rc != ECORE_SUCCESS)
558 p_ramrod = &p_ent->ramrod.rx_queue_start;
560 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
561 p_ramrod->sb_index = sb_index;
562 p_ramrod->vport_id = abs_vport_id;
563 p_ramrod->stats_counter_id = stats_id;
564 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
565 p_ramrod->complete_cqe_flg = 0;
566 p_ramrod->complete_event_flg = 1;
568 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
569 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
571 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
572 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
574 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
577 enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
585 dma_addr_t bd_chain_phys_addr,
586 dma_addr_t cqe_pbl_addr,
588 void OSAL_IOMEM * *pp_prod)
590 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
592 u16 abs_l2_queue = 0;
593 enum _ecore_status_t rc;
594 u64 init_prod_val = 0;
596 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_l2_queue);
597 if (rc != ECORE_SUCCESS)
600 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
601 if (rc != ECORE_SUCCESS)
604 *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
605 GTT_BAR0_MAP_REG_MSDM_RAM + MSTORM_PRODS_OFFSET(abs_l2_queue);
607 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
608 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
609 (u32 *)(&init_prod_val));
611 /* Allocate a CID for the queue */
612 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid);
613 if (rc != ECORE_SUCCESS) {
614 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
617 p_rx_cid->b_cid_allocated = true;
619 rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
629 cqe_pbl_addr, cqe_pbl_size);
631 if (rc != ECORE_SUCCESS)
632 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
638 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
642 u8 complete_event_flg,
643 enum spq_mode comp_mode,
644 struct ecore_spq_comp_cb *p_comp_data)
646 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
647 struct ecore_spq_entry *p_ent = OSAL_NULL;
648 enum _ecore_status_t rc = ECORE_NOTIMPL;
649 struct ecore_sp_init_data init_data;
650 struct ecore_hw_cid_data *p_rx_cid;
651 u16 qid, abs_rx_q_id = 0;
654 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
655 init_data.comp_mode = comp_mode;
656 init_data.p_comp_data = p_comp_data;
658 for (i = 0; i < num_rxqs; i++) {
659 qid = rx_queue_id + i;
660 p_rx_cid = &p_hwfn->p_rx_cids[qid];
663 init_data.cid = p_rx_cid->cid;
664 init_data.opaque_fid = p_rx_cid->opaque_fid;
666 rc = ecore_sp_init_request(p_hwfn, &p_ent,
667 ETH_RAMROD_RX_QUEUE_UPDATE,
668 PROTOCOLID_ETH, &init_data);
669 if (rc != ECORE_SUCCESS)
672 p_ramrod = &p_ent->ramrod.rx_queue_update;
674 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
675 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
676 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
677 p_ramrod->complete_cqe_flg = complete_cqe_flg;
678 p_ramrod->complete_event_flg = complete_event_flg;
680 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
689 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
691 bool eq_completion_only, bool cqe_completion)
693 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
694 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
695 struct ecore_spq_entry *p_ent = OSAL_NULL;
696 enum _ecore_status_t rc = ECORE_NOTIMPL;
697 struct ecore_sp_init_data init_data;
701 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
702 init_data.cid = p_rx_cid->cid;
703 init_data.opaque_fid = p_rx_cid->opaque_fid;
704 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
706 rc = ecore_sp_init_request(p_hwfn, &p_ent,
707 ETH_RAMROD_RX_QUEUE_STOP,
708 PROTOCOLID_ETH, &init_data);
709 if (rc != ECORE_SUCCESS)
712 p_ramrod = &p_ent->ramrod.rx_queue_stop;
714 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
715 ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
716 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
718 /* Cleaning the queue requires the completion to arrive there.
719 * In addition, VFs require the answer to come as eqe to PF.
721 p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
722 p_hwfn->hw_info.opaque_fid) &&
723 !eq_completion_only) || cqe_completion;
724 p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
725 p_hwfn->hw_info.opaque_fid) ||
728 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
729 if (rc != ECORE_SUCCESS)
732 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
738 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
748 union ecore_qm_pq_params *p_pq_params)
750 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
751 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
752 struct ecore_spq_entry *p_ent = OSAL_NULL;
753 enum _ecore_status_t rc = ECORE_NOTIMPL;
754 struct ecore_sp_init_data init_data;
755 u16 pq_id, abs_tx_q_id = 0;
758 /* Store information for the stop */
760 p_tx_cid->opaque_fid = opaque_fid;
762 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
763 if (rc != ECORE_SUCCESS)
766 rc = ecore_fw_l2_queue(p_hwfn, tx_queue_id, &abs_tx_q_id);
767 if (rc != ECORE_SUCCESS)
771 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
773 init_data.opaque_fid = opaque_fid;
774 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
776 rc = ecore_sp_init_request(p_hwfn, &p_ent,
777 ETH_RAMROD_TX_QUEUE_START,
778 PROTOCOLID_ETH, &init_data);
779 if (rc != ECORE_SUCCESS)
782 p_ramrod = &p_ent->ramrod.tx_queue_start;
783 p_ramrod->vport_id = abs_vport_id;
785 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
786 p_ramrod->sb_index = sb_index;
787 p_ramrod->stats_counter_id = stats_id;
789 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
791 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
792 p_ramrod->pbl_base_addr.hi = DMA_HI_LE(pbl_addr);
793 p_ramrod->pbl_base_addr.lo = DMA_LO_LE(pbl_addr);
795 pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
796 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
798 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
801 enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
810 void OSAL_IOMEM * *pp_doorbell)
812 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
813 union ecore_qm_pq_params pq_params;
814 enum _ecore_status_t rc;
817 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
818 if (rc != ECORE_SUCCESS)
821 OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
822 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
824 /* Allocate a CID for the queue */
825 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
826 if (rc != ECORE_SUCCESS) {
827 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
830 p_tx_cid->b_cid_allocated = true;
832 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
833 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
834 opaque_fid, p_tx_cid->cid, tx_queue_id, vport_id, sb);
836 /* TODO - set tc in the pq_params for multi-cos */
837 rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
845 pbl_addr, pbl_size, &pq_params);
847 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
848 DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
850 if (rc != ECORE_SUCCESS)
851 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
856 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
858 return ECORE_NOTIMPL;
861 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
864 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
865 struct tx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
866 struct ecore_spq_entry *p_ent = OSAL_NULL;
867 enum _ecore_status_t rc = ECORE_NOTIMPL;
868 struct ecore_sp_init_data init_data;
871 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
872 init_data.cid = p_tx_cid->cid;
873 init_data.opaque_fid = p_tx_cid->opaque_fid;
874 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
876 rc = ecore_sp_init_request(p_hwfn, &p_ent,
877 ETH_RAMROD_TX_QUEUE_STOP,
878 PROTOCOLID_ETH, &init_data);
879 if (rc != ECORE_SUCCESS)
882 p_ramrod = &p_ent->ramrod.tx_queue_stop;
884 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
885 if (rc != ECORE_SUCCESS)
888 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
892 static enum eth_filter_action
893 ecore_filter_action(enum ecore_filter_opcode opcode)
895 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
898 case ECORE_FILTER_ADD:
899 action = ETH_FILTER_ACTION_ADD;
901 case ECORE_FILTER_REMOVE:
902 action = ETH_FILTER_ACTION_REMOVE;
904 case ECORE_FILTER_FLUSH:
905 action = ETH_FILTER_ACTION_REMOVE_ALL;
908 action = MAX_ETH_FILTER_ACTION;
914 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
915 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
917 ((u8 *)fw_msb)[0] = mac[1];
918 ((u8 *)fw_msb)[1] = mac[0];
919 ((u8 *)fw_mid)[0] = mac[3];
920 ((u8 *)fw_mid)[1] = mac[2];
921 ((u8 *)fw_lsb)[0] = mac[5];
922 ((u8 *)fw_lsb)[1] = mac[4];
925 static enum _ecore_status_t
926 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
928 struct ecore_filter_ucast *p_filter_cmd,
929 struct vport_filter_update_ramrod_data **pp_ramrod,
930 struct ecore_spq_entry **pp_ent,
931 enum spq_mode comp_mode,
932 struct ecore_spq_comp_cb *p_comp_data)
934 struct vport_filter_update_ramrod_data *p_ramrod;
935 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
936 struct eth_filter_cmd *p_first_filter;
937 struct eth_filter_cmd *p_second_filter;
938 struct ecore_sp_init_data init_data;
939 enum eth_filter_action action;
940 enum _ecore_status_t rc;
942 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
943 &vport_to_remove_from);
944 if (rc != ECORE_SUCCESS)
947 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
949 if (rc != ECORE_SUCCESS)
953 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
954 init_data.cid = ecore_spq_get_cid(p_hwfn);
955 init_data.opaque_fid = opaque_fid;
956 init_data.comp_mode = comp_mode;
957 init_data.p_comp_data = p_comp_data;
959 rc = ecore_sp_init_request(p_hwfn, pp_ent,
960 ETH_RAMROD_FILTERS_UPDATE,
961 PROTOCOLID_ETH, &init_data);
962 if (rc != ECORE_SUCCESS)
965 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
966 p_ramrod = *pp_ramrod;
967 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
968 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
971 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
972 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
973 "Non-Asic - prevent Tx filters\n");
974 p_ramrod->filter_cmd_hdr.tx = 0;
978 switch (p_filter_cmd->opcode) {
979 case ECORE_FILTER_REPLACE:
980 case ECORE_FILTER_MOVE:
981 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
984 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
988 p_first_filter = &p_ramrod->filter_cmds[0];
989 p_second_filter = &p_ramrod->filter_cmds[1];
991 switch (p_filter_cmd->type) {
992 case ECORE_FILTER_MAC:
993 p_first_filter->type = ETH_FILTER_TYPE_MAC;
995 case ECORE_FILTER_VLAN:
996 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
998 case ECORE_FILTER_MAC_VLAN:
999 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1001 case ECORE_FILTER_INNER_MAC:
1002 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1004 case ECORE_FILTER_INNER_VLAN:
1005 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1007 case ECORE_FILTER_INNER_PAIR:
1008 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1010 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1011 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1013 case ECORE_FILTER_MAC_VNI_PAIR:
1014 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1016 case ECORE_FILTER_VNI:
1017 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1021 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1022 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1023 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1024 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1025 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1026 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1027 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1028 &p_first_filter->mac_mid,
1029 &p_first_filter->mac_lsb,
1030 (u8 *)p_filter_cmd->mac);
1032 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1033 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1034 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1035 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1036 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1038 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1039 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1040 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1041 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1043 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1044 p_second_filter->type = p_first_filter->type;
1045 p_second_filter->mac_msb = p_first_filter->mac_msb;
1046 p_second_filter->mac_mid = p_first_filter->mac_mid;
1047 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1048 p_second_filter->vlan_id = p_first_filter->vlan_id;
1049 p_second_filter->vni = p_first_filter->vni;
1051 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1053 p_first_filter->vport_id = vport_to_remove_from;
1055 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1056 p_second_filter->vport_id = vport_to_add_to;
1057 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1058 p_first_filter->vport_id = vport_to_add_to;
1059 OSAL_MEMCPY(p_second_filter, p_first_filter,
1060 sizeof(*p_second_filter));
1061 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1062 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1064 action = ecore_filter_action(p_filter_cmd->opcode);
1066 if (action == MAX_ETH_FILTER_ACTION) {
1067 DP_NOTICE(p_hwfn, true,
1068 "%d is not supported yet\n",
1069 p_filter_cmd->opcode);
1070 return ECORE_NOTIMPL;
1073 p_first_filter->action = action;
1074 p_first_filter->vport_id =
1075 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1076 vport_to_remove_from : vport_to_add_to;
1079 return ECORE_SUCCESS;
1082 enum _ecore_status_t
1083 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1085 struct ecore_filter_ucast *p_filter_cmd,
1086 enum spq_mode comp_mode,
1087 struct ecore_spq_comp_cb *p_comp_data)
1089 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1090 struct ecore_spq_entry *p_ent = OSAL_NULL;
1091 struct eth_filter_cmd_header *p_header;
1092 enum _ecore_status_t rc;
1094 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1096 comp_mode, p_comp_data);
1097 if (rc != ECORE_SUCCESS) {
1098 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1101 p_header = &p_ramrod->filter_cmd_hdr;
1102 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1104 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1105 if (rc != ECORE_SUCCESS) {
1106 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1110 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1111 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1112 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1113 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1115 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1116 "MOVE" : "REPLACE")),
1117 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1118 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1119 "VLAN" : "MAC & VLAN"),
1120 p_ramrod->filter_cmd_hdr.cmd_cnt,
1121 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1122 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1123 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1124 p_filter_cmd->vport_to_add_to,
1125 p_filter_cmd->vport_to_remove_from,
1126 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1127 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1128 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1129 p_filter_cmd->vlan);
1131 return ECORE_SUCCESS;
1134 /*******************************************************************************
1136 * Calculates crc 32 on a buffer
1137 * Note: crc32_length MUST be aligned to 8
1139 ******************************************************************************/
1140 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1141 u32 crc32_length, u32 crc32_seed, u8 complement)
1143 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1144 u8 msb = 0, current_byte = 0;
1146 if ((crc32_packet == OSAL_NULL) ||
1147 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1148 return crc32_result;
1151 for (byte = 0; byte < crc32_length; byte++) {
1152 current_byte = crc32_packet[byte];
1153 for (bit = 0; bit < 8; bit++) {
1154 msb = (u8)(crc32_result >> 31);
1155 crc32_result = crc32_result << 1;
1156 if (msb != (0x1 & (current_byte >> bit))) {
1157 crc32_result = crc32_result ^ CRC32_POLY;
1163 return crc32_result;
1166 static OSAL_INLINE u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1168 u32 packet_buf[2] = { 0 };
1170 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1171 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1174 u8 ecore_mcast_bin_from_mac(u8 *mac)
1176 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1182 static enum _ecore_status_t
1183 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1185 struct ecore_filter_mcast *p_filter_cmd,
1186 enum spq_mode comp_mode,
1187 struct ecore_spq_comp_cb *p_comp_data)
1189 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1190 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1191 struct ecore_spq_entry *p_ent = OSAL_NULL;
1192 struct ecore_sp_init_data init_data;
1193 enum _ecore_status_t rc;
1194 u8 abs_vport_id = 0;
1197 rc = ecore_fw_vport(p_hwfn,
1198 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ?
1199 p_filter_cmd->vport_to_add_to :
1200 p_filter_cmd->vport_to_remove_from, &abs_vport_id);
1201 if (rc != ECORE_SUCCESS)
1205 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1206 init_data.cid = ecore_spq_get_cid(p_hwfn);
1207 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1208 init_data.comp_mode = comp_mode;
1209 init_data.p_comp_data = p_comp_data;
1211 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1212 ETH_RAMROD_VPORT_UPDATE,
1213 PROTOCOLID_ETH, &init_data);
1214 if (rc != ECORE_SUCCESS) {
1215 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1219 p_ramrod = &p_ent->ramrod.vport_update;
1220 p_ramrod->common.update_approx_mcast_flg = 1;
1222 /* explicitly clear out the entire vector */
1223 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1224 0, sizeof(p_ramrod->approx_mcast.bins));
1225 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1226 ETH_MULTICAST_MAC_BINS_IN_REGS);
1228 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1229 /* filter ADD op is explicit set op and it removes
1230 * any existing filters for the vport.
1232 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1235 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1236 OSAL_SET_BIT(bit, bins);
1239 /* Convert to correct endianity */
1240 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1241 struct vport_update_ramrod_mcast *p_ramrod_bins;
1242 u32 *p_bins = (u32 *)bins;
1244 p_ramrod_bins = &p_ramrod->approx_mcast;
1245 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1249 p_ramrod->common.vport_id = abs_vport_id;
1251 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1252 if (rc != ECORE_SUCCESS)
1253 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1258 enum _ecore_status_t
1259 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1260 struct ecore_filter_mcast *p_filter_cmd,
1261 enum spq_mode comp_mode,
1262 struct ecore_spq_comp_cb *p_comp_data)
1264 enum _ecore_status_t rc = ECORE_SUCCESS;
1267 /* only ADD and REMOVE operations are supported for multi-cast */
1268 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1269 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1270 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1274 for_each_hwfn(p_dev, i) {
1275 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1277 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1278 p_hwfn->hw_info.opaque_fid,
1280 comp_mode, p_comp_data);
1281 if (rc != ECORE_SUCCESS)
1288 enum _ecore_status_t
1289 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1290 struct ecore_filter_ucast *p_filter_cmd,
1291 enum spq_mode comp_mode,
1292 struct ecore_spq_comp_cb *p_comp_data)
1294 enum _ecore_status_t rc = ECORE_SUCCESS;
1297 for_each_hwfn(p_dev, i) {
1298 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1300 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1301 p_hwfn->hw_info.opaque_fid,
1303 comp_mode, p_comp_data);
1304 if (rc != ECORE_SUCCESS)
1311 /* Statistics related code */
1312 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1313 u32 *p_addr, u32 *p_len,
1316 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1317 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1318 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1321 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1322 struct ecore_ptt *p_ptt,
1323 struct ecore_eth_stats *p_stats,
1326 struct eth_pstorm_per_queue_stat pstats;
1327 u32 pstats_addr = 0, pstats_len = 0;
1329 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1332 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1333 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1335 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1336 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1337 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1338 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1339 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1340 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1341 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1344 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1345 struct ecore_ptt *p_ptt,
1346 struct ecore_eth_stats *p_stats,
1349 struct tstorm_per_port_stat tstats;
1350 u32 tstats_addr, tstats_len;
1352 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1353 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1354 tstats_len = sizeof(struct tstorm_per_port_stat);
1356 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1357 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1359 p_stats->mftag_filter_discards +=
1360 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1361 p_stats->mac_filter_discards +=
1362 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1365 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1366 u32 *p_addr, u32 *p_len,
1369 *p_addr = BAR0_MAP_REG_USDM_RAM +
1370 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1371 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1374 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1375 struct ecore_ptt *p_ptt,
1376 struct ecore_eth_stats *p_stats,
1379 struct eth_ustorm_per_queue_stat ustats;
1380 u32 ustats_addr = 0, ustats_len = 0;
1382 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1385 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1386 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1388 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1389 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1390 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1391 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1392 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1393 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1396 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1397 u32 *p_addr, u32 *p_len,
1400 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1401 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1402 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1405 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1406 struct ecore_ptt *p_ptt,
1407 struct ecore_eth_stats *p_stats,
1410 struct eth_mstorm_per_queue_stat mstats;
1411 u32 mstats_addr = 0, mstats_len = 0;
1413 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1416 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1417 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1419 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1420 p_stats->packet_too_big_discard +=
1421 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1422 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1423 p_stats->tpa_coalesced_pkts +=
1424 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1425 p_stats->tpa_coalesced_events +=
1426 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1427 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1428 p_stats->tpa_coalesced_bytes +=
1429 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1432 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1433 struct ecore_ptt *p_ptt,
1434 struct ecore_eth_stats *p_stats)
1436 struct port_stats port_stats;
1439 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1441 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1442 p_hwfn->mcp_info->port_addr +
1443 OFFSETOF(struct public_port, stats),
1444 sizeof(port_stats));
1446 p_stats->rx_64_byte_packets += port_stats.pmm.r64;
1447 p_stats->rx_65_to_127_byte_packets += port_stats.pmm.r127;
1448 p_stats->rx_128_to_255_byte_packets += port_stats.pmm.r255;
1449 p_stats->rx_256_to_511_byte_packets += port_stats.pmm.r511;
1450 p_stats->rx_512_to_1023_byte_packets += port_stats.pmm.r1023;
1451 p_stats->rx_1024_to_1518_byte_packets += port_stats.pmm.r1518;
1452 p_stats->rx_1519_to_1522_byte_packets += port_stats.pmm.r1522;
1453 p_stats->rx_1519_to_2047_byte_packets += port_stats.pmm.r2047;
1454 p_stats->rx_2048_to_4095_byte_packets += port_stats.pmm.r4095;
1455 p_stats->rx_4096_to_9216_byte_packets += port_stats.pmm.r9216;
1456 p_stats->rx_9217_to_16383_byte_packets += port_stats.pmm.r16383;
1457 p_stats->rx_crc_errors += port_stats.pmm.rfcs;
1458 p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1459 p_stats->rx_pause_frames += port_stats.pmm.rxpf;
1460 p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
1461 p_stats->rx_align_errors += port_stats.pmm.raln;
1462 p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
1463 p_stats->rx_oversize_packets += port_stats.pmm.rovr;
1464 p_stats->rx_jabbers += port_stats.pmm.rjbr;
1465 p_stats->rx_undersize_packets += port_stats.pmm.rund;
1466 p_stats->rx_fragments += port_stats.pmm.rfrg;
1467 p_stats->tx_64_byte_packets += port_stats.pmm.t64;
1468 p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1469 p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1470 p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1471 p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1472 p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1473 p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1474 p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1475 p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1476 p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1477 p_stats->tx_pause_frames += port_stats.pmm.txpf;
1478 p_stats->tx_pfc_frames += port_stats.pmm.txpp;
1479 p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1480 p_stats->tx_total_collisions += port_stats.pmm.tncl;
1481 p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
1482 p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1483 p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1484 p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1485 p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1486 p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
1487 p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1488 p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1489 p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1490 p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1491 for (j = 0; j < 8; j++) {
1492 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1493 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1497 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1498 struct ecore_ptt *p_ptt,
1499 struct ecore_eth_stats *stats,
1500 u16 statistics_bin, bool b_get_port_stats)
1502 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1503 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1504 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1505 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1508 /* Avoid getting PORT stats for emulation. */
1509 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1513 if (b_get_port_stats && p_hwfn->mcp_info)
1514 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1517 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1518 struct ecore_eth_stats *stats)
1523 OSAL_MEMSET(stats, 0, sizeof(*stats));
1525 for_each_hwfn(p_dev, i) {
1526 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1527 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1529 /* The main vport index is relative first */
1530 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1531 DP_ERR(p_hwfn, "No vport available!\n");
1536 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1540 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1544 ecore_ptt_release(p_hwfn, p_ptt);
1548 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1549 struct ecore_eth_stats *stats)
1554 OSAL_MEMSET(stats, 0, sizeof(*stats));
1558 _ecore_get_vport_stats(p_dev, stats);
1560 if (!p_dev->reset_stats)
1563 /* Reduce the statistics baseline */
1564 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1565 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1568 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1569 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1573 for_each_hwfn(p_dev, i) {
1574 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1575 struct eth_mstorm_per_queue_stat mstats;
1576 struct eth_ustorm_per_queue_stat ustats;
1577 struct eth_pstorm_per_queue_stat pstats;
1578 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1579 u32 addr = 0, len = 0;
1582 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1586 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1587 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1588 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1590 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1591 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1592 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1594 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1595 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1596 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1598 ecore_ptt_release(p_hwfn, p_ptt);
1601 /* PORT statistics are not necessarily reset, so we need to
1602 * read and create a baseline for future statistics.
1604 if (!p_dev->reset_stats)
1605 DP_INFO(p_dev, "Reset stats not allocated\n");
1607 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);