2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
26 #include "ecore_sriov.h"
27 #include "ecore_mcp.h"
29 #define ECORE_MAX_SGES_NUM 16
30 #define CRC32_POLY 0x1edc6f41
32 struct ecore_l2_info {
34 unsigned long **pp_qid_usage;
36 /* The lock is meant to synchronize access to the qid usage */
40 enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn)
42 struct ecore_l2_info *p_l2_info;
43 unsigned long **pp_qids;
46 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
49 p_l2_info = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_l2_info));
52 p_hwfn->p_l2_info = p_l2_info;
54 if (IS_PF(p_hwfn->p_dev)) {
55 p_l2_info->queues = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
59 ecore_vf_get_num_rxqs(p_hwfn, &rx);
60 ecore_vf_get_num_txqs(p_hwfn, &tx);
62 p_l2_info->queues = (u32)OSAL_MAX_T(u8, rx, tx);
65 pp_qids = OSAL_VZALLOC(p_hwfn->p_dev,
66 sizeof(unsigned long *) *
68 if (pp_qids == OSAL_NULL)
70 p_l2_info->pp_qid_usage = pp_qids;
72 for (i = 0; i < p_l2_info->queues; i++) {
73 pp_qids[i] = OSAL_VZALLOC(p_hwfn->p_dev,
74 MAX_QUEUES_PER_QZONE / 8);
75 if (pp_qids[i] == OSAL_NULL)
79 #ifdef CONFIG_ECORE_LOCK_ALLOC
80 OSAL_MUTEX_ALLOC(p_hwfn, &p_l2_info->lock);
86 void ecore_l2_setup(struct ecore_hwfn *p_hwfn)
88 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
91 OSAL_MUTEX_INIT(&p_hwfn->p_l2_info->lock);
94 void ecore_l2_free(struct ecore_hwfn *p_hwfn)
98 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
101 if (p_hwfn->p_l2_info == OSAL_NULL)
104 if (p_hwfn->p_l2_info->pp_qid_usage == OSAL_NULL)
107 /* Free until hit first uninitialized entry */
108 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
109 if (p_hwfn->p_l2_info->pp_qid_usage[i] == OSAL_NULL)
111 OSAL_VFREE(p_hwfn->p_dev,
112 p_hwfn->p_l2_info->pp_qid_usage[i]);
115 #ifdef CONFIG_ECORE_LOCK_ALLOC
116 /* Lock is last to initialize, if everything else was */
117 if (i == p_hwfn->p_l2_info->queues)
118 OSAL_MUTEX_DEALLOC(&p_hwfn->p_l2_info->lock);
121 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info->pp_qid_usage);
124 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info);
125 p_hwfn->p_l2_info = OSAL_NULL;
128 /* TODO - we'll need locking around these... */
129 static bool ecore_eth_queue_qid_usage_add(struct ecore_hwfn *p_hwfn,
130 struct ecore_queue_cid *p_cid)
132 struct ecore_l2_info *p_l2_info = p_hwfn->p_l2_info;
133 u16 queue_id = p_cid->rel.queue_id;
137 OSAL_MUTEX_ACQUIRE(&p_l2_info->lock);
139 if (queue_id > p_l2_info->queues) {
140 DP_NOTICE(p_hwfn, true,
141 "Requested to increase usage for qzone %04x out of %08x\n",
142 queue_id, p_l2_info->queues);
147 first = (u8)OSAL_FIND_FIRST_ZERO_BIT(p_l2_info->pp_qid_usage[queue_id],
148 MAX_QUEUES_PER_QZONE);
149 if (first >= MAX_QUEUES_PER_QZONE) {
154 OSAL_SET_BIT(first, p_l2_info->pp_qid_usage[queue_id]);
155 p_cid->qid_usage_idx = first;
158 OSAL_MUTEX_RELEASE(&p_l2_info->lock);
162 static void ecore_eth_queue_qid_usage_del(struct ecore_hwfn *p_hwfn,
163 struct ecore_queue_cid *p_cid)
165 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_l2_info->lock);
167 OSAL_CLEAR_BIT(p_cid->qid_usage_idx,
168 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
170 OSAL_MUTEX_RELEASE(&p_hwfn->p_l2_info->lock);
173 void ecore_eth_queue_cid_release(struct ecore_hwfn *p_hwfn,
174 struct ecore_queue_cid *p_cid)
176 /* For VF-queues, stuff is a bit complicated as:
177 * - They always maintain the qid_usage on their own.
178 * - In legacy mode, they also maintain their CIDs.
181 /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
182 if (IS_PF(p_hwfn->p_dev) && !p_cid->b_legacy_vf)
183 _ecore_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
184 if (!p_cid->b_legacy_vf)
185 ecore_eth_queue_qid_usage_del(p_hwfn, p_cid);
186 OSAL_VFREE(p_hwfn->p_dev, p_cid);
189 /* The internal is only meant to be directly called by PFs initializeing CIDs
192 static struct ecore_queue_cid *
193 _ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn,
194 u16 opaque_fid, u32 cid,
195 struct ecore_queue_start_common_params *p_params,
196 struct ecore_queue_cid_vf_params *p_vf_params)
198 struct ecore_queue_cid *p_cid;
199 enum _ecore_status_t rc;
201 p_cid = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_cid));
202 if (p_cid == OSAL_NULL)
205 p_cid->opaque_fid = opaque_fid;
207 p_cid->rel = *p_params;
208 p_cid->p_owner = p_hwfn;
210 /* Fill-in bits related to VFs' queues if information was provided */
211 if (p_vf_params != OSAL_NULL) {
212 p_cid->vfid = p_vf_params->vfid;
213 p_cid->vf_qid = p_vf_params->vf_qid;
214 p_cid->b_legacy_vf = p_vf_params->b_legacy;
216 p_cid->vfid = ECORE_QUEUE_CID_PF;
219 /* Don't try calculating the absolute indices for VFs */
220 if (IS_VF(p_hwfn->p_dev)) {
221 p_cid->abs = p_cid->rel;
226 /* Calculate the engine-absolute indices of the resources.
227 * The would guarantee they're valid later on.
228 * In some cases [SBs] we already have the right values.
230 rc = ecore_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
231 if (rc != ECORE_SUCCESS)
234 rc = ecore_fw_l2_queue(p_hwfn, p_cid->rel.queue_id,
235 &p_cid->abs.queue_id);
236 if (rc != ECORE_SUCCESS)
239 /* In case of a PF configuring its VF's queues, the stats-id is already
240 * absolute [since there's a single index that's suitable per-VF].
242 if (p_cid->vfid == ECORE_QUEUE_CID_PF) {
243 rc = ecore_fw_vport(p_hwfn, p_cid->rel.stats_id,
244 &p_cid->abs.stats_id);
245 if (rc != ECORE_SUCCESS)
248 p_cid->abs.stats_id = p_cid->rel.stats_id;
251 /* SBs relevant information was already provided as absolute */
252 p_cid->abs.sb = p_cid->rel.sb;
253 p_cid->abs.sb_idx = p_cid->rel.sb_idx;
256 /* VF-images have provided the qid_usage_idx on their own.
257 * Otherwise, we need to allocate a unique one.
260 if (!ecore_eth_queue_qid_usage_add(p_hwfn, p_cid))
263 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
266 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
267 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
268 p_cid->opaque_fid, p_cid->cid,
269 p_cid->rel.vport_id, p_cid->abs.vport_id,
270 p_cid->rel.queue_id, p_cid->qid_usage_idx,
272 p_cid->rel.stats_id, p_cid->abs.stats_id,
273 p_cid->abs.sb, p_cid->abs.sb_idx);
278 OSAL_VFREE(p_hwfn->p_dev, p_cid);
282 struct ecore_queue_cid *
283 ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
284 struct ecore_queue_start_common_params *p_params,
285 struct ecore_queue_cid_vf_params *p_vf_params)
287 struct ecore_queue_cid *p_cid;
288 u8 vfid = ECORE_CXT_PF_CID;
289 bool b_legacy_vf = false;
292 /* In case of legacy VFs, The CID can be derived from the additional
293 * VF parameters - the VF assumes queue X uses CID X, so we can simply
294 * use the vf_qid for this purpose as well.
297 vfid = p_vf_params->vfid;
299 if (p_vf_params->b_legacy) {
301 cid = p_vf_params->vf_qid;
305 /* Get a unique firmware CID for this queue, in case it's a PF.
306 * VF's don't need a CID as the queue configuration will be done
309 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf) {
310 if (_ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
311 &cid, vfid) != ECORE_SUCCESS) {
312 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
317 p_cid = _ecore_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
318 p_params, p_vf_params);
319 if ((p_cid == OSAL_NULL) && IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
320 _ecore_cxt_release_cid(p_hwfn, cid, vfid);
325 static struct ecore_queue_cid *
326 ecore_eth_queue_to_cid_pf(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
327 struct ecore_queue_start_common_params *p_params)
329 return ecore_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, OSAL_NULL);
333 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
334 struct ecore_sp_vport_start_params *p_params)
336 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
337 struct ecore_spq_entry *p_ent = OSAL_NULL;
338 struct ecore_sp_init_data init_data;
339 u16 rx_mode = 0, tx_err = 0;
341 enum _ecore_status_t rc = ECORE_NOTIMPL;
343 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
344 if (rc != ECORE_SUCCESS)
348 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
349 init_data.cid = ecore_spq_get_cid(p_hwfn);
350 init_data.opaque_fid = p_params->opaque_fid;
351 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
353 rc = ecore_sp_init_request(p_hwfn, &p_ent,
354 ETH_RAMROD_VPORT_START,
355 PROTOCOLID_ETH, &init_data);
356 if (rc != ECORE_SUCCESS)
359 p_ramrod = &p_ent->ramrod.vport_start;
360 p_ramrod->vport_id = abs_vport_id;
362 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
363 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
364 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
365 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
366 p_ramrod->untagged = p_params->only_untagged;
367 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
369 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
370 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
372 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
374 /* Handle requests for strict behavior on transmission errors */
375 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE,
376 p_params->b_err_illegal_vlan_mode ?
377 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
378 SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL,
379 p_params->b_err_small_pkt ?
380 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
381 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR,
382 p_params->b_err_anti_spoof ?
383 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
384 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS,
385 p_params->b_err_illegal_inband_mode ?
386 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
387 SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG,
388 p_params->b_err_vlan_insert_with_inband ?
389 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
390 SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION,
391 p_params->b_err_big_pkt ?
392 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
393 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME,
394 p_params->b_err_ctrl_frame ?
395 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
396 p_ramrod->tx_err_behav.values = OSAL_CPU_TO_LE16(tx_err);
398 /* TPA related fields */
399 OSAL_MEMSET(&p_ramrod->tpa_param, 0,
400 sizeof(struct eth_vport_tpa_param));
401 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
403 switch (p_params->tpa_mode) {
404 case ECORE_TPA_MODE_GRO:
405 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
406 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
407 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
408 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
409 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
410 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
411 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
412 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
413 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
414 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
420 p_ramrod->tx_switching_en = p_params->tx_switching;
422 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
423 p_ramrod->tx_switching_en = 0;
426 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
427 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
429 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
430 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
431 p_params->concrete_fid);
433 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
437 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
438 struct ecore_sp_vport_start_params *p_params)
440 if (IS_VF(p_hwfn->p_dev))
441 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
443 p_params->remove_inner_vlan,
445 p_params->max_buffers_per_cqe,
446 p_params->only_untagged);
448 return ecore_sp_eth_vport_start(p_hwfn, p_params);
451 static enum _ecore_status_t
452 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
453 struct vport_update_ramrod_data *p_ramrod,
454 struct ecore_rss_params *p_rss)
456 struct eth_vport_rss_config *p_config;
458 enum _ecore_status_t rc = ECORE_SUCCESS;
461 p_ramrod->common.update_rss_flg = 0;
464 p_config = &p_ramrod->rss_config;
466 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
467 ETH_RSS_IND_TABLE_ENTRIES_NUM);
469 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
470 if (rc != ECORE_SUCCESS)
473 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
474 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
475 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
476 p_config->update_rss_key = p_rss->update_rss_key;
478 p_config->rss_mode = p_rss->rss_enable ?
479 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
481 p_config->capabilities = 0;
483 SET_FIELD(p_config->capabilities,
484 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
485 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
486 SET_FIELD(p_config->capabilities,
487 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
488 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
489 SET_FIELD(p_config->capabilities,
490 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
491 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
492 SET_FIELD(p_config->capabilities,
493 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
494 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
495 SET_FIELD(p_config->capabilities,
496 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
497 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
498 SET_FIELD(p_config->capabilities,
499 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
500 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
501 p_config->tbl_size = p_rss->rss_table_size_log;
502 p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
504 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
505 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
506 p_ramrod->common.update_rss_flg,
508 p_config->update_rss_capabilities,
509 p_config->capabilities,
510 p_config->update_rss_ind_table, p_config->update_rss_key);
512 table_size = OSAL_MIN_T(int, ECORE_RSS_IND_TABLE_SIZE,
513 1 << p_config->tbl_size);
514 for (i = 0; i < table_size; i++) {
515 struct ecore_queue_cid *p_queue = p_rss->rss_ind_table[i];
520 p_config->indirection_table[i] =
521 OSAL_CPU_TO_LE16(p_queue->abs.queue_id);
524 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
525 "Configured RSS indirection table [%d entries]:\n",
527 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i += 0x10) {
528 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
529 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
530 OSAL_LE16_TO_CPU(p_config->indirection_table[i]),
531 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 1]),
532 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 2]),
533 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 3]),
534 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 4]),
535 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 5]),
536 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 6]),
537 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 7]),
538 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 8]),
539 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 9]),
540 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 10]),
541 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 11]),
542 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 12]),
543 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 13]),
544 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 14]),
545 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 15]));
548 for (i = 0; i < 10; i++)
549 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
555 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
556 struct vport_update_ramrod_data *p_ramrod,
557 struct ecore_filter_accept_flags accept_flags)
559 p_ramrod->common.update_rx_mode_flg =
560 accept_flags.update_rx_mode_config;
561 p_ramrod->common.update_tx_mode_flg =
562 accept_flags.update_tx_mode_config;
565 /* On B0 emulation we cannot enable Tx, since this would cause writes
566 * to PVFC HW block which isn't implemented in emulation.
568 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
569 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
570 "Non-Asic - prevent Tx mode in vport update\n");
571 p_ramrod->common.update_tx_mode_flg = 0;
575 /* Set Rx mode accept flags */
576 if (p_ramrod->common.update_rx_mode_flg) {
577 u8 accept_filter = accept_flags.rx_accept_filter;
580 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
581 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
582 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
584 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
585 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
587 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
588 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
589 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
591 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
592 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
593 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
595 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
596 !!(accept_filter & ECORE_ACCEPT_BCAST));
598 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
599 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
600 "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n",
601 p_ramrod->common.vport_id, state);
604 /* Set Tx mode accept flags */
605 if (p_ramrod->common.update_tx_mode_flg) {
606 u8 accept_filter = accept_flags.tx_accept_filter;
609 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
610 !!(accept_filter & ECORE_ACCEPT_NONE));
612 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
613 !!(accept_filter & ECORE_ACCEPT_NONE));
615 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
616 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
617 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
619 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
620 !!(accept_filter & ECORE_ACCEPT_BCAST));
622 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
623 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
624 "vport[%02x] p_ramrod->tx_mode.state = 0x%x\n",
625 p_ramrod->common.vport_id, state);
630 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
631 struct vport_update_ramrod_data *p_ramrod,
632 struct ecore_sge_tpa_params *p_params)
634 struct eth_vport_tpa_param *p_tpa;
637 p_ramrod->common.update_tpa_param_flg = 0;
638 p_ramrod->common.update_tpa_en_flg = 0;
639 p_ramrod->common.update_tpa_param_flg = 0;
643 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
644 p_tpa = &p_ramrod->tpa_param;
645 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
646 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
647 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
648 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
650 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
651 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
652 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
653 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
654 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
655 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
656 p_tpa->tpa_max_size = p_params->tpa_max_size;
657 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
658 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
662 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
663 struct vport_update_ramrod_data *p_ramrod,
664 struct ecore_sp_vport_update_params *p_params)
668 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
669 sizeof(p_ramrod->approx_mcast.bins));
671 if (!p_params->update_approx_mcast_flg)
674 p_ramrod->common.update_approx_mcast_flg = 1;
675 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
676 u32 *p_bins = (u32 *)p_params->bins;
678 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
683 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
684 struct ecore_sp_vport_update_params *p_params,
685 enum spq_mode comp_mode,
686 struct ecore_spq_comp_cb *p_comp_data)
688 struct ecore_rss_params *p_rss_params = p_params->rss_params;
689 struct vport_update_ramrod_data_cmn *p_cmn;
690 struct ecore_sp_init_data init_data;
691 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
692 struct ecore_spq_entry *p_ent = OSAL_NULL;
693 u8 abs_vport_id = 0, val;
694 enum _ecore_status_t rc = ECORE_NOTIMPL;
696 if (IS_VF(p_hwfn->p_dev)) {
697 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
701 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
702 if (rc != ECORE_SUCCESS)
706 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
707 init_data.cid = ecore_spq_get_cid(p_hwfn);
708 init_data.opaque_fid = p_params->opaque_fid;
709 init_data.comp_mode = comp_mode;
710 init_data.p_comp_data = p_comp_data;
712 rc = ecore_sp_init_request(p_hwfn, &p_ent,
713 ETH_RAMROD_VPORT_UPDATE,
714 PROTOCOLID_ETH, &init_data);
715 if (rc != ECORE_SUCCESS)
718 /* Copy input params to ramrod according to FW struct */
719 p_ramrod = &p_ent->ramrod.vport_update;
720 p_cmn = &p_ramrod->common;
722 p_cmn->vport_id = abs_vport_id;
724 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
725 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
726 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
727 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
729 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
730 val = p_params->update_accept_any_vlan_flg;
731 p_cmn->update_accept_any_vlan_flg = val;
733 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
734 val = p_params->update_inner_vlan_removal_flg;
735 p_cmn->update_inner_vlan_removal_en_flg = val;
737 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
738 val = p_params->update_default_vlan_enable_flg;
739 p_cmn->update_default_vlan_en_flg = val;
741 p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
742 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
744 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
746 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
749 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
750 if (p_ramrod->common.tx_switching_en ||
751 p_ramrod->common.update_tx_switching_en_flg) {
752 DP_NOTICE(p_hwfn, false,
753 "FPGA - why are we seeing tx-switching? Overriding it\n");
754 p_ramrod->common.tx_switching_en = 0;
755 p_ramrod->common.update_tx_switching_en_flg = 1;
758 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
760 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
761 val = p_params->update_anti_spoofing_en_flg;
762 p_ramrod->common.update_anti_spoofing_en_flg = val;
764 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
765 if (rc != ECORE_SUCCESS) {
766 /* Return spq entry which is taken in ecore_sp_init_request()*/
767 ecore_spq_return_entry(p_hwfn, p_ent);
771 /* Update mcast bins for VFs, PF doesn't use this functionality */
772 ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
774 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
775 ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
776 p_params->sge_tpa_params);
778 p_ramrod->common.update_mtu_flg = 1;
779 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
782 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
785 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
786 u16 opaque_fid, u8 vport_id)
788 struct vport_stop_ramrod_data *p_ramrod;
789 struct ecore_sp_init_data init_data;
790 struct ecore_spq_entry *p_ent;
792 enum _ecore_status_t rc;
794 if (IS_VF(p_hwfn->p_dev))
795 return ecore_vf_pf_vport_stop(p_hwfn);
797 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
798 if (rc != ECORE_SUCCESS)
802 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
803 init_data.cid = ecore_spq_get_cid(p_hwfn);
804 init_data.opaque_fid = opaque_fid;
805 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
807 rc = ecore_sp_init_request(p_hwfn, &p_ent,
808 ETH_RAMROD_VPORT_STOP,
809 PROTOCOLID_ETH, &init_data);
810 if (rc != ECORE_SUCCESS)
813 p_ramrod = &p_ent->ramrod.vport_stop;
814 p_ramrod->vport_id = abs_vport_id;
816 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
819 static enum _ecore_status_t
820 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
821 struct ecore_filter_accept_flags *p_accept_flags)
823 struct ecore_sp_vport_update_params s_params;
825 OSAL_MEMSET(&s_params, 0, sizeof(s_params));
826 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
827 sizeof(struct ecore_filter_accept_flags));
829 return ecore_vf_pf_vport_update(p_hwfn, &s_params);
833 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
835 struct ecore_filter_accept_flags accept_flags,
836 u8 update_accept_any_vlan,
838 enum spq_mode comp_mode,
839 struct ecore_spq_comp_cb *p_comp_data)
841 struct ecore_sp_vport_update_params vport_update_params;
844 /* Prepare and send the vport rx_mode change */
845 OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
846 vport_update_params.vport_id = vport;
847 vport_update_params.accept_flags = accept_flags;
848 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
849 vport_update_params.accept_any_vlan = accept_any_vlan;
851 for_each_hwfn(p_dev, i) {
852 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
854 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
857 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
858 if (rc != ECORE_SUCCESS)
863 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
864 comp_mode, p_comp_data);
865 if (rc != ECORE_SUCCESS) {
866 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
870 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
871 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
872 accept_flags.rx_accept_filter,
873 accept_flags.tx_accept_filter);
875 if (update_accept_any_vlan)
876 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
877 "accept_any_vlan=%d configured\n",
885 ecore_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
886 struct ecore_queue_cid *p_cid,
888 dma_addr_t bd_chain_phys_addr,
889 dma_addr_t cqe_pbl_addr,
892 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
893 struct ecore_spq_entry *p_ent = OSAL_NULL;
894 struct ecore_sp_init_data init_data;
895 enum _ecore_status_t rc = ECORE_NOTIMPL;
897 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
898 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
899 p_cid->opaque_fid, p_cid->cid, p_cid->abs.queue_id,
900 p_cid->abs.vport_id, p_cid->abs.sb);
903 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
904 init_data.cid = p_cid->cid;
905 init_data.opaque_fid = p_cid->opaque_fid;
906 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
908 rc = ecore_sp_init_request(p_hwfn, &p_ent,
909 ETH_RAMROD_RX_QUEUE_START,
910 PROTOCOLID_ETH, &init_data);
911 if (rc != ECORE_SUCCESS)
914 p_ramrod = &p_ent->ramrod.rx_queue_start;
916 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->abs.sb);
917 p_ramrod->sb_index = p_cid->abs.sb_idx;
918 p_ramrod->vport_id = p_cid->abs.vport_id;
919 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
920 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
921 p_ramrod->complete_cqe_flg = 0;
922 p_ramrod->complete_event_flg = 1;
924 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
925 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
927 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
928 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
930 if (p_cid->vfid != ECORE_QUEUE_CID_PF) {
931 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
932 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
933 "Queue%s is meant for VF rxq[%02x]\n",
934 !!p_cid->b_legacy_vf ? " [legacy]" : "",
936 p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
939 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
942 static enum _ecore_status_t
943 ecore_eth_pf_rx_queue_start(struct ecore_hwfn *p_hwfn,
944 struct ecore_queue_cid *p_cid,
946 dma_addr_t bd_chain_phys_addr,
947 dma_addr_t cqe_pbl_addr,
949 void OSAL_IOMEM * *pp_prod)
951 u32 init_prod_val = 0;
953 *pp_prod = (u8 OSAL_IOMEM *)
955 GTT_BAR0_MAP_REG_MSDM_RAM +
956 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
958 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
959 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
960 (u32 *)(&init_prod_val));
962 return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid,
965 cqe_pbl_addr, cqe_pbl_size);
969 ecore_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
971 struct ecore_queue_start_common_params *p_params,
973 dma_addr_t bd_chain_phys_addr,
974 dma_addr_t cqe_pbl_addr,
976 struct ecore_rxq_start_ret_params *p_ret_params)
978 struct ecore_queue_cid *p_cid;
979 enum _ecore_status_t rc;
981 /* Allocate a CID for the queue */
982 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
983 if (p_cid == OSAL_NULL)
986 if (IS_PF(p_hwfn->p_dev))
987 rc = ecore_eth_pf_rx_queue_start(p_hwfn, p_cid,
990 cqe_pbl_addr, cqe_pbl_size,
991 &p_ret_params->p_prod);
993 rc = ecore_vf_pf_rxq_start(p_hwfn, p_cid,
998 &p_ret_params->p_prod);
1000 /* Provide the caller with a reference to as handler */
1001 if (rc != ECORE_SUCCESS)
1002 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1004 p_ret_params->p_handle = (void *)p_cid;
1009 enum _ecore_status_t
1010 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
1011 void **pp_rxq_handles,
1013 u8 complete_cqe_flg,
1014 u8 complete_event_flg,
1015 enum spq_mode comp_mode,
1016 struct ecore_spq_comp_cb *p_comp_data)
1018 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
1019 struct ecore_spq_entry *p_ent = OSAL_NULL;
1020 struct ecore_sp_init_data init_data;
1021 struct ecore_queue_cid *p_cid;
1022 enum _ecore_status_t rc = ECORE_NOTIMPL;
1025 if (IS_VF(p_hwfn->p_dev))
1026 return ecore_vf_pf_rxqs_update(p_hwfn,
1027 (struct ecore_queue_cid **)
1031 complete_event_flg);
1033 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1034 init_data.comp_mode = comp_mode;
1035 init_data.p_comp_data = p_comp_data;
1037 for (i = 0; i < num_rxqs; i++) {
1038 p_cid = ((struct ecore_queue_cid **)pp_rxq_handles)[i];
1041 init_data.cid = p_cid->cid;
1042 init_data.opaque_fid = p_cid->opaque_fid;
1044 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1045 ETH_RAMROD_RX_QUEUE_UPDATE,
1046 PROTOCOLID_ETH, &init_data);
1047 if (rc != ECORE_SUCCESS)
1050 p_ramrod = &p_ent->ramrod.rx_queue_update;
1051 p_ramrod->vport_id = p_cid->abs.vport_id;
1053 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1054 p_ramrod->complete_cqe_flg = complete_cqe_flg;
1055 p_ramrod->complete_event_flg = complete_event_flg;
1057 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1058 if (rc != ECORE_SUCCESS)
1065 static enum _ecore_status_t
1066 ecore_eth_pf_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1067 struct ecore_queue_cid *p_cid,
1068 bool b_eq_completion_only,
1069 bool b_cqe_completion)
1071 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
1072 struct ecore_spq_entry *p_ent = OSAL_NULL;
1073 struct ecore_sp_init_data init_data;
1074 enum _ecore_status_t rc;
1076 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1077 init_data.cid = p_cid->cid;
1078 init_data.opaque_fid = p_cid->opaque_fid;
1079 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1081 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1082 ETH_RAMROD_RX_QUEUE_STOP,
1083 PROTOCOLID_ETH, &init_data);
1084 if (rc != ECORE_SUCCESS)
1087 p_ramrod = &p_ent->ramrod.rx_queue_stop;
1088 p_ramrod->vport_id = p_cid->abs.vport_id;
1089 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1091 /* Cleaning the queue requires the completion to arrive there.
1092 * In addition, VFs require the answer to come as eqe to PF.
1094 p_ramrod->complete_cqe_flg = ((p_cid->vfid == ECORE_QUEUE_CID_PF) &&
1095 !b_eq_completion_only) ||
1097 p_ramrod->complete_event_flg = (p_cid->vfid != ECORE_QUEUE_CID_PF) ||
1098 b_eq_completion_only;
1100 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1103 enum _ecore_status_t ecore_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1105 bool eq_completion_only,
1106 bool cqe_completion)
1108 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_rxq;
1109 enum _ecore_status_t rc = ECORE_NOTIMPL;
1111 if (IS_PF(p_hwfn->p_dev))
1112 rc = ecore_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1116 rc = ecore_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1118 if (rc == ECORE_SUCCESS)
1119 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1123 enum _ecore_status_t
1124 ecore_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
1125 struct ecore_queue_cid *p_cid,
1126 dma_addr_t pbl_addr, u16 pbl_size,
1129 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
1130 struct ecore_spq_entry *p_ent = OSAL_NULL;
1131 struct ecore_sp_init_data init_data;
1132 enum _ecore_status_t rc = ECORE_NOTIMPL;
1135 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1136 init_data.cid = p_cid->cid;
1137 init_data.opaque_fid = p_cid->opaque_fid;
1138 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1140 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1141 ETH_RAMROD_TX_QUEUE_START,
1142 PROTOCOLID_ETH, &init_data);
1143 if (rc != ECORE_SUCCESS)
1146 p_ramrod = &p_ent->ramrod.tx_queue_start;
1147 p_ramrod->vport_id = p_cid->abs.vport_id;
1149 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->abs.sb);
1150 p_ramrod->sb_index = p_cid->abs.sb_idx;
1151 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
1153 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1154 p_ramrod->same_as_last_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1156 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
1157 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
1159 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
1161 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1164 static enum _ecore_status_t
1165 ecore_eth_pf_tx_queue_start(struct ecore_hwfn *p_hwfn,
1166 struct ecore_queue_cid *p_cid,
1168 dma_addr_t pbl_addr, u16 pbl_size,
1169 void OSAL_IOMEM * *pp_doorbell)
1171 enum _ecore_status_t rc;
1173 /* TODO - set tc in the pq_params for multi-cos */
1174 rc = ecore_eth_txq_start_ramrod(p_hwfn, p_cid,
1176 ecore_get_cm_pq_idx_mcos(p_hwfn, tc));
1177 if (rc != ECORE_SUCCESS)
1180 /* Provide the caller with the necessary return values */
1181 *pp_doorbell = (u8 OSAL_IOMEM *)
1183 DB_ADDR(p_cid->cid, DQ_DEMS_LEGACY);
1185 return ECORE_SUCCESS;
1188 enum _ecore_status_t
1189 ecore_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
1190 struct ecore_queue_start_common_params *p_params,
1192 dma_addr_t pbl_addr, u16 pbl_size,
1193 struct ecore_txq_start_ret_params *p_ret_params)
1195 struct ecore_queue_cid *p_cid;
1196 enum _ecore_status_t rc;
1198 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
1199 if (p_cid == OSAL_NULL)
1202 if (IS_PF(p_hwfn->p_dev))
1203 rc = ecore_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1205 &p_ret_params->p_doorbell);
1207 rc = ecore_vf_pf_txq_start(p_hwfn, p_cid,
1209 &p_ret_params->p_doorbell);
1211 if (rc != ECORE_SUCCESS)
1212 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1214 p_ret_params->p_handle = (void *)p_cid;
1219 static enum _ecore_status_t
1220 ecore_eth_pf_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1221 struct ecore_queue_cid *p_cid)
1223 struct ecore_spq_entry *p_ent = OSAL_NULL;
1224 struct ecore_sp_init_data init_data;
1225 enum _ecore_status_t rc;
1227 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1228 init_data.cid = p_cid->cid;
1229 init_data.opaque_fid = p_cid->opaque_fid;
1230 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1232 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1233 ETH_RAMROD_TX_QUEUE_STOP,
1234 PROTOCOLID_ETH, &init_data);
1235 if (rc != ECORE_SUCCESS)
1238 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1241 enum _ecore_status_t ecore_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1244 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
1245 enum _ecore_status_t rc;
1247 if (IS_PF(p_hwfn->p_dev))
1248 rc = ecore_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1250 rc = ecore_vf_pf_txq_stop(p_hwfn, p_cid);
1252 if (rc == ECORE_SUCCESS)
1253 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1257 static enum eth_filter_action
1258 ecore_filter_action(enum ecore_filter_opcode opcode)
1260 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1263 case ECORE_FILTER_ADD:
1264 action = ETH_FILTER_ACTION_ADD;
1266 case ECORE_FILTER_REMOVE:
1267 action = ETH_FILTER_ACTION_REMOVE;
1269 case ECORE_FILTER_FLUSH:
1270 action = ETH_FILTER_ACTION_REMOVE_ALL;
1273 action = MAX_ETH_FILTER_ACTION;
1279 static enum _ecore_status_t
1280 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1282 struct ecore_filter_ucast *p_filter_cmd,
1283 struct vport_filter_update_ramrod_data **pp_ramrod,
1284 struct ecore_spq_entry **pp_ent,
1285 enum spq_mode comp_mode,
1286 struct ecore_spq_comp_cb *p_comp_data)
1288 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1289 struct vport_filter_update_ramrod_data *p_ramrod;
1290 struct eth_filter_cmd *p_first_filter;
1291 struct eth_filter_cmd *p_second_filter;
1292 struct ecore_sp_init_data init_data;
1293 enum eth_filter_action action;
1294 enum _ecore_status_t rc;
1296 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1297 &vport_to_remove_from);
1298 if (rc != ECORE_SUCCESS)
1301 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1303 if (rc != ECORE_SUCCESS)
1307 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1308 init_data.cid = ecore_spq_get_cid(p_hwfn);
1309 init_data.opaque_fid = opaque_fid;
1310 init_data.comp_mode = comp_mode;
1311 init_data.p_comp_data = p_comp_data;
1313 rc = ecore_sp_init_request(p_hwfn, pp_ent,
1314 ETH_RAMROD_FILTERS_UPDATE,
1315 PROTOCOLID_ETH, &init_data);
1316 if (rc != ECORE_SUCCESS)
1319 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1320 p_ramrod = *pp_ramrod;
1321 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1322 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1325 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1326 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1327 "Non-Asic - prevent Tx filters\n");
1328 p_ramrod->filter_cmd_hdr.tx = 0;
1332 switch (p_filter_cmd->opcode) {
1333 case ECORE_FILTER_REPLACE:
1334 case ECORE_FILTER_MOVE:
1335 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1338 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1342 p_first_filter = &p_ramrod->filter_cmds[0];
1343 p_second_filter = &p_ramrod->filter_cmds[1];
1345 switch (p_filter_cmd->type) {
1346 case ECORE_FILTER_MAC:
1347 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1349 case ECORE_FILTER_VLAN:
1350 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1352 case ECORE_FILTER_MAC_VLAN:
1353 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1355 case ECORE_FILTER_INNER_MAC:
1356 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1358 case ECORE_FILTER_INNER_VLAN:
1359 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1361 case ECORE_FILTER_INNER_PAIR:
1362 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1364 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1365 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1367 case ECORE_FILTER_MAC_VNI_PAIR:
1368 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1370 case ECORE_FILTER_VNI:
1371 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1373 case ECORE_FILTER_UNUSED: /* @DPDK */
1374 p_first_filter->type = MAX_ETH_FILTER_TYPE;
1378 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1379 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1380 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1381 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1382 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1383 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1384 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1385 &p_first_filter->mac_mid,
1386 &p_first_filter->mac_lsb,
1387 (u8 *)p_filter_cmd->mac);
1389 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1390 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1391 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1392 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1393 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1395 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1396 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1397 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1398 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1400 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1401 p_second_filter->type = p_first_filter->type;
1402 p_second_filter->mac_msb = p_first_filter->mac_msb;
1403 p_second_filter->mac_mid = p_first_filter->mac_mid;
1404 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1405 p_second_filter->vlan_id = p_first_filter->vlan_id;
1406 p_second_filter->vni = p_first_filter->vni;
1408 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1410 p_first_filter->vport_id = vport_to_remove_from;
1412 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1413 p_second_filter->vport_id = vport_to_add_to;
1414 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1415 p_first_filter->vport_id = vport_to_add_to;
1416 OSAL_MEMCPY(p_second_filter, p_first_filter,
1417 sizeof(*p_second_filter));
1418 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1419 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1421 action = ecore_filter_action(p_filter_cmd->opcode);
1423 if (action == MAX_ETH_FILTER_ACTION) {
1424 DP_NOTICE(p_hwfn, true,
1425 "%d is not supported yet\n",
1426 p_filter_cmd->opcode);
1427 return ECORE_NOTIMPL;
1430 p_first_filter->action = action;
1431 p_first_filter->vport_id =
1432 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1433 vport_to_remove_from : vport_to_add_to;
1436 return ECORE_SUCCESS;
1439 enum _ecore_status_t
1440 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1442 struct ecore_filter_ucast *p_filter_cmd,
1443 enum spq_mode comp_mode,
1444 struct ecore_spq_comp_cb *p_comp_data)
1446 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1447 struct ecore_spq_entry *p_ent = OSAL_NULL;
1448 struct eth_filter_cmd_header *p_header;
1449 enum _ecore_status_t rc;
1451 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1453 comp_mode, p_comp_data);
1454 if (rc != ECORE_SUCCESS) {
1455 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1458 p_header = &p_ramrod->filter_cmd_hdr;
1459 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1461 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1462 if (rc != ECORE_SUCCESS) {
1463 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1467 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1468 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1469 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1470 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1472 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1473 "MOVE" : "REPLACE")),
1474 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1475 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1476 "VLAN" : "MAC & VLAN"),
1477 p_ramrod->filter_cmd_hdr.cmd_cnt,
1478 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1479 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1480 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1481 p_filter_cmd->vport_to_add_to,
1482 p_filter_cmd->vport_to_remove_from,
1483 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1484 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1485 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1486 p_filter_cmd->vlan);
1488 return ECORE_SUCCESS;
1491 /*******************************************************************************
1493 * Calculates crc 32 on a buffer
1494 * Note: crc32_length MUST be aligned to 8
1496 ******************************************************************************/
1497 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1498 u32 crc32_length, u32 crc32_seed, u8 complement)
1500 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1501 u8 msb = 0, current_byte = 0;
1503 if ((crc32_packet == OSAL_NULL) ||
1504 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1505 return crc32_result;
1508 for (byte = 0; byte < crc32_length; byte++) {
1509 current_byte = crc32_packet[byte];
1510 for (bit = 0; bit < 8; bit++) {
1511 msb = (u8)(crc32_result >> 31);
1512 crc32_result = crc32_result << 1;
1513 if (msb != (0x1 & (current_byte >> bit))) {
1514 crc32_result = crc32_result ^ CRC32_POLY;
1520 return crc32_result;
1523 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1525 u32 packet_buf[2] = { 0 };
1527 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1528 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1531 u8 ecore_mcast_bin_from_mac(u8 *mac)
1533 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1539 static enum _ecore_status_t
1540 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1542 struct ecore_filter_mcast *p_filter_cmd,
1543 enum spq_mode comp_mode,
1544 struct ecore_spq_comp_cb *p_comp_data)
1546 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1547 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1548 struct ecore_spq_entry *p_ent = OSAL_NULL;
1549 struct ecore_sp_init_data init_data;
1550 u8 abs_vport_id = 0;
1551 enum _ecore_status_t rc;
1554 if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1555 rc = ecore_fw_vport(p_hwfn,
1556 p_filter_cmd->vport_to_add_to,
1559 rc = ecore_fw_vport(p_hwfn,
1560 p_filter_cmd->vport_to_remove_from,
1562 if (rc != ECORE_SUCCESS)
1566 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1567 init_data.cid = ecore_spq_get_cid(p_hwfn);
1568 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1569 init_data.comp_mode = comp_mode;
1570 init_data.p_comp_data = p_comp_data;
1572 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1573 ETH_RAMROD_VPORT_UPDATE,
1574 PROTOCOLID_ETH, &init_data);
1575 if (rc != ECORE_SUCCESS) {
1576 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1580 p_ramrod = &p_ent->ramrod.vport_update;
1581 p_ramrod->common.update_approx_mcast_flg = 1;
1583 /* explicitly clear out the entire vector */
1584 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1585 0, sizeof(p_ramrod->approx_mcast.bins));
1586 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1587 ETH_MULTICAST_MAC_BINS_IN_REGS);
1588 /* filter ADD op is explicit set op and it removes
1589 * any existing filters for the vport.
1591 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1592 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1595 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1596 OSAL_SET_BIT(bit, bins);
1599 /* Convert to correct endianity */
1600 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1601 struct vport_update_ramrod_mcast *p_ramrod_bins;
1602 u32 *p_bins = (u32 *)bins;
1604 p_ramrod_bins = &p_ramrod->approx_mcast;
1605 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1609 p_ramrod->common.vport_id = abs_vport_id;
1611 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1612 if (rc != ECORE_SUCCESS)
1613 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1618 enum _ecore_status_t
1619 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1620 struct ecore_filter_mcast *p_filter_cmd,
1621 enum spq_mode comp_mode,
1622 struct ecore_spq_comp_cb *p_comp_data)
1624 enum _ecore_status_t rc = ECORE_SUCCESS;
1627 /* only ADD and REMOVE operations are supported for multi-cast */
1628 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1629 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1630 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1634 for_each_hwfn(p_dev, i) {
1635 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1639 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1643 opaque_fid = p_hwfn->hw_info.opaque_fid;
1644 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1647 comp_mode, p_comp_data);
1648 if (rc != ECORE_SUCCESS)
1655 enum _ecore_status_t
1656 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1657 struct ecore_filter_ucast *p_filter_cmd,
1658 enum spq_mode comp_mode,
1659 struct ecore_spq_comp_cb *p_comp_data)
1661 enum _ecore_status_t rc = ECORE_SUCCESS;
1664 for_each_hwfn(p_dev, i) {
1665 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1669 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1673 opaque_fid = p_hwfn->hw_info.opaque_fid;
1674 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1677 comp_mode, p_comp_data);
1678 if (rc != ECORE_SUCCESS)
1685 /* Statistics related code */
1686 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1687 u32 *p_addr, u32 *p_len,
1690 if (IS_PF(p_hwfn->p_dev)) {
1691 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1692 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1693 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1695 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1696 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1698 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1699 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1703 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1704 struct ecore_ptt *p_ptt,
1705 struct ecore_eth_stats *p_stats,
1708 struct eth_pstorm_per_queue_stat pstats;
1709 u32 pstats_addr = 0, pstats_len = 0;
1711 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1714 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1715 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1717 p_stats->common.tx_ucast_bytes +=
1718 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1719 p_stats->common.tx_mcast_bytes +=
1720 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1721 p_stats->common.tx_bcast_bytes +=
1722 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1723 p_stats->common.tx_ucast_pkts +=
1724 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1725 p_stats->common.tx_mcast_pkts +=
1726 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1727 p_stats->common.tx_bcast_pkts +=
1728 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1729 p_stats->common.tx_err_drop_pkts +=
1730 HILO_64_REGPAIR(pstats.error_drop_pkts);
1733 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1734 struct ecore_ptt *p_ptt,
1735 struct ecore_eth_stats *p_stats,
1738 struct tstorm_per_port_stat tstats;
1739 u32 tstats_addr, tstats_len;
1741 if (IS_PF(p_hwfn->p_dev)) {
1742 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1743 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1744 tstats_len = sizeof(struct tstorm_per_port_stat);
1746 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1747 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1749 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1750 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1753 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1754 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1756 p_stats->common.mftag_filter_discards +=
1757 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1758 p_stats->common.mac_filter_discards +=
1759 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1762 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1763 u32 *p_addr, u32 *p_len,
1766 if (IS_PF(p_hwfn->p_dev)) {
1767 *p_addr = BAR0_MAP_REG_USDM_RAM +
1768 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1769 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1771 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1772 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1774 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1775 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1779 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1780 struct ecore_ptt *p_ptt,
1781 struct ecore_eth_stats *p_stats,
1784 struct eth_ustorm_per_queue_stat ustats;
1785 u32 ustats_addr = 0, ustats_len = 0;
1787 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1790 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1791 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1793 p_stats->common.rx_ucast_bytes +=
1794 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1795 p_stats->common.rx_mcast_bytes +=
1796 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1797 p_stats->common.rx_bcast_bytes +=
1798 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1799 p_stats->common.rx_ucast_pkts +=
1800 HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1801 p_stats->common.rx_mcast_pkts +=
1802 HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1803 p_stats->common.rx_bcast_pkts +=
1804 HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1807 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1808 u32 *p_addr, u32 *p_len,
1811 if (IS_PF(p_hwfn->p_dev)) {
1812 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1813 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1814 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1816 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1817 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1819 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1820 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1824 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1825 struct ecore_ptt *p_ptt,
1826 struct ecore_eth_stats *p_stats,
1829 struct eth_mstorm_per_queue_stat mstats;
1830 u32 mstats_addr = 0, mstats_len = 0;
1832 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1835 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1836 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1838 p_stats->common.no_buff_discards +=
1839 HILO_64_REGPAIR(mstats.no_buff_discard);
1840 p_stats->common.packet_too_big_discard +=
1841 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1842 p_stats->common.ttl0_discard +=
1843 HILO_64_REGPAIR(mstats.ttl0_discard);
1844 p_stats->common.tpa_coalesced_pkts +=
1845 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1846 p_stats->common.tpa_coalesced_events +=
1847 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1848 p_stats->common.tpa_aborts_num +=
1849 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1850 p_stats->common.tpa_coalesced_bytes +=
1851 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1854 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1855 struct ecore_ptt *p_ptt,
1856 struct ecore_eth_stats *p_stats)
1858 struct ecore_eth_stats_common *p_common = &p_stats->common;
1859 struct port_stats port_stats;
1862 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1864 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1865 p_hwfn->mcp_info->port_addr +
1866 OFFSETOF(struct public_port, stats),
1867 sizeof(port_stats));
1869 p_common->rx_64_byte_packets += port_stats.eth.r64;
1870 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1871 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1872 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1873 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1874 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1875 p_common->rx_crc_errors += port_stats.eth.rfcs;
1876 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1877 p_common->rx_pause_frames += port_stats.eth.rxpf;
1878 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1879 p_common->rx_align_errors += port_stats.eth.raln;
1880 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1881 p_common->rx_oversize_packets += port_stats.eth.rovr;
1882 p_common->rx_jabbers += port_stats.eth.rjbr;
1883 p_common->rx_undersize_packets += port_stats.eth.rund;
1884 p_common->rx_fragments += port_stats.eth.rfrg;
1885 p_common->tx_64_byte_packets += port_stats.eth.t64;
1886 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1887 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1888 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1889 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1890 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1891 p_common->tx_pause_frames += port_stats.eth.txpf;
1892 p_common->tx_pfc_frames += port_stats.eth.txpp;
1893 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1894 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1895 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1896 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1897 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1898 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1899 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1900 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1901 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1902 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
1903 for (j = 0; j < 8; j++) {
1904 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1905 p_common->brb_discards += port_stats.brb.brb_discard[j];
1908 if (ECORE_IS_BB(p_hwfn->p_dev)) {
1909 struct ecore_eth_stats_bb *p_bb = &p_stats->bb;
1911 p_bb->rx_1519_to_1522_byte_packets +=
1912 port_stats.eth.u0.bb0.r1522;
1913 p_bb->rx_1519_to_2047_byte_packets +=
1914 port_stats.eth.u0.bb0.r2047;
1915 p_bb->rx_2048_to_4095_byte_packets +=
1916 port_stats.eth.u0.bb0.r4095;
1917 p_bb->rx_4096_to_9216_byte_packets +=
1918 port_stats.eth.u0.bb0.r9216;
1919 p_bb->rx_9217_to_16383_byte_packets +=
1920 port_stats.eth.u0.bb0.r16383;
1921 p_bb->tx_1519_to_2047_byte_packets +=
1922 port_stats.eth.u1.bb1.t2047;
1923 p_bb->tx_2048_to_4095_byte_packets +=
1924 port_stats.eth.u1.bb1.t4095;
1925 p_bb->tx_4096_to_9216_byte_packets +=
1926 port_stats.eth.u1.bb1.t9216;
1927 p_bb->tx_9217_to_16383_byte_packets +=
1928 port_stats.eth.u1.bb1.t16383;
1929 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1930 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1932 struct ecore_eth_stats_ah *p_ah = &p_stats->ah;
1934 p_ah->rx_1519_to_max_byte_packets +=
1935 port_stats.eth.u0.ah0.r1519_to_max;
1936 p_ah->tx_1519_to_max_byte_packets =
1937 port_stats.eth.u1.ah1.t1519_to_max;
1941 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1942 struct ecore_ptt *p_ptt,
1943 struct ecore_eth_stats *stats,
1944 u16 statistics_bin, bool b_get_port_stats)
1946 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1947 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1948 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1949 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1952 /* Avoid getting PORT stats for emulation. */
1953 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1957 if (b_get_port_stats && p_hwfn->mcp_info)
1958 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1961 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1962 struct ecore_eth_stats *stats)
1967 OSAL_MEMSET(stats, 0, sizeof(*stats));
1969 for_each_hwfn(p_dev, i) {
1970 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1971 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1972 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1975 /* The main vport index is relative first */
1976 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1977 DP_ERR(p_hwfn, "No vport available!\n");
1982 if (IS_PF(p_dev) && !p_ptt) {
1983 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1987 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1988 IS_PF(p_dev) ? true : false);
1991 if (IS_PF(p_dev) && p_ptt)
1992 ecore_ptt_release(p_hwfn, p_ptt);
1996 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1997 struct ecore_eth_stats *stats)
2002 OSAL_MEMSET(stats, 0, sizeof(*stats));
2006 _ecore_get_vport_stats(p_dev, stats);
2008 if (!p_dev->reset_stats)
2011 /* Reduce the statistics baseline */
2012 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
2013 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
2016 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
2017 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
2021 for_each_hwfn(p_dev, i) {
2022 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2023 struct eth_mstorm_per_queue_stat mstats;
2024 struct eth_ustorm_per_queue_stat ustats;
2025 struct eth_pstorm_per_queue_stat pstats;
2026 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
2027 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
2028 u32 addr = 0, len = 0;
2030 if (IS_PF(p_dev) && !p_ptt) {
2031 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
2035 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
2036 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
2037 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
2039 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
2040 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
2041 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
2043 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
2044 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
2045 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
2048 ecore_ptt_release(p_hwfn, p_ptt);
2051 /* PORT statistics are not necessarily reset, so we need to
2052 * read and create a baseline for future statistics.
2054 if (!p_dev->reset_stats)
2055 DP_INFO(p_dev, "Reset stats not allocated\n");
2057 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
2060 void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
2061 struct ecore_ptt *p_ptt,
2062 struct ecore_arfs_config_params *p_cfg_params)
2064 if (p_cfg_params->arfs_enable) {
2065 ecore_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2069 p_cfg_params->ipv6);
2070 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2071 "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
2072 p_cfg_params->tcp ? "Enable" : "Disable",
2073 p_cfg_params->udp ? "Enable" : "Disable",
2074 p_cfg_params->ipv4 ? "Enable" : "Disable",
2075 p_cfg_params->ipv6 ? "Enable" : "Disable");
2077 ecore_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2079 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n",
2080 p_cfg_params->arfs_enable ? "Enable" : "Disable");
2083 enum _ecore_status_t
2084 ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn,
2085 struct ecore_ptt *p_ptt,
2086 struct ecore_spq_comp_cb *p_cb,
2087 dma_addr_t p_addr, u16 length,
2088 u16 qid, u8 vport_id,
2091 struct rx_update_gft_filter_data *p_ramrod = OSAL_NULL;
2092 struct ecore_spq_entry *p_ent = OSAL_NULL;
2093 struct ecore_sp_init_data init_data;
2094 u16 abs_rx_q_id = 0;
2095 u8 abs_vport_id = 0;
2096 enum _ecore_status_t rc = ECORE_NOTIMPL;
2098 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
2099 if (rc != ECORE_SUCCESS)
2102 rc = ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
2103 if (rc != ECORE_SUCCESS)
2107 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
2108 init_data.cid = ecore_spq_get_cid(p_hwfn);
2110 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2113 init_data.comp_mode = ECORE_SPQ_MODE_CB;
2114 init_data.p_comp_data = p_cb;
2116 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
2119 rc = ecore_sp_init_request(p_hwfn, &p_ent,
2120 ETH_RAMROD_GFT_UPDATE_FILTER,
2121 PROTOCOLID_ETH, &init_data);
2122 if (rc != ECORE_SUCCESS)
2125 p_ramrod = &p_ent->ramrod.rx_update_gft;
2127 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
2128 p_ramrod->pkt_hdr_length = OSAL_CPU_TO_LE16(length);
2129 p_ramrod->rx_qid_or_action_icid = OSAL_CPU_TO_LE16(abs_rx_q_id);
2130 p_ramrod->vport_id = abs_vport_id;
2131 p_ramrod->filter_type = RFS_FILTER_TYPE;
2132 p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER
2133 : GFT_DELETE_FILTER;
2135 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2136 "V[%0x], Q[%04x] - %s filter from 0x%lx [length %04xb]\n",
2137 abs_vport_id, abs_rx_q_id,
2138 b_is_add ? "Adding" : "Removing",
2139 (unsigned long)p_addr, length);
2141 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);