2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
26 #include "ecore_sriov.h"
27 #include "ecore_mcp.h"
29 #define ECORE_MAX_SGES_NUM 16
30 #define CRC32_POLY 0x1edc6f41
33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
34 struct ecore_sp_vport_start_params *p_params)
36 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
37 struct ecore_spq_entry *p_ent = OSAL_NULL;
38 struct ecore_sp_init_data init_data;
40 enum _ecore_status_t rc = ECORE_NOTIMPL;
43 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
44 if (rc != ECORE_SUCCESS)
48 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
49 init_data.cid = ecore_spq_get_cid(p_hwfn);
50 init_data.opaque_fid = p_params->opaque_fid;
51 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
53 rc = ecore_sp_init_request(p_hwfn, &p_ent,
54 ETH_RAMROD_VPORT_START,
55 PROTOCOLID_ETH, &init_data);
56 if (rc != ECORE_SUCCESS)
59 p_ramrod = &p_ent->ramrod.vport_start;
60 p_ramrod->vport_id = abs_vport_id;
62 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
63 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
64 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
65 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
66 p_ramrod->untagged = p_params->only_untagged;
67 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
69 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
70 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
72 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
74 /* TPA related fields */
75 OSAL_MEMSET(&p_ramrod->tpa_param, 0,
76 sizeof(struct eth_vport_tpa_param));
77 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
79 switch (p_params->tpa_mode) {
80 case ECORE_TPA_MODE_GRO:
81 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
82 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
83 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
84 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
85 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
86 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
87 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
88 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
89 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
90 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
96 p_ramrod->tx_switching_en = p_params->tx_switching;
98 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
99 p_ramrod->tx_switching_en = 0;
102 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
103 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
105 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
106 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
107 p_params->concrete_fid);
109 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
113 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
114 struct ecore_sp_vport_start_params *p_params)
116 if (IS_VF(p_hwfn->p_dev))
117 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
119 p_params->remove_inner_vlan,
121 p_params->max_buffers_per_cqe,
122 p_params->only_untagged);
124 return ecore_sp_eth_vport_start(p_hwfn, p_params);
127 static enum _ecore_status_t
128 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
129 struct vport_update_ramrod_data *p_ramrod,
130 struct ecore_rss_params *p_rss)
132 enum _ecore_status_t rc = ECORE_SUCCESS;
133 struct eth_vport_rss_config *p_config;
134 u16 abs_l2_queue = 0;
138 p_ramrod->common.update_rss_flg = 0;
141 p_config = &p_ramrod->rss_config;
143 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
144 ETH_RSS_IND_TABLE_ENTRIES_NUM);
146 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
147 if (rc != ECORE_SUCCESS)
150 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
151 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
152 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
153 p_config->update_rss_key = p_rss->update_rss_key;
155 p_config->rss_mode = p_rss->rss_enable ?
156 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
158 p_config->capabilities = 0;
160 SET_FIELD(p_config->capabilities,
161 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
162 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
163 SET_FIELD(p_config->capabilities,
164 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
165 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
166 SET_FIELD(p_config->capabilities,
167 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
168 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
169 SET_FIELD(p_config->capabilities,
170 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
171 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
172 SET_FIELD(p_config->capabilities,
173 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
174 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
175 SET_FIELD(p_config->capabilities,
176 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
177 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
178 p_config->tbl_size = p_rss->rss_table_size_log;
179 p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
181 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
182 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
183 p_ramrod->common.update_rss_flg,
185 p_config->update_rss_capabilities,
186 p_config->capabilities,
187 p_config->update_rss_ind_table, p_config->update_rss_key);
189 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
190 rc = ecore_fw_l2_queue(p_hwfn,
191 (u8)p_rss->rss_ind_table[i],
193 if (rc != ECORE_SUCCESS)
196 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
197 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
198 i, p_config->indirection_table[i]);
201 for (i = 0; i < 10; i++)
202 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
208 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
209 struct vport_update_ramrod_data *p_ramrod,
210 struct ecore_filter_accept_flags accept_flags)
212 p_ramrod->common.update_rx_mode_flg =
213 accept_flags.update_rx_mode_config;
214 p_ramrod->common.update_tx_mode_flg =
215 accept_flags.update_tx_mode_config;
218 /* On B0 emulation we cannot enable Tx, since this would cause writes
219 * to PVFC HW block which isn't implemented in emulation.
221 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
222 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
223 "Non-Asic - prevent Tx mode in vport update\n");
224 p_ramrod->common.update_tx_mode_flg = 0;
228 /* Set Rx mode accept flags */
229 if (p_ramrod->common.update_rx_mode_flg) {
230 u8 accept_filter = accept_flags.rx_accept_filter;
233 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
234 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
235 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
237 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
238 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
240 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
241 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
242 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
244 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
245 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
246 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
248 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
249 !!(accept_filter & ECORE_ACCEPT_BCAST));
251 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
252 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
253 "p_ramrod->rx_mode.state = 0x%x\n",
257 /* Set Tx mode accept flags */
258 if (p_ramrod->common.update_tx_mode_flg) {
259 u8 accept_filter = accept_flags.tx_accept_filter;
262 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
263 !!(accept_filter & ECORE_ACCEPT_NONE));
265 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
266 !!(accept_filter & ECORE_ACCEPT_NONE));
268 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
269 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
270 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
272 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
273 !!(accept_filter & ECORE_ACCEPT_BCAST));
275 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
276 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
277 "p_ramrod->tx_mode.state = 0x%x\n",
283 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
284 struct vport_update_ramrod_data *p_ramrod,
285 struct ecore_sge_tpa_params *p_params)
287 struct eth_vport_tpa_param *p_tpa;
290 p_ramrod->common.update_tpa_param_flg = 0;
291 p_ramrod->common.update_tpa_en_flg = 0;
292 p_ramrod->common.update_tpa_param_flg = 0;
296 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
297 p_tpa = &p_ramrod->tpa_param;
298 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
299 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
300 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
301 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
303 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
304 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
305 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
306 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
307 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
308 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
309 p_tpa->tpa_max_size = p_params->tpa_max_size;
310 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
311 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
315 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
316 struct vport_update_ramrod_data *p_ramrod,
317 struct ecore_sp_vport_update_params *p_params)
321 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
322 sizeof(p_ramrod->approx_mcast.bins));
324 if (!p_params->update_approx_mcast_flg)
327 p_ramrod->common.update_approx_mcast_flg = 1;
328 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
329 u32 *p_bins = (u32 *)p_params->bins;
331 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
336 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
337 struct ecore_sp_vport_update_params *p_params,
338 enum spq_mode comp_mode,
339 struct ecore_spq_comp_cb *p_comp_data)
341 struct ecore_rss_params *p_rss_params = p_params->rss_params;
342 struct vport_update_ramrod_data_cmn *p_cmn;
343 struct ecore_sp_init_data init_data;
344 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
345 struct ecore_spq_entry *p_ent = OSAL_NULL;
346 u8 abs_vport_id = 0, val;
347 enum _ecore_status_t rc = ECORE_NOTIMPL;
349 if (IS_VF(p_hwfn->p_dev)) {
350 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
354 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
355 if (rc != ECORE_SUCCESS)
359 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
360 init_data.cid = ecore_spq_get_cid(p_hwfn);
361 init_data.opaque_fid = p_params->opaque_fid;
362 init_data.comp_mode = comp_mode;
363 init_data.p_comp_data = p_comp_data;
365 rc = ecore_sp_init_request(p_hwfn, &p_ent,
366 ETH_RAMROD_VPORT_UPDATE,
367 PROTOCOLID_ETH, &init_data);
368 if (rc != ECORE_SUCCESS)
371 /* Copy input params to ramrod according to FW struct */
372 p_ramrod = &p_ent->ramrod.vport_update;
373 p_cmn = &p_ramrod->common;
375 p_cmn->vport_id = abs_vport_id;
377 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
378 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
379 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
380 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
382 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
383 val = p_params->update_accept_any_vlan_flg;
384 p_cmn->update_accept_any_vlan_flg = val;
386 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
387 val = p_params->update_inner_vlan_removal_flg;
388 p_cmn->update_inner_vlan_removal_en_flg = val;
390 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
391 val = p_params->update_default_vlan_enable_flg;
392 p_cmn->update_default_vlan_en_flg = val;
394 p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
395 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
397 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
399 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
402 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
403 if (p_ramrod->common.tx_switching_en ||
404 p_ramrod->common.update_tx_switching_en_flg) {
405 DP_NOTICE(p_hwfn, false,
406 "FPGA - why are we seeing tx-switching? Overriding it\n");
407 p_ramrod->common.tx_switching_en = 0;
408 p_ramrod->common.update_tx_switching_en_flg = 1;
411 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
413 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
414 val = p_params->update_anti_spoofing_en_flg;
415 p_ramrod->common.update_anti_spoofing_en_flg = val;
417 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
418 if (rc != ECORE_SUCCESS) {
419 /* Return spq entry which is taken in ecore_sp_init_request()*/
420 ecore_spq_return_entry(p_hwfn, p_ent);
424 /* Update mcast bins for VFs, PF doesn't use this functionality */
425 ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
427 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
428 ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
429 p_params->sge_tpa_params);
430 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
433 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
434 u16 opaque_fid, u8 vport_id)
436 struct vport_stop_ramrod_data *p_ramrod;
437 struct ecore_sp_init_data init_data;
438 struct ecore_spq_entry *p_ent;
440 enum _ecore_status_t rc;
442 if (IS_VF(p_hwfn->p_dev))
443 return ecore_vf_pf_vport_stop(p_hwfn);
445 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
446 if (rc != ECORE_SUCCESS)
450 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
451 init_data.cid = ecore_spq_get_cid(p_hwfn);
452 init_data.opaque_fid = opaque_fid;
453 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
455 rc = ecore_sp_init_request(p_hwfn, &p_ent,
456 ETH_RAMROD_VPORT_STOP,
457 PROTOCOLID_ETH, &init_data);
458 if (rc != ECORE_SUCCESS)
461 p_ramrod = &p_ent->ramrod.vport_stop;
462 p_ramrod->vport_id = abs_vport_id;
464 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
467 static enum _ecore_status_t
468 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
469 struct ecore_filter_accept_flags *p_accept_flags)
471 struct ecore_sp_vport_update_params s_params;
473 OSAL_MEMSET(&s_params, 0, sizeof(s_params));
474 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
475 sizeof(struct ecore_filter_accept_flags));
477 return ecore_vf_pf_vport_update(p_hwfn, &s_params);
481 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
483 struct ecore_filter_accept_flags accept_flags,
484 u8 update_accept_any_vlan,
486 enum spq_mode comp_mode,
487 struct ecore_spq_comp_cb *p_comp_data)
489 struct ecore_sp_vport_update_params vport_update_params;
492 /* Prepare and send the vport rx_mode change */
493 OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
494 vport_update_params.vport_id = vport;
495 vport_update_params.accept_flags = accept_flags;
496 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
497 vport_update_params.accept_any_vlan = accept_any_vlan;
499 for_each_hwfn(p_dev, i) {
500 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
502 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
505 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
506 if (rc != ECORE_SUCCESS)
511 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
512 comp_mode, p_comp_data);
513 if (rc != ECORE_SUCCESS) {
514 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
518 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
519 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
520 accept_flags.rx_accept_filter,
521 accept_flags.tx_accept_filter);
523 if (update_accept_any_vlan)
524 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
525 "accept_any_vlan=%d configured\n",
532 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
533 struct ecore_hw_cid_data *p_cid_data)
535 if (!p_cid_data->b_cid_allocated)
538 ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
539 p_cid_data->b_cid_allocated = false;
543 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
553 dma_addr_t bd_chain_phys_addr,
554 dma_addr_t cqe_pbl_addr,
555 u16 cqe_pbl_size, bool b_use_zone_a_prod)
557 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
558 struct ecore_spq_entry *p_ent = OSAL_NULL;
559 struct ecore_sp_init_data init_data;
560 struct ecore_hw_cid_data *p_rx_cid;
563 enum _ecore_status_t rc = ECORE_NOTIMPL;
565 /* Store information for the stop */
566 p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
568 p_rx_cid->opaque_fid = opaque_fid;
569 p_rx_cid->vport_id = vport_id;
571 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
572 if (rc != ECORE_SUCCESS)
575 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
576 if (rc != ECORE_SUCCESS)
579 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
580 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
581 opaque_fid, cid, rx_queue_id, vport_id, sb);
584 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
586 init_data.opaque_fid = opaque_fid;
587 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
589 rc = ecore_sp_init_request(p_hwfn, &p_ent,
590 ETH_RAMROD_RX_QUEUE_START,
591 PROTOCOLID_ETH, &init_data);
592 if (rc != ECORE_SUCCESS)
595 p_ramrod = &p_ent->ramrod.rx_queue_start;
597 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
598 p_ramrod->sb_index = sb_index;
599 p_ramrod->vport_id = abs_vport_id;
600 p_ramrod->stats_counter_id = stats_id;
601 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
602 p_ramrod->complete_cqe_flg = 0;
603 p_ramrod->complete_event_flg = 1;
605 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
606 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
608 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
609 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
611 if (vf_rx_queue_id || b_use_zone_a_prod) {
612 p_ramrod->vf_rx_prod_index = vf_rx_queue_id;
613 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
614 "Queue%s is meant for VF rxq[%02x]\n",
615 b_use_zone_a_prod ? " [legacy]" : "",
617 p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
620 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
623 enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
631 dma_addr_t bd_chain_phys_addr,
632 dma_addr_t cqe_pbl_addr,
634 void OSAL_IOMEM **pp_prod)
636 struct ecore_hw_cid_data *p_rx_cid;
637 u32 init_prod_val = 0;
638 u16 abs_l2_queue = 0;
640 enum _ecore_status_t rc;
642 if (IS_VF(p_hwfn->p_dev)) {
643 return ecore_vf_pf_rxq_start(p_hwfn,
650 cqe_pbl_size, pp_prod);
653 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_l2_queue);
654 if (rc != ECORE_SUCCESS)
657 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
658 if (rc != ECORE_SUCCESS)
661 *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
662 GTT_BAR0_MAP_REG_MSDM_RAM +
663 MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
665 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
666 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
667 (u32 *)(&init_prod_val));
669 /* Allocate a CID for the queue */
670 p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
671 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
673 if (rc != ECORE_SUCCESS) {
674 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
677 p_rx_cid->b_cid_allocated = true;
679 rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
694 if (rc != ECORE_SUCCESS)
695 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
701 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
705 u8 complete_event_flg,
706 enum spq_mode comp_mode,
707 struct ecore_spq_comp_cb *p_comp_data)
709 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
710 struct ecore_spq_entry *p_ent = OSAL_NULL;
711 struct ecore_sp_init_data init_data;
712 struct ecore_hw_cid_data *p_rx_cid;
713 u16 qid, abs_rx_q_id = 0;
714 enum _ecore_status_t rc = ECORE_NOTIMPL;
717 if (IS_VF(p_hwfn->p_dev))
718 return ecore_vf_pf_rxqs_update(p_hwfn,
724 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
725 init_data.comp_mode = comp_mode;
726 init_data.p_comp_data = p_comp_data;
728 for (i = 0; i < num_rxqs; i++) {
729 qid = rx_queue_id + i;
730 p_rx_cid = &p_hwfn->p_rx_cids[qid];
733 init_data.cid = p_rx_cid->cid;
734 init_data.opaque_fid = p_rx_cid->opaque_fid;
736 rc = ecore_sp_init_request(p_hwfn, &p_ent,
737 ETH_RAMROD_RX_QUEUE_UPDATE,
738 PROTOCOLID_ETH, &init_data);
739 if (rc != ECORE_SUCCESS)
742 p_ramrod = &p_ent->ramrod.rx_queue_update;
744 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
745 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
746 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
747 p_ramrod->complete_cqe_flg = complete_cqe_flg;
748 p_ramrod->complete_event_flg = complete_event_flg;
750 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
759 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
761 bool eq_completion_only, bool cqe_completion)
763 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
764 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
765 struct ecore_spq_entry *p_ent = OSAL_NULL;
766 struct ecore_sp_init_data init_data;
768 enum _ecore_status_t rc = ECORE_NOTIMPL;
770 if (IS_VF(p_hwfn->p_dev))
771 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
775 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
776 init_data.cid = p_rx_cid->cid;
777 init_data.opaque_fid = p_rx_cid->opaque_fid;
778 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
780 rc = ecore_sp_init_request(p_hwfn, &p_ent,
781 ETH_RAMROD_RX_QUEUE_STOP,
782 PROTOCOLID_ETH, &init_data);
783 if (rc != ECORE_SUCCESS)
786 p_ramrod = &p_ent->ramrod.rx_queue_stop;
788 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
789 ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
790 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
792 /* Cleaning the queue requires the completion to arrive there.
793 * In addition, VFs require the answer to come as eqe to PF.
795 p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
796 p_hwfn->hw_info.opaque_fid) &&
797 !eq_completion_only) || cqe_completion;
798 p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
799 p_hwfn->hw_info.opaque_fid) ||
802 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
803 if (rc != ECORE_SUCCESS)
806 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
812 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
822 union ecore_qm_pq_params *p_pq_params)
824 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
825 struct ecore_spq_entry *p_ent = OSAL_NULL;
826 struct ecore_sp_init_data init_data;
827 struct ecore_hw_cid_data *p_tx_cid;
828 u16 pq_id, abs_tx_q_id = 0;
830 enum _ecore_status_t rc = ECORE_NOTIMPL;
832 /* Store information for the stop */
833 p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
835 p_tx_cid->opaque_fid = opaque_fid;
837 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
838 if (rc != ECORE_SUCCESS)
841 rc = ecore_fw_l2_queue(p_hwfn, tx_queue_id, &abs_tx_q_id);
842 if (rc != ECORE_SUCCESS)
846 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
848 init_data.opaque_fid = opaque_fid;
849 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
851 rc = ecore_sp_init_request(p_hwfn, &p_ent,
852 ETH_RAMROD_TX_QUEUE_START,
853 PROTOCOLID_ETH, &init_data);
854 if (rc != ECORE_SUCCESS)
857 p_ramrod = &p_ent->ramrod.tx_queue_start;
858 p_ramrod->vport_id = abs_vport_id;
860 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
861 p_ramrod->sb_index = sb_index;
862 p_ramrod->stats_counter_id = stats_id;
864 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
866 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
867 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
869 pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
870 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
872 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
875 enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
885 void OSAL_IOMEM **pp_doorbell)
887 struct ecore_hw_cid_data *p_tx_cid;
888 union ecore_qm_pq_params pq_params;
890 enum _ecore_status_t rc;
892 if (IS_VF(p_hwfn->p_dev)) {
893 return ecore_vf_pf_txq_start(p_hwfn,
902 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
903 if (rc != ECORE_SUCCESS)
906 p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
907 OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
908 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
910 pq_params.eth.tc = tc;
912 /* Allocate a CID for the queue */
913 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
914 if (rc != ECORE_SUCCESS) {
915 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
918 p_tx_cid->b_cid_allocated = true;
920 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
921 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
922 opaque_fid, p_tx_cid->cid, tx_queue_id,
925 /* TODO - set tc in the pq_params for multi-cos */
926 rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
938 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
939 DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
941 if (rc != ECORE_SUCCESS)
942 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
947 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
949 return ECORE_NOTIMPL;
952 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
955 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
956 struct ecore_spq_entry *p_ent = OSAL_NULL;
957 struct ecore_sp_init_data init_data;
958 enum _ecore_status_t rc = ECORE_NOTIMPL;
960 if (IS_VF(p_hwfn->p_dev))
961 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
964 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
965 init_data.cid = p_tx_cid->cid;
966 init_data.opaque_fid = p_tx_cid->opaque_fid;
967 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
969 rc = ecore_sp_init_request(p_hwfn, &p_ent,
970 ETH_RAMROD_TX_QUEUE_STOP,
971 PROTOCOLID_ETH, &init_data);
972 if (rc != ECORE_SUCCESS)
975 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
976 if (rc != ECORE_SUCCESS)
979 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
983 static enum eth_filter_action
984 ecore_filter_action(enum ecore_filter_opcode opcode)
986 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
989 case ECORE_FILTER_ADD:
990 action = ETH_FILTER_ACTION_ADD;
992 case ECORE_FILTER_REMOVE:
993 action = ETH_FILTER_ACTION_REMOVE;
995 case ECORE_FILTER_FLUSH:
996 action = ETH_FILTER_ACTION_REMOVE_ALL;
999 action = MAX_ETH_FILTER_ACTION;
1005 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
1006 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
1008 ((u8 *)fw_msb)[0] = mac[1];
1009 ((u8 *)fw_msb)[1] = mac[0];
1010 ((u8 *)fw_mid)[0] = mac[3];
1011 ((u8 *)fw_mid)[1] = mac[2];
1012 ((u8 *)fw_lsb)[0] = mac[5];
1013 ((u8 *)fw_lsb)[1] = mac[4];
1016 static enum _ecore_status_t
1017 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1019 struct ecore_filter_ucast *p_filter_cmd,
1020 struct vport_filter_update_ramrod_data **pp_ramrod,
1021 struct ecore_spq_entry **pp_ent,
1022 enum spq_mode comp_mode,
1023 struct ecore_spq_comp_cb *p_comp_data)
1025 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1026 struct vport_filter_update_ramrod_data *p_ramrod;
1027 struct eth_filter_cmd *p_first_filter;
1028 struct eth_filter_cmd *p_second_filter;
1029 struct ecore_sp_init_data init_data;
1030 enum eth_filter_action action;
1031 enum _ecore_status_t rc;
1033 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1034 &vport_to_remove_from);
1035 if (rc != ECORE_SUCCESS)
1038 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1040 if (rc != ECORE_SUCCESS)
1044 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1045 init_data.cid = ecore_spq_get_cid(p_hwfn);
1046 init_data.opaque_fid = opaque_fid;
1047 init_data.comp_mode = comp_mode;
1048 init_data.p_comp_data = p_comp_data;
1050 rc = ecore_sp_init_request(p_hwfn, pp_ent,
1051 ETH_RAMROD_FILTERS_UPDATE,
1052 PROTOCOLID_ETH, &init_data);
1053 if (rc != ECORE_SUCCESS)
1056 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1057 p_ramrod = *pp_ramrod;
1058 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1059 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1062 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1063 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1064 "Non-Asic - prevent Tx filters\n");
1065 p_ramrod->filter_cmd_hdr.tx = 0;
1069 switch (p_filter_cmd->opcode) {
1070 case ECORE_FILTER_REPLACE:
1071 case ECORE_FILTER_MOVE:
1072 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1075 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1079 p_first_filter = &p_ramrod->filter_cmds[0];
1080 p_second_filter = &p_ramrod->filter_cmds[1];
1082 switch (p_filter_cmd->type) {
1083 case ECORE_FILTER_MAC:
1084 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1086 case ECORE_FILTER_VLAN:
1087 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1089 case ECORE_FILTER_MAC_VLAN:
1090 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1092 case ECORE_FILTER_INNER_MAC:
1093 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1095 case ECORE_FILTER_INNER_VLAN:
1096 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1098 case ECORE_FILTER_INNER_PAIR:
1099 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1101 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1102 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1104 case ECORE_FILTER_MAC_VNI_PAIR:
1105 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1107 case ECORE_FILTER_VNI:
1108 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1112 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1113 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1114 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1115 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1116 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1117 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1118 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1119 &p_first_filter->mac_mid,
1120 &p_first_filter->mac_lsb,
1121 (u8 *)p_filter_cmd->mac);
1123 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1124 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1125 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1126 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1127 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1129 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1130 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1131 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1132 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1134 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1135 p_second_filter->type = p_first_filter->type;
1136 p_second_filter->mac_msb = p_first_filter->mac_msb;
1137 p_second_filter->mac_mid = p_first_filter->mac_mid;
1138 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1139 p_second_filter->vlan_id = p_first_filter->vlan_id;
1140 p_second_filter->vni = p_first_filter->vni;
1142 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1144 p_first_filter->vport_id = vport_to_remove_from;
1146 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1147 p_second_filter->vport_id = vport_to_add_to;
1148 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1149 p_first_filter->vport_id = vport_to_add_to;
1150 OSAL_MEMCPY(p_second_filter, p_first_filter,
1151 sizeof(*p_second_filter));
1152 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1153 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1155 action = ecore_filter_action(p_filter_cmd->opcode);
1157 if (action == MAX_ETH_FILTER_ACTION) {
1158 DP_NOTICE(p_hwfn, true,
1159 "%d is not supported yet\n",
1160 p_filter_cmd->opcode);
1161 return ECORE_NOTIMPL;
1164 p_first_filter->action = action;
1165 p_first_filter->vport_id =
1166 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1167 vport_to_remove_from : vport_to_add_to;
1170 return ECORE_SUCCESS;
1173 enum _ecore_status_t
1174 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1176 struct ecore_filter_ucast *p_filter_cmd,
1177 enum spq_mode comp_mode,
1178 struct ecore_spq_comp_cb *p_comp_data)
1180 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1181 struct ecore_spq_entry *p_ent = OSAL_NULL;
1182 struct eth_filter_cmd_header *p_header;
1183 enum _ecore_status_t rc;
1185 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1187 comp_mode, p_comp_data);
1188 if (rc != ECORE_SUCCESS) {
1189 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1192 p_header = &p_ramrod->filter_cmd_hdr;
1193 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1195 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1196 if (rc != ECORE_SUCCESS) {
1197 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1201 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1202 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1203 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1204 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1206 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1207 "MOVE" : "REPLACE")),
1208 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1209 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1210 "VLAN" : "MAC & VLAN"),
1211 p_ramrod->filter_cmd_hdr.cmd_cnt,
1212 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1213 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1214 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1215 p_filter_cmd->vport_to_add_to,
1216 p_filter_cmd->vport_to_remove_from,
1217 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1218 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1219 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1220 p_filter_cmd->vlan);
1222 return ECORE_SUCCESS;
1225 /*******************************************************************************
1227 * Calculates crc 32 on a buffer
1228 * Note: crc32_length MUST be aligned to 8
1230 ******************************************************************************/
1231 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1232 u32 crc32_length, u32 crc32_seed, u8 complement)
1234 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1235 u8 msb = 0, current_byte = 0;
1237 if ((crc32_packet == OSAL_NULL) ||
1238 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1239 return crc32_result;
1242 for (byte = 0; byte < crc32_length; byte++) {
1243 current_byte = crc32_packet[byte];
1244 for (bit = 0; bit < 8; bit++) {
1245 msb = (u8)(crc32_result >> 31);
1246 crc32_result = crc32_result << 1;
1247 if (msb != (0x1 & (current_byte >> bit))) {
1248 crc32_result = crc32_result ^ CRC32_POLY;
1254 return crc32_result;
1257 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1259 u32 packet_buf[2] = { 0 };
1261 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1262 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1265 u8 ecore_mcast_bin_from_mac(u8 *mac)
1267 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1273 static enum _ecore_status_t
1274 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1276 struct ecore_filter_mcast *p_filter_cmd,
1277 enum spq_mode comp_mode,
1278 struct ecore_spq_comp_cb *p_comp_data)
1280 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1281 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1282 struct ecore_spq_entry *p_ent = OSAL_NULL;
1283 struct ecore_sp_init_data init_data;
1284 u8 abs_vport_id = 0;
1285 enum _ecore_status_t rc;
1288 if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1289 rc = ecore_fw_vport(p_hwfn,
1290 p_filter_cmd->vport_to_add_to,
1293 rc = ecore_fw_vport(p_hwfn,
1294 p_filter_cmd->vport_to_remove_from,
1296 if (rc != ECORE_SUCCESS)
1300 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1301 init_data.cid = ecore_spq_get_cid(p_hwfn);
1302 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1303 init_data.comp_mode = comp_mode;
1304 init_data.p_comp_data = p_comp_data;
1306 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1307 ETH_RAMROD_VPORT_UPDATE,
1308 PROTOCOLID_ETH, &init_data);
1309 if (rc != ECORE_SUCCESS) {
1310 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1314 p_ramrod = &p_ent->ramrod.vport_update;
1315 p_ramrod->common.update_approx_mcast_flg = 1;
1317 /* explicitly clear out the entire vector */
1318 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1319 0, sizeof(p_ramrod->approx_mcast.bins));
1320 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1321 ETH_MULTICAST_MAC_BINS_IN_REGS);
1322 /* filter ADD op is explicit set op and it removes
1323 * any existing filters for the vport.
1325 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1326 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1329 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1330 OSAL_SET_BIT(bit, bins);
1333 /* Convert to correct endianity */
1334 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1335 struct vport_update_ramrod_mcast *p_ramrod_bins;
1336 u32 *p_bins = (u32 *)bins;
1338 p_ramrod_bins = &p_ramrod->approx_mcast;
1339 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1343 p_ramrod->common.vport_id = abs_vport_id;
1345 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1346 if (rc != ECORE_SUCCESS)
1347 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1352 enum _ecore_status_t
1353 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1354 struct ecore_filter_mcast *p_filter_cmd,
1355 enum spq_mode comp_mode,
1356 struct ecore_spq_comp_cb *p_comp_data)
1358 enum _ecore_status_t rc = ECORE_SUCCESS;
1361 /* only ADD and REMOVE operations are supported for multi-cast */
1362 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1363 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1364 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1368 for_each_hwfn(p_dev, i) {
1369 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1373 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1377 opaque_fid = p_hwfn->hw_info.opaque_fid;
1378 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1381 comp_mode, p_comp_data);
1382 if (rc != ECORE_SUCCESS)
1389 enum _ecore_status_t
1390 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1391 struct ecore_filter_ucast *p_filter_cmd,
1392 enum spq_mode comp_mode,
1393 struct ecore_spq_comp_cb *p_comp_data)
1395 enum _ecore_status_t rc = ECORE_SUCCESS;
1398 for_each_hwfn(p_dev, i) {
1399 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1403 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1407 opaque_fid = p_hwfn->hw_info.opaque_fid;
1408 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1411 comp_mode, p_comp_data);
1412 if (rc != ECORE_SUCCESS)
1419 /* Statistics related code */
1420 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1421 u32 *p_addr, u32 *p_len,
1424 if (IS_PF(p_hwfn->p_dev)) {
1425 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1426 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1427 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1429 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1430 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1432 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1433 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1437 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1438 struct ecore_ptt *p_ptt,
1439 struct ecore_eth_stats *p_stats,
1442 struct eth_pstorm_per_queue_stat pstats;
1443 u32 pstats_addr = 0, pstats_len = 0;
1445 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1448 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1449 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1451 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1452 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1453 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1454 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1455 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1456 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1457 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1460 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1461 struct ecore_ptt *p_ptt,
1462 struct ecore_eth_stats *p_stats,
1465 struct tstorm_per_port_stat tstats;
1466 u32 tstats_addr, tstats_len;
1468 if (IS_PF(p_hwfn->p_dev)) {
1469 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1470 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1471 tstats_len = sizeof(struct tstorm_per_port_stat);
1473 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1474 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1476 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1477 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1480 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1481 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1483 p_stats->mftag_filter_discards +=
1484 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1485 p_stats->mac_filter_discards +=
1486 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1489 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1490 u32 *p_addr, u32 *p_len,
1493 if (IS_PF(p_hwfn->p_dev)) {
1494 *p_addr = BAR0_MAP_REG_USDM_RAM +
1495 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1496 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1498 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1499 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1501 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1502 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1506 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1507 struct ecore_ptt *p_ptt,
1508 struct ecore_eth_stats *p_stats,
1511 struct eth_ustorm_per_queue_stat ustats;
1512 u32 ustats_addr = 0, ustats_len = 0;
1514 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1517 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1518 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1520 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1521 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1522 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1523 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1524 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1525 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1528 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1529 u32 *p_addr, u32 *p_len,
1532 if (IS_PF(p_hwfn->p_dev)) {
1533 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1534 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1535 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1537 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1538 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1540 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1541 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1545 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1546 struct ecore_ptt *p_ptt,
1547 struct ecore_eth_stats *p_stats,
1550 struct eth_mstorm_per_queue_stat mstats;
1551 u32 mstats_addr = 0, mstats_len = 0;
1553 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1556 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1557 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1559 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1560 p_stats->packet_too_big_discard +=
1561 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1562 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1563 p_stats->tpa_coalesced_pkts +=
1564 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1565 p_stats->tpa_coalesced_events +=
1566 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1567 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1568 p_stats->tpa_coalesced_bytes +=
1569 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1572 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1573 struct ecore_ptt *p_ptt,
1574 struct ecore_eth_stats *p_stats)
1576 struct port_stats port_stats;
1579 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1581 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1582 p_hwfn->mcp_info->port_addr +
1583 OFFSETOF(struct public_port, stats),
1584 sizeof(port_stats));
1586 p_stats->rx_64_byte_packets += port_stats.eth.r64;
1587 p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
1588 p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
1589 p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
1590 p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1591 p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1592 p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
1593 p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
1594 p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
1595 p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
1596 p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
1597 p_stats->rx_crc_errors += port_stats.eth.rfcs;
1598 p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
1599 p_stats->rx_pause_frames += port_stats.eth.rxpf;
1600 p_stats->rx_pfc_frames += port_stats.eth.rxpp;
1601 p_stats->rx_align_errors += port_stats.eth.raln;
1602 p_stats->rx_carrier_errors += port_stats.eth.rfcr;
1603 p_stats->rx_oversize_packets += port_stats.eth.rovr;
1604 p_stats->rx_jabbers += port_stats.eth.rjbr;
1605 p_stats->rx_undersize_packets += port_stats.eth.rund;
1606 p_stats->rx_fragments += port_stats.eth.rfrg;
1607 p_stats->tx_64_byte_packets += port_stats.eth.t64;
1608 p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
1609 p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
1610 p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
1611 p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1612 p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1613 p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
1614 p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
1615 p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
1616 p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
1617 p_stats->tx_pause_frames += port_stats.eth.txpf;
1618 p_stats->tx_pfc_frames += port_stats.eth.txpp;
1619 p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
1620 p_stats->tx_total_collisions += port_stats.eth.tncl;
1621 p_stats->rx_mac_bytes += port_stats.eth.rbyte;
1622 p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
1623 p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
1624 p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
1625 p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
1626 p_stats->tx_mac_bytes += port_stats.eth.tbyte;
1627 p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
1628 p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
1629 p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
1630 p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
1631 for (j = 0; j < 8; j++) {
1632 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1633 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1637 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1638 struct ecore_ptt *p_ptt,
1639 struct ecore_eth_stats *stats,
1640 u16 statistics_bin, bool b_get_port_stats)
1642 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1643 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1644 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1645 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1648 /* Avoid getting PORT stats for emulation. */
1649 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1653 if (b_get_port_stats && p_hwfn->mcp_info)
1654 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1657 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1658 struct ecore_eth_stats *stats)
1663 OSAL_MEMSET(stats, 0, sizeof(*stats));
1665 for_each_hwfn(p_dev, i) {
1666 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1667 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1668 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1671 /* The main vport index is relative first */
1672 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1673 DP_ERR(p_hwfn, "No vport available!\n");
1678 if (IS_PF(p_dev) && !p_ptt) {
1679 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1683 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1684 IS_PF(p_dev) ? true : false);
1687 if (IS_PF(p_dev) && p_ptt)
1688 ecore_ptt_release(p_hwfn, p_ptt);
1692 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1693 struct ecore_eth_stats *stats)
1698 OSAL_MEMSET(stats, 0, sizeof(*stats));
1702 _ecore_get_vport_stats(p_dev, stats);
1704 if (!p_dev->reset_stats)
1707 /* Reduce the statistics baseline */
1708 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1709 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1712 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1713 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1717 for_each_hwfn(p_dev, i) {
1718 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1719 struct eth_mstorm_per_queue_stat mstats;
1720 struct eth_ustorm_per_queue_stat ustats;
1721 struct eth_pstorm_per_queue_stat pstats;
1722 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1723 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1724 u32 addr = 0, len = 0;
1726 if (IS_PF(p_dev) && !p_ptt) {
1727 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1731 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1732 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1733 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1735 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1736 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1737 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1739 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1740 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1741 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1744 ecore_ptt_release(p_hwfn, p_ptt);
1747 /* PORT statistics are not necessarily reset, so we need to
1748 * read and create a baseline for future statistics.
1750 if (!p_dev->reset_stats)
1751 DP_INFO(p_dev, "Reset stats not allocated\n");
1753 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);