2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
26 #include "ecore_sriov.h"
27 #include "ecore_mcp.h"
29 #define ECORE_MAX_SGES_NUM 16
30 #define CRC32_POLY 0x1edc6f41
32 struct ecore_l2_info {
34 unsigned long **pp_qid_usage;
36 /* The lock is meant to synchronize access to the qid usage */
40 enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn)
42 struct ecore_l2_info *p_l2_info;
43 unsigned long **pp_qids;
46 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
49 p_l2_info = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_l2_info));
52 p_hwfn->p_l2_info = p_l2_info;
54 if (IS_PF(p_hwfn->p_dev)) {
55 p_l2_info->queues = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
59 ecore_vf_get_num_rxqs(p_hwfn, &rx);
60 ecore_vf_get_num_txqs(p_hwfn, &tx);
62 p_l2_info->queues = (u32)OSAL_MAX_T(u8, rx, tx);
65 pp_qids = OSAL_VZALLOC(p_hwfn->p_dev,
66 sizeof(unsigned long *) *
68 if (pp_qids == OSAL_NULL)
70 p_l2_info->pp_qid_usage = pp_qids;
72 for (i = 0; i < p_l2_info->queues; i++) {
73 pp_qids[i] = OSAL_VZALLOC(p_hwfn->p_dev,
74 MAX_QUEUES_PER_QZONE / 8);
75 if (pp_qids[i] == OSAL_NULL)
79 #ifdef CONFIG_ECORE_LOCK_ALLOC
80 OSAL_MUTEX_ALLOC(p_hwfn, &p_l2_info->lock);
86 void ecore_l2_setup(struct ecore_hwfn *p_hwfn)
88 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
91 OSAL_MUTEX_INIT(&p_hwfn->p_l2_info->lock);
94 void ecore_l2_free(struct ecore_hwfn *p_hwfn)
98 if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
101 if (p_hwfn->p_l2_info == OSAL_NULL)
104 if (p_hwfn->p_l2_info->pp_qid_usage == OSAL_NULL)
107 /* Free until hit first uninitialized entry */
108 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
109 if (p_hwfn->p_l2_info->pp_qid_usage[i] == OSAL_NULL)
111 OSAL_VFREE(p_hwfn->p_dev,
112 p_hwfn->p_l2_info->pp_qid_usage[i]);
115 #ifdef CONFIG_ECORE_LOCK_ALLOC
116 /* Lock is last to initialize, if everything else was */
117 if (i == p_hwfn->p_l2_info->queues)
118 OSAL_MUTEX_DEALLOC(&p_hwfn->p_l2_info->lock);
121 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info->pp_qid_usage);
124 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info);
125 p_hwfn->p_l2_info = OSAL_NULL;
128 /* TODO - we'll need locking around these... */
129 static bool ecore_eth_queue_qid_usage_add(struct ecore_hwfn *p_hwfn,
130 struct ecore_queue_cid *p_cid)
132 struct ecore_l2_info *p_l2_info = p_hwfn->p_l2_info;
133 u16 queue_id = p_cid->rel.queue_id;
137 OSAL_MUTEX_ACQUIRE(&p_l2_info->lock);
139 if (queue_id > p_l2_info->queues) {
140 DP_NOTICE(p_hwfn, true,
141 "Requested to increase usage for qzone %04x out of %08x\n",
142 queue_id, p_l2_info->queues);
147 first = (u8)OSAL_FIND_FIRST_ZERO_BIT(p_l2_info->pp_qid_usage[queue_id],
148 MAX_QUEUES_PER_QZONE);
149 if (first >= MAX_QUEUES_PER_QZONE) {
154 OSAL_SET_BIT(first, p_l2_info->pp_qid_usage[queue_id]);
155 p_cid->qid_usage_idx = first;
158 OSAL_MUTEX_RELEASE(&p_l2_info->lock);
162 static void ecore_eth_queue_qid_usage_del(struct ecore_hwfn *p_hwfn,
163 struct ecore_queue_cid *p_cid)
165 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_l2_info->lock);
167 OSAL_CLEAR_BIT(p_cid->qid_usage_idx,
168 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
170 OSAL_MUTEX_RELEASE(&p_hwfn->p_l2_info->lock);
173 void ecore_eth_queue_cid_release(struct ecore_hwfn *p_hwfn,
174 struct ecore_queue_cid *p_cid)
176 bool b_legacy_vf = !!(p_cid->vf_legacy &
177 ECORE_QCID_LEGACY_VF_CID);
179 /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF.
180 * For legacy vf-queues, the CID doesn't go through here.
182 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
183 _ecore_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
185 /* VFs maintain the index inside queue-zone on their own */
186 if (p_cid->vfid == ECORE_QUEUE_CID_PF)
187 ecore_eth_queue_qid_usage_del(p_hwfn, p_cid);
189 OSAL_VFREE(p_hwfn->p_dev, p_cid);
192 /* The internal is only meant to be directly called by PFs initializeing CIDs
195 static struct ecore_queue_cid *
196 _ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn,
197 u16 opaque_fid, u32 cid,
198 struct ecore_queue_start_common_params *p_params,
199 struct ecore_queue_cid_vf_params *p_vf_params)
201 struct ecore_queue_cid *p_cid;
202 enum _ecore_status_t rc;
204 p_cid = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_cid));
205 if (p_cid == OSAL_NULL)
208 p_cid->opaque_fid = opaque_fid;
210 p_cid->p_owner = p_hwfn;
212 /* Fill in parameters */
213 p_cid->rel.vport_id = p_params->vport_id;
214 p_cid->rel.queue_id = p_params->queue_id;
215 p_cid->rel.stats_id = p_params->stats_id;
216 p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
217 p_cid->sb_idx = p_params->sb_idx;
219 /* Fill-in bits related to VFs' queues if information was provided */
220 if (p_vf_params != OSAL_NULL) {
221 p_cid->vfid = p_vf_params->vfid;
222 p_cid->vf_qid = p_vf_params->vf_qid;
223 p_cid->vf_legacy = p_vf_params->vf_legacy;
225 p_cid->vfid = ECORE_QUEUE_CID_PF;
228 /* Don't try calculating the absolute indices for VFs */
229 if (IS_VF(p_hwfn->p_dev)) {
230 p_cid->abs = p_cid->rel;
235 /* Calculate the engine-absolute indices of the resources.
236 * The would guarantee they're valid later on.
237 * In some cases [SBs] we already have the right values.
239 rc = ecore_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
240 if (rc != ECORE_SUCCESS)
243 rc = ecore_fw_l2_queue(p_hwfn, p_cid->rel.queue_id,
244 &p_cid->abs.queue_id);
245 if (rc != ECORE_SUCCESS)
248 /* In case of a PF configuring its VF's queues, the stats-id is already
249 * absolute [since there's a single index that's suitable per-VF].
251 if (p_cid->vfid == ECORE_QUEUE_CID_PF) {
252 rc = ecore_fw_vport(p_hwfn, p_cid->rel.stats_id,
253 &p_cid->abs.stats_id);
254 if (rc != ECORE_SUCCESS)
257 p_cid->abs.stats_id = p_cid->rel.stats_id;
261 /* VF-images have provided the qid_usage_idx on their own.
262 * Otherwise, we need to allocate a unique one.
265 if (!ecore_eth_queue_qid_usage_add(p_hwfn, p_cid))
268 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
271 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
272 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
273 p_cid->opaque_fid, p_cid->cid,
274 p_cid->rel.vport_id, p_cid->abs.vport_id,
275 p_cid->rel.queue_id, p_cid->qid_usage_idx,
277 p_cid->rel.stats_id, p_cid->abs.stats_id,
278 p_cid->sb_igu_id, p_cid->sb_idx);
283 OSAL_VFREE(p_hwfn->p_dev, p_cid);
287 struct ecore_queue_cid *
288 ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
289 struct ecore_queue_start_common_params *p_params,
290 struct ecore_queue_cid_vf_params *p_vf_params)
292 struct ecore_queue_cid *p_cid;
293 u8 vfid = ECORE_CXT_PF_CID;
294 bool b_legacy_vf = false;
297 /* In case of legacy VFs, The CID can be derived from the additional
298 * VF parameters - the VF assumes queue X uses CID X, so we can simply
299 * use the vf_qid for this purpose as well.
302 vfid = p_vf_params->vfid;
304 if (p_vf_params->vf_legacy &
305 ECORE_QCID_LEGACY_VF_CID) {
307 cid = p_vf_params->vf_qid;
311 /* Get a unique firmware CID for this queue, in case it's a PF.
312 * VF's don't need a CID as the queue configuration will be done
315 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf) {
316 if (_ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
317 &cid, vfid) != ECORE_SUCCESS) {
318 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
323 p_cid = _ecore_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
324 p_params, p_vf_params);
325 if ((p_cid == OSAL_NULL) && IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
326 _ecore_cxt_release_cid(p_hwfn, cid, vfid);
331 static struct ecore_queue_cid *
332 ecore_eth_queue_to_cid_pf(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
333 struct ecore_queue_start_common_params *p_params)
335 return ecore_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, OSAL_NULL);
339 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
340 struct ecore_sp_vport_start_params *p_params)
342 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
343 struct ecore_spq_entry *p_ent = OSAL_NULL;
344 struct ecore_sp_init_data init_data;
345 u16 rx_mode = 0, tx_err = 0;
347 enum _ecore_status_t rc = ECORE_NOTIMPL;
349 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
350 if (rc != ECORE_SUCCESS)
354 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
355 init_data.cid = ecore_spq_get_cid(p_hwfn);
356 init_data.opaque_fid = p_params->opaque_fid;
357 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
359 rc = ecore_sp_init_request(p_hwfn, &p_ent,
360 ETH_RAMROD_VPORT_START,
361 PROTOCOLID_ETH, &init_data);
362 if (rc != ECORE_SUCCESS)
365 p_ramrod = &p_ent->ramrod.vport_start;
366 p_ramrod->vport_id = abs_vport_id;
368 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
369 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
370 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
371 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
372 p_ramrod->untagged = p_params->only_untagged;
373 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
375 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
376 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
378 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
380 /* Handle requests for strict behavior on transmission errors */
381 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE,
382 p_params->b_err_illegal_vlan_mode ?
383 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
384 SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL,
385 p_params->b_err_small_pkt ?
386 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
387 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR,
388 p_params->b_err_anti_spoof ?
389 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
390 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS,
391 p_params->b_err_illegal_inband_mode ?
392 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
393 SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG,
394 p_params->b_err_vlan_insert_with_inband ?
395 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
396 SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION,
397 p_params->b_err_big_pkt ?
398 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
399 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME,
400 p_params->b_err_ctrl_frame ?
401 ETH_TX_ERR_ASSERT_MALICIOUS : 0);
402 p_ramrod->tx_err_behav.values = OSAL_CPU_TO_LE16(tx_err);
404 /* TPA related fields */
405 OSAL_MEMSET(&p_ramrod->tpa_param, 0,
406 sizeof(struct eth_vport_tpa_param));
407 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
409 switch (p_params->tpa_mode) {
410 case ECORE_TPA_MODE_GRO:
411 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
412 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
413 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
414 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
415 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
416 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
417 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
418 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
419 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
420 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
426 p_ramrod->tx_switching_en = p_params->tx_switching;
428 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
429 p_ramrod->tx_switching_en = 0;
432 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
433 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
435 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
436 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
437 p_params->concrete_fid);
439 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
443 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
444 struct ecore_sp_vport_start_params *p_params)
446 if (IS_VF(p_hwfn->p_dev))
447 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
449 p_params->remove_inner_vlan,
451 p_params->max_buffers_per_cqe,
452 p_params->only_untagged);
454 return ecore_sp_eth_vport_start(p_hwfn, p_params);
457 static enum _ecore_status_t
458 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
459 struct vport_update_ramrod_data *p_ramrod,
460 struct ecore_rss_params *p_rss)
462 struct eth_vport_rss_config *p_config;
464 enum _ecore_status_t rc = ECORE_SUCCESS;
467 p_ramrod->common.update_rss_flg = 0;
470 p_config = &p_ramrod->rss_config;
472 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
473 ETH_RSS_IND_TABLE_ENTRIES_NUM);
475 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
476 if (rc != ECORE_SUCCESS)
479 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
480 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
481 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
482 p_config->update_rss_key = p_rss->update_rss_key;
484 p_config->rss_mode = p_rss->rss_enable ?
485 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
487 p_config->capabilities = 0;
489 SET_FIELD(p_config->capabilities,
490 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
491 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
492 SET_FIELD(p_config->capabilities,
493 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
494 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
495 SET_FIELD(p_config->capabilities,
496 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
497 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
498 SET_FIELD(p_config->capabilities,
499 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
500 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
501 SET_FIELD(p_config->capabilities,
502 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
503 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
504 SET_FIELD(p_config->capabilities,
505 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
506 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
507 p_config->tbl_size = p_rss->rss_table_size_log;
508 p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
510 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
511 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
512 p_ramrod->common.update_rss_flg,
514 p_config->update_rss_capabilities,
515 p_config->capabilities,
516 p_config->update_rss_ind_table, p_config->update_rss_key);
518 table_size = OSAL_MIN_T(int, ECORE_RSS_IND_TABLE_SIZE,
519 1 << p_config->tbl_size);
520 for (i = 0; i < table_size; i++) {
521 struct ecore_queue_cid *p_queue = p_rss->rss_ind_table[i];
526 p_config->indirection_table[i] =
527 OSAL_CPU_TO_LE16(p_queue->abs.queue_id);
530 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
531 "Configured RSS indirection table [%d entries]:\n",
533 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i += 0x10) {
534 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
535 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
536 OSAL_LE16_TO_CPU(p_config->indirection_table[i]),
537 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 1]),
538 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 2]),
539 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 3]),
540 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 4]),
541 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 5]),
542 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 6]),
543 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 7]),
544 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 8]),
545 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 9]),
546 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 10]),
547 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 11]),
548 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 12]),
549 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 13]),
550 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 14]),
551 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 15]));
554 for (i = 0; i < 10; i++)
555 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
561 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
562 struct vport_update_ramrod_data *p_ramrod,
563 struct ecore_filter_accept_flags accept_flags)
565 p_ramrod->common.update_rx_mode_flg =
566 accept_flags.update_rx_mode_config;
567 p_ramrod->common.update_tx_mode_flg =
568 accept_flags.update_tx_mode_config;
571 /* On B0 emulation we cannot enable Tx, since this would cause writes
572 * to PVFC HW block which isn't implemented in emulation.
574 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
575 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
576 "Non-Asic - prevent Tx mode in vport update\n");
577 p_ramrod->common.update_tx_mode_flg = 0;
581 /* Set Rx mode accept flags */
582 if (p_ramrod->common.update_rx_mode_flg) {
583 u8 accept_filter = accept_flags.rx_accept_filter;
586 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
587 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
588 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
590 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
591 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
593 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
594 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
595 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
597 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
598 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
599 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
601 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
602 !!(accept_filter & ECORE_ACCEPT_BCAST));
604 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
605 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
606 "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n",
607 p_ramrod->common.vport_id, state);
610 /* Set Tx mode accept flags */
611 if (p_ramrod->common.update_tx_mode_flg) {
612 u8 accept_filter = accept_flags.tx_accept_filter;
615 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
616 !!(accept_filter & ECORE_ACCEPT_NONE));
618 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
619 !!(accept_filter & ECORE_ACCEPT_NONE));
621 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
622 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
623 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
625 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
626 !!(accept_filter & ECORE_ACCEPT_BCAST));
628 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
629 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
630 "vport[%02x] p_ramrod->tx_mode.state = 0x%x\n",
631 p_ramrod->common.vport_id, state);
636 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
637 struct vport_update_ramrod_data *p_ramrod,
638 struct ecore_sge_tpa_params *p_params)
640 struct eth_vport_tpa_param *p_tpa;
643 p_ramrod->common.update_tpa_param_flg = 0;
644 p_ramrod->common.update_tpa_en_flg = 0;
645 p_ramrod->common.update_tpa_param_flg = 0;
649 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
650 p_tpa = &p_ramrod->tpa_param;
651 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
652 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
653 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
654 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
656 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
657 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
658 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
659 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
660 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
661 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
662 p_tpa->tpa_max_size = p_params->tpa_max_size;
663 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
664 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
668 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
669 struct vport_update_ramrod_data *p_ramrod,
670 struct ecore_sp_vport_update_params *p_params)
674 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
675 sizeof(p_ramrod->approx_mcast.bins));
677 if (!p_params->update_approx_mcast_flg)
680 p_ramrod->common.update_approx_mcast_flg = 1;
681 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
682 u32 *p_bins = (u32 *)p_params->bins;
684 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
689 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
690 struct ecore_sp_vport_update_params *p_params,
691 enum spq_mode comp_mode,
692 struct ecore_spq_comp_cb *p_comp_data)
694 struct ecore_rss_params *p_rss_params = p_params->rss_params;
695 struct vport_update_ramrod_data_cmn *p_cmn;
696 struct ecore_sp_init_data init_data;
697 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
698 struct ecore_spq_entry *p_ent = OSAL_NULL;
699 u8 abs_vport_id = 0, val;
700 enum _ecore_status_t rc = ECORE_NOTIMPL;
702 if (IS_VF(p_hwfn->p_dev)) {
703 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
707 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
708 if (rc != ECORE_SUCCESS)
712 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
713 init_data.cid = ecore_spq_get_cid(p_hwfn);
714 init_data.opaque_fid = p_params->opaque_fid;
715 init_data.comp_mode = comp_mode;
716 init_data.p_comp_data = p_comp_data;
718 rc = ecore_sp_init_request(p_hwfn, &p_ent,
719 ETH_RAMROD_VPORT_UPDATE,
720 PROTOCOLID_ETH, &init_data);
721 if (rc != ECORE_SUCCESS)
724 /* Copy input params to ramrod according to FW struct */
725 p_ramrod = &p_ent->ramrod.vport_update;
726 p_cmn = &p_ramrod->common;
728 p_cmn->vport_id = abs_vport_id;
730 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
731 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
732 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
733 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
735 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
736 val = p_params->update_accept_any_vlan_flg;
737 p_cmn->update_accept_any_vlan_flg = val;
739 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
740 val = p_params->update_inner_vlan_removal_flg;
741 p_cmn->update_inner_vlan_removal_en_flg = val;
743 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
744 val = p_params->update_default_vlan_enable_flg;
745 p_cmn->update_default_vlan_en_flg = val;
747 p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
748 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
750 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
752 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
755 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
756 if (p_ramrod->common.tx_switching_en ||
757 p_ramrod->common.update_tx_switching_en_flg) {
758 DP_NOTICE(p_hwfn, false,
759 "FPGA - why are we seeing tx-switching? Overriding it\n");
760 p_ramrod->common.tx_switching_en = 0;
761 p_ramrod->common.update_tx_switching_en_flg = 1;
764 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
766 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
767 val = p_params->update_anti_spoofing_en_flg;
768 p_ramrod->common.update_anti_spoofing_en_flg = val;
770 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
771 if (rc != ECORE_SUCCESS) {
772 /* Return spq entry which is taken in ecore_sp_init_request()*/
773 ecore_spq_return_entry(p_hwfn, p_ent);
777 /* Update mcast bins for VFs, PF doesn't use this functionality */
778 ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
780 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
781 ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
782 p_params->sge_tpa_params);
784 p_ramrod->common.update_mtu_flg = 1;
785 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
788 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
791 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
792 u16 opaque_fid, u8 vport_id)
794 struct vport_stop_ramrod_data *p_ramrod;
795 struct ecore_sp_init_data init_data;
796 struct ecore_spq_entry *p_ent;
798 enum _ecore_status_t rc;
800 if (IS_VF(p_hwfn->p_dev))
801 return ecore_vf_pf_vport_stop(p_hwfn);
803 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
804 if (rc != ECORE_SUCCESS)
808 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
809 init_data.cid = ecore_spq_get_cid(p_hwfn);
810 init_data.opaque_fid = opaque_fid;
811 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
813 rc = ecore_sp_init_request(p_hwfn, &p_ent,
814 ETH_RAMROD_VPORT_STOP,
815 PROTOCOLID_ETH, &init_data);
816 if (rc != ECORE_SUCCESS)
819 p_ramrod = &p_ent->ramrod.vport_stop;
820 p_ramrod->vport_id = abs_vport_id;
822 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
825 static enum _ecore_status_t
826 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
827 struct ecore_filter_accept_flags *p_accept_flags)
829 struct ecore_sp_vport_update_params s_params;
831 OSAL_MEMSET(&s_params, 0, sizeof(s_params));
832 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
833 sizeof(struct ecore_filter_accept_flags));
835 return ecore_vf_pf_vport_update(p_hwfn, &s_params);
839 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
841 struct ecore_filter_accept_flags accept_flags,
842 u8 update_accept_any_vlan,
844 enum spq_mode comp_mode,
845 struct ecore_spq_comp_cb *p_comp_data)
847 struct ecore_sp_vport_update_params vport_update_params;
850 /* Prepare and send the vport rx_mode change */
851 OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
852 vport_update_params.vport_id = vport;
853 vport_update_params.accept_flags = accept_flags;
854 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
855 vport_update_params.accept_any_vlan = accept_any_vlan;
857 for_each_hwfn(p_dev, i) {
858 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
860 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
863 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
864 if (rc != ECORE_SUCCESS)
869 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
870 comp_mode, p_comp_data);
871 if (rc != ECORE_SUCCESS) {
872 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
876 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
877 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
878 accept_flags.rx_accept_filter,
879 accept_flags.tx_accept_filter);
881 if (update_accept_any_vlan)
882 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
883 "accept_any_vlan=%d configured\n",
891 ecore_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
892 struct ecore_queue_cid *p_cid,
894 dma_addr_t bd_chain_phys_addr,
895 dma_addr_t cqe_pbl_addr,
898 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
899 struct ecore_spq_entry *p_ent = OSAL_NULL;
900 struct ecore_sp_init_data init_data;
901 enum _ecore_status_t rc = ECORE_NOTIMPL;
903 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
904 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
905 p_cid->opaque_fid, p_cid->cid, p_cid->abs.queue_id,
906 p_cid->abs.vport_id, p_cid->sb_igu_id);
909 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
910 init_data.cid = p_cid->cid;
911 init_data.opaque_fid = p_cid->opaque_fid;
912 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
914 rc = ecore_sp_init_request(p_hwfn, &p_ent,
915 ETH_RAMROD_RX_QUEUE_START,
916 PROTOCOLID_ETH, &init_data);
917 if (rc != ECORE_SUCCESS)
920 p_ramrod = &p_ent->ramrod.rx_queue_start;
922 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id);
923 p_ramrod->sb_index = p_cid->sb_idx;
924 p_ramrod->vport_id = p_cid->abs.vport_id;
925 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
926 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
927 p_ramrod->complete_cqe_flg = 0;
928 p_ramrod->complete_event_flg = 1;
930 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
931 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
933 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
934 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
936 if (p_cid->vfid != ECORE_QUEUE_CID_PF) {
937 bool b_legacy_vf = !!(p_cid->vf_legacy &
938 ECORE_QCID_LEGACY_VF_RX_PROD);
940 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
941 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
942 "Queue%s is meant for VF rxq[%02x]\n",
943 b_legacy_vf ? " [legacy]" : "",
945 p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
948 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
951 static enum _ecore_status_t
952 ecore_eth_pf_rx_queue_start(struct ecore_hwfn *p_hwfn,
953 struct ecore_queue_cid *p_cid,
955 dma_addr_t bd_chain_phys_addr,
956 dma_addr_t cqe_pbl_addr,
958 void OSAL_IOMEM * *pp_prod)
960 u32 init_prod_val = 0;
962 *pp_prod = (u8 OSAL_IOMEM *)
964 GTT_BAR0_MAP_REG_MSDM_RAM +
965 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
967 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
968 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
969 (u32 *)(&init_prod_val));
971 return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid,
974 cqe_pbl_addr, cqe_pbl_size);
978 ecore_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
980 struct ecore_queue_start_common_params *p_params,
982 dma_addr_t bd_chain_phys_addr,
983 dma_addr_t cqe_pbl_addr,
985 struct ecore_rxq_start_ret_params *p_ret_params)
987 struct ecore_queue_cid *p_cid;
988 enum _ecore_status_t rc;
990 /* Allocate a CID for the queue */
991 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
992 if (p_cid == OSAL_NULL)
995 if (IS_PF(p_hwfn->p_dev))
996 rc = ecore_eth_pf_rx_queue_start(p_hwfn, p_cid,
999 cqe_pbl_addr, cqe_pbl_size,
1000 &p_ret_params->p_prod);
1002 rc = ecore_vf_pf_rxq_start(p_hwfn, p_cid,
1007 &p_ret_params->p_prod);
1009 /* Provide the caller with a reference to as handler */
1010 if (rc != ECORE_SUCCESS)
1011 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1013 p_ret_params->p_handle = (void *)p_cid;
1018 enum _ecore_status_t
1019 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
1020 void **pp_rxq_handles,
1022 u8 complete_cqe_flg,
1023 u8 complete_event_flg,
1024 enum spq_mode comp_mode,
1025 struct ecore_spq_comp_cb *p_comp_data)
1027 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
1028 struct ecore_spq_entry *p_ent = OSAL_NULL;
1029 struct ecore_sp_init_data init_data;
1030 struct ecore_queue_cid *p_cid;
1031 enum _ecore_status_t rc = ECORE_NOTIMPL;
1034 if (IS_VF(p_hwfn->p_dev))
1035 return ecore_vf_pf_rxqs_update(p_hwfn,
1036 (struct ecore_queue_cid **)
1040 complete_event_flg);
1042 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1043 init_data.comp_mode = comp_mode;
1044 init_data.p_comp_data = p_comp_data;
1046 for (i = 0; i < num_rxqs; i++) {
1047 p_cid = ((struct ecore_queue_cid **)pp_rxq_handles)[i];
1050 init_data.cid = p_cid->cid;
1051 init_data.opaque_fid = p_cid->opaque_fid;
1053 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1054 ETH_RAMROD_RX_QUEUE_UPDATE,
1055 PROTOCOLID_ETH, &init_data);
1056 if (rc != ECORE_SUCCESS)
1059 p_ramrod = &p_ent->ramrod.rx_queue_update;
1060 p_ramrod->vport_id = p_cid->abs.vport_id;
1062 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1063 p_ramrod->complete_cqe_flg = complete_cqe_flg;
1064 p_ramrod->complete_event_flg = complete_event_flg;
1066 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1067 if (rc != ECORE_SUCCESS)
1074 static enum _ecore_status_t
1075 ecore_eth_pf_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1076 struct ecore_queue_cid *p_cid,
1077 bool b_eq_completion_only,
1078 bool b_cqe_completion)
1080 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
1081 struct ecore_spq_entry *p_ent = OSAL_NULL;
1082 struct ecore_sp_init_data init_data;
1083 enum _ecore_status_t rc;
1085 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1086 init_data.cid = p_cid->cid;
1087 init_data.opaque_fid = p_cid->opaque_fid;
1088 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1090 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1091 ETH_RAMROD_RX_QUEUE_STOP,
1092 PROTOCOLID_ETH, &init_data);
1093 if (rc != ECORE_SUCCESS)
1096 p_ramrod = &p_ent->ramrod.rx_queue_stop;
1097 p_ramrod->vport_id = p_cid->abs.vport_id;
1098 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1100 /* Cleaning the queue requires the completion to arrive there.
1101 * In addition, VFs require the answer to come as eqe to PF.
1103 p_ramrod->complete_cqe_flg = ((p_cid->vfid == ECORE_QUEUE_CID_PF) &&
1104 !b_eq_completion_only) ||
1106 p_ramrod->complete_event_flg = (p_cid->vfid != ECORE_QUEUE_CID_PF) ||
1107 b_eq_completion_only;
1109 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1112 enum _ecore_status_t ecore_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1114 bool eq_completion_only,
1115 bool cqe_completion)
1117 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_rxq;
1118 enum _ecore_status_t rc = ECORE_NOTIMPL;
1120 if (IS_PF(p_hwfn->p_dev))
1121 rc = ecore_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1125 rc = ecore_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1127 if (rc == ECORE_SUCCESS)
1128 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1132 enum _ecore_status_t
1133 ecore_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
1134 struct ecore_queue_cid *p_cid,
1135 dma_addr_t pbl_addr, u16 pbl_size,
1138 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
1139 struct ecore_spq_entry *p_ent = OSAL_NULL;
1140 struct ecore_sp_init_data init_data;
1141 enum _ecore_status_t rc = ECORE_NOTIMPL;
1144 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1145 init_data.cid = p_cid->cid;
1146 init_data.opaque_fid = p_cid->opaque_fid;
1147 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1149 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1150 ETH_RAMROD_TX_QUEUE_START,
1151 PROTOCOLID_ETH, &init_data);
1152 if (rc != ECORE_SUCCESS)
1155 p_ramrod = &p_ent->ramrod.tx_queue_start;
1156 p_ramrod->vport_id = p_cid->abs.vport_id;
1158 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id);
1159 p_ramrod->sb_index = p_cid->sb_idx;
1160 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
1162 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1163 p_ramrod->same_as_last_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1165 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
1166 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
1168 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
1170 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1173 static enum _ecore_status_t
1174 ecore_eth_pf_tx_queue_start(struct ecore_hwfn *p_hwfn,
1175 struct ecore_queue_cid *p_cid,
1177 dma_addr_t pbl_addr, u16 pbl_size,
1178 void OSAL_IOMEM * *pp_doorbell)
1180 enum _ecore_status_t rc;
1182 /* TODO - set tc in the pq_params for multi-cos */
1183 rc = ecore_eth_txq_start_ramrod(p_hwfn, p_cid,
1185 ecore_get_cm_pq_idx_mcos(p_hwfn, tc));
1186 if (rc != ECORE_SUCCESS)
1189 /* Provide the caller with the necessary return values */
1190 *pp_doorbell = (u8 OSAL_IOMEM *)
1192 DB_ADDR(p_cid->cid, DQ_DEMS_LEGACY);
1194 return ECORE_SUCCESS;
1197 enum _ecore_status_t
1198 ecore_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
1199 struct ecore_queue_start_common_params *p_params,
1201 dma_addr_t pbl_addr, u16 pbl_size,
1202 struct ecore_txq_start_ret_params *p_ret_params)
1204 struct ecore_queue_cid *p_cid;
1205 enum _ecore_status_t rc;
1207 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
1208 if (p_cid == OSAL_NULL)
1211 if (IS_PF(p_hwfn->p_dev))
1212 rc = ecore_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1214 &p_ret_params->p_doorbell);
1216 rc = ecore_vf_pf_txq_start(p_hwfn, p_cid,
1218 &p_ret_params->p_doorbell);
1220 if (rc != ECORE_SUCCESS)
1221 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1223 p_ret_params->p_handle = (void *)p_cid;
1228 static enum _ecore_status_t
1229 ecore_eth_pf_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1230 struct ecore_queue_cid *p_cid)
1232 struct ecore_spq_entry *p_ent = OSAL_NULL;
1233 struct ecore_sp_init_data init_data;
1234 enum _ecore_status_t rc;
1236 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1237 init_data.cid = p_cid->cid;
1238 init_data.opaque_fid = p_cid->opaque_fid;
1239 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1241 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1242 ETH_RAMROD_TX_QUEUE_STOP,
1243 PROTOCOLID_ETH, &init_data);
1244 if (rc != ECORE_SUCCESS)
1247 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1250 enum _ecore_status_t ecore_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1253 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
1254 enum _ecore_status_t rc;
1256 if (IS_PF(p_hwfn->p_dev))
1257 rc = ecore_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1259 rc = ecore_vf_pf_txq_stop(p_hwfn, p_cid);
1261 if (rc == ECORE_SUCCESS)
1262 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1266 static enum eth_filter_action
1267 ecore_filter_action(enum ecore_filter_opcode opcode)
1269 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1272 case ECORE_FILTER_ADD:
1273 action = ETH_FILTER_ACTION_ADD;
1275 case ECORE_FILTER_REMOVE:
1276 action = ETH_FILTER_ACTION_REMOVE;
1278 case ECORE_FILTER_FLUSH:
1279 action = ETH_FILTER_ACTION_REMOVE_ALL;
1282 action = MAX_ETH_FILTER_ACTION;
1288 static enum _ecore_status_t
1289 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1291 struct ecore_filter_ucast *p_filter_cmd,
1292 struct vport_filter_update_ramrod_data **pp_ramrod,
1293 struct ecore_spq_entry **pp_ent,
1294 enum spq_mode comp_mode,
1295 struct ecore_spq_comp_cb *p_comp_data)
1297 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1298 struct vport_filter_update_ramrod_data *p_ramrod;
1299 struct eth_filter_cmd *p_first_filter;
1300 struct eth_filter_cmd *p_second_filter;
1301 struct ecore_sp_init_data init_data;
1302 enum eth_filter_action action;
1303 enum _ecore_status_t rc;
1305 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1306 &vport_to_remove_from);
1307 if (rc != ECORE_SUCCESS)
1310 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1312 if (rc != ECORE_SUCCESS)
1316 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1317 init_data.cid = ecore_spq_get_cid(p_hwfn);
1318 init_data.opaque_fid = opaque_fid;
1319 init_data.comp_mode = comp_mode;
1320 init_data.p_comp_data = p_comp_data;
1322 rc = ecore_sp_init_request(p_hwfn, pp_ent,
1323 ETH_RAMROD_FILTERS_UPDATE,
1324 PROTOCOLID_ETH, &init_data);
1325 if (rc != ECORE_SUCCESS)
1328 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1329 p_ramrod = *pp_ramrod;
1330 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1331 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1334 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1335 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1336 "Non-Asic - prevent Tx filters\n");
1337 p_ramrod->filter_cmd_hdr.tx = 0;
1341 switch (p_filter_cmd->opcode) {
1342 case ECORE_FILTER_REPLACE:
1343 case ECORE_FILTER_MOVE:
1344 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1347 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1351 p_first_filter = &p_ramrod->filter_cmds[0];
1352 p_second_filter = &p_ramrod->filter_cmds[1];
1354 switch (p_filter_cmd->type) {
1355 case ECORE_FILTER_MAC:
1356 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1358 case ECORE_FILTER_VLAN:
1359 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1361 case ECORE_FILTER_MAC_VLAN:
1362 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1364 case ECORE_FILTER_INNER_MAC:
1365 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1367 case ECORE_FILTER_INNER_VLAN:
1368 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1370 case ECORE_FILTER_INNER_PAIR:
1371 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1373 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1374 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1376 case ECORE_FILTER_MAC_VNI_PAIR:
1377 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1379 case ECORE_FILTER_VNI:
1380 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1382 case ECORE_FILTER_UNUSED: /* @DPDK */
1383 p_first_filter->type = MAX_ETH_FILTER_TYPE;
1387 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1388 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1389 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1390 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1391 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1392 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1393 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1394 &p_first_filter->mac_mid,
1395 &p_first_filter->mac_lsb,
1396 (u8 *)p_filter_cmd->mac);
1398 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1399 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1400 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1401 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1402 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1404 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1405 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1406 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1407 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1409 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1410 p_second_filter->type = p_first_filter->type;
1411 p_second_filter->mac_msb = p_first_filter->mac_msb;
1412 p_second_filter->mac_mid = p_first_filter->mac_mid;
1413 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1414 p_second_filter->vlan_id = p_first_filter->vlan_id;
1415 p_second_filter->vni = p_first_filter->vni;
1417 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1419 p_first_filter->vport_id = vport_to_remove_from;
1421 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1422 p_second_filter->vport_id = vport_to_add_to;
1423 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1424 p_first_filter->vport_id = vport_to_add_to;
1425 OSAL_MEMCPY(p_second_filter, p_first_filter,
1426 sizeof(*p_second_filter));
1427 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1428 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1430 action = ecore_filter_action(p_filter_cmd->opcode);
1432 if (action == MAX_ETH_FILTER_ACTION) {
1433 DP_NOTICE(p_hwfn, true,
1434 "%d is not supported yet\n",
1435 p_filter_cmd->opcode);
1436 return ECORE_NOTIMPL;
1439 p_first_filter->action = action;
1440 p_first_filter->vport_id =
1441 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1442 vport_to_remove_from : vport_to_add_to;
1445 return ECORE_SUCCESS;
1448 enum _ecore_status_t
1449 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1451 struct ecore_filter_ucast *p_filter_cmd,
1452 enum spq_mode comp_mode,
1453 struct ecore_spq_comp_cb *p_comp_data)
1455 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1456 struct ecore_spq_entry *p_ent = OSAL_NULL;
1457 struct eth_filter_cmd_header *p_header;
1458 enum _ecore_status_t rc;
1460 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1462 comp_mode, p_comp_data);
1463 if (rc != ECORE_SUCCESS) {
1464 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1467 p_header = &p_ramrod->filter_cmd_hdr;
1468 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1470 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1471 if (rc != ECORE_SUCCESS) {
1472 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1476 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1477 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1478 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1479 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1481 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1482 "MOVE" : "REPLACE")),
1483 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1484 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1485 "VLAN" : "MAC & VLAN"),
1486 p_ramrod->filter_cmd_hdr.cmd_cnt,
1487 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1488 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1489 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1490 p_filter_cmd->vport_to_add_to,
1491 p_filter_cmd->vport_to_remove_from,
1492 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1493 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1494 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1495 p_filter_cmd->vlan);
1497 return ECORE_SUCCESS;
1500 /*******************************************************************************
1502 * Calculates crc 32 on a buffer
1503 * Note: crc32_length MUST be aligned to 8
1505 ******************************************************************************/
1506 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1507 u32 crc32_length, u32 crc32_seed, u8 complement)
1509 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1510 u8 msb = 0, current_byte = 0;
1512 if ((crc32_packet == OSAL_NULL) ||
1513 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1514 return crc32_result;
1517 for (byte = 0; byte < crc32_length; byte++) {
1518 current_byte = crc32_packet[byte];
1519 for (bit = 0; bit < 8; bit++) {
1520 msb = (u8)(crc32_result >> 31);
1521 crc32_result = crc32_result << 1;
1522 if (msb != (0x1 & (current_byte >> bit))) {
1523 crc32_result = crc32_result ^ CRC32_POLY;
1529 return crc32_result;
1532 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1534 u32 packet_buf[2] = { 0 };
1536 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1537 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1540 u8 ecore_mcast_bin_from_mac(u8 *mac)
1542 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1548 static enum _ecore_status_t
1549 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1551 struct ecore_filter_mcast *p_filter_cmd,
1552 enum spq_mode comp_mode,
1553 struct ecore_spq_comp_cb *p_comp_data)
1555 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1556 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1557 struct ecore_spq_entry *p_ent = OSAL_NULL;
1558 struct ecore_sp_init_data init_data;
1559 u8 abs_vport_id = 0;
1560 enum _ecore_status_t rc;
1563 if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1564 rc = ecore_fw_vport(p_hwfn,
1565 p_filter_cmd->vport_to_add_to,
1568 rc = ecore_fw_vport(p_hwfn,
1569 p_filter_cmd->vport_to_remove_from,
1571 if (rc != ECORE_SUCCESS)
1575 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1576 init_data.cid = ecore_spq_get_cid(p_hwfn);
1577 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1578 init_data.comp_mode = comp_mode;
1579 init_data.p_comp_data = p_comp_data;
1581 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1582 ETH_RAMROD_VPORT_UPDATE,
1583 PROTOCOLID_ETH, &init_data);
1584 if (rc != ECORE_SUCCESS) {
1585 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1589 p_ramrod = &p_ent->ramrod.vport_update;
1590 p_ramrod->common.update_approx_mcast_flg = 1;
1592 /* explicitly clear out the entire vector */
1593 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1594 0, sizeof(p_ramrod->approx_mcast.bins));
1595 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1596 ETH_MULTICAST_MAC_BINS_IN_REGS);
1597 /* filter ADD op is explicit set op and it removes
1598 * any existing filters for the vport.
1600 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1601 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1604 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1605 OSAL_SET_BIT(bit, bins);
1608 /* Convert to correct endianity */
1609 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1610 struct vport_update_ramrod_mcast *p_ramrod_bins;
1611 u32 *p_bins = (u32 *)bins;
1613 p_ramrod_bins = &p_ramrod->approx_mcast;
1614 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1618 p_ramrod->common.vport_id = abs_vport_id;
1620 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1621 if (rc != ECORE_SUCCESS)
1622 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1627 enum _ecore_status_t
1628 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1629 struct ecore_filter_mcast *p_filter_cmd,
1630 enum spq_mode comp_mode,
1631 struct ecore_spq_comp_cb *p_comp_data)
1633 enum _ecore_status_t rc = ECORE_SUCCESS;
1636 /* only ADD and REMOVE operations are supported for multi-cast */
1637 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1638 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1639 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1643 for_each_hwfn(p_dev, i) {
1644 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1648 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1652 opaque_fid = p_hwfn->hw_info.opaque_fid;
1653 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1656 comp_mode, p_comp_data);
1657 if (rc != ECORE_SUCCESS)
1664 enum _ecore_status_t
1665 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1666 struct ecore_filter_ucast *p_filter_cmd,
1667 enum spq_mode comp_mode,
1668 struct ecore_spq_comp_cb *p_comp_data)
1670 enum _ecore_status_t rc = ECORE_SUCCESS;
1673 for_each_hwfn(p_dev, i) {
1674 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1678 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1682 opaque_fid = p_hwfn->hw_info.opaque_fid;
1683 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1686 comp_mode, p_comp_data);
1687 if (rc != ECORE_SUCCESS)
1694 /* Statistics related code */
1695 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1696 u32 *p_addr, u32 *p_len,
1699 if (IS_PF(p_hwfn->p_dev)) {
1700 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1701 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1702 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1704 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1705 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1707 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1708 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1712 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1713 struct ecore_ptt *p_ptt,
1714 struct ecore_eth_stats *p_stats,
1717 struct eth_pstorm_per_queue_stat pstats;
1718 u32 pstats_addr = 0, pstats_len = 0;
1720 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1723 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1724 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1726 p_stats->common.tx_ucast_bytes +=
1727 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1728 p_stats->common.tx_mcast_bytes +=
1729 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1730 p_stats->common.tx_bcast_bytes +=
1731 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1732 p_stats->common.tx_ucast_pkts +=
1733 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1734 p_stats->common.tx_mcast_pkts +=
1735 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1736 p_stats->common.tx_bcast_pkts +=
1737 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1738 p_stats->common.tx_err_drop_pkts +=
1739 HILO_64_REGPAIR(pstats.error_drop_pkts);
1742 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1743 struct ecore_ptt *p_ptt,
1744 struct ecore_eth_stats *p_stats,
1747 struct tstorm_per_port_stat tstats;
1748 u32 tstats_addr, tstats_len;
1750 if (IS_PF(p_hwfn->p_dev)) {
1751 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1752 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1753 tstats_len = sizeof(struct tstorm_per_port_stat);
1755 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1756 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1758 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1759 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1762 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1763 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1765 p_stats->common.mftag_filter_discards +=
1766 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1767 p_stats->common.mac_filter_discards +=
1768 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1771 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1772 u32 *p_addr, u32 *p_len,
1775 if (IS_PF(p_hwfn->p_dev)) {
1776 *p_addr = BAR0_MAP_REG_USDM_RAM +
1777 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1778 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1780 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1781 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1783 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1784 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1788 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1789 struct ecore_ptt *p_ptt,
1790 struct ecore_eth_stats *p_stats,
1793 struct eth_ustorm_per_queue_stat ustats;
1794 u32 ustats_addr = 0, ustats_len = 0;
1796 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1799 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1800 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1802 p_stats->common.rx_ucast_bytes +=
1803 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1804 p_stats->common.rx_mcast_bytes +=
1805 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1806 p_stats->common.rx_bcast_bytes +=
1807 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1808 p_stats->common.rx_ucast_pkts +=
1809 HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1810 p_stats->common.rx_mcast_pkts +=
1811 HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1812 p_stats->common.rx_bcast_pkts +=
1813 HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1816 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1817 u32 *p_addr, u32 *p_len,
1820 if (IS_PF(p_hwfn->p_dev)) {
1821 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1822 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1823 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1825 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1826 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1828 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1829 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1833 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1834 struct ecore_ptt *p_ptt,
1835 struct ecore_eth_stats *p_stats,
1838 struct eth_mstorm_per_queue_stat mstats;
1839 u32 mstats_addr = 0, mstats_len = 0;
1841 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1844 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1845 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1847 p_stats->common.no_buff_discards +=
1848 HILO_64_REGPAIR(mstats.no_buff_discard);
1849 p_stats->common.packet_too_big_discard +=
1850 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1851 p_stats->common.ttl0_discard +=
1852 HILO_64_REGPAIR(mstats.ttl0_discard);
1853 p_stats->common.tpa_coalesced_pkts +=
1854 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1855 p_stats->common.tpa_coalesced_events +=
1856 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1857 p_stats->common.tpa_aborts_num +=
1858 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1859 p_stats->common.tpa_coalesced_bytes +=
1860 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1863 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1864 struct ecore_ptt *p_ptt,
1865 struct ecore_eth_stats *p_stats)
1867 struct ecore_eth_stats_common *p_common = &p_stats->common;
1868 struct port_stats port_stats;
1871 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1873 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1874 p_hwfn->mcp_info->port_addr +
1875 OFFSETOF(struct public_port, stats),
1876 sizeof(port_stats));
1878 p_common->rx_64_byte_packets += port_stats.eth.r64;
1879 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1880 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1881 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1882 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1883 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1884 p_common->rx_crc_errors += port_stats.eth.rfcs;
1885 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1886 p_common->rx_pause_frames += port_stats.eth.rxpf;
1887 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1888 p_common->rx_align_errors += port_stats.eth.raln;
1889 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1890 p_common->rx_oversize_packets += port_stats.eth.rovr;
1891 p_common->rx_jabbers += port_stats.eth.rjbr;
1892 p_common->rx_undersize_packets += port_stats.eth.rund;
1893 p_common->rx_fragments += port_stats.eth.rfrg;
1894 p_common->tx_64_byte_packets += port_stats.eth.t64;
1895 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1896 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1897 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1898 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1899 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1900 p_common->tx_pause_frames += port_stats.eth.txpf;
1901 p_common->tx_pfc_frames += port_stats.eth.txpp;
1902 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1903 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1904 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1905 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1906 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1907 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1908 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1909 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1910 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1911 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
1912 for (j = 0; j < 8; j++) {
1913 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1914 p_common->brb_discards += port_stats.brb.brb_discard[j];
1917 if (ECORE_IS_BB(p_hwfn->p_dev)) {
1918 struct ecore_eth_stats_bb *p_bb = &p_stats->bb;
1920 p_bb->rx_1519_to_1522_byte_packets +=
1921 port_stats.eth.u0.bb0.r1522;
1922 p_bb->rx_1519_to_2047_byte_packets +=
1923 port_stats.eth.u0.bb0.r2047;
1924 p_bb->rx_2048_to_4095_byte_packets +=
1925 port_stats.eth.u0.bb0.r4095;
1926 p_bb->rx_4096_to_9216_byte_packets +=
1927 port_stats.eth.u0.bb0.r9216;
1928 p_bb->rx_9217_to_16383_byte_packets +=
1929 port_stats.eth.u0.bb0.r16383;
1930 p_bb->tx_1519_to_2047_byte_packets +=
1931 port_stats.eth.u1.bb1.t2047;
1932 p_bb->tx_2048_to_4095_byte_packets +=
1933 port_stats.eth.u1.bb1.t4095;
1934 p_bb->tx_4096_to_9216_byte_packets +=
1935 port_stats.eth.u1.bb1.t9216;
1936 p_bb->tx_9217_to_16383_byte_packets +=
1937 port_stats.eth.u1.bb1.t16383;
1938 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1939 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1941 struct ecore_eth_stats_ah *p_ah = &p_stats->ah;
1943 p_ah->rx_1519_to_max_byte_packets +=
1944 port_stats.eth.u0.ah0.r1519_to_max;
1945 p_ah->tx_1519_to_max_byte_packets =
1946 port_stats.eth.u1.ah1.t1519_to_max;
1950 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1951 struct ecore_ptt *p_ptt,
1952 struct ecore_eth_stats *stats,
1953 u16 statistics_bin, bool b_get_port_stats)
1955 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1956 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1957 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1958 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1961 /* Avoid getting PORT stats for emulation. */
1962 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1966 if (b_get_port_stats && p_hwfn->mcp_info)
1967 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1970 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1971 struct ecore_eth_stats *stats)
1976 OSAL_MEMSET(stats, 0, sizeof(*stats));
1978 for_each_hwfn(p_dev, i) {
1979 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1980 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1981 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1984 /* The main vport index is relative first */
1985 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1986 DP_ERR(p_hwfn, "No vport available!\n");
1991 if (IS_PF(p_dev) && !p_ptt) {
1992 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1996 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1997 IS_PF(p_dev) ? true : false);
2000 if (IS_PF(p_dev) && p_ptt)
2001 ecore_ptt_release(p_hwfn, p_ptt);
2005 void ecore_get_vport_stats(struct ecore_dev *p_dev,
2006 struct ecore_eth_stats *stats)
2011 OSAL_MEMSET(stats, 0, sizeof(*stats));
2015 _ecore_get_vport_stats(p_dev, stats);
2017 if (!p_dev->reset_stats)
2020 /* Reduce the statistics baseline */
2021 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
2022 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
2025 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
2026 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
2030 for_each_hwfn(p_dev, i) {
2031 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2032 struct eth_mstorm_per_queue_stat mstats;
2033 struct eth_ustorm_per_queue_stat ustats;
2034 struct eth_pstorm_per_queue_stat pstats;
2035 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
2036 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
2037 u32 addr = 0, len = 0;
2039 if (IS_PF(p_dev) && !p_ptt) {
2040 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
2044 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
2045 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
2046 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
2048 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
2049 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
2050 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
2052 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
2053 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
2054 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
2057 ecore_ptt_release(p_hwfn, p_ptt);
2060 /* PORT statistics are not necessarily reset, so we need to
2061 * read and create a baseline for future statistics.
2063 if (!p_dev->reset_stats)
2064 DP_INFO(p_dev, "Reset stats not allocated\n");
2066 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
2069 void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
2070 struct ecore_ptt *p_ptt,
2071 struct ecore_arfs_config_params *p_cfg_params)
2073 if (p_cfg_params->arfs_enable) {
2074 ecore_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2078 p_cfg_params->ipv6);
2079 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2080 "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
2081 p_cfg_params->tcp ? "Enable" : "Disable",
2082 p_cfg_params->udp ? "Enable" : "Disable",
2083 p_cfg_params->ipv4 ? "Enable" : "Disable",
2084 p_cfg_params->ipv6 ? "Enable" : "Disable");
2086 ecore_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2088 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n",
2089 p_cfg_params->arfs_enable ? "Enable" : "Disable");
2092 enum _ecore_status_t
2093 ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn,
2094 struct ecore_ptt *p_ptt,
2095 struct ecore_spq_comp_cb *p_cb,
2096 dma_addr_t p_addr, u16 length,
2097 u16 qid, u8 vport_id,
2100 struct rx_update_gft_filter_data *p_ramrod = OSAL_NULL;
2101 struct ecore_spq_entry *p_ent = OSAL_NULL;
2102 struct ecore_sp_init_data init_data;
2103 u16 abs_rx_q_id = 0;
2104 u8 abs_vport_id = 0;
2105 enum _ecore_status_t rc = ECORE_NOTIMPL;
2107 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
2108 if (rc != ECORE_SUCCESS)
2111 rc = ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
2112 if (rc != ECORE_SUCCESS)
2116 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
2117 init_data.cid = ecore_spq_get_cid(p_hwfn);
2119 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2122 init_data.comp_mode = ECORE_SPQ_MODE_CB;
2123 init_data.p_comp_data = p_cb;
2125 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
2128 rc = ecore_sp_init_request(p_hwfn, &p_ent,
2129 ETH_RAMROD_GFT_UPDATE_FILTER,
2130 PROTOCOLID_ETH, &init_data);
2131 if (rc != ECORE_SUCCESS)
2134 p_ramrod = &p_ent->ramrod.rx_update_gft;
2136 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
2137 p_ramrod->pkt_hdr_length = OSAL_CPU_TO_LE16(length);
2138 p_ramrod->rx_qid_or_action_icid = OSAL_CPU_TO_LE16(abs_rx_q_id);
2139 p_ramrod->vport_id = abs_vport_id;
2140 p_ramrod->filter_type = RFS_FILTER_TYPE;
2141 p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER
2142 : GFT_DELETE_FILTER;
2144 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2145 "V[%0x], Q[%04x] - %s filter from 0x%lx [length %04xb]\n",
2146 abs_vport_id, abs_rx_q_id,
2147 b_is_add ? "Adding" : "Removing",
2148 (unsigned long)p_addr, length);
2150 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);