2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
23 #include "ecore_sp_commands.h"
24 #include "ecore_cxt.h"
26 #define CHIP_MCP_RESP_ITER_US 10
27 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
29 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
30 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
32 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
33 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
36 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
37 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
39 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
40 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
41 OFFSETOF(struct public_drv_mb, _field), _val)
43 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
44 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
45 OFFSETOF(struct public_drv_mb, _field))
47 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
48 DRV_ID_PDA_COMP_VER_OFFSET)
50 #define MCP_BYTES_PER_MBIT_OFFSET 17
54 static int loaded_port[MAX_NUM_PORTS] = { 0 };
57 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
59 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
64 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
66 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
68 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
70 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
72 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
73 "port_addr = 0x%x, port_id 0x%02x\n",
74 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
77 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
79 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
84 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
88 if (!p_hwfn->mcp_info->public_base)
91 for (i = 0; i < length; i++) {
92 tmp = ecore_rd(p_hwfn, p_ptt,
93 p_hwfn->mcp_info->mfw_mb_addr +
94 (i << 2) + sizeof(u32));
96 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
97 OSAL_BE32_TO_CPU(tmp);
101 struct ecore_mcp_cmd_elem {
102 osal_list_entry_t list;
103 struct ecore_mcp_mb_params *p_mb_params;
104 u16 expected_seq_num;
108 /* Must be called while cmd_lock is acquired */
109 static struct ecore_mcp_cmd_elem *
110 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
111 struct ecore_mcp_mb_params *p_mb_params,
112 u16 expected_seq_num)
114 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
116 p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
117 sizeof(*p_cmd_elem));
119 DP_NOTICE(p_hwfn, false,
120 "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
124 p_cmd_elem->p_mb_params = p_mb_params;
125 p_cmd_elem->expected_seq_num = expected_seq_num;
126 OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
131 /* Must be called while cmd_lock is acquired */
132 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
133 struct ecore_mcp_cmd_elem *p_cmd_elem)
135 OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
136 OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
139 /* Must be called while cmd_lock is acquired */
140 static struct ecore_mcp_cmd_elem *
141 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
143 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
145 OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
146 struct ecore_mcp_cmd_elem) {
147 if (p_cmd_elem->expected_seq_num == seq_num)
154 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
156 if (p_hwfn->mcp_info) {
157 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
159 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
160 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
161 &p_hwfn->mcp_info->cmd_list, list,
162 struct ecore_mcp_cmd_elem) {
163 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
165 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
167 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
168 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
169 #ifdef CONFIG_ECORE_LOCK_ALLOC
170 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
171 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
175 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
177 return ECORE_SUCCESS;
180 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
181 struct ecore_ptt *p_ptt)
183 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
184 u32 drv_mb_offsize, mfw_mb_offsize;
185 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
188 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
189 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
190 p_info->public_base = 0;
195 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
196 if (!p_info->public_base)
199 p_info->public_base |= GRCBASE_MCP;
201 /* Calculate the driver and MFW mailbox address */
202 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
203 SECTION_OFFSIZE_ADDR(p_info->public_base,
205 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
206 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
207 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
208 " mcp_pf_id = 0x%x\n",
209 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
211 /* Set the MFW MB address */
212 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
213 SECTION_OFFSIZE_ADDR(p_info->public_base,
215 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
216 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
217 p_info->mfw_mb_addr);
219 /* Get the current driver mailbox sequence before sending
222 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
223 DRV_MSG_SEQ_NUMBER_MASK;
225 /* Get current FW pulse sequence */
226 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
229 p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
231 return ECORE_SUCCESS;
234 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
235 struct ecore_ptt *p_ptt)
237 struct ecore_mcp_info *p_info;
240 /* Allocate mcp_info structure */
241 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
242 sizeof(*p_hwfn->mcp_info));
243 if (!p_hwfn->mcp_info)
245 p_info = p_hwfn->mcp_info;
247 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
248 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
249 /* Do not free mcp_info here, since public_base indicate that
250 * the MCP is not initialized
252 return ECORE_SUCCESS;
255 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
256 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
257 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
258 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
261 /* Initialize the MFW spinlocks */
262 #ifdef CONFIG_ECORE_LOCK_ALLOC
263 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
264 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
266 OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
267 OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
269 OSAL_LIST_INIT(&p_info->cmd_list);
271 return ECORE_SUCCESS;
274 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
275 ecore_mcp_free(p_hwfn);
279 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
280 struct ecore_ptt *p_ptt)
282 u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
284 /* Use MCP history register to check if MCP reset occurred between init
287 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
288 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
289 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
290 p_hwfn->mcp_info->mcp_hist, generic_por_0);
292 ecore_load_mcp_offsets(p_hwfn, p_ptt);
293 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
297 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
298 struct ecore_ptt *p_ptt)
300 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
301 enum _ecore_status_t rc = ECORE_SUCCESS;
304 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
305 delay = EMUL_MCP_RESP_ITER_US;
308 if (p_hwfn->mcp_info->b_block_cmd) {
309 DP_NOTICE(p_hwfn, false,
310 "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
311 return ECORE_ABORTED;
314 /* Ensure that only a single thread is accessing the mailbox */
315 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
317 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
319 /* Set drv command along with the updated sequence */
320 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
321 seq = ++p_hwfn->mcp_info->drv_mb_seq;
322 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
325 /* Wait for MFW response */
327 /* Give the FW up to 500 second (50*1000*10usec) */
328 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
329 MISCS_REG_GENERIC_POR_0)) &&
330 (cnt++ < ECORE_MCP_RESET_RETRIES));
332 if (org_mcp_reset_seq !=
333 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
334 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
335 "MCP was reset after %d usec\n", cnt * delay);
337 DP_ERR(p_hwfn, "Failed to reset MCP\n");
341 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
346 /* Must be called while cmd_lock is acquired */
347 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
349 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
351 /* There is at most one pending command at a certain time, and if it
352 * exists - it is placed at the HEAD of the list.
354 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
355 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
356 struct ecore_mcp_cmd_elem,
358 return !p_cmd_elem->b_is_completed;
364 /* Must be called while cmd_lock is acquired */
365 static enum _ecore_status_t
366 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
368 struct ecore_mcp_mb_params *p_mb_params;
369 struct ecore_mcp_cmd_elem *p_cmd_elem;
373 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
374 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
376 /* Return if no new non-handled response has been received */
377 if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
380 p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
383 "Failed to find a pending mailbox cmd that expects sequence number %d\n",
385 return ECORE_UNKNOWN_ERROR;
388 p_mb_params = p_cmd_elem->p_mb_params;
390 /* Get the MFW response along with the sequence number */
391 p_mb_params->mcp_resp = mcp_resp;
393 /* Get the MFW param */
394 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
396 /* Get the union data */
397 if (p_mb_params->p_data_dst != OSAL_NULL &&
398 p_mb_params->data_dst_size) {
399 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
400 OFFSETOF(struct public_drv_mb,
402 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
403 union_data_addr, p_mb_params->data_dst_size);
406 p_cmd_elem->b_is_completed = true;
408 return ECORE_SUCCESS;
411 /* Must be called while cmd_lock is acquired */
412 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
413 struct ecore_ptt *p_ptt,
414 struct ecore_mcp_mb_params *p_mb_params,
417 union drv_union_data union_data;
420 /* Set the union data */
421 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
422 OFFSETOF(struct public_drv_mb, union_data);
423 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
424 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
425 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
426 p_mb_params->data_src_size);
427 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
430 /* Set the drv param */
431 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
433 /* Set the drv command along with the sequence number */
434 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
436 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
437 "MFW mailbox: command 0x%08x param 0x%08x\n",
438 (p_mb_params->cmd | seq_num), p_mb_params->param);
441 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
444 p_hwfn->mcp_info->b_block_cmd = block_cmd;
446 DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
447 block_cmd ? "Block" : "Unblock");
450 static enum _ecore_status_t
451 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
452 struct ecore_mcp_mb_params *p_mb_params,
453 u32 max_retries, u32 delay)
455 struct ecore_mcp_cmd_elem *p_cmd_elem;
458 enum _ecore_status_t rc = ECORE_SUCCESS;
460 /* Wait until the mailbox is non-occupied */
462 /* Exit the loop if there is no pending command, or if the
463 * pending command is completed during this iteration.
464 * The spinlock stays locked until the command is sent.
467 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
469 if (!ecore_mcp_has_pending_cmd(p_hwfn))
472 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
473 if (rc == ECORE_SUCCESS)
475 else if (rc != ECORE_AGAIN)
478 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
480 } while (++cnt < max_retries);
482 if (cnt >= max_retries) {
483 DP_NOTICE(p_hwfn, false,
484 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
485 p_mb_params->cmd, p_mb_params->param);
489 /* Send the mailbox command */
490 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
491 seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
492 p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
498 __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
499 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
501 /* Wait for the MFW response */
503 /* Exit the loop if the command is already completed, or if the
504 * command is completed during this iteration.
505 * The spinlock stays locked until the list element is removed.
509 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
511 if (p_cmd_elem->b_is_completed)
514 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
515 if (rc == ECORE_SUCCESS)
517 else if (rc != ECORE_AGAIN)
520 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
521 } while (++cnt < max_retries);
523 if (cnt >= max_retries) {
524 DP_NOTICE(p_hwfn, false,
525 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
526 p_mb_params->cmd, p_mb_params->param);
528 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
529 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
530 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
532 ecore_mcp_cmd_set_blocking(p_hwfn, true);
533 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
537 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
538 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
540 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
541 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
542 p_mb_params->mcp_resp, p_mb_params->mcp_param,
543 (cnt * delay) / 1000, (cnt * delay) % 1000);
545 /* Clear the sequence number from the MFW response */
546 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
548 return ECORE_SUCCESS;
551 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
555 static enum _ecore_status_t
556 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
557 struct ecore_ptt *p_ptt,
558 struct ecore_mcp_mb_params *p_mb_params)
560 osal_size_t union_data_size = sizeof(union drv_union_data);
561 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
562 u32 delay = CHIP_MCP_RESP_ITER_US;
565 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
566 delay = EMUL_MCP_RESP_ITER_US;
567 /* There is a built-in delay of 100usec in each MFW response read */
568 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
572 /* MCP not initialized */
573 if (!ecore_mcp_is_init(p_hwfn)) {
574 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
578 if (p_mb_params->data_src_size > union_data_size ||
579 p_mb_params->data_dst_size > union_data_size) {
581 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
582 p_mb_params->data_src_size, p_mb_params->data_dst_size,
587 if (p_hwfn->mcp_info->b_block_cmd) {
588 DP_NOTICE(p_hwfn, false,
589 "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
590 p_mb_params->cmd, p_mb_params->param);
591 return ECORE_ABORTED;
594 return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
598 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
599 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
600 u32 *o_mcp_resp, u32 *o_mcp_param)
602 struct ecore_mcp_mb_params mb_params;
603 enum _ecore_status_t rc;
606 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
607 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
609 loaded_port[p_hwfn->port_id]--;
610 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
613 return ECORE_SUCCESS;
617 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
619 mb_params.param = param;
620 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
621 if (rc != ECORE_SUCCESS)
624 *o_mcp_resp = mb_params.mcp_resp;
625 *o_mcp_param = mb_params.mcp_param;
627 return ECORE_SUCCESS;
630 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
631 struct ecore_ptt *p_ptt,
636 u32 i_txn_size, u32 *i_buf)
638 struct ecore_mcp_mb_params mb_params;
639 enum _ecore_status_t rc;
641 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
643 mb_params.param = param;
644 mb_params.p_data_src = i_buf;
645 mb_params.data_src_size = (u8)i_txn_size;
646 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
647 if (rc != ECORE_SUCCESS)
650 *o_mcp_resp = mb_params.mcp_resp;
651 *o_mcp_param = mb_params.mcp_param;
653 return ECORE_SUCCESS;
656 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
657 struct ecore_ptt *p_ptt,
662 u32 *o_txn_size, u32 *o_buf)
664 struct ecore_mcp_mb_params mb_params;
665 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
666 enum _ecore_status_t rc;
668 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
670 mb_params.param = param;
671 mb_params.p_data_dst = raw_data;
673 /* Use the maximal value since the actual one is part of the response */
674 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
676 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
677 if (rc != ECORE_SUCCESS)
680 *o_mcp_resp = mb_params.mcp_resp;
681 *o_mcp_param = mb_params.mcp_param;
683 *o_txn_size = *o_mcp_param;
685 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
687 return ECORE_SUCCESS;
691 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
694 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
697 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
698 else if (!loaded_port[p_hwfn->port_id])
699 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
701 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
703 /* On CMT, always tell that it's engine */
704 if (ECORE_IS_CMT(p_hwfn->p_dev))
705 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
707 *p_load_code = load_phase;
709 loaded_port[p_hwfn->port_id]++;
711 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
712 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
713 *p_load_code, loaded, p_hwfn->port_id,
714 loaded_port[p_hwfn->port_id]);
719 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
720 enum ecore_override_force_load override_force_load)
722 bool can_force_load = false;
724 switch (override_force_load) {
725 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
726 can_force_load = true;
728 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
729 can_force_load = false;
732 can_force_load = (drv_role == DRV_ROLE_OS &&
733 exist_drv_role == DRV_ROLE_PREBOOT) ||
734 (drv_role == DRV_ROLE_KDUMP &&
735 exist_drv_role == DRV_ROLE_OS);
739 return can_force_load;
742 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
743 struct ecore_ptt *p_ptt)
745 u32 resp = 0, param = 0;
746 enum _ecore_status_t rc;
748 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
750 if (rc != ECORE_SUCCESS)
751 DP_NOTICE(p_hwfn, false,
752 "Failed to send cancel load request, rc = %d\n", rc);
757 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
758 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
759 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
760 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
761 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
762 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
763 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
765 static u32 ecore_get_config_bitmap(void)
767 u32 config_bitmap = 0x0;
769 #ifdef CONFIG_ECORE_L2
770 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
772 #ifdef CONFIG_ECORE_SRIOV
773 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
775 #ifdef CONFIG_ECORE_ROCE
776 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
778 #ifdef CONFIG_ECORE_IWARP
779 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
781 #ifdef CONFIG_ECORE_FCOE
782 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
784 #ifdef CONFIG_ECORE_ISCSI
785 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
787 #ifdef CONFIG_ECORE_LL2
788 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
791 return config_bitmap;
794 struct ecore_load_req_in_params {
796 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
797 #define ECORE_LOAD_REQ_HSI_VER_1 1
804 bool avoid_eng_reset;
807 struct ecore_load_req_out_params {
817 static enum _ecore_status_t
818 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
819 struct ecore_load_req_in_params *p_in_params,
820 struct ecore_load_req_out_params *p_out_params)
822 struct ecore_mcp_mb_params mb_params;
823 struct load_req_stc load_req;
824 struct load_rsp_stc load_rsp;
826 enum _ecore_status_t rc;
828 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
829 load_req.drv_ver_0 = p_in_params->drv_ver_0;
830 load_req.drv_ver_1 = p_in_params->drv_ver_1;
831 load_req.fw_ver = p_in_params->fw_ver;
832 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
833 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
834 p_in_params->timeout_val);
835 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
836 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
837 p_in_params->avoid_eng_reset);
839 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
840 DRV_ID_MCP_HSI_VER_CURRENT :
841 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
843 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
844 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
845 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
846 mb_params.p_data_src = &load_req;
847 mb_params.data_src_size = sizeof(load_req);
848 mb_params.p_data_dst = &load_rsp;
849 mb_params.data_dst_size = sizeof(load_rsp);
851 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
852 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
854 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
855 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
856 GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
857 GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
859 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
860 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
861 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
862 load_req.drv_ver_0, load_req.drv_ver_1,
863 load_req.fw_ver, load_req.misc0,
864 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
865 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
866 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
867 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
869 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
870 if (rc != ECORE_SUCCESS) {
871 DP_NOTICE(p_hwfn, false,
872 "Failed to send load request, rc = %d\n", rc);
876 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
877 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
878 p_out_params->load_code = mb_params.mcp_resp;
880 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
881 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
882 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
883 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
884 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
885 load_rsp.fw_ver, load_rsp.misc0,
886 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
887 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
888 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
890 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
891 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
892 p_out_params->exist_fw_ver = load_rsp.fw_ver;
893 p_out_params->exist_drv_role =
894 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
895 p_out_params->mfw_hsi_ver =
896 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
897 p_out_params->drv_exists =
898 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
899 LOAD_RSP_FLAGS0_DRV_EXISTS;
902 return ECORE_SUCCESS;
905 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
909 case ECORE_DRV_ROLE_OS:
910 *p_mfw_drv_role = DRV_ROLE_OS;
912 case ECORE_DRV_ROLE_KDUMP:
913 *p_mfw_drv_role = DRV_ROLE_KDUMP;
918 enum ecore_load_req_force {
919 ECORE_LOAD_REQ_FORCE_NONE,
920 ECORE_LOAD_REQ_FORCE_PF,
921 ECORE_LOAD_REQ_FORCE_ALL,
924 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
928 case ECORE_LOAD_REQ_FORCE_NONE:
929 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
931 case ECORE_LOAD_REQ_FORCE_PF:
932 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
934 case ECORE_LOAD_REQ_FORCE_ALL:
935 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
940 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
941 struct ecore_ptt *p_ptt,
942 struct ecore_load_req_params *p_params)
944 struct ecore_load_req_out_params out_params;
945 struct ecore_load_req_in_params in_params;
946 u8 mfw_drv_role = 0, mfw_force_cmd;
947 enum _ecore_status_t rc;
950 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
951 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
952 return ECORE_SUCCESS;
956 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
957 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
958 in_params.drv_ver_0 = ECORE_VERSION;
959 in_params.drv_ver_1 = ecore_get_config_bitmap();
960 in_params.fw_ver = STORM_FW_VERSION;
961 ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
962 in_params.drv_role = mfw_drv_role;
963 in_params.timeout_val = p_params->timeout_val;
964 ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
965 in_params.force_cmd = mfw_force_cmd;
966 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
968 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
969 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
970 if (rc != ECORE_SUCCESS)
973 /* First handle cases where another load request should/might be sent:
974 * - MFW expects the old interface [HSI version = 1]
975 * - MFW responds that a force load request is required
977 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
979 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
981 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
982 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
983 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
985 if (rc != ECORE_SUCCESS)
987 } else if (out_params.load_code ==
988 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
989 if (ecore_mcp_can_force_load(in_params.drv_role,
990 out_params.exist_drv_role,
991 p_params->override_force_load)) {
993 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
994 in_params.drv_role, in_params.fw_ver,
995 in_params.drv_ver_0, in_params.drv_ver_1,
996 out_params.exist_drv_role,
997 out_params.exist_fw_ver,
998 out_params.exist_drv_ver_0,
999 out_params.exist_drv_ver_1);
1001 ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1004 in_params.force_cmd = mfw_force_cmd;
1005 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1006 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1008 if (rc != ECORE_SUCCESS)
1011 DP_NOTICE(p_hwfn, false,
1012 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1013 in_params.drv_role, in_params.fw_ver,
1014 in_params.drv_ver_0, in_params.drv_ver_1,
1015 out_params.exist_drv_role,
1016 out_params.exist_fw_ver,
1017 out_params.exist_drv_ver_0,
1018 out_params.exist_drv_ver_1);
1020 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1025 /* Now handle the other types of responses.
1026 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1027 * expected here after the additional revised load requests were sent.
1029 switch (out_params.load_code) {
1030 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1031 case FW_MSG_CODE_DRV_LOAD_PORT:
1032 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1033 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1034 out_params.drv_exists) {
1035 /* The role and fw/driver version match, but the PF is
1036 * already loaded and has not been unloaded gracefully.
1037 * This is unexpected since a quasi-FLR request was
1038 * previously sent as part of ecore_hw_prepare().
1040 DP_NOTICE(p_hwfn, false,
1041 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1046 DP_NOTICE(p_hwfn, false,
1047 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1048 out_params.load_code);
1052 p_params->load_code = out_params.load_code;
1054 return ECORE_SUCCESS;
1057 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1058 struct ecore_ptt *p_ptt)
1060 u32 resp = 0, param = 0;
1061 enum _ecore_status_t rc;
1063 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1065 if (rc != ECORE_SUCCESS) {
1066 DP_NOTICE(p_hwfn, false,
1067 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1071 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1072 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1073 DP_NOTICE(p_hwfn, false,
1074 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1076 return ECORE_SUCCESS;
1079 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1080 struct ecore_ptt *p_ptt)
1082 u32 wol_param, mcp_resp, mcp_param;
1085 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1087 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1088 &mcp_resp, &mcp_param);
1091 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1092 struct ecore_ptt *p_ptt)
1094 struct ecore_mcp_mb_params mb_params;
1095 struct mcp_mac wol_mac;
1097 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1098 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1100 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1103 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1104 struct ecore_ptt *p_ptt)
1106 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1108 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1109 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1110 ECORE_PATH_ID(p_hwfn));
1111 u32 disabled_vfs[VF_MAX_STATIC / 32];
1114 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1115 "Reading Disabled VF information from [offset %08x],"
1116 " path_addr %08x\n",
1117 mfw_path_offsize, path_addr);
1119 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1120 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1122 OFFSETOF(struct public_path,
1125 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1126 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1127 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1130 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1131 OSAL_VF_FLR_UPDATE(p_hwfn);
1134 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1135 struct ecore_ptt *p_ptt,
1138 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1140 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1141 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1143 struct ecore_mcp_mb_params mb_params;
1144 enum _ecore_status_t rc;
1147 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1148 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1149 "Acking VFs [%08x,...,%08x] - %08x\n",
1150 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1152 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1153 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1154 mb_params.p_data_src = vfs_to_ack;
1155 mb_params.data_src_size = VF_MAX_STATIC / 8;
1156 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1158 if (rc != ECORE_SUCCESS) {
1159 DP_NOTICE(p_hwfn, false,
1160 "Failed to pass ACK for VF flr to MFW\n");
1161 return ECORE_TIMEOUT;
1164 /* TMP - clear the ACK bits; should be done by MFW */
1165 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1166 ecore_wr(p_hwfn, p_ptt,
1168 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1169 i * sizeof(u32), 0);
1174 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1175 struct ecore_ptt *p_ptt)
1177 u32 transceiver_state;
1179 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1180 p_hwfn->mcp_info->port_addr +
1181 OFFSETOF(struct public_port,
1184 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1185 "Received transceiver state update [0x%08x] from mfw"
1187 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1188 OFFSETOF(struct public_port,
1189 transceiver_data)));
1191 transceiver_state = GET_MFW_FIELD(transceiver_state,
1192 ETH_TRANSCEIVER_STATE);
1194 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1195 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1197 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1200 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1201 struct ecore_ptt *p_ptt,
1202 struct ecore_mcp_link_state *p_link)
1204 u32 eee_status, val;
1206 p_link->eee_adv_caps = 0;
1207 p_link->eee_lp_adv_caps = 0;
1208 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1209 OFFSETOF(struct public_port, eee_status));
1210 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1211 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1212 if (val & EEE_1G_ADV)
1213 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1214 if (val & EEE_10G_ADV)
1215 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1216 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1217 if (val & EEE_1G_ADV)
1218 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1219 if (val & EEE_10G_ADV)
1220 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1223 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1224 struct ecore_ptt *p_ptt,
1225 struct public_func *p_data,
1228 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1230 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1231 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1234 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1236 size = OSAL_MIN_T(u32, sizeof(*p_data),
1237 SECTION_SIZE(mfw_path_offsize));
1238 for (i = 0; i < size / sizeof(u32); i++)
1239 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1240 func_addr + (i << 2));
1245 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1246 struct ecore_ptt *p_ptt,
1249 struct ecore_mcp_link_state *p_link;
1253 /* Prevent SW/attentions from doing this at the same time */
1254 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1256 p_link = &p_hwfn->mcp_info->link_output;
1257 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1259 status = ecore_rd(p_hwfn, p_ptt,
1260 p_hwfn->mcp_info->port_addr +
1261 OFFSETOF(struct public_port, link_status));
1262 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1263 "Received link update [0x%08x] from mfw"
1265 status, (u32)(p_hwfn->mcp_info->port_addr +
1266 OFFSETOF(struct public_port,
1269 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1270 "Resetting link indications\n");
1274 if (p_hwfn->b_drv_link_init) {
1275 /* Link indication with modern MFW arrives as per-PF
1278 if (p_hwfn->mcp_info->capabilities &
1279 FW_MB_PARAM_FEATURE_SUPPORT_VLINK) {
1280 struct public_func shmem_info;
1282 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1284 p_link->link_up = !!(shmem_info.status &
1285 FUNC_STATUS_VIRTUAL_LINK_UP);
1287 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1290 p_link->link_up = false;
1293 p_link->full_duplex = true;
1294 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1295 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1296 p_link->speed = 100000;
1298 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1299 p_link->speed = 50000;
1301 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1302 p_link->speed = 40000;
1304 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1305 p_link->speed = 25000;
1307 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1308 p_link->speed = 20000;
1310 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1311 p_link->speed = 10000;
1313 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1314 p_link->full_duplex = false;
1316 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1317 p_link->speed = 1000;
1323 /* We never store total line speed as p_link->speed is
1324 * again changes according to bandwidth allocation.
1326 if (p_link->link_up && p_link->speed)
1327 p_link->line_speed = p_link->speed;
1329 p_link->line_speed = 0;
1331 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1332 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1334 /* Max bandwidth configuration */
1335 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1338 /* Mintz bandwidth configuration */
1339 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1341 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1342 p_link->min_pf_rate);
1344 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1345 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1346 p_link->parallel_detection = !!(status &
1347 LINK_STATUS_PARALLEL_DETECTION_USED);
1348 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1350 p_link->partner_adv_speed |=
1351 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1352 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1353 p_link->partner_adv_speed |=
1354 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1355 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1356 p_link->partner_adv_speed |=
1357 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1358 ECORE_LINK_PARTNER_SPEED_10G : 0;
1359 p_link->partner_adv_speed |=
1360 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1361 ECORE_LINK_PARTNER_SPEED_20G : 0;
1362 p_link->partner_adv_speed |=
1363 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1364 ECORE_LINK_PARTNER_SPEED_25G : 0;
1365 p_link->partner_adv_speed |=
1366 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1367 ECORE_LINK_PARTNER_SPEED_40G : 0;
1368 p_link->partner_adv_speed |=
1369 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1370 ECORE_LINK_PARTNER_SPEED_50G : 0;
1371 p_link->partner_adv_speed |=
1372 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1373 ECORE_LINK_PARTNER_SPEED_100G : 0;
1375 p_link->partner_tx_flow_ctrl_en =
1376 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1377 p_link->partner_rx_flow_ctrl_en =
1378 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1380 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1381 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1382 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1384 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1385 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1387 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1388 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1391 p_link->partner_adv_pause = 0;
1394 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1396 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1397 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1399 OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1401 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1404 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1405 struct ecore_ptt *p_ptt, bool b_up)
1407 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1408 struct ecore_mcp_mb_params mb_params;
1409 struct eth_phy_cfg phy_cfg;
1410 enum _ecore_status_t rc = ECORE_SUCCESS;
1414 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1415 return ECORE_SUCCESS;
1418 /* Set the shmem configuration according to params */
1419 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1420 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1421 if (!params->speed.autoneg)
1422 phy_cfg.speed = params->speed.forced_speed;
1423 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1424 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1425 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1426 phy_cfg.adv_speed = params->speed.advertised_speeds;
1427 phy_cfg.loopback_mode = params->loopback_mode;
1429 /* There are MFWs that share this capability regardless of whether
1430 * this is feasible or not. And given that at the very least adv_caps
1431 * would be set internally by ecore, we want to make sure LFA would
1434 if ((p_hwfn->mcp_info->capabilities &
1435 FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1436 params->eee.enable) {
1437 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1438 if (params->eee.tx_lpi_enable)
1439 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1440 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1441 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1442 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1443 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1444 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1445 EEE_TX_TIMER_USEC_OFFSET) &
1446 EEE_TX_TIMER_USEC_MASK;
1449 p_hwfn->b_drv_link_init = b_up;
1452 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1453 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1454 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1455 phy_cfg.loopback_mode);
1457 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1459 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1460 mb_params.cmd = cmd;
1461 mb_params.p_data_src = &phy_cfg;
1462 mb_params.data_src_size = sizeof(phy_cfg);
1463 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1465 /* if mcp fails to respond we must abort */
1466 if (rc != ECORE_SUCCESS) {
1467 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1471 /* Mimic link-change attention, done for several reasons:
1472 * - On reset, there's no guarantee MFW would trigger
1474 * - On initialization, older MFWs might not indicate link change
1475 * during LFA, so we'll never get an UP indication.
1477 ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1479 return ECORE_SUCCESS;
1482 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1483 struct ecore_ptt *p_ptt)
1485 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1487 /* TODO - Add support for VFs */
1488 if (IS_VF(p_hwfn->p_dev))
1491 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1493 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1494 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1496 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1498 OFFSETOF(struct public_path, process_kill)) &
1499 PROCESS_KILL_COUNTER_MASK;
1501 return proc_kill_cnt;
1504 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1505 struct ecore_ptt *p_ptt)
1507 struct ecore_dev *p_dev = p_hwfn->p_dev;
1510 /* Prevent possible attentions/interrupts during the recovery handling
1511 * and till its load phase, during which they will be re-enabled.
1513 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1515 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1517 /* The following operations should be done once, and thus in CMT mode
1518 * are carried out by only the first HW function.
1520 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1523 if (p_dev->recov_in_prog) {
1524 DP_NOTICE(p_hwfn, false,
1525 "Ignoring the indication since a recovery"
1526 " process is already in progress\n");
1530 p_dev->recov_in_prog = true;
1532 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1533 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1535 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1538 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1539 struct ecore_ptt *p_ptt,
1540 enum MFW_DRV_MSG_TYPE type)
1542 enum ecore_mcp_protocol_type stats_type;
1543 union ecore_mcp_protocol_stats stats;
1544 struct ecore_mcp_mb_params mb_params;
1546 enum _ecore_status_t rc;
1549 case MFW_DRV_MSG_GET_LAN_STATS:
1550 stats_type = ECORE_MCP_LAN_STATS;
1551 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1554 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1555 "Invalid protocol type %d\n", type);
1559 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1561 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1562 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1563 mb_params.param = hsi_param;
1564 mb_params.p_data_src = &stats;
1565 mb_params.data_src_size = sizeof(stats);
1566 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1567 if (rc != ECORE_SUCCESS)
1568 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1571 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1572 struct public_func *p_shmem_info)
1574 struct ecore_mcp_function_info *p_info;
1576 p_info = &p_hwfn->mcp_info->func_info;
1578 /* TODO - bandwidth min/max should have valid values of 1-100,
1579 * as well as some indication that the feature is disabled.
1580 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1581 * limit and correct value to min `1' and max `100' if limit isn't in
1584 p_info->bandwidth_min = (p_shmem_info->config &
1585 FUNC_MF_CFG_MIN_BW_MASK) >>
1586 FUNC_MF_CFG_MIN_BW_OFFSET;
1587 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1589 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1590 p_info->bandwidth_min);
1591 p_info->bandwidth_min = 1;
1594 p_info->bandwidth_max = (p_shmem_info->config &
1595 FUNC_MF_CFG_MAX_BW_MASK) >>
1596 FUNC_MF_CFG_MAX_BW_OFFSET;
1597 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1599 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1600 p_info->bandwidth_max);
1601 p_info->bandwidth_max = 100;
1606 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1608 struct ecore_mcp_function_info *p_info;
1609 struct public_func shmem_info;
1610 u32 resp = 0, param = 0;
1612 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1614 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1616 p_info = &p_hwfn->mcp_info->func_info;
1618 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1620 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1622 /* Acknowledge the MFW */
1623 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1627 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1629 /* A single notification should be sent to upper driver in CMT mode */
1630 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1633 DP_NOTICE(p_hwfn, false,
1634 "Fan failure was detected on the network interface card"
1635 " and it's going to be shut down.\n");
1637 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1640 struct ecore_mdump_cmd_params {
1649 static enum _ecore_status_t
1650 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1651 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1653 struct ecore_mcp_mb_params mb_params;
1654 enum _ecore_status_t rc;
1656 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1657 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1658 mb_params.param = p_mdump_cmd_params->cmd;
1659 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1660 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1661 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1662 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1663 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1664 if (rc != ECORE_SUCCESS)
1667 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1669 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1671 "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1672 p_mdump_cmd_params->cmd);
1674 } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1676 "The mdump command is not supported by the MFW\n");
1683 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1684 struct ecore_ptt *p_ptt)
1686 struct ecore_mdump_cmd_params mdump_cmd_params;
1688 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1689 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1691 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1694 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1695 struct ecore_ptt *p_ptt,
1698 struct ecore_mdump_cmd_params mdump_cmd_params;
1700 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1701 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1702 mdump_cmd_params.p_data_src = &epoch;
1703 mdump_cmd_params.data_src_size = sizeof(epoch);
1705 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1708 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1709 struct ecore_ptt *p_ptt)
1711 struct ecore_mdump_cmd_params mdump_cmd_params;
1713 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1714 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1716 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1719 static enum _ecore_status_t
1720 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1721 struct mdump_config_stc *p_mdump_config)
1723 struct ecore_mdump_cmd_params mdump_cmd_params;
1724 enum _ecore_status_t rc;
1726 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1727 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1728 mdump_cmd_params.p_data_dst = p_mdump_config;
1729 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1731 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1732 if (rc != ECORE_SUCCESS)
1735 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1737 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1738 mdump_cmd_params.mcp_resp);
1739 rc = ECORE_UNKNOWN_ERROR;
1745 enum _ecore_status_t
1746 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1747 struct ecore_mdump_info *p_mdump_info)
1749 u32 addr, global_offsize, global_addr;
1750 struct mdump_config_stc mdump_config;
1751 enum _ecore_status_t rc;
1753 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1755 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1757 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1758 global_addr = SECTION_ADDR(global_offsize, 0);
1759 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1761 OFFSETOF(struct public_global,
1764 if (p_mdump_info->reason) {
1765 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1766 if (rc != ECORE_SUCCESS)
1769 p_mdump_info->version = mdump_config.version;
1770 p_mdump_info->config = mdump_config.config;
1771 p_mdump_info->epoch = mdump_config.epoc;
1772 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1773 p_mdump_info->valid_logs = mdump_config.valid_logs;
1775 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1776 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1777 p_mdump_info->reason, p_mdump_info->version,
1778 p_mdump_info->config, p_mdump_info->epoch,
1779 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1781 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1782 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1785 return ECORE_SUCCESS;
1788 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1789 struct ecore_ptt *p_ptt)
1791 struct ecore_mdump_cmd_params mdump_cmd_params;
1793 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1794 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1796 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1799 enum _ecore_status_t
1800 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1801 struct ecore_mdump_retain_data *p_mdump_retain)
1803 struct ecore_mdump_cmd_params mdump_cmd_params;
1804 struct mdump_retain_data_stc mfw_mdump_retain;
1805 enum _ecore_status_t rc;
1807 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1808 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1809 mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1810 mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1812 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1813 if (rc != ECORE_SUCCESS)
1816 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1818 "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1819 mdump_cmd_params.mcp_resp);
1820 return ECORE_UNKNOWN_ERROR;
1823 p_mdump_retain->valid = mfw_mdump_retain.valid;
1824 p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1825 p_mdump_retain->pf = mfw_mdump_retain.pf;
1826 p_mdump_retain->status = mfw_mdump_retain.status;
1828 return ECORE_SUCCESS;
1831 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1832 struct ecore_ptt *p_ptt)
1834 struct ecore_mdump_cmd_params mdump_cmd_params;
1836 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1837 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1839 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1842 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1843 struct ecore_ptt *p_ptt)
1845 struct ecore_mdump_retain_data mdump_retain;
1846 enum _ecore_status_t rc;
1848 /* In CMT mode - no need for more than a single acknowledgment to the
1849 * MFW, and no more than a single notification to the upper driver.
1851 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1854 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1855 if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1856 DP_NOTICE(p_hwfn, false,
1857 "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1858 mdump_retain.epoch, mdump_retain.pf,
1859 mdump_retain.status);
1861 DP_NOTICE(p_hwfn, false,
1862 "The MFW notified that a critical error occurred in the device\n");
1865 if (p_hwfn->p_dev->allow_mdump) {
1866 DP_NOTICE(p_hwfn, false,
1867 "Not acknowledging the notification to allow the MFW crash dump\n");
1871 DP_NOTICE(p_hwfn, false,
1872 "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1873 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1874 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1878 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1880 struct public_func shmem_info;
1883 if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
1886 OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1887 port_cfg = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1888 OFFSETOF(struct public_port, oem_cfg_port));
1889 val = GET_MFW_FIELD(port_cfg, OEM_CFG_CHANNEL_TYPE);
1890 if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1891 DP_NOTICE(p_hwfn, false, "Incorrect UFP Channel type %d\n",
1894 val = GET_MFW_FIELD(port_cfg, OEM_CFG_SCHED_TYPE);
1895 if (val == OEM_CFG_SCHED_TYPE_ETS)
1896 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_ETS;
1897 else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW)
1898 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_VNIC_BW;
1900 DP_NOTICE(p_hwfn, false, "Unknown UFP scheduling mode %d\n",
1903 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1905 val = GET_MFW_FIELD(shmem_info.oem_cfg_func, OEM_CFG_FUNC_TC);
1906 p_hwfn->ufp_info.tc = (u8)val;
1907 val = GET_MFW_FIELD(shmem_info.oem_cfg_func,
1908 OEM_CFG_FUNC_HOST_PRI_CTRL);
1909 if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC)
1910 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_VNIC;
1911 else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS)
1912 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_OS;
1914 DP_NOTICE(p_hwfn, false, "Unknown Host priority control %d\n",
1917 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1918 "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1919 p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1920 p_hwfn->ufp_info.pri_type);
1923 static enum _ecore_status_t
1924 ecore_mcp_handle_ufp_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1926 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
1928 if (p_hwfn->ufp_info.mode == ECORE_UFP_MODE_VNIC_BW) {
1929 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1930 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1932 ecore_qm_reconf(p_hwfn, p_ptt);
1934 /* Merge UFP TC with the dcbx TC data */
1935 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1936 ECORE_DCBX_OPERATIONAL_MIB);
1939 /* update storm FW with negotiation results */
1940 ecore_sp_pf_update_ufp(p_hwfn);
1942 return ECORE_SUCCESS;
1945 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1946 struct ecore_ptt *p_ptt)
1948 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1949 enum _ecore_status_t rc = ECORE_SUCCESS;
1953 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1955 /* Read Messages from MFW */
1956 ecore_mcp_read_mb(p_hwfn, p_ptt);
1958 /* Compare current messages to old ones */
1959 for (i = 0; i < info->mfw_mb_length; i++) {
1960 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1965 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1966 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1967 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1970 case MFW_DRV_MSG_LINK_CHANGE:
1971 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1973 case MFW_DRV_MSG_VF_DISABLED:
1974 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1976 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1977 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1978 ECORE_DCBX_REMOTE_LLDP_MIB);
1980 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1981 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1982 ECORE_DCBX_REMOTE_MIB);
1984 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1985 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1986 ECORE_DCBX_OPERATIONAL_MIB);
1987 /* clear the user-config cache */
1988 OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
1989 sizeof(struct ecore_dcbx_set));
1991 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1992 ecore_mcp_handle_ufp_event(p_hwfn, p_ptt);
1994 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1995 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1997 case MFW_DRV_MSG_ERROR_RECOVERY:
1998 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
2000 case MFW_DRV_MSG_GET_LAN_STATS:
2001 case MFW_DRV_MSG_GET_FCOE_STATS:
2002 case MFW_DRV_MSG_GET_ISCSI_STATS:
2003 case MFW_DRV_MSG_GET_RDMA_STATS:
2004 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
2006 case MFW_DRV_MSG_BW_UPDATE:
2007 ecore_mcp_update_bw(p_hwfn, p_ptt);
2009 case MFW_DRV_MSG_FAILURE_DETECTED:
2010 ecore_mcp_handle_fan_failure(p_hwfn);
2012 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
2013 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
2016 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
2021 /* ACK everything */
2022 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2023 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
2025 /* MFW expect answer in BE, so we force write in that format */
2026 ecore_wr(p_hwfn, p_ptt,
2027 info->mfw_mb_addr + sizeof(u32) +
2028 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2029 sizeof(u32) + i * sizeof(u32), val);
2033 DP_NOTICE(p_hwfn, false,
2034 "Received an MFW message indication but no"
2039 /* Copy the new mfw messages into the shadow */
2040 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2045 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
2046 struct ecore_ptt *p_ptt,
2048 u32 *p_running_bundle_id)
2053 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2054 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
2055 return ECORE_SUCCESS;
2059 if (IS_VF(p_hwfn->p_dev)) {
2060 if (p_hwfn->vf_iov_info) {
2061 struct pfvf_acquire_resp_tlv *p_resp;
2063 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2064 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2065 return ECORE_SUCCESS;
2067 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2068 "VF requested MFW version prior to ACQUIRE\n");
2073 global_offsize = ecore_rd(p_hwfn, p_ptt,
2074 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
2078 ecore_rd(p_hwfn, p_ptt,
2079 SECTION_ADDR(global_offsize,
2080 0) + OFFSETOF(struct public_global, mfw_ver));
2082 if (p_running_bundle_id != OSAL_NULL) {
2083 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
2084 SECTION_ADDR(global_offsize,
2086 OFFSETOF(struct public_global,
2087 running_bundle_id));
2090 return ECORE_SUCCESS;
2093 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2094 struct ecore_ptt *p_ptt,
2098 /* TODO - Add support for VFs */
2099 if (IS_VF(p_hwfn->p_dev))
2102 if (!ecore_mcp_is_init(p_hwfn)) {
2103 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2108 *p_media_type = MEDIA_UNSPECIFIED;
2111 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2112 p_hwfn->mcp_info->port_addr +
2113 OFFSETOF(struct public_port,
2117 return ECORE_SUCCESS;
2121 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2123 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2124 enum ecore_pci_personality *p_proto)
2126 *p_proto = ECORE_PCI_ETH;
2128 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2129 "According to Legacy capabilities, L2 personality is %08x\n",
2134 static enum _ecore_status_t
2135 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2136 struct ecore_ptt *p_ptt,
2137 enum ecore_pci_personality *p_proto)
2139 u32 resp = 0, param = 0;
2140 enum _ecore_status_t rc;
2142 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2143 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2144 (u32)*p_proto, resp, param);
2145 return ECORE_SUCCESS;
2148 static enum _ecore_status_t
2149 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2150 struct public_func *p_info,
2151 struct ecore_ptt *p_ptt,
2152 enum ecore_pci_personality *p_proto)
2154 enum _ecore_status_t rc = ECORE_SUCCESS;
2156 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2157 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2158 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2160 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2169 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2170 struct ecore_ptt *p_ptt)
2172 struct ecore_mcp_function_info *info;
2173 struct public_func shmem_info;
2175 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2176 info = &p_hwfn->mcp_info->func_info;
2178 info->pause_on_host = (shmem_info.config &
2179 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2181 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2183 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2184 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2188 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2190 if (shmem_info.mac_upper || shmem_info.mac_lower) {
2191 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2192 info->mac[1] = (u8)(shmem_info.mac_upper);
2193 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2194 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2195 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2196 info->mac[5] = (u8)(shmem_info.mac_lower);
2198 /* TODO - are there protocols for which there's no MAC? */
2199 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2202 /* TODO - are these calculations true for BE machine? */
2203 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2204 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2205 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2206 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2208 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2210 info->mtu = (u16)shmem_info.mtu_size;
2215 info->mtu = (u16)shmem_info.mtu_size;
2217 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2218 "Read configuration from shmem: pause_on_host %02x"
2219 " protocol %02x BW [%02x - %02x]"
2220 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2221 " node %lx ovlan %04x\n",
2222 info->pause_on_host, info->protocol,
2223 info->bandwidth_min, info->bandwidth_max,
2224 info->mac[0], info->mac[1], info->mac[2],
2225 info->mac[3], info->mac[4], info->mac[5],
2226 (unsigned long)info->wwn_port,
2227 (unsigned long)info->wwn_node, info->ovlan);
2229 return ECORE_SUCCESS;
2232 struct ecore_mcp_link_params
2233 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2235 if (!p_hwfn || !p_hwfn->mcp_info)
2237 return &p_hwfn->mcp_info->link_input;
2240 struct ecore_mcp_link_state
2241 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2243 if (!p_hwfn || !p_hwfn->mcp_info)
2247 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2248 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2249 p_hwfn->mcp_info->link_output.link_up = true;
2253 return &p_hwfn->mcp_info->link_output;
2256 struct ecore_mcp_link_capabilities
2257 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2259 if (!p_hwfn || !p_hwfn->mcp_info)
2261 return &p_hwfn->mcp_info->link_capabilities;
2264 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2265 struct ecore_ptt *p_ptt)
2267 u32 resp = 0, param = 0;
2268 enum _ecore_status_t rc;
2270 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2271 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
2273 /* Wait for the drain to complete before returning */
2279 const struct ecore_mcp_function_info
2280 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2282 if (!p_hwfn || !p_hwfn->mcp_info)
2284 return &p_hwfn->mcp_info->func_info;
2287 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2288 struct ecore_ptt *p_ptt, u32 personalities)
2290 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2291 struct public_func shmem_info;
2292 int i, count = 0, num_pfs;
2294 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2296 for (i = 0; i < num_pfs; i++) {
2297 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2298 MCP_PF_ID_BY_REL(p_hwfn, i));
2299 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2302 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2307 if ((1 << ((u32)protocol)) & personalities)
2314 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2315 struct ecore_ptt *p_ptt,
2321 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2322 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2327 if (IS_VF(p_hwfn->p_dev))
2330 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2331 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2332 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2333 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2335 *p_flash_size = flash_size;
2337 return ECORE_SUCCESS;
2340 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2341 struct ecore_ptt *p_ptt)
2343 struct ecore_dev *p_dev = p_hwfn->p_dev;
2345 if (p_dev->recov_in_prog) {
2346 DP_NOTICE(p_hwfn, false,
2347 "Avoid triggering a recovery since such a process"
2348 " is already in progress\n");
2352 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2353 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2355 return ECORE_SUCCESS;
2358 static enum _ecore_status_t
2359 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2360 struct ecore_ptt *p_ptt,
2363 u32 resp = 0, param = 0, rc_param = 0;
2364 enum _ecore_status_t rc;
2366 /* Only Leader can configure MSIX, and need to take CMT into account */
2368 if (!IS_LEAD_HWFN(p_hwfn))
2369 return ECORE_SUCCESS;
2370 num *= p_hwfn->p_dev->num_hwfns;
2372 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2373 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2374 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2375 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2377 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2380 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2381 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2385 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2386 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2393 static enum _ecore_status_t
2394 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2395 struct ecore_ptt *p_ptt,
2398 u32 resp = 0, param = num, rc_param = 0;
2399 enum _ecore_status_t rc;
2401 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2402 param, &resp, &rc_param);
2404 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2405 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2408 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2409 "Requested 0x%02x MSI-x interrupts for VFs\n",
2416 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2417 struct ecore_ptt *p_ptt,
2420 if (ECORE_IS_BB(p_hwfn->p_dev))
2421 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2423 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2426 enum _ecore_status_t
2427 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2428 struct ecore_mcp_drv_version *p_ver)
2430 struct ecore_mcp_mb_params mb_params;
2431 struct drv_version_stc drv_version;
2435 enum _ecore_status_t rc;
2438 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2439 return ECORE_SUCCESS;
2442 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2443 drv_version.version = p_ver->version;
2444 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2445 for (i = 0; i < num_words; i++) {
2446 /* The driver name is expected to be in a big-endian format */
2447 p_name = &p_ver->name[i * sizeof(u32)];
2448 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2449 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2452 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2453 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2454 mb_params.p_data_src = &drv_version;
2455 mb_params.data_src_size = sizeof(drv_version);
2456 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2457 if (rc != ECORE_SUCCESS)
2458 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2463 /* A maximal 100 msec waiting time for the MCP to halt */
2464 #define ECORE_MCP_HALT_SLEEP_MS 10
2465 #define ECORE_MCP_HALT_MAX_RETRIES 10
2467 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2468 struct ecore_ptt *p_ptt)
2470 u32 resp = 0, param = 0, cpu_state, cnt = 0;
2471 enum _ecore_status_t rc;
2473 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2475 if (rc != ECORE_SUCCESS) {
2476 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2481 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2482 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2483 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2485 } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2487 if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2488 DP_NOTICE(p_hwfn, false,
2489 "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2490 ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2494 ecore_mcp_cmd_set_blocking(p_hwfn, true);
2496 return ECORE_SUCCESS;
2499 #define ECORE_MCP_RESUME_SLEEP_MS 10
2501 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2502 struct ecore_ptt *p_ptt)
2504 u32 cpu_mode, cpu_state;
2506 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2508 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2509 cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2510 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2512 OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2513 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2515 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2516 DP_NOTICE(p_hwfn, false,
2517 "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2518 cpu_mode, cpu_state);
2522 ecore_mcp_cmd_set_blocking(p_hwfn, false);
2524 return ECORE_SUCCESS;
2527 enum _ecore_status_t
2528 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2529 struct ecore_ptt *p_ptt,
2530 enum ecore_ov_client client)
2532 enum _ecore_status_t rc;
2533 u32 resp = 0, param = 0;
2537 case ECORE_OV_CLIENT_DRV:
2538 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2540 case ECORE_OV_CLIENT_USER:
2541 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2543 case ECORE_OV_CLIENT_VENDOR_SPEC:
2544 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2547 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2551 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2552 drv_mb_param, &resp, ¶m);
2553 if (rc != ECORE_SUCCESS)
2554 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2559 enum _ecore_status_t
2560 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2561 struct ecore_ptt *p_ptt,
2562 enum ecore_ov_driver_state drv_state)
2564 enum _ecore_status_t rc;
2565 u32 resp = 0, param = 0;
2568 switch (drv_state) {
2569 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2570 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2572 case ECORE_OV_DRIVER_STATE_DISABLED:
2573 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2575 case ECORE_OV_DRIVER_STATE_ACTIVE:
2576 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2579 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2583 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2584 drv_mb_param, &resp, ¶m);
2585 if (rc != ECORE_SUCCESS)
2586 DP_ERR(p_hwfn, "Failed to send driver state\n");
2591 enum _ecore_status_t
2592 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2593 struct ecore_fc_npiv_tbl *p_table)
2598 enum _ecore_status_t
2599 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2600 struct ecore_ptt *p_ptt, u16 mtu)
2605 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2606 struct ecore_ptt *p_ptt,
2607 enum ecore_led_mode mode)
2609 u32 resp = 0, param = 0, drv_mb_param;
2610 enum _ecore_status_t rc;
2613 case ECORE_LED_MODE_ON:
2614 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2616 case ECORE_LED_MODE_OFF:
2617 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2619 case ECORE_LED_MODE_RESTORE:
2620 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2623 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2627 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2628 drv_mb_param, &resp, ¶m);
2629 if (rc != ECORE_SUCCESS)
2630 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2635 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2636 struct ecore_ptt *p_ptt,
2639 u32 resp = 0, param = 0;
2640 enum _ecore_status_t rc;
2642 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2643 mask_parities, &resp, ¶m);
2645 if (rc != ECORE_SUCCESS) {
2647 "MCP response failure for mask parities, aborting\n");
2648 } else if (resp != FW_MSG_CODE_OK) {
2650 "MCP did not ack mask parity request. Old MFW?\n");
2657 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2660 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2661 u32 bytes_left, offset, bytes_to_copy, buf_size;
2662 u32 nvm_offset, resp, param;
2663 struct ecore_ptt *p_ptt;
2664 enum _ecore_status_t rc = ECORE_SUCCESS;
2666 p_ptt = ecore_ptt_acquire(p_hwfn);
2672 while (bytes_left > 0) {
2673 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2674 MCP_DRV_NVM_BUF_LEN);
2675 nvm_offset = (addr + offset) | (bytes_to_copy <<
2676 DRV_MB_PARAM_NVM_LEN_OFFSET);
2677 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2678 DRV_MSG_CODE_NVM_READ_NVRAM,
2679 nvm_offset, &resp, ¶m, &buf_size,
2680 (u32 *)(p_buf + offset));
2681 if (rc != ECORE_SUCCESS) {
2682 DP_NOTICE(p_dev, false,
2683 "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2685 resp = FW_MSG_CODE_ERROR;
2689 if (resp != FW_MSG_CODE_NVM_OK) {
2690 DP_NOTICE(p_dev, false,
2691 "nvm read failed, resp = 0x%08x\n", resp);
2692 rc = ECORE_UNKNOWN_ERROR;
2696 /* This can be a lengthy process, and it's possible scheduler
2697 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2699 if (bytes_left % 0x1000 <
2700 (bytes_left - buf_size) % 0x1000)
2704 bytes_left -= buf_size;
2707 p_dev->mcp_nvm_resp = resp;
2708 ecore_ptt_release(p_hwfn, p_ptt);
2713 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2714 u32 addr, u8 *p_buf, u32 len)
2716 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2717 struct ecore_ptt *p_ptt;
2719 enum _ecore_status_t rc;
2721 p_ptt = ecore_ptt_acquire(p_hwfn);
2725 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2726 (cmd == ECORE_PHY_CORE_READ) ?
2727 DRV_MSG_CODE_PHY_CORE_READ :
2728 DRV_MSG_CODE_PHY_RAW_READ,
2729 addr, &resp, ¶m, &len, (u32 *)p_buf);
2730 if (rc != ECORE_SUCCESS)
2731 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2733 p_dev->mcp_nvm_resp = resp;
2734 ecore_ptt_release(p_hwfn, p_ptt);
2739 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2741 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2742 struct ecore_ptt *p_ptt;
2744 p_ptt = ecore_ptt_acquire(p_hwfn);
2748 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2749 ecore_ptt_release(p_hwfn, p_ptt);
2751 return ECORE_SUCCESS;
2754 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2756 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2757 struct ecore_ptt *p_ptt;
2759 enum _ecore_status_t rc;
2761 p_ptt = ecore_ptt_acquire(p_hwfn);
2764 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2766 p_dev->mcp_nvm_resp = resp;
2767 ecore_ptt_release(p_hwfn, p_ptt);
2772 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2775 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2776 struct ecore_ptt *p_ptt;
2778 enum _ecore_status_t rc;
2780 p_ptt = ecore_ptt_acquire(p_hwfn);
2783 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2785 p_dev->mcp_nvm_resp = resp;
2786 ecore_ptt_release(p_hwfn, p_ptt);
2791 /* rc receives ECORE_INVAL as default parameter because
2792 * it might not enter the while loop if the len is 0
2794 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2795 u32 addr, u8 *p_buf, u32 len)
2797 u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2798 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2799 enum _ecore_status_t rc = ECORE_INVAL;
2800 struct ecore_ptt *p_ptt;
2802 p_ptt = ecore_ptt_acquire(p_hwfn);
2807 case ECORE_PUT_FILE_DATA:
2808 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2810 case ECORE_NVM_WRITE_NVRAM:
2811 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2813 case ECORE_EXT_PHY_FW_UPGRADE:
2814 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2817 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2824 while (buf_idx < len) {
2825 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2826 MCP_DRV_NVM_BUF_LEN);
2827 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2830 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2831 &resp, ¶m, buf_size,
2832 (u32 *)&p_buf[buf_idx]);
2833 if (rc != ECORE_SUCCESS) {
2834 DP_NOTICE(p_dev, false,
2835 "ecore_mcp_nvm_write() failed, rc = %d\n",
2837 resp = FW_MSG_CODE_ERROR;
2841 if (resp != FW_MSG_CODE_OK &&
2842 resp != FW_MSG_CODE_NVM_OK &&
2843 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2844 DP_NOTICE(p_dev, false,
2845 "nvm write failed, resp = 0x%08x\n", resp);
2846 rc = ECORE_UNKNOWN_ERROR;
2850 /* This can be a lengthy process, and it's possible scheduler
2851 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2853 if (buf_idx % 0x1000 >
2854 (buf_idx + buf_size) % 0x1000)
2857 buf_idx += buf_size;
2860 p_dev->mcp_nvm_resp = resp;
2862 ecore_ptt_release(p_hwfn, p_ptt);
2867 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2868 u32 addr, u8 *p_buf, u32 len)
2870 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2871 struct ecore_ptt *p_ptt;
2872 u32 resp, param, nvm_cmd;
2873 enum _ecore_status_t rc;
2875 p_ptt = ecore_ptt_acquire(p_hwfn);
2879 nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ? DRV_MSG_CODE_PHY_CORE_WRITE :
2880 DRV_MSG_CODE_PHY_RAW_WRITE;
2881 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2882 &resp, ¶m, len, (u32 *)p_buf);
2883 if (rc != ECORE_SUCCESS)
2884 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2885 p_dev->mcp_nvm_resp = resp;
2886 ecore_ptt_release(p_hwfn, p_ptt);
2891 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2894 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2895 struct ecore_ptt *p_ptt;
2897 enum _ecore_status_t rc;
2899 p_ptt = ecore_ptt_acquire(p_hwfn);
2903 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2905 p_dev->mcp_nvm_resp = resp;
2906 ecore_ptt_release(p_hwfn, p_ptt);
2911 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2912 struct ecore_ptt *p_ptt,
2913 u32 port, u32 addr, u32 offset,
2916 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2918 enum _ecore_status_t rc;
2920 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2921 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2925 while (bytes_left > 0) {
2926 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2927 MAX_I2C_TRANSACTION_SIZE);
2928 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2929 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2930 nvm_offset |= ((addr + offset) <<
2931 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2932 nvm_offset |= (bytes_to_copy <<
2933 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2934 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2935 DRV_MSG_CODE_TRANSCEIVER_READ,
2936 nvm_offset, &resp, ¶m, &buf_size,
2937 (u32 *)(p_buf + offset));
2938 if ((resp & FW_MSG_CODE_MASK) ==
2939 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2941 } else if ((resp & FW_MSG_CODE_MASK) !=
2942 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2943 return ECORE_UNKNOWN_ERROR;
2946 bytes_left -= buf_size;
2949 return ECORE_SUCCESS;
2952 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2953 struct ecore_ptt *p_ptt,
2954 u32 port, u32 addr, u32 offset,
2957 u32 buf_idx, buf_size, nvm_offset, resp, param;
2958 enum _ecore_status_t rc;
2960 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2961 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2963 while (buf_idx < len) {
2964 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2965 MAX_I2C_TRANSACTION_SIZE);
2966 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2967 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2968 nvm_offset |= ((offset + buf_idx) <<
2969 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2970 nvm_offset |= (buf_size <<
2971 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2972 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2973 DRV_MSG_CODE_TRANSCEIVER_WRITE,
2974 nvm_offset, &resp, ¶m, buf_size,
2975 (u32 *)&p_buf[buf_idx]);
2976 if ((resp & FW_MSG_CODE_MASK) ==
2977 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2979 } else if ((resp & FW_MSG_CODE_MASK) !=
2980 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2981 return ECORE_UNKNOWN_ERROR;
2983 buf_idx += buf_size;
2986 return ECORE_SUCCESS;
2989 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2990 struct ecore_ptt *p_ptt,
2991 u16 gpio, u32 *gpio_val)
2993 enum _ecore_status_t rc = ECORE_SUCCESS;
2994 u32 drv_mb_param = 0, rsp;
2996 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2998 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2999 drv_mb_param, &rsp, gpio_val);
3001 if (rc != ECORE_SUCCESS)
3004 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3005 return ECORE_UNKNOWN_ERROR;
3007 return ECORE_SUCCESS;
3010 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
3011 struct ecore_ptt *p_ptt,
3012 u16 gpio, u16 gpio_val)
3014 enum _ecore_status_t rc = ECORE_SUCCESS;
3015 u32 drv_mb_param = 0, param, rsp;
3017 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
3018 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
3020 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
3021 drv_mb_param, &rsp, ¶m);
3023 if (rc != ECORE_SUCCESS)
3026 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3027 return ECORE_UNKNOWN_ERROR;
3029 return ECORE_SUCCESS;
3032 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
3033 struct ecore_ptt *p_ptt,
3034 u16 gpio, u32 *gpio_direction,
3037 u32 drv_mb_param = 0, rsp, val = 0;
3038 enum _ecore_status_t rc = ECORE_SUCCESS;
3040 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
3042 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
3043 drv_mb_param, &rsp, &val);
3044 if (rc != ECORE_SUCCESS)
3047 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
3048 DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
3049 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
3050 DRV_MB_PARAM_GPIO_CTRL_OFFSET;
3052 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3053 return ECORE_UNKNOWN_ERROR;
3055 return ECORE_SUCCESS;
3058 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
3059 struct ecore_ptt *p_ptt)
3061 u32 drv_mb_param = 0, rsp, param;
3062 enum _ecore_status_t rc = ECORE_SUCCESS;
3064 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3065 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3067 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3068 drv_mb_param, &rsp, ¶m);
3070 if (rc != ECORE_SUCCESS)
3073 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3074 (param != DRV_MB_PARAM_BIST_RC_PASSED))
3075 rc = ECORE_UNKNOWN_ERROR;
3080 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
3081 struct ecore_ptt *p_ptt)
3083 u32 drv_mb_param, rsp, param;
3084 enum _ecore_status_t rc = ECORE_SUCCESS;
3086 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3087 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3089 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3090 drv_mb_param, &rsp, ¶m);
3092 if (rc != ECORE_SUCCESS)
3095 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3096 (param != DRV_MB_PARAM_BIST_RC_PASSED))
3097 rc = ECORE_UNKNOWN_ERROR;
3102 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3103 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3105 u32 drv_mb_param = 0, rsp;
3106 enum _ecore_status_t rc = ECORE_SUCCESS;
3108 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3109 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3111 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3112 drv_mb_param, &rsp, num_images);
3114 if (rc != ECORE_SUCCESS)
3117 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3118 rc = ECORE_UNKNOWN_ERROR;
3123 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3124 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3125 struct bist_nvm_image_att *p_image_att, u32 image_index)
3127 u32 buf_size, nvm_offset, resp, param;
3128 enum _ecore_status_t rc;
3130 nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3131 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3132 nvm_offset |= (image_index <<
3133 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3134 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3135 nvm_offset, &resp, ¶m, &buf_size,
3136 (u32 *)p_image_att);
3137 if (rc != ECORE_SUCCESS)
3140 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3141 (p_image_att->return_code != 1))
3142 rc = ECORE_UNKNOWN_ERROR;
3147 enum _ecore_status_t
3148 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3149 struct ecore_ptt *p_ptt,
3150 struct ecore_temperature_info *p_temp_info)
3152 struct ecore_temperature_sensor *p_temp_sensor;
3153 struct temperature_status_stc mfw_temp_info;
3154 struct ecore_mcp_mb_params mb_params;
3156 enum _ecore_status_t rc;
3159 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3160 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3161 mb_params.p_data_dst = &mfw_temp_info;
3162 mb_params.data_dst_size = sizeof(mfw_temp_info);
3163 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3164 if (rc != ECORE_SUCCESS)
3167 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3168 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3169 ECORE_MAX_NUM_OF_SENSORS);
3170 for (i = 0; i < p_temp_info->num_sensors; i++) {
3171 val = mfw_temp_info.sensor[i];
3172 p_temp_sensor = &p_temp_info->sensors[i];
3173 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3174 SENSOR_LOCATION_OFFSET;
3175 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3176 THRESHOLD_HIGH_OFFSET;
3177 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3178 CRITICAL_TEMPERATURE_OFFSET;
3179 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3180 CURRENT_TEMP_OFFSET;
3183 return ECORE_SUCCESS;
3186 enum _ecore_status_t ecore_mcp_get_mba_versions(
3187 struct ecore_hwfn *p_hwfn,
3188 struct ecore_ptt *p_ptt,
3189 struct ecore_mba_vers *p_mba_vers)
3191 u32 buf_size, resp, param;
3192 enum _ecore_status_t rc;
3194 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3195 0, &resp, ¶m, &buf_size,
3196 &p_mba_vers->mba_vers[0]);
3198 if (rc != ECORE_SUCCESS)
3201 if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3202 rc = ECORE_UNKNOWN_ERROR;
3204 if (buf_size != MCP_DRV_NVM_BUF_LEN)
3205 rc = ECORE_UNKNOWN_ERROR;
3210 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3211 struct ecore_ptt *p_ptt,
3216 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3217 0, &rsp, (u32 *)num_events);
3220 static enum resource_id_enum
3221 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3223 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3227 mfw_res_id = RESOURCE_NUM_SB_E;
3229 case ECORE_L2_QUEUE:
3230 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3233 mfw_res_id = RESOURCE_NUM_VPORT_E;
3236 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3239 mfw_res_id = RESOURCE_NUM_PQ_E;
3242 mfw_res_id = RESOURCE_NUM_RL_E;
3246 /* Each VFC resource can accommodate both a MAC and a VLAN */
3247 mfw_res_id = RESOURCE_VFC_FILTER_E;
3250 mfw_res_id = RESOURCE_ILT_E;
3252 case ECORE_LL2_QUEUE:
3253 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3255 case ECORE_RDMA_CNQ_RAM:
3256 case ECORE_CMDQS_CQS:
3257 /* CNQ/CMDQS are the same resource */
3258 mfw_res_id = RESOURCE_CQS_E;
3260 case ECORE_RDMA_STATS_QUEUE:
3261 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3264 mfw_res_id = RESOURCE_BDQ_E;
3273 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
3274 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
3275 #define ECORE_RESC_ALLOC_VERSION \
3276 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
3277 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) | \
3278 (ECORE_RESC_ALLOC_VERSION_MINOR << \
3279 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3281 struct ecore_resc_alloc_in_params {
3283 enum ecore_resources res_id;
3287 struct ecore_resc_alloc_out_params {
3297 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
3299 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3301 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3302 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3303 enum _ecore_status_t rc;
3305 /* Allow ongoing PCIe transactions to complete */
3306 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3308 /* Clear the PF's internal FID_enable in the PXP */
3309 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3310 if (rc != ECORE_SUCCESS)
3311 DP_NOTICE(p_hwfn, false,
3312 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3318 static enum _ecore_status_t
3319 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3320 struct ecore_ptt *p_ptt,
3321 struct ecore_resc_alloc_in_params *p_in_params,
3322 struct ecore_resc_alloc_out_params *p_out_params)
3324 struct ecore_mcp_mb_params mb_params;
3325 struct resource_info mfw_resc_info;
3326 enum _ecore_status_t rc;
3328 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3330 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3331 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3333 "Failed to match resource %d [%s] with the MFW resources\n",
3334 p_in_params->res_id,
3335 ecore_hw_get_resc_name(p_in_params->res_id));
3339 switch (p_in_params->cmd) {
3340 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3341 mfw_resc_info.size = p_in_params->resc_max_val;
3343 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3346 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3351 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3352 mb_params.cmd = p_in_params->cmd;
3353 mb_params.param = ECORE_RESC_ALLOC_VERSION;
3354 mb_params.p_data_src = &mfw_resc_info;
3355 mb_params.data_src_size = sizeof(mfw_resc_info);
3356 mb_params.p_data_dst = mb_params.p_data_src;
3357 mb_params.data_dst_size = mb_params.data_src_size;
3359 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3360 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3361 p_in_params->cmd, p_in_params->res_id,
3362 ecore_hw_get_resc_name(p_in_params->res_id),
3363 GET_MFW_FIELD(mb_params.param,
3364 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3365 GET_MFW_FIELD(mb_params.param,
3366 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3367 p_in_params->resc_max_val);
3369 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3370 if (rc != ECORE_SUCCESS)
3373 p_out_params->mcp_resp = mb_params.mcp_resp;
3374 p_out_params->mcp_param = mb_params.mcp_param;
3375 p_out_params->resc_num = mfw_resc_info.size;
3376 p_out_params->resc_start = mfw_resc_info.offset;
3377 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3378 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3379 p_out_params->flags = mfw_resc_info.flags;
3381 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3382 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3383 GET_MFW_FIELD(p_out_params->mcp_param,
3384 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3385 GET_MFW_FIELD(p_out_params->mcp_param,
3386 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3387 p_out_params->resc_num, p_out_params->resc_start,
3388 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3389 p_out_params->flags);
3391 return ECORE_SUCCESS;
3394 enum _ecore_status_t
3395 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3396 enum ecore_resources res_id, u32 resc_max_val,
3399 struct ecore_resc_alloc_out_params out_params;
3400 struct ecore_resc_alloc_in_params in_params;
3401 enum _ecore_status_t rc;
3403 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3404 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3405 in_params.res_id = res_id;
3406 in_params.resc_max_val = resc_max_val;
3407 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3408 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3410 if (rc != ECORE_SUCCESS)
3413 *p_mcp_resp = out_params.mcp_resp;
3415 return ECORE_SUCCESS;
3418 enum _ecore_status_t
3419 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3420 enum ecore_resources res_id, u32 *p_mcp_resp,
3421 u32 *p_resc_num, u32 *p_resc_start)
3423 struct ecore_resc_alloc_out_params out_params;
3424 struct ecore_resc_alloc_in_params in_params;
3425 enum _ecore_status_t rc;
3427 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3428 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3429 in_params.res_id = res_id;
3430 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3431 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3433 if (rc != ECORE_SUCCESS)
3436 *p_mcp_resp = out_params.mcp_resp;
3438 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3439 *p_resc_num = out_params.resc_num;
3440 *p_resc_start = out_params.resc_start;
3443 return ECORE_SUCCESS;
3446 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3447 struct ecore_ptt *p_ptt)
3449 u32 mcp_resp, mcp_param;
3451 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3452 &mcp_resp, &mcp_param);
3455 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3456 struct ecore_ptt *p_ptt,
3457 u32 param, u32 *p_mcp_resp,
3460 enum _ecore_status_t rc;
3462 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3463 p_mcp_resp, p_mcp_param);
3464 if (rc != ECORE_SUCCESS)
3467 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3469 "The resource command is unsupported by the MFW\n");
3470 return ECORE_NOTIMPL;
3473 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3474 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3476 DP_NOTICE(p_hwfn, false,
3477 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3485 enum _ecore_status_t
3486 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3487 struct ecore_resc_lock_params *p_params)
3489 u32 param = 0, mcp_resp, mcp_param;
3491 enum _ecore_status_t rc;
3493 switch (p_params->timeout) {
3494 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3495 opcode = RESOURCE_OPCODE_REQ;
3496 p_params->timeout = 0;
3498 case ECORE_MCP_RESC_LOCK_TO_NONE:
3499 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3500 p_params->timeout = 0;
3503 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3507 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3508 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3509 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3511 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3512 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3513 param, p_params->timeout, opcode, p_params->resource);
3515 /* Attempt to acquire the resource */
3516 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3518 if (rc != ECORE_SUCCESS)
3521 /* Analyze the response */
3522 p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3523 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3525 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3526 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3527 mcp_param, opcode, p_params->owner);
3530 case RESOURCE_OPCODE_GNT:
3531 p_params->b_granted = true;
3533 case RESOURCE_OPCODE_BUSY:
3534 p_params->b_granted = false;
3537 DP_NOTICE(p_hwfn, false,
3538 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3543 return ECORE_SUCCESS;
3546 enum _ecore_status_t
3547 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3548 struct ecore_resc_lock_params *p_params)
3551 enum _ecore_status_t rc;
3554 /* No need for an interval before the first iteration */
3556 if (p_params->sleep_b4_retry) {
3557 u16 retry_interval_in_ms =
3558 DIV_ROUND_UP(p_params->retry_interval,
3561 OSAL_MSLEEP(retry_interval_in_ms);
3563 OSAL_UDELAY(p_params->retry_interval);
3567 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3568 if (rc != ECORE_SUCCESS)
3571 if (p_params->b_granted)
3573 } while (retry_cnt++ < p_params->retry_num);
3575 return ECORE_SUCCESS;
3578 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3579 struct ecore_resc_unlock_params *p_unlock,
3580 enum ecore_resc_lock resource,
3581 bool b_is_permanent)
3583 if (p_lock != OSAL_NULL) {
3584 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3586 /* Permanent resources don't require aging, and there's no
3587 * point in trying to acquire them more than once since it's
3588 * unexpected another entity would release them.
3590 if (b_is_permanent) {
3591 p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3593 p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3594 p_lock->retry_interval =
3595 ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3596 p_lock->sleep_b4_retry = true;
3599 p_lock->resource = resource;
3602 if (p_unlock != OSAL_NULL) {
3603 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3604 p_unlock->resource = resource;
3608 enum _ecore_status_t
3609 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3610 struct ecore_resc_unlock_params *p_params)
3612 u32 param = 0, mcp_resp, mcp_param;
3614 enum _ecore_status_t rc;
3616 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3617 : RESOURCE_OPCODE_RELEASE;
3618 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3619 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3621 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3622 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3623 param, opcode, p_params->resource);
3625 /* Attempt to release the resource */
3626 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3628 if (rc != ECORE_SUCCESS)
3631 /* Analyze the response */
3632 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3634 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3635 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3639 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3641 "Resource unlock request for an already released resource [%d]\n",
3642 p_params->resource);
3644 case RESOURCE_OPCODE_RELEASED:
3645 p_params->b_released = true;
3647 case RESOURCE_OPCODE_WRONG_OWNER:
3648 p_params->b_released = false;
3651 DP_NOTICE(p_hwfn, false,
3652 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3657 return ECORE_SUCCESS;
3660 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3662 return !!(p_hwfn->mcp_info->capabilities &
3663 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3666 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3667 struct ecore_ptt *p_ptt)
3670 enum _ecore_status_t rc;
3672 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3673 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3674 if (rc == ECORE_SUCCESS)
3675 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3676 "MFW supported features: %08x\n",
3677 p_hwfn->mcp_info->capabilities);
3682 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3683 struct ecore_ptt *p_ptt)
3685 u32 mcp_resp, mcp_param, features;
3687 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3688 DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE |
3689 DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK;
3691 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3692 features, &mcp_resp, &mcp_param);
3695 enum _ecore_status_t
3696 ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3697 struct ecore_mcp_drv_attr *p_drv_attr)
3699 struct attribute_cmd_write_stc attr_cmd_write;
3700 enum _attribute_commands_e mfw_attr_cmd;
3701 struct ecore_mcp_mb_params mb_params;
3702 enum _ecore_status_t rc;
3704 switch (p_drv_attr->attr_cmd) {
3705 case ECORE_MCP_DRV_ATTR_CMD_READ:
3706 mfw_attr_cmd = ATTRIBUTE_CMD_READ;
3708 case ECORE_MCP_DRV_ATTR_CMD_WRITE:
3709 mfw_attr_cmd = ATTRIBUTE_CMD_WRITE;
3711 case ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR:
3712 mfw_attr_cmd = ATTRIBUTE_CMD_READ_CLEAR;
3714 case ECORE_MCP_DRV_ATTR_CMD_CLEAR:
3715 mfw_attr_cmd = ATTRIBUTE_CMD_CLEAR;
3718 DP_NOTICE(p_hwfn, false, "Unknown attribute command %d\n",
3719 p_drv_attr->attr_cmd);
3723 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3724 mb_params.cmd = DRV_MSG_CODE_ATTRIBUTE;
3725 SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_KEY,
3726 p_drv_attr->attr_num);
3727 SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_CMD,
3729 if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_WRITE) {
3730 OSAL_MEM_ZERO(&attr_cmd_write, sizeof(attr_cmd_write));
3731 attr_cmd_write.val = p_drv_attr->val;
3732 attr_cmd_write.mask = p_drv_attr->mask;
3733 attr_cmd_write.offset = p_drv_attr->offset;
3735 mb_params.p_data_src = &attr_cmd_write;
3736 mb_params.data_src_size = sizeof(attr_cmd_write);
3739 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3740 if (rc != ECORE_SUCCESS)
3743 if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3745 "The attribute command is not supported by the MFW\n");
3746 return ECORE_NOTIMPL;
3747 } else if (mb_params.mcp_resp != FW_MSG_CODE_OK) {
3749 "Failed to send an attribute command [mcp_resp 0x%x, attr_cmd %d, attr_num %d]\n",
3750 mb_params.mcp_resp, p_drv_attr->attr_cmd,
3751 p_drv_attr->attr_num);
3755 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3756 "Attribute Command: cmd %d [mfw_cmd %d], num %d, in={val 0x%08x, mask 0x%08x, offset 0x%08x}, out={val 0x%08x}\n",
3757 p_drv_attr->attr_cmd, mfw_attr_cmd, p_drv_attr->attr_num,
3758 p_drv_attr->val, p_drv_attr->mask, p_drv_attr->offset,
3759 mb_params.mcp_param);
3761 if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ ||
3762 p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR)
3763 p_drv_attr->val = mb_params.mcp_param;
3765 return ECORE_SUCCESS;
3768 void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3769 u32 offset, u32 val)
3771 struct ecore_mcp_mb_params mb_params = {0};
3772 enum _ecore_status_t rc = ECORE_SUCCESS;
3775 mb_params.cmd = DRV_MSG_CODE_WRITE_WOL_REG;
3776 mb_params.param = offset;
3777 mb_params.p_data_src = &dword;
3778 mb_params.data_src_size = sizeof(dword);
3780 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3781 if (rc != ECORE_SUCCESS) {
3782 DP_NOTICE(p_hwfn, false,
3783 "Failed to wol write request, rc = %d\n", rc);
3786 if (mb_params.mcp_resp != FW_MSG_CODE_WOL_READ_WRITE_OK) {
3787 DP_NOTICE(p_hwfn, false,
3788 "Failed to write value 0x%x to offset 0x%x [mcp_resp 0x%x]\n",
3789 val, offset, mb_params.mcp_resp);
3790 rc = ECORE_UNKNOWN_ERROR;