2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
23 #include "ecore_sp_commands.h"
25 #define CHIP_MCP_RESP_ITER_US 10
26 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
28 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
29 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
31 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
32 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
35 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
36 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
38 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
39 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
40 OFFSETOF(struct public_drv_mb, _field), _val)
42 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
43 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
44 OFFSETOF(struct public_drv_mb, _field))
46 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
47 DRV_ID_PDA_COMP_VER_OFFSET)
49 #define MCP_BYTES_PER_MBIT_OFFSET 17
53 static int loaded_port[MAX_NUM_PORTS] = { 0 };
56 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
58 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
63 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
65 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
67 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
69 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
71 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
72 "port_addr = 0x%x, port_id 0x%02x\n",
73 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
76 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
78 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
83 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
87 if (!p_hwfn->mcp_info->public_base)
90 for (i = 0; i < length; i++) {
91 tmp = ecore_rd(p_hwfn, p_ptt,
92 p_hwfn->mcp_info->mfw_mb_addr +
93 (i << 2) + sizeof(u32));
95 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
96 OSAL_BE32_TO_CPU(tmp);
100 struct ecore_mcp_cmd_elem {
101 osal_list_entry_t list;
102 struct ecore_mcp_mb_params *p_mb_params;
103 u16 expected_seq_num;
107 /* Must be called while cmd_lock is acquired */
108 static struct ecore_mcp_cmd_elem *
109 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
110 struct ecore_mcp_mb_params *p_mb_params,
111 u16 expected_seq_num)
113 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
115 p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
116 sizeof(*p_cmd_elem));
118 DP_NOTICE(p_hwfn, false,
119 "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
123 p_cmd_elem->p_mb_params = p_mb_params;
124 p_cmd_elem->expected_seq_num = expected_seq_num;
125 OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
130 /* Must be called while cmd_lock is acquired */
131 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
132 struct ecore_mcp_cmd_elem *p_cmd_elem)
134 OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
135 OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
138 /* Must be called while cmd_lock is acquired */
139 static struct ecore_mcp_cmd_elem *
140 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
142 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
144 OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
145 struct ecore_mcp_cmd_elem) {
146 if (p_cmd_elem->expected_seq_num == seq_num)
153 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
155 if (p_hwfn->mcp_info) {
156 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
158 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
159 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
160 &p_hwfn->mcp_info->cmd_list, list,
161 struct ecore_mcp_cmd_elem) {
162 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
164 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
166 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
167 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
168 #ifdef CONFIG_ECORE_LOCK_ALLOC
169 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
170 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
174 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
176 return ECORE_SUCCESS;
179 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
180 struct ecore_ptt *p_ptt)
182 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
183 u32 drv_mb_offsize, mfw_mb_offsize;
184 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
187 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
188 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
189 p_info->public_base = 0;
194 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
195 if (!p_info->public_base)
198 p_info->public_base |= GRCBASE_MCP;
200 /* Calculate the driver and MFW mailbox address */
201 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
202 SECTION_OFFSIZE_ADDR(p_info->public_base,
204 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
205 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
206 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
207 " mcp_pf_id = 0x%x\n",
208 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
210 /* Set the MFW MB address */
211 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
212 SECTION_OFFSIZE_ADDR(p_info->public_base,
214 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
215 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
216 p_info->mfw_mb_addr);
218 /* Get the current driver mailbox sequence before sending
221 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
222 DRV_MSG_SEQ_NUMBER_MASK;
224 /* Get current FW pulse sequence */
225 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
228 p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
230 return ECORE_SUCCESS;
233 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
234 struct ecore_ptt *p_ptt)
236 struct ecore_mcp_info *p_info;
239 /* Allocate mcp_info structure */
240 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
241 sizeof(*p_hwfn->mcp_info));
242 if (!p_hwfn->mcp_info)
244 p_info = p_hwfn->mcp_info;
246 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
247 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
248 /* Do not free mcp_info here, since public_base indicate that
249 * the MCP is not initialized
251 return ECORE_SUCCESS;
254 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
255 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
256 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
257 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
260 /* Initialize the MFW spinlocks */
261 #ifdef CONFIG_ECORE_LOCK_ALLOC
262 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
263 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
265 OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
266 OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
268 OSAL_LIST_INIT(&p_info->cmd_list);
270 return ECORE_SUCCESS;
273 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
274 ecore_mcp_free(p_hwfn);
278 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
279 struct ecore_ptt *p_ptt)
281 u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
283 /* Use MCP history register to check if MCP reset occurred between init
286 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
287 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
288 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
289 p_hwfn->mcp_info->mcp_hist, generic_por_0);
291 ecore_load_mcp_offsets(p_hwfn, p_ptt);
292 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
296 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
297 struct ecore_ptt *p_ptt)
299 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
300 enum _ecore_status_t rc = ECORE_SUCCESS;
303 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
304 delay = EMUL_MCP_RESP_ITER_US;
307 if (p_hwfn->mcp_info->b_block_cmd) {
308 DP_NOTICE(p_hwfn, false,
309 "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
310 return ECORE_ABORTED;
313 /* Ensure that only a single thread is accessing the mailbox */
314 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
316 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
318 /* Set drv command along with the updated sequence */
319 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
320 seq = ++p_hwfn->mcp_info->drv_mb_seq;
321 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
324 /* Wait for MFW response */
326 /* Give the FW up to 500 second (50*1000*10usec) */
327 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
328 MISCS_REG_GENERIC_POR_0)) &&
329 (cnt++ < ECORE_MCP_RESET_RETRIES));
331 if (org_mcp_reset_seq !=
332 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
333 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
334 "MCP was reset after %d usec\n", cnt * delay);
336 DP_ERR(p_hwfn, "Failed to reset MCP\n");
340 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
345 /* Must be called while cmd_lock is acquired */
346 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
348 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
350 /* There is at most one pending command at a certain time, and if it
351 * exists - it is placed at the HEAD of the list.
353 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
354 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
355 struct ecore_mcp_cmd_elem,
357 return !p_cmd_elem->b_is_completed;
363 /* Must be called while cmd_lock is acquired */
364 static enum _ecore_status_t
365 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
367 struct ecore_mcp_mb_params *p_mb_params;
368 struct ecore_mcp_cmd_elem *p_cmd_elem;
372 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
373 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
375 /* Return if no new non-handled response has been received */
376 if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
379 p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
382 "Failed to find a pending mailbox cmd that expects sequence number %d\n",
384 return ECORE_UNKNOWN_ERROR;
387 p_mb_params = p_cmd_elem->p_mb_params;
389 /* Get the MFW response along with the sequence number */
390 p_mb_params->mcp_resp = mcp_resp;
392 /* Get the MFW param */
393 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
395 /* Get the union data */
396 if (p_mb_params->p_data_dst != OSAL_NULL &&
397 p_mb_params->data_dst_size) {
398 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
399 OFFSETOF(struct public_drv_mb,
401 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
402 union_data_addr, p_mb_params->data_dst_size);
405 p_cmd_elem->b_is_completed = true;
407 return ECORE_SUCCESS;
410 /* Must be called while cmd_lock is acquired */
411 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
412 struct ecore_ptt *p_ptt,
413 struct ecore_mcp_mb_params *p_mb_params,
416 union drv_union_data union_data;
419 /* Set the union data */
420 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
421 OFFSETOF(struct public_drv_mb, union_data);
422 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
423 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
424 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
425 p_mb_params->data_src_size);
426 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
429 /* Set the drv param */
430 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
432 /* Set the drv command along with the sequence number */
433 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
435 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
436 "MFW mailbox: command 0x%08x param 0x%08x\n",
437 (p_mb_params->cmd | seq_num), p_mb_params->param);
440 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
443 p_hwfn->mcp_info->b_block_cmd = block_cmd;
445 DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
446 block_cmd ? "Block" : "Unblock");
449 static enum _ecore_status_t
450 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
451 struct ecore_mcp_mb_params *p_mb_params,
452 u32 max_retries, u32 delay)
454 struct ecore_mcp_cmd_elem *p_cmd_elem;
457 enum _ecore_status_t rc = ECORE_SUCCESS;
459 /* Wait until the mailbox is non-occupied */
461 /* Exit the loop if there is no pending command, or if the
462 * pending command is completed during this iteration.
463 * The spinlock stays locked until the command is sent.
466 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
468 if (!ecore_mcp_has_pending_cmd(p_hwfn))
471 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
472 if (rc == ECORE_SUCCESS)
474 else if (rc != ECORE_AGAIN)
477 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
479 } while (++cnt < max_retries);
481 if (cnt >= max_retries) {
482 DP_NOTICE(p_hwfn, false,
483 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
484 p_mb_params->cmd, p_mb_params->param);
488 /* Send the mailbox command */
489 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
490 seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
491 p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
497 __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
498 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
500 /* Wait for the MFW response */
502 /* Exit the loop if the command is already completed, or if the
503 * command is completed during this iteration.
504 * The spinlock stays locked until the list element is removed.
508 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
510 if (p_cmd_elem->b_is_completed)
513 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
514 if (rc == ECORE_SUCCESS)
516 else if (rc != ECORE_AGAIN)
519 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
520 } while (++cnt < max_retries);
522 if (cnt >= max_retries) {
523 DP_NOTICE(p_hwfn, false,
524 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
525 p_mb_params->cmd, p_mb_params->param);
527 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
528 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
529 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
531 ecore_mcp_cmd_set_blocking(p_hwfn, true);
532 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
536 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
537 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
539 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
540 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
541 p_mb_params->mcp_resp, p_mb_params->mcp_param,
542 (cnt * delay) / 1000, (cnt * delay) % 1000);
544 /* Clear the sequence number from the MFW response */
545 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
547 return ECORE_SUCCESS;
550 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
554 static enum _ecore_status_t
555 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
556 struct ecore_ptt *p_ptt,
557 struct ecore_mcp_mb_params *p_mb_params)
559 osal_size_t union_data_size = sizeof(union drv_union_data);
560 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
561 u32 delay = CHIP_MCP_RESP_ITER_US;
564 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
565 delay = EMUL_MCP_RESP_ITER_US;
566 /* There is a built-in delay of 100usec in each MFW response read */
567 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
571 /* MCP not initialized */
572 if (!ecore_mcp_is_init(p_hwfn)) {
573 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
577 if (p_mb_params->data_src_size > union_data_size ||
578 p_mb_params->data_dst_size > union_data_size) {
580 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
581 p_mb_params->data_src_size, p_mb_params->data_dst_size,
586 if (p_hwfn->mcp_info->b_block_cmd) {
587 DP_NOTICE(p_hwfn, false,
588 "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
589 p_mb_params->cmd, p_mb_params->param);
590 return ECORE_ABORTED;
593 return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
597 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
598 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
599 u32 *o_mcp_resp, u32 *o_mcp_param)
601 struct ecore_mcp_mb_params mb_params;
602 enum _ecore_status_t rc;
605 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
606 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
608 loaded_port[p_hwfn->port_id]--;
609 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
612 return ECORE_SUCCESS;
616 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
618 mb_params.param = param;
619 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
620 if (rc != ECORE_SUCCESS)
623 *o_mcp_resp = mb_params.mcp_resp;
624 *o_mcp_param = mb_params.mcp_param;
626 return ECORE_SUCCESS;
629 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
630 struct ecore_ptt *p_ptt,
635 u32 i_txn_size, u32 *i_buf)
637 struct ecore_mcp_mb_params mb_params;
638 enum _ecore_status_t rc;
640 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
642 mb_params.param = param;
643 mb_params.p_data_src = i_buf;
644 mb_params.data_src_size = (u8)i_txn_size;
645 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
646 if (rc != ECORE_SUCCESS)
649 *o_mcp_resp = mb_params.mcp_resp;
650 *o_mcp_param = mb_params.mcp_param;
652 return ECORE_SUCCESS;
655 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
656 struct ecore_ptt *p_ptt,
661 u32 *o_txn_size, u32 *o_buf)
663 struct ecore_mcp_mb_params mb_params;
664 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
665 enum _ecore_status_t rc;
667 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
669 mb_params.param = param;
670 mb_params.p_data_dst = raw_data;
672 /* Use the maximal value since the actual one is part of the response */
673 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
675 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
676 if (rc != ECORE_SUCCESS)
679 *o_mcp_resp = mb_params.mcp_resp;
680 *o_mcp_param = mb_params.mcp_param;
682 *o_txn_size = *o_mcp_param;
684 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
686 return ECORE_SUCCESS;
690 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
693 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
696 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
697 else if (!loaded_port[p_hwfn->port_id])
698 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
700 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
702 /* On CMT, always tell that it's engine */
703 if (p_hwfn->p_dev->num_hwfns > 1)
704 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
706 *p_load_code = load_phase;
708 loaded_port[p_hwfn->port_id]++;
710 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
711 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
712 *p_load_code, loaded, p_hwfn->port_id,
713 loaded_port[p_hwfn->port_id]);
718 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
719 enum ecore_override_force_load override_force_load)
721 bool can_force_load = false;
723 switch (override_force_load) {
724 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
725 can_force_load = true;
727 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
728 can_force_load = false;
731 can_force_load = (drv_role == DRV_ROLE_OS &&
732 exist_drv_role == DRV_ROLE_PREBOOT) ||
733 (drv_role == DRV_ROLE_KDUMP &&
734 exist_drv_role == DRV_ROLE_OS);
738 return can_force_load;
741 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
742 struct ecore_ptt *p_ptt)
744 u32 resp = 0, param = 0;
745 enum _ecore_status_t rc;
747 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
749 if (rc != ECORE_SUCCESS)
750 DP_NOTICE(p_hwfn, false,
751 "Failed to send cancel load request, rc = %d\n", rc);
756 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
757 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
758 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
759 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
760 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
761 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
762 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
764 static u32 ecore_get_config_bitmap(void)
766 u32 config_bitmap = 0x0;
768 #ifdef CONFIG_ECORE_L2
769 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
771 #ifdef CONFIG_ECORE_SRIOV
772 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
774 #ifdef CONFIG_ECORE_ROCE
775 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
777 #ifdef CONFIG_ECORE_IWARP
778 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
780 #ifdef CONFIG_ECORE_FCOE
781 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
783 #ifdef CONFIG_ECORE_ISCSI
784 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
786 #ifdef CONFIG_ECORE_LL2
787 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
790 return config_bitmap;
793 struct ecore_load_req_in_params {
795 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
796 #define ECORE_LOAD_REQ_HSI_VER_1 1
803 bool avoid_eng_reset;
806 struct ecore_load_req_out_params {
816 static enum _ecore_status_t
817 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
818 struct ecore_load_req_in_params *p_in_params,
819 struct ecore_load_req_out_params *p_out_params)
821 struct ecore_mcp_mb_params mb_params;
822 struct load_req_stc load_req;
823 struct load_rsp_stc load_rsp;
825 enum _ecore_status_t rc;
827 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
828 load_req.drv_ver_0 = p_in_params->drv_ver_0;
829 load_req.drv_ver_1 = p_in_params->drv_ver_1;
830 load_req.fw_ver = p_in_params->fw_ver;
831 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
832 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
833 p_in_params->timeout_val);
834 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
835 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
836 p_in_params->avoid_eng_reset);
838 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
839 DRV_ID_MCP_HSI_VER_CURRENT :
840 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
842 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
843 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
844 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
845 mb_params.p_data_src = &load_req;
846 mb_params.data_src_size = sizeof(load_req);
847 mb_params.p_data_dst = &load_rsp;
848 mb_params.data_dst_size = sizeof(load_rsp);
850 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
851 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
853 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
854 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
855 GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
856 GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
858 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
859 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
860 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
861 load_req.drv_ver_0, load_req.drv_ver_1,
862 load_req.fw_ver, load_req.misc0,
863 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
864 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
865 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
866 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
868 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
869 if (rc != ECORE_SUCCESS) {
870 DP_NOTICE(p_hwfn, false,
871 "Failed to send load request, rc = %d\n", rc);
875 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
876 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
877 p_out_params->load_code = mb_params.mcp_resp;
879 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
880 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
881 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
882 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
883 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
884 load_rsp.fw_ver, load_rsp.misc0,
885 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
886 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
887 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
889 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
890 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
891 p_out_params->exist_fw_ver = load_rsp.fw_ver;
892 p_out_params->exist_drv_role =
893 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
894 p_out_params->mfw_hsi_ver =
895 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
896 p_out_params->drv_exists =
897 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
898 LOAD_RSP_FLAGS0_DRV_EXISTS;
901 return ECORE_SUCCESS;
904 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
908 case ECORE_DRV_ROLE_OS:
909 *p_mfw_drv_role = DRV_ROLE_OS;
911 case ECORE_DRV_ROLE_KDUMP:
912 *p_mfw_drv_role = DRV_ROLE_KDUMP;
917 enum ecore_load_req_force {
918 ECORE_LOAD_REQ_FORCE_NONE,
919 ECORE_LOAD_REQ_FORCE_PF,
920 ECORE_LOAD_REQ_FORCE_ALL,
923 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
927 case ECORE_LOAD_REQ_FORCE_NONE:
928 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
930 case ECORE_LOAD_REQ_FORCE_PF:
931 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
933 case ECORE_LOAD_REQ_FORCE_ALL:
934 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
939 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
940 struct ecore_ptt *p_ptt,
941 struct ecore_load_req_params *p_params)
943 struct ecore_load_req_out_params out_params;
944 struct ecore_load_req_in_params in_params;
945 u8 mfw_drv_role = 0, mfw_force_cmd;
946 enum _ecore_status_t rc;
949 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
950 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
951 return ECORE_SUCCESS;
955 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
956 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
957 in_params.drv_ver_0 = ECORE_VERSION;
958 in_params.drv_ver_1 = ecore_get_config_bitmap();
959 in_params.fw_ver = STORM_FW_VERSION;
960 ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
961 in_params.drv_role = mfw_drv_role;
962 in_params.timeout_val = p_params->timeout_val;
963 ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
964 in_params.force_cmd = mfw_force_cmd;
965 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
967 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
968 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
969 if (rc != ECORE_SUCCESS)
972 /* First handle cases where another load request should/might be sent:
973 * - MFW expects the old interface [HSI version = 1]
974 * - MFW responds that a force load request is required
976 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
978 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
980 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
981 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
982 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
984 if (rc != ECORE_SUCCESS)
986 } else if (out_params.load_code ==
987 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
988 if (ecore_mcp_can_force_load(in_params.drv_role,
989 out_params.exist_drv_role,
990 p_params->override_force_load)) {
992 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
993 in_params.drv_role, in_params.fw_ver,
994 in_params.drv_ver_0, in_params.drv_ver_1,
995 out_params.exist_drv_role,
996 out_params.exist_fw_ver,
997 out_params.exist_drv_ver_0,
998 out_params.exist_drv_ver_1);
1000 ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1003 in_params.force_cmd = mfw_force_cmd;
1004 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1005 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1007 if (rc != ECORE_SUCCESS)
1010 DP_NOTICE(p_hwfn, false,
1011 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1012 in_params.drv_role, in_params.fw_ver,
1013 in_params.drv_ver_0, in_params.drv_ver_1,
1014 out_params.exist_drv_role,
1015 out_params.exist_fw_ver,
1016 out_params.exist_drv_ver_0,
1017 out_params.exist_drv_ver_1);
1019 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1024 /* Now handle the other types of responses.
1025 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1026 * expected here after the additional revised load requests were sent.
1028 switch (out_params.load_code) {
1029 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1030 case FW_MSG_CODE_DRV_LOAD_PORT:
1031 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1032 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1033 out_params.drv_exists) {
1034 /* The role and fw/driver version match, but the PF is
1035 * already loaded and has not been unloaded gracefully.
1036 * This is unexpected since a quasi-FLR request was
1037 * previously sent as part of ecore_hw_prepare().
1039 DP_NOTICE(p_hwfn, false,
1040 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1045 DP_NOTICE(p_hwfn, false,
1046 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1047 out_params.load_code);
1051 p_params->load_code = out_params.load_code;
1053 return ECORE_SUCCESS;
1056 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1057 struct ecore_ptt *p_ptt)
1059 u32 resp = 0, param = 0;
1060 enum _ecore_status_t rc;
1062 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1064 if (rc != ECORE_SUCCESS) {
1065 DP_NOTICE(p_hwfn, false,
1066 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1070 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
1072 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1073 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1074 DP_NOTICE(p_hwfn, false,
1075 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1077 return ECORE_SUCCESS;
1080 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1081 struct ecore_ptt *p_ptt)
1083 u32 wol_param, mcp_resp, mcp_param;
1086 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1088 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1089 &mcp_resp, &mcp_param);
1092 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1093 struct ecore_ptt *p_ptt)
1095 struct ecore_mcp_mb_params mb_params;
1096 struct mcp_mac wol_mac;
1098 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1099 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1101 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1104 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1105 struct ecore_ptt *p_ptt)
1107 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1109 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1110 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1111 ECORE_PATH_ID(p_hwfn));
1112 u32 disabled_vfs[VF_MAX_STATIC / 32];
1115 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1116 "Reading Disabled VF information from [offset %08x],"
1117 " path_addr %08x\n",
1118 mfw_path_offsize, path_addr);
1120 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1121 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1123 OFFSETOF(struct public_path,
1126 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1127 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1128 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1131 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1132 OSAL_VF_FLR_UPDATE(p_hwfn);
1135 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1136 struct ecore_ptt *p_ptt,
1139 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1141 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1142 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1144 struct ecore_mcp_mb_params mb_params;
1145 enum _ecore_status_t rc;
1148 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1149 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1150 "Acking VFs [%08x,...,%08x] - %08x\n",
1151 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1153 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1154 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1155 mb_params.p_data_src = vfs_to_ack;
1156 mb_params.data_src_size = VF_MAX_STATIC / 8;
1157 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1159 if (rc != ECORE_SUCCESS) {
1160 DP_NOTICE(p_hwfn, false,
1161 "Failed to pass ACK for VF flr to MFW\n");
1162 return ECORE_TIMEOUT;
1165 /* TMP - clear the ACK bits; should be done by MFW */
1166 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1167 ecore_wr(p_hwfn, p_ptt,
1169 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1170 i * sizeof(u32), 0);
1175 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1176 struct ecore_ptt *p_ptt)
1178 u32 transceiver_state;
1180 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1181 p_hwfn->mcp_info->port_addr +
1182 OFFSETOF(struct public_port,
1185 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1186 "Received transceiver state update [0x%08x] from mfw"
1188 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1189 OFFSETOF(struct public_port,
1190 transceiver_data)));
1192 transceiver_state = GET_MFW_FIELD(transceiver_state,
1193 ETH_TRANSCEIVER_STATE);
1195 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1196 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1198 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1201 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1202 struct ecore_ptt *p_ptt,
1203 struct ecore_mcp_link_state *p_link)
1205 u32 eee_status, val;
1207 p_link->eee_adv_caps = 0;
1208 p_link->eee_lp_adv_caps = 0;
1209 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1210 OFFSETOF(struct public_port, eee_status));
1211 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1212 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1213 if (val & EEE_1G_ADV)
1214 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1215 if (val & EEE_10G_ADV)
1216 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1217 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1218 if (val & EEE_1G_ADV)
1219 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1220 if (val & EEE_10G_ADV)
1221 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1224 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1225 struct ecore_ptt *p_ptt,
1228 struct ecore_mcp_link_state *p_link;
1232 /* Prevent SW/attentions from doing this at the same time */
1233 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1235 p_link = &p_hwfn->mcp_info->link_output;
1236 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1238 status = ecore_rd(p_hwfn, p_ptt,
1239 p_hwfn->mcp_info->port_addr +
1240 OFFSETOF(struct public_port, link_status));
1241 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1242 "Received link update [0x%08x] from mfw"
1244 status, (u32)(p_hwfn->mcp_info->port_addr +
1245 OFFSETOF(struct public_port,
1248 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1249 "Resetting link indications\n");
1253 if (p_hwfn->b_drv_link_init)
1254 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1256 p_link->link_up = false;
1258 p_link->full_duplex = true;
1259 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1260 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1261 p_link->speed = 100000;
1263 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1264 p_link->speed = 50000;
1266 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1267 p_link->speed = 40000;
1269 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1270 p_link->speed = 25000;
1272 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1273 p_link->speed = 20000;
1275 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1276 p_link->speed = 10000;
1278 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1279 p_link->full_duplex = false;
1281 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1282 p_link->speed = 1000;
1288 /* We never store total line speed as p_link->speed is
1289 * again changes according to bandwidth allocation.
1291 if (p_link->link_up && p_link->speed)
1292 p_link->line_speed = p_link->speed;
1294 p_link->line_speed = 0;
1296 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1297 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1299 /* Max bandwidth configuration */
1300 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1303 /* Mintz bandwidth configuration */
1304 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1306 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1307 p_link->min_pf_rate);
1309 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1310 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1311 p_link->parallel_detection = !!(status &
1312 LINK_STATUS_PARALLEL_DETECTION_USED);
1313 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1315 p_link->partner_adv_speed |=
1316 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1317 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1318 p_link->partner_adv_speed |=
1319 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1320 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1321 p_link->partner_adv_speed |=
1322 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1323 ECORE_LINK_PARTNER_SPEED_10G : 0;
1324 p_link->partner_adv_speed |=
1325 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1326 ECORE_LINK_PARTNER_SPEED_20G : 0;
1327 p_link->partner_adv_speed |=
1328 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1329 ECORE_LINK_PARTNER_SPEED_25G : 0;
1330 p_link->partner_adv_speed |=
1331 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1332 ECORE_LINK_PARTNER_SPEED_40G : 0;
1333 p_link->partner_adv_speed |=
1334 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1335 ECORE_LINK_PARTNER_SPEED_50G : 0;
1336 p_link->partner_adv_speed |=
1337 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1338 ECORE_LINK_PARTNER_SPEED_100G : 0;
1340 p_link->partner_tx_flow_ctrl_en =
1341 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1342 p_link->partner_rx_flow_ctrl_en =
1343 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1345 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1346 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1347 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1349 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1350 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1352 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1353 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1356 p_link->partner_adv_pause = 0;
1359 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1361 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1362 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1364 OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1366 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1369 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1370 struct ecore_ptt *p_ptt, bool b_up)
1372 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1373 struct ecore_mcp_mb_params mb_params;
1374 struct eth_phy_cfg phy_cfg;
1375 enum _ecore_status_t rc = ECORE_SUCCESS;
1379 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1380 return ECORE_SUCCESS;
1383 /* Set the shmem configuration according to params */
1384 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1385 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1386 if (!params->speed.autoneg)
1387 phy_cfg.speed = params->speed.forced_speed;
1388 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1389 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1390 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1391 phy_cfg.adv_speed = params->speed.advertised_speeds;
1392 phy_cfg.loopback_mode = params->loopback_mode;
1394 /* There are MFWs that share this capability regardless of whether
1395 * this is feasible or not. And given that at the very least adv_caps
1396 * would be set internally by ecore, we want to make sure LFA would
1399 if ((p_hwfn->mcp_info->capabilities &
1400 FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1401 params->eee.enable) {
1402 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1403 if (params->eee.tx_lpi_enable)
1404 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1405 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1406 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1407 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1408 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1409 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1410 EEE_TX_TIMER_USEC_OFFSET) &
1411 EEE_TX_TIMER_USEC_MASK;
1414 p_hwfn->b_drv_link_init = b_up;
1417 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1418 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1419 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1420 phy_cfg.loopback_mode);
1422 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1424 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1425 mb_params.cmd = cmd;
1426 mb_params.p_data_src = &phy_cfg;
1427 mb_params.data_src_size = sizeof(phy_cfg);
1428 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1430 /* if mcp fails to respond we must abort */
1431 if (rc != ECORE_SUCCESS) {
1432 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1436 /* Mimic link-change attention, done for several reasons:
1437 * - On reset, there's no guarantee MFW would trigger
1439 * - On initialization, older MFWs might not indicate link change
1440 * during LFA, so we'll never get an UP indication.
1442 ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1444 return ECORE_SUCCESS;
1447 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1448 struct ecore_ptt *p_ptt)
1450 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1452 /* TODO - Add support for VFs */
1453 if (IS_VF(p_hwfn->p_dev))
1456 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1458 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1459 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1461 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1463 OFFSETOF(struct public_path, process_kill)) &
1464 PROCESS_KILL_COUNTER_MASK;
1466 return proc_kill_cnt;
1469 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1470 struct ecore_ptt *p_ptt)
1472 struct ecore_dev *p_dev = p_hwfn->p_dev;
1475 /* Prevent possible attentions/interrupts during the recovery handling
1476 * and till its load phase, during which they will be re-enabled.
1478 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1480 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1482 /* The following operations should be done once, and thus in CMT mode
1483 * are carried out by only the first HW function.
1485 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1488 if (p_dev->recov_in_prog) {
1489 DP_NOTICE(p_hwfn, false,
1490 "Ignoring the indication since a recovery"
1491 " process is already in progress\n");
1495 p_dev->recov_in_prog = true;
1497 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1498 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1500 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1503 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1504 struct ecore_ptt *p_ptt,
1505 enum MFW_DRV_MSG_TYPE type)
1507 enum ecore_mcp_protocol_type stats_type;
1508 union ecore_mcp_protocol_stats stats;
1509 struct ecore_mcp_mb_params mb_params;
1511 enum _ecore_status_t rc;
1514 case MFW_DRV_MSG_GET_LAN_STATS:
1515 stats_type = ECORE_MCP_LAN_STATS;
1516 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1519 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1523 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1525 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1526 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1527 mb_params.param = hsi_param;
1528 mb_params.p_data_src = &stats;
1529 mb_params.data_src_size = sizeof(stats);
1530 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1531 if (rc != ECORE_SUCCESS)
1532 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1535 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1536 struct public_func *p_shmem_info)
1538 struct ecore_mcp_function_info *p_info;
1540 p_info = &p_hwfn->mcp_info->func_info;
1542 /* TODO - bandwidth min/max should have valid values of 1-100,
1543 * as well as some indication that the feature is disabled.
1544 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1545 * limit and correct value to min `1' and max `100' if limit isn't in
1548 p_info->bandwidth_min = (p_shmem_info->config &
1549 FUNC_MF_CFG_MIN_BW_MASK) >>
1550 FUNC_MF_CFG_MIN_BW_OFFSET;
1551 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1553 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1554 p_info->bandwidth_min);
1555 p_info->bandwidth_min = 1;
1558 p_info->bandwidth_max = (p_shmem_info->config &
1559 FUNC_MF_CFG_MAX_BW_MASK) >>
1560 FUNC_MF_CFG_MAX_BW_OFFSET;
1561 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1563 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1564 p_info->bandwidth_max);
1565 p_info->bandwidth_max = 100;
1569 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1570 struct ecore_ptt *p_ptt,
1571 struct public_func *p_data,
1574 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1576 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1577 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1580 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1582 size = OSAL_MIN_T(u32, sizeof(*p_data),
1583 SECTION_SIZE(mfw_path_offsize));
1584 for (i = 0; i < size / sizeof(u32); i++)
1585 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1586 func_addr + (i << 2));
1592 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1594 struct ecore_mcp_function_info *p_info;
1595 struct public_func shmem_info;
1596 u32 resp = 0, param = 0;
1598 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1600 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1602 p_info = &p_hwfn->mcp_info->func_info;
1604 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1606 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1608 /* Acknowledge the MFW */
1609 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1613 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1615 /* A single notification should be sent to upper driver in CMT mode */
1616 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1619 DP_NOTICE(p_hwfn, false,
1620 "Fan failure was detected on the network interface card"
1621 " and it's going to be shut down.\n");
1623 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1626 struct ecore_mdump_cmd_params {
1635 static enum _ecore_status_t
1636 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1637 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1639 struct ecore_mcp_mb_params mb_params;
1640 enum _ecore_status_t rc;
1642 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1643 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1644 mb_params.param = p_mdump_cmd_params->cmd;
1645 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1646 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1647 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1648 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1649 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1650 if (rc != ECORE_SUCCESS)
1653 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1655 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1657 "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1658 p_mdump_cmd_params->cmd);
1660 } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1662 "The mdump command is not supported by the MFW\n");
1669 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1670 struct ecore_ptt *p_ptt)
1672 struct ecore_mdump_cmd_params mdump_cmd_params;
1674 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1675 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1677 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1680 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1681 struct ecore_ptt *p_ptt,
1684 struct ecore_mdump_cmd_params mdump_cmd_params;
1686 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1687 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1688 mdump_cmd_params.p_data_src = &epoch;
1689 mdump_cmd_params.data_src_size = sizeof(epoch);
1691 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1694 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1695 struct ecore_ptt *p_ptt)
1697 struct ecore_mdump_cmd_params mdump_cmd_params;
1699 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1700 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1702 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1705 static enum _ecore_status_t
1706 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1707 struct mdump_config_stc *p_mdump_config)
1709 struct ecore_mdump_cmd_params mdump_cmd_params;
1710 enum _ecore_status_t rc;
1712 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1713 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1714 mdump_cmd_params.p_data_dst = p_mdump_config;
1715 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1717 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1718 if (rc != ECORE_SUCCESS)
1721 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1723 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1724 mdump_cmd_params.mcp_resp);
1725 rc = ECORE_UNKNOWN_ERROR;
1731 enum _ecore_status_t
1732 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1733 struct ecore_mdump_info *p_mdump_info)
1735 u32 addr, global_offsize, global_addr;
1736 struct mdump_config_stc mdump_config;
1737 enum _ecore_status_t rc;
1739 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1741 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1743 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1744 global_addr = SECTION_ADDR(global_offsize, 0);
1745 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1747 OFFSETOF(struct public_global,
1750 if (p_mdump_info->reason) {
1751 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1752 if (rc != ECORE_SUCCESS)
1755 p_mdump_info->version = mdump_config.version;
1756 p_mdump_info->config = mdump_config.config;
1757 p_mdump_info->epoch = mdump_config.epoc;
1758 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1759 p_mdump_info->valid_logs = mdump_config.valid_logs;
1761 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1762 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1763 p_mdump_info->reason, p_mdump_info->version,
1764 p_mdump_info->config, p_mdump_info->epoch,
1765 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1767 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1768 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1771 return ECORE_SUCCESS;
1774 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1775 struct ecore_ptt *p_ptt)
1777 struct ecore_mdump_cmd_params mdump_cmd_params;
1779 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1780 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1782 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1785 enum _ecore_status_t
1786 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1787 struct ecore_mdump_retain_data *p_mdump_retain)
1789 struct ecore_mdump_cmd_params mdump_cmd_params;
1790 struct mdump_retain_data_stc mfw_mdump_retain;
1791 enum _ecore_status_t rc;
1793 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1794 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1795 mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1796 mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1798 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1799 if (rc != ECORE_SUCCESS)
1802 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1804 "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1805 mdump_cmd_params.mcp_resp);
1806 return ECORE_UNKNOWN_ERROR;
1809 p_mdump_retain->valid = mfw_mdump_retain.valid;
1810 p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1811 p_mdump_retain->pf = mfw_mdump_retain.pf;
1812 p_mdump_retain->status = mfw_mdump_retain.status;
1814 return ECORE_SUCCESS;
1817 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1818 struct ecore_ptt *p_ptt)
1820 struct ecore_mdump_cmd_params mdump_cmd_params;
1822 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1823 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1825 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1828 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1829 struct ecore_ptt *p_ptt)
1831 struct ecore_mdump_retain_data mdump_retain;
1832 enum _ecore_status_t rc;
1834 /* In CMT mode - no need for more than a single acknowledgment to the
1835 * MFW, and no more than a single notification to the upper driver.
1837 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1840 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1841 if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1842 DP_NOTICE(p_hwfn, false,
1843 "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1844 mdump_retain.epoch, mdump_retain.pf,
1845 mdump_retain.status);
1847 DP_NOTICE(p_hwfn, false,
1848 "The MFW notified that a critical error occurred in the device\n");
1851 if (p_hwfn->p_dev->allow_mdump) {
1852 DP_NOTICE(p_hwfn, false,
1853 "Not acknowledging the notification to allow the MFW crash dump\n");
1857 DP_NOTICE(p_hwfn, false,
1858 "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1859 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1860 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1863 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1864 struct ecore_ptt *p_ptt)
1866 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1867 enum _ecore_status_t rc = ECORE_SUCCESS;
1871 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1873 /* Read Messages from MFW */
1874 ecore_mcp_read_mb(p_hwfn, p_ptt);
1876 /* Compare current messages to old ones */
1877 for (i = 0; i < info->mfw_mb_length; i++) {
1878 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1883 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1884 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1885 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1888 case MFW_DRV_MSG_LINK_CHANGE:
1889 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1891 case MFW_DRV_MSG_VF_DISABLED:
1892 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1894 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1895 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1896 ECORE_DCBX_REMOTE_LLDP_MIB);
1898 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1899 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1900 ECORE_DCBX_REMOTE_MIB);
1902 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1903 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1904 ECORE_DCBX_OPERATIONAL_MIB);
1906 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1907 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1909 case MFW_DRV_MSG_ERROR_RECOVERY:
1910 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1912 case MFW_DRV_MSG_GET_LAN_STATS:
1913 case MFW_DRV_MSG_GET_FCOE_STATS:
1914 case MFW_DRV_MSG_GET_ISCSI_STATS:
1915 case MFW_DRV_MSG_GET_RDMA_STATS:
1916 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1918 case MFW_DRV_MSG_BW_UPDATE:
1919 ecore_mcp_update_bw(p_hwfn, p_ptt);
1921 case MFW_DRV_MSG_FAILURE_DETECTED:
1922 ecore_mcp_handle_fan_failure(p_hwfn);
1924 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1925 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1928 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1933 /* ACK everything */
1934 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1935 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1937 /* MFW expect answer in BE, so we force write in that format */
1938 ecore_wr(p_hwfn, p_ptt,
1939 info->mfw_mb_addr + sizeof(u32) +
1940 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1941 sizeof(u32) + i * sizeof(u32), val);
1945 DP_NOTICE(p_hwfn, false,
1946 "Received an MFW message indication but no"
1951 /* Copy the new mfw messages into the shadow */
1952 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1957 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1958 struct ecore_ptt *p_ptt,
1960 u32 *p_running_bundle_id)
1965 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1966 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1967 return ECORE_SUCCESS;
1971 if (IS_VF(p_hwfn->p_dev)) {
1972 if (p_hwfn->vf_iov_info) {
1973 struct pfvf_acquire_resp_tlv *p_resp;
1975 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1976 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1977 return ECORE_SUCCESS;
1979 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1980 "VF requested MFW version prior to ACQUIRE\n");
1985 global_offsize = ecore_rd(p_hwfn, p_ptt,
1986 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1990 ecore_rd(p_hwfn, p_ptt,
1991 SECTION_ADDR(global_offsize,
1992 0) + OFFSETOF(struct public_global, mfw_ver));
1994 if (p_running_bundle_id != OSAL_NULL) {
1995 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1996 SECTION_ADDR(global_offsize,
1998 OFFSETOF(struct public_global,
1999 running_bundle_id));
2002 return ECORE_SUCCESS;
2005 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2006 struct ecore_ptt *p_ptt,
2010 /* TODO - Add support for VFs */
2011 if (IS_VF(p_hwfn->p_dev))
2014 if (!ecore_mcp_is_init(p_hwfn)) {
2015 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2020 *p_media_type = MEDIA_UNSPECIFIED;
2023 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2024 p_hwfn->mcp_info->port_addr +
2025 OFFSETOF(struct public_port,
2029 return ECORE_SUCCESS;
2033 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2035 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2036 enum ecore_pci_personality *p_proto)
2038 *p_proto = ECORE_PCI_ETH;
2040 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2041 "According to Legacy capabilities, L2 personality is %08x\n",
2046 static enum _ecore_status_t
2047 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2048 struct ecore_ptt *p_ptt,
2049 enum ecore_pci_personality *p_proto)
2051 u32 resp = 0, param = 0;
2052 enum _ecore_status_t rc;
2054 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2055 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2056 (u32)*p_proto, resp, param);
2057 return ECORE_SUCCESS;
2060 static enum _ecore_status_t
2061 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2062 struct public_func *p_info,
2063 struct ecore_ptt *p_ptt,
2064 enum ecore_pci_personality *p_proto)
2066 enum _ecore_status_t rc = ECORE_SUCCESS;
2068 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2069 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2070 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2072 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2081 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2082 struct ecore_ptt *p_ptt)
2084 struct ecore_mcp_function_info *info;
2085 struct public_func shmem_info;
2087 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2088 info = &p_hwfn->mcp_info->func_info;
2090 info->pause_on_host = (shmem_info.config &
2091 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2093 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2095 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2096 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2100 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2102 if (shmem_info.mac_upper || shmem_info.mac_lower) {
2103 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2104 info->mac[1] = (u8)(shmem_info.mac_upper);
2105 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2106 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2107 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2108 info->mac[5] = (u8)(shmem_info.mac_lower);
2110 /* TODO - are there protocols for which there's no MAC? */
2111 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2114 /* TODO - are these calculations true for BE machine? */
2115 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2116 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2117 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2118 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2120 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2122 info->mtu = (u16)shmem_info.mtu_size;
2127 info->mtu = (u16)shmem_info.mtu_size;
2129 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2130 "Read configuration from shmem: pause_on_host %02x"
2131 " protocol %02x BW [%02x - %02x]"
2132 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2133 " node %lx ovlan %04x\n",
2134 info->pause_on_host, info->protocol,
2135 info->bandwidth_min, info->bandwidth_max,
2136 info->mac[0], info->mac[1], info->mac[2],
2137 info->mac[3], info->mac[4], info->mac[5],
2138 (unsigned long)info->wwn_port,
2139 (unsigned long)info->wwn_node, info->ovlan);
2141 return ECORE_SUCCESS;
2144 struct ecore_mcp_link_params
2145 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2147 if (!p_hwfn || !p_hwfn->mcp_info)
2149 return &p_hwfn->mcp_info->link_input;
2152 struct ecore_mcp_link_state
2153 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2155 if (!p_hwfn || !p_hwfn->mcp_info)
2159 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2160 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2161 p_hwfn->mcp_info->link_output.link_up = true;
2165 return &p_hwfn->mcp_info->link_output;
2168 struct ecore_mcp_link_capabilities
2169 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2171 if (!p_hwfn || !p_hwfn->mcp_info)
2173 return &p_hwfn->mcp_info->link_capabilities;
2176 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2177 struct ecore_ptt *p_ptt)
2179 u32 resp = 0, param = 0;
2180 enum _ecore_status_t rc;
2182 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2183 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
2185 /* Wait for the drain to complete before returning */
2191 const struct ecore_mcp_function_info
2192 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2194 if (!p_hwfn || !p_hwfn->mcp_info)
2196 return &p_hwfn->mcp_info->func_info;
2199 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2200 struct ecore_ptt *p_ptt, u32 personalities)
2202 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2203 struct public_func shmem_info;
2204 int i, count = 0, num_pfs;
2206 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2208 for (i = 0; i < num_pfs; i++) {
2209 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2210 MCP_PF_ID_BY_REL(p_hwfn, i));
2211 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2214 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2219 if ((1 << ((u32)protocol)) & personalities)
2226 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2227 struct ecore_ptt *p_ptt,
2233 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2234 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2239 if (IS_VF(p_hwfn->p_dev))
2242 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2243 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2244 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2245 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2247 *p_flash_size = flash_size;
2249 return ECORE_SUCCESS;
2252 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2253 struct ecore_ptt *p_ptt)
2255 struct ecore_dev *p_dev = p_hwfn->p_dev;
2257 if (p_dev->recov_in_prog) {
2258 DP_NOTICE(p_hwfn, false,
2259 "Avoid triggering a recovery since such a process"
2260 " is already in progress\n");
2264 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2265 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2267 return ECORE_SUCCESS;
2270 static enum _ecore_status_t
2271 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2272 struct ecore_ptt *p_ptt,
2275 u32 resp = 0, param = 0, rc_param = 0;
2276 enum _ecore_status_t rc;
2278 /* Only Leader can configure MSIX, and need to take CMT into account */
2280 if (!IS_LEAD_HWFN(p_hwfn))
2281 return ECORE_SUCCESS;
2282 num *= p_hwfn->p_dev->num_hwfns;
2284 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2285 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2286 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2287 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2289 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2292 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2293 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2297 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2298 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2305 static enum _ecore_status_t
2306 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2307 struct ecore_ptt *p_ptt,
2310 u32 resp = 0, param = num, rc_param = 0;
2311 enum _ecore_status_t rc;
2313 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2314 param, &resp, &rc_param);
2316 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2317 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2320 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2321 "Requested 0x%02x MSI-x interrupts for VFs\n",
2328 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2329 struct ecore_ptt *p_ptt,
2332 if (ECORE_IS_BB(p_hwfn->p_dev))
2333 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2335 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2338 enum _ecore_status_t
2339 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2340 struct ecore_mcp_drv_version *p_ver)
2342 struct ecore_mcp_mb_params mb_params;
2343 struct drv_version_stc drv_version;
2347 enum _ecore_status_t rc;
2350 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2351 return ECORE_SUCCESS;
2354 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2355 drv_version.version = p_ver->version;
2356 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2357 for (i = 0; i < num_words; i++) {
2358 /* The driver name is expected to be in a big-endian format */
2359 p_name = &p_ver->name[i * sizeof(u32)];
2360 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2361 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2364 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2365 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2366 mb_params.p_data_src = &drv_version;
2367 mb_params.data_src_size = sizeof(drv_version);
2368 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2369 if (rc != ECORE_SUCCESS)
2370 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2375 /* A maximal 100 msec waiting time for the MCP to halt */
2376 #define ECORE_MCP_HALT_SLEEP_MS 10
2377 #define ECORE_MCP_HALT_MAX_RETRIES 10
2379 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2380 struct ecore_ptt *p_ptt)
2382 u32 resp = 0, param = 0, cpu_state, cnt = 0;
2383 enum _ecore_status_t rc;
2385 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2387 if (rc != ECORE_SUCCESS) {
2388 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2393 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2394 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2395 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2397 } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2399 if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2400 DP_NOTICE(p_hwfn, false,
2401 "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2402 ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2406 ecore_mcp_cmd_set_blocking(p_hwfn, true);
2408 return ECORE_SUCCESS;
2411 #define ECORE_MCP_RESUME_SLEEP_MS 10
2413 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2414 struct ecore_ptt *p_ptt)
2416 u32 cpu_mode, cpu_state;
2418 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2420 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2421 cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2422 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2424 OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2425 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2427 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2428 DP_NOTICE(p_hwfn, false,
2429 "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2430 cpu_mode, cpu_state);
2434 ecore_mcp_cmd_set_blocking(p_hwfn, false);
2436 return ECORE_SUCCESS;
2439 enum _ecore_status_t
2440 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2441 struct ecore_ptt *p_ptt,
2442 enum ecore_ov_client client)
2444 enum _ecore_status_t rc;
2445 u32 resp = 0, param = 0;
2449 case ECORE_OV_CLIENT_DRV:
2450 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2452 case ECORE_OV_CLIENT_USER:
2453 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2455 case ECORE_OV_CLIENT_VENDOR_SPEC:
2456 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2459 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2463 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2464 drv_mb_param, &resp, ¶m);
2465 if (rc != ECORE_SUCCESS)
2466 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2471 enum _ecore_status_t
2472 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2473 struct ecore_ptt *p_ptt,
2474 enum ecore_ov_driver_state drv_state)
2476 enum _ecore_status_t rc;
2477 u32 resp = 0, param = 0;
2480 switch (drv_state) {
2481 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2482 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2484 case ECORE_OV_DRIVER_STATE_DISABLED:
2485 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2487 case ECORE_OV_DRIVER_STATE_ACTIVE:
2488 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2491 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2495 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2496 drv_mb_param, &resp, ¶m);
2497 if (rc != ECORE_SUCCESS)
2498 DP_ERR(p_hwfn, "Failed to send driver state\n");
2503 enum _ecore_status_t
2504 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2505 struct ecore_fc_npiv_tbl *p_table)
2510 enum _ecore_status_t
2511 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2512 struct ecore_ptt *p_ptt, u16 mtu)
2517 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2518 struct ecore_ptt *p_ptt,
2519 enum ecore_led_mode mode)
2521 u32 resp = 0, param = 0, drv_mb_param;
2522 enum _ecore_status_t rc;
2525 case ECORE_LED_MODE_ON:
2526 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2528 case ECORE_LED_MODE_OFF:
2529 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2531 case ECORE_LED_MODE_RESTORE:
2532 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2535 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2539 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2540 drv_mb_param, &resp, ¶m);
2541 if (rc != ECORE_SUCCESS)
2542 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2547 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2548 struct ecore_ptt *p_ptt,
2551 u32 resp = 0, param = 0;
2552 enum _ecore_status_t rc;
2554 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2555 mask_parities, &resp, ¶m);
2557 if (rc != ECORE_SUCCESS) {
2559 "MCP response failure for mask parities, aborting\n");
2560 } else if (resp != FW_MSG_CODE_OK) {
2562 "MCP did not ack mask parity request. Old MFW?\n");
2569 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2572 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2573 u32 bytes_left, offset, bytes_to_copy, buf_size;
2574 u32 nvm_offset, resp, param;
2575 struct ecore_ptt *p_ptt;
2576 enum _ecore_status_t rc = ECORE_SUCCESS;
2578 p_ptt = ecore_ptt_acquire(p_hwfn);
2584 while (bytes_left > 0) {
2585 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2586 MCP_DRV_NVM_BUF_LEN);
2587 nvm_offset = (addr + offset) | (bytes_to_copy <<
2588 DRV_MB_PARAM_NVM_LEN_OFFSET);
2589 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2590 DRV_MSG_CODE_NVM_READ_NVRAM,
2591 nvm_offset, &resp, ¶m, &buf_size,
2592 (u32 *)(p_buf + offset));
2593 if (rc != ECORE_SUCCESS) {
2594 DP_NOTICE(p_dev, false,
2595 "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2597 resp = FW_MSG_CODE_ERROR;
2601 if (resp != FW_MSG_CODE_NVM_OK) {
2602 DP_NOTICE(p_dev, false,
2603 "nvm read failed, resp = 0x%08x\n", resp);
2604 rc = ECORE_UNKNOWN_ERROR;
2608 /* This can be a lengthy process, and it's possible scheduler
2609 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2611 if (bytes_left % 0x1000 <
2612 (bytes_left - buf_size) % 0x1000)
2616 bytes_left -= buf_size;
2619 p_dev->mcp_nvm_resp = resp;
2620 ecore_ptt_release(p_hwfn, p_ptt);
2625 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2626 u32 addr, u8 *p_buf, u32 len)
2628 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2629 struct ecore_ptt *p_ptt;
2631 enum _ecore_status_t rc;
2633 p_ptt = ecore_ptt_acquire(p_hwfn);
2637 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2638 (cmd == ECORE_PHY_CORE_READ) ?
2639 DRV_MSG_CODE_PHY_CORE_READ :
2640 DRV_MSG_CODE_PHY_RAW_READ,
2641 addr, &resp, ¶m, &len, (u32 *)p_buf);
2642 if (rc != ECORE_SUCCESS)
2643 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2645 p_dev->mcp_nvm_resp = resp;
2646 ecore_ptt_release(p_hwfn, p_ptt);
2651 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2653 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2654 struct ecore_ptt *p_ptt;
2656 p_ptt = ecore_ptt_acquire(p_hwfn);
2660 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2661 ecore_ptt_release(p_hwfn, p_ptt);
2663 return ECORE_SUCCESS;
2666 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2668 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2669 struct ecore_ptt *p_ptt;
2671 enum _ecore_status_t rc;
2673 p_ptt = ecore_ptt_acquire(p_hwfn);
2676 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2678 p_dev->mcp_nvm_resp = resp;
2679 ecore_ptt_release(p_hwfn, p_ptt);
2684 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2687 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2688 struct ecore_ptt *p_ptt;
2690 enum _ecore_status_t rc;
2692 p_ptt = ecore_ptt_acquire(p_hwfn);
2695 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2697 p_dev->mcp_nvm_resp = resp;
2698 ecore_ptt_release(p_hwfn, p_ptt);
2703 /* rc receives ECORE_INVAL as default parameter because
2704 * it might not enter the while loop if the len is 0
2706 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2707 u32 addr, u8 *p_buf, u32 len)
2709 u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2710 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2711 enum _ecore_status_t rc = ECORE_INVAL;
2712 struct ecore_ptt *p_ptt;
2714 p_ptt = ecore_ptt_acquire(p_hwfn);
2719 case ECORE_PUT_FILE_DATA:
2720 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2722 case ECORE_NVM_WRITE_NVRAM:
2723 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2725 case ECORE_EXT_PHY_FW_UPGRADE:
2726 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2729 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2736 while (buf_idx < len) {
2737 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2738 MCP_DRV_NVM_BUF_LEN);
2739 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2742 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2743 &resp, ¶m, buf_size,
2744 (u32 *)&p_buf[buf_idx]);
2745 if (rc != ECORE_SUCCESS) {
2746 DP_NOTICE(p_dev, false,
2747 "ecore_mcp_nvm_write() failed, rc = %d\n",
2749 resp = FW_MSG_CODE_ERROR;
2753 if (resp != FW_MSG_CODE_OK &&
2754 resp != FW_MSG_CODE_NVM_OK &&
2755 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2756 DP_NOTICE(p_dev, false,
2757 "nvm write failed, resp = 0x%08x\n", resp);
2758 rc = ECORE_UNKNOWN_ERROR;
2762 /* This can be a lengthy process, and it's possible scheduler
2763 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2765 if (buf_idx % 0x1000 >
2766 (buf_idx + buf_size) % 0x1000)
2769 buf_idx += buf_size;
2772 p_dev->mcp_nvm_resp = resp;
2774 ecore_ptt_release(p_hwfn, p_ptt);
2779 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2780 u32 addr, u8 *p_buf, u32 len)
2782 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2783 struct ecore_ptt *p_ptt;
2784 u32 resp, param, nvm_cmd;
2785 enum _ecore_status_t rc;
2787 p_ptt = ecore_ptt_acquire(p_hwfn);
2791 nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ? DRV_MSG_CODE_PHY_CORE_WRITE :
2792 DRV_MSG_CODE_PHY_RAW_WRITE;
2793 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2794 &resp, ¶m, len, (u32 *)p_buf);
2795 if (rc != ECORE_SUCCESS)
2796 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2797 p_dev->mcp_nvm_resp = resp;
2798 ecore_ptt_release(p_hwfn, p_ptt);
2803 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2806 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2807 struct ecore_ptt *p_ptt;
2809 enum _ecore_status_t rc;
2811 p_ptt = ecore_ptt_acquire(p_hwfn);
2815 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2817 p_dev->mcp_nvm_resp = resp;
2818 ecore_ptt_release(p_hwfn, p_ptt);
2823 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2824 struct ecore_ptt *p_ptt,
2825 u32 port, u32 addr, u32 offset,
2828 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2830 enum _ecore_status_t rc;
2832 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2833 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2837 while (bytes_left > 0) {
2838 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2839 MAX_I2C_TRANSACTION_SIZE);
2840 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2841 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2842 nvm_offset |= ((addr + offset) <<
2843 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2844 nvm_offset |= (bytes_to_copy <<
2845 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2846 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2847 DRV_MSG_CODE_TRANSCEIVER_READ,
2848 nvm_offset, &resp, ¶m, &buf_size,
2849 (u32 *)(p_buf + offset));
2850 if ((resp & FW_MSG_CODE_MASK) ==
2851 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2853 } else if ((resp & FW_MSG_CODE_MASK) !=
2854 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2855 return ECORE_UNKNOWN_ERROR;
2858 bytes_left -= buf_size;
2861 return ECORE_SUCCESS;
2864 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2865 struct ecore_ptt *p_ptt,
2866 u32 port, u32 addr, u32 offset,
2869 u32 buf_idx, buf_size, nvm_offset, resp, param;
2870 enum _ecore_status_t rc;
2872 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2873 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2875 while (buf_idx < len) {
2876 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2877 MAX_I2C_TRANSACTION_SIZE);
2878 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2879 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2880 nvm_offset |= ((offset + buf_idx) <<
2881 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2882 nvm_offset |= (buf_size <<
2883 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2884 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2885 DRV_MSG_CODE_TRANSCEIVER_WRITE,
2886 nvm_offset, &resp, ¶m, buf_size,
2887 (u32 *)&p_buf[buf_idx]);
2888 if ((resp & FW_MSG_CODE_MASK) ==
2889 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2891 } else if ((resp & FW_MSG_CODE_MASK) !=
2892 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2893 return ECORE_UNKNOWN_ERROR;
2895 buf_idx += buf_size;
2898 return ECORE_SUCCESS;
2901 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2902 struct ecore_ptt *p_ptt,
2903 u16 gpio, u32 *gpio_val)
2905 enum _ecore_status_t rc = ECORE_SUCCESS;
2906 u32 drv_mb_param = 0, rsp;
2908 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2910 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2911 drv_mb_param, &rsp, gpio_val);
2913 if (rc != ECORE_SUCCESS)
2916 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2917 return ECORE_UNKNOWN_ERROR;
2919 return ECORE_SUCCESS;
2922 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2923 struct ecore_ptt *p_ptt,
2924 u16 gpio, u16 gpio_val)
2926 enum _ecore_status_t rc = ECORE_SUCCESS;
2927 u32 drv_mb_param = 0, param, rsp;
2929 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
2930 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
2932 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2933 drv_mb_param, &rsp, ¶m);
2935 if (rc != ECORE_SUCCESS)
2938 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2939 return ECORE_UNKNOWN_ERROR;
2941 return ECORE_SUCCESS;
2944 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2945 struct ecore_ptt *p_ptt,
2946 u16 gpio, u32 *gpio_direction,
2949 u32 drv_mb_param = 0, rsp, val = 0;
2950 enum _ecore_status_t rc = ECORE_SUCCESS;
2952 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
2954 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2955 drv_mb_param, &rsp, &val);
2956 if (rc != ECORE_SUCCESS)
2959 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2960 DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
2961 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2962 DRV_MB_PARAM_GPIO_CTRL_OFFSET;
2964 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2965 return ECORE_UNKNOWN_ERROR;
2967 return ECORE_SUCCESS;
2970 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2971 struct ecore_ptt *p_ptt)
2973 u32 drv_mb_param = 0, rsp, param;
2974 enum _ecore_status_t rc = ECORE_SUCCESS;
2976 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2977 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2979 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2980 drv_mb_param, &rsp, ¶m);
2982 if (rc != ECORE_SUCCESS)
2985 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2986 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2987 rc = ECORE_UNKNOWN_ERROR;
2992 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2993 struct ecore_ptt *p_ptt)
2995 u32 drv_mb_param, rsp, param;
2996 enum _ecore_status_t rc = ECORE_SUCCESS;
2998 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2999 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3001 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3002 drv_mb_param, &rsp, ¶m);
3004 if (rc != ECORE_SUCCESS)
3007 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3008 (param != DRV_MB_PARAM_BIST_RC_PASSED))
3009 rc = ECORE_UNKNOWN_ERROR;
3014 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3015 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3017 u32 drv_mb_param = 0, rsp;
3018 enum _ecore_status_t rc = ECORE_SUCCESS;
3020 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3021 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3023 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3024 drv_mb_param, &rsp, num_images);
3026 if (rc != ECORE_SUCCESS)
3029 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3030 rc = ECORE_UNKNOWN_ERROR;
3035 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3036 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3037 struct bist_nvm_image_att *p_image_att, u32 image_index)
3039 u32 buf_size, nvm_offset, resp, param;
3040 enum _ecore_status_t rc;
3042 nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3043 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3044 nvm_offset |= (image_index <<
3045 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3046 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3047 nvm_offset, &resp, ¶m, &buf_size,
3048 (u32 *)p_image_att);
3049 if (rc != ECORE_SUCCESS)
3052 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3053 (p_image_att->return_code != 1))
3054 rc = ECORE_UNKNOWN_ERROR;
3059 enum _ecore_status_t
3060 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3061 struct ecore_ptt *p_ptt,
3062 struct ecore_temperature_info *p_temp_info)
3064 struct ecore_temperature_sensor *p_temp_sensor;
3065 struct temperature_status_stc mfw_temp_info;
3066 struct ecore_mcp_mb_params mb_params;
3068 enum _ecore_status_t rc;
3071 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3072 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3073 mb_params.p_data_dst = &mfw_temp_info;
3074 mb_params.data_dst_size = sizeof(mfw_temp_info);
3075 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3076 if (rc != ECORE_SUCCESS)
3079 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3080 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3081 ECORE_MAX_NUM_OF_SENSORS);
3082 for (i = 0; i < p_temp_info->num_sensors; i++) {
3083 val = mfw_temp_info.sensor[i];
3084 p_temp_sensor = &p_temp_info->sensors[i];
3085 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3086 SENSOR_LOCATION_OFFSET;
3087 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3088 THRESHOLD_HIGH_OFFSET;
3089 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3090 CRITICAL_TEMPERATURE_OFFSET;
3091 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3092 CURRENT_TEMP_OFFSET;
3095 return ECORE_SUCCESS;
3098 enum _ecore_status_t ecore_mcp_get_mba_versions(
3099 struct ecore_hwfn *p_hwfn,
3100 struct ecore_ptt *p_ptt,
3101 struct ecore_mba_vers *p_mba_vers)
3103 u32 buf_size, resp, param;
3104 enum _ecore_status_t rc;
3106 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3107 0, &resp, ¶m, &buf_size,
3108 &p_mba_vers->mba_vers[0]);
3110 if (rc != ECORE_SUCCESS)
3113 if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3114 rc = ECORE_UNKNOWN_ERROR;
3116 if (buf_size != MCP_DRV_NVM_BUF_LEN)
3117 rc = ECORE_UNKNOWN_ERROR;
3122 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3123 struct ecore_ptt *p_ptt,
3128 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3129 0, &rsp, (u32 *)num_events);
3132 static enum resource_id_enum
3133 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3135 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3139 mfw_res_id = RESOURCE_NUM_SB_E;
3141 case ECORE_L2_QUEUE:
3142 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3145 mfw_res_id = RESOURCE_NUM_VPORT_E;
3148 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3151 mfw_res_id = RESOURCE_NUM_PQ_E;
3154 mfw_res_id = RESOURCE_NUM_RL_E;
3158 /* Each VFC resource can accommodate both a MAC and a VLAN */
3159 mfw_res_id = RESOURCE_VFC_FILTER_E;
3162 mfw_res_id = RESOURCE_ILT_E;
3164 case ECORE_LL2_QUEUE:
3165 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3167 case ECORE_RDMA_CNQ_RAM:
3168 case ECORE_CMDQS_CQS:
3169 /* CNQ/CMDQS are the same resource */
3170 mfw_res_id = RESOURCE_CQS_E;
3172 case ECORE_RDMA_STATS_QUEUE:
3173 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3176 mfw_res_id = RESOURCE_BDQ_E;
3185 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
3186 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
3187 #define ECORE_RESC_ALLOC_VERSION \
3188 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
3189 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) | \
3190 (ECORE_RESC_ALLOC_VERSION_MINOR << \
3191 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3193 struct ecore_resc_alloc_in_params {
3195 enum ecore_resources res_id;
3199 struct ecore_resc_alloc_out_params {
3209 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
3211 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3213 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3214 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3215 enum _ecore_status_t rc;
3217 /* Allow ongoing PCIe transactions to complete */
3218 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3220 /* Clear the PF's internal FID_enable in the PXP */
3221 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3222 if (rc != ECORE_SUCCESS)
3223 DP_NOTICE(p_hwfn, false,
3224 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3230 static enum _ecore_status_t
3231 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3232 struct ecore_ptt *p_ptt,
3233 struct ecore_resc_alloc_in_params *p_in_params,
3234 struct ecore_resc_alloc_out_params *p_out_params)
3236 struct ecore_mcp_mb_params mb_params;
3237 struct resource_info mfw_resc_info;
3238 enum _ecore_status_t rc;
3240 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3242 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3243 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3245 "Failed to match resource %d [%s] with the MFW resources\n",
3246 p_in_params->res_id,
3247 ecore_hw_get_resc_name(p_in_params->res_id));
3251 switch (p_in_params->cmd) {
3252 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3253 mfw_resc_info.size = p_in_params->resc_max_val;
3255 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3258 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3263 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3264 mb_params.cmd = p_in_params->cmd;
3265 mb_params.param = ECORE_RESC_ALLOC_VERSION;
3266 mb_params.p_data_src = &mfw_resc_info;
3267 mb_params.data_src_size = sizeof(mfw_resc_info);
3268 mb_params.p_data_dst = mb_params.p_data_src;
3269 mb_params.data_dst_size = mb_params.data_src_size;
3271 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3272 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3273 p_in_params->cmd, p_in_params->res_id,
3274 ecore_hw_get_resc_name(p_in_params->res_id),
3275 GET_MFW_FIELD(mb_params.param,
3276 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3277 GET_MFW_FIELD(mb_params.param,
3278 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3279 p_in_params->resc_max_val);
3281 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3282 if (rc != ECORE_SUCCESS)
3285 p_out_params->mcp_resp = mb_params.mcp_resp;
3286 p_out_params->mcp_param = mb_params.mcp_param;
3287 p_out_params->resc_num = mfw_resc_info.size;
3288 p_out_params->resc_start = mfw_resc_info.offset;
3289 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3290 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3291 p_out_params->flags = mfw_resc_info.flags;
3293 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3294 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3295 GET_MFW_FIELD(p_out_params->mcp_param,
3296 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3297 GET_MFW_FIELD(p_out_params->mcp_param,
3298 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3299 p_out_params->resc_num, p_out_params->resc_start,
3300 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3301 p_out_params->flags);
3303 return ECORE_SUCCESS;
3306 enum _ecore_status_t
3307 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3308 enum ecore_resources res_id, u32 resc_max_val,
3311 struct ecore_resc_alloc_out_params out_params;
3312 struct ecore_resc_alloc_in_params in_params;
3313 enum _ecore_status_t rc;
3315 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3316 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3317 in_params.res_id = res_id;
3318 in_params.resc_max_val = resc_max_val;
3319 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3320 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3322 if (rc != ECORE_SUCCESS)
3325 *p_mcp_resp = out_params.mcp_resp;
3327 return ECORE_SUCCESS;
3330 enum _ecore_status_t
3331 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3332 enum ecore_resources res_id, u32 *p_mcp_resp,
3333 u32 *p_resc_num, u32 *p_resc_start)
3335 struct ecore_resc_alloc_out_params out_params;
3336 struct ecore_resc_alloc_in_params in_params;
3337 enum _ecore_status_t rc;
3339 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3340 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3341 in_params.res_id = res_id;
3342 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3343 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3345 if (rc != ECORE_SUCCESS)
3348 *p_mcp_resp = out_params.mcp_resp;
3350 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3351 *p_resc_num = out_params.resc_num;
3352 *p_resc_start = out_params.resc_start;
3355 return ECORE_SUCCESS;
3358 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3359 struct ecore_ptt *p_ptt)
3361 u32 mcp_resp, mcp_param;
3363 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3364 &mcp_resp, &mcp_param);
3367 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3368 struct ecore_ptt *p_ptt,
3369 u32 param, u32 *p_mcp_resp,
3372 enum _ecore_status_t rc;
3374 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3375 p_mcp_resp, p_mcp_param);
3376 if (rc != ECORE_SUCCESS)
3379 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3381 "The resource command is unsupported by the MFW\n");
3382 return ECORE_NOTIMPL;
3385 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3386 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3388 DP_NOTICE(p_hwfn, false,
3389 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3397 enum _ecore_status_t
3398 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3399 struct ecore_resc_lock_params *p_params)
3401 u32 param = 0, mcp_resp, mcp_param;
3403 enum _ecore_status_t rc;
3405 switch (p_params->timeout) {
3406 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3407 opcode = RESOURCE_OPCODE_REQ;
3408 p_params->timeout = 0;
3410 case ECORE_MCP_RESC_LOCK_TO_NONE:
3411 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3412 p_params->timeout = 0;
3415 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3419 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3420 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3421 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3423 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3424 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3425 param, p_params->timeout, opcode, p_params->resource);
3427 /* Attempt to acquire the resource */
3428 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3430 if (rc != ECORE_SUCCESS)
3433 /* Analyze the response */
3434 p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3435 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3437 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3438 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3439 mcp_param, opcode, p_params->owner);
3442 case RESOURCE_OPCODE_GNT:
3443 p_params->b_granted = true;
3445 case RESOURCE_OPCODE_BUSY:
3446 p_params->b_granted = false;
3449 DP_NOTICE(p_hwfn, false,
3450 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3455 return ECORE_SUCCESS;
3458 enum _ecore_status_t
3459 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3460 struct ecore_resc_lock_params *p_params)
3463 enum _ecore_status_t rc;
3466 /* No need for an interval before the first iteration */
3468 if (p_params->sleep_b4_retry) {
3469 u16 retry_interval_in_ms =
3470 DIV_ROUND_UP(p_params->retry_interval,
3473 OSAL_MSLEEP(retry_interval_in_ms);
3475 OSAL_UDELAY(p_params->retry_interval);
3479 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3480 if (rc != ECORE_SUCCESS)
3483 if (p_params->b_granted)
3485 } while (retry_cnt++ < p_params->retry_num);
3487 return ECORE_SUCCESS;
3490 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3491 struct ecore_resc_unlock_params *p_unlock,
3492 enum ecore_resc_lock resource,
3493 bool b_is_permanent)
3495 if (p_lock != OSAL_NULL) {
3496 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3498 /* Permanent resources don't require aging, and there's no
3499 * point in trying to acquire them more than once since it's
3500 * unexpected another entity would release them.
3502 if (b_is_permanent) {
3503 p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3505 p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3506 p_lock->retry_interval =
3507 ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3508 p_lock->sleep_b4_retry = true;
3511 p_lock->resource = resource;
3514 if (p_unlock != OSAL_NULL) {
3515 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3516 p_unlock->resource = resource;
3520 enum _ecore_status_t
3521 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3522 struct ecore_resc_unlock_params *p_params)
3524 u32 param = 0, mcp_resp, mcp_param;
3526 enum _ecore_status_t rc;
3528 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3529 : RESOURCE_OPCODE_RELEASE;
3530 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3531 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3533 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3534 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3535 param, opcode, p_params->resource);
3537 /* Attempt to release the resource */
3538 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3540 if (rc != ECORE_SUCCESS)
3543 /* Analyze the response */
3544 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3546 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3547 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3551 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3553 "Resource unlock request for an already released resource [%d]\n",
3554 p_params->resource);
3556 case RESOURCE_OPCODE_RELEASED:
3557 p_params->b_released = true;
3559 case RESOURCE_OPCODE_WRONG_OWNER:
3560 p_params->b_released = false;
3563 DP_NOTICE(p_hwfn, false,
3564 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3569 return ECORE_SUCCESS;
3572 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3574 return !!(p_hwfn->mcp_info->capabilities &
3575 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3578 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3579 struct ecore_ptt *p_ptt)
3582 enum _ecore_status_t rc;
3584 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3585 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3586 if (rc == ECORE_SUCCESS)
3587 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3588 "MFW supported features: %08x\n",
3589 p_hwfn->mcp_info->capabilities);
3594 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3595 struct ecore_ptt *p_ptt)
3597 u32 mcp_resp, mcp_param, features;
3599 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3600 DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3602 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3603 features, &mcp_resp, &mcp_param);