drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 100 {
 101         if (p_hwfn->mcp_info) {
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 103                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 104                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 105         }
 106         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 107         p_hwfn->mcp_info = OSAL_NULL;
 108
 109         return ECORE_SUCCESS;
 110 }
 111
 112 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 113                                                    struct ecore_ptt *p_ptt)
 114 {
 115         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 116         u32 drv_mb_offsize, mfw_mb_offsize;
 117         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 118
 119 #ifndef ASIC_ONLY
 120         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 121                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 122                 p_info->public_base = 0;
 123                 return ECORE_INVAL;
 124         }
 125 #endif
 126
 127         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 128         if (!p_info->public_base)
 129                 return ECORE_INVAL;
 130
 131         p_info->public_base |= GRCBASE_MCP;
 132
 133         /* Calculate the driver and MFW mailbox address */
 134         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 135                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 136                                                        PUBLIC_DRV_MB));
 137         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 138         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 139                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 140                    " mcp_pf_id = 0x%x\n",
 141                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 142
 143         /* Set the MFW MB address */
 144         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 145                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 146                                                        PUBLIC_MFW_MB));
 147         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 148         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 149                                                p_info->mfw_mb_addr);
 150
 151         /* Get the current driver mailbox sequence before sending
 152          * the first command
 153          */
 154         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 155             DRV_MSG_SEQ_NUMBER_MASK;
 156
 157         /* Get current FW pulse sequence */
 158         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 159             DRV_PULSE_SEQ_MASK;
 160
 161         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 162                                           MISCS_REG_GENERIC_POR_0);
 163
 164         return ECORE_SUCCESS;
 165 }
 166
 167 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 168                                         struct ecore_ptt *p_ptt)
 169 {
 170         struct ecore_mcp_info *p_info;
 171         u32 size;
 172
 173         /* Allocate mcp_info structure */
 174         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 175                                        sizeof(*p_hwfn->mcp_info));
 176         if (!p_hwfn->mcp_info)
 177                 goto err;
 178         p_info = p_hwfn->mcp_info;
 179
 180         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 181                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 182                 /* Do not free mcp_info here, since public_base indicate that
 183                  * the MCP is not initialized
 184                  */
 185                 return ECORE_SUCCESS;
 186         }
 187
 188         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 189         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 191         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 192                 goto err;
 193
 194         /* Initialize the MFW spinlock */
 195         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 196         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 197
 198         return ECORE_SUCCESS;
 199
 200 err:
 201         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 202         ecore_mcp_free(p_hwfn);
 203         return ECORE_NOMEM;
 204 }
 205
 206 /* Locks the MFW mailbox of a PF to ensure a single access.
 207  * The lock is achieved in most cases by holding a spinlock, causing other
 208  * threads to wait till a previous access is done.
 209  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 210  * access is achieved by setting a blocking flag, which will fail other
 211  * competing contexts to send their mailboxes.
 212  */
 213 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 214                                               u32 cmd)
 215 {
 216         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 217
 218         /* The spinlock shouldn't be acquired when the mailbox command is
 219          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 220          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 221          * (i.e. interrupts are disabled) - can lead to a deadlock.
 222          * It is assumed that for a single PF, no other mailbox commands can be
 223          * sent from another context while sending LOAD_REQ, and that any
 224          * parallel commands to UNLOAD_REQ can be cancelled.
 225          */
 226         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 227                 p_hwfn->mcp_info->block_mb_sending = false;
 228
 229         if (p_hwfn->mcp_info->block_mb_sending) {
 230                 DP_NOTICE(p_hwfn, false,
 231                           "Trying to send a MFW mailbox command [0x%x]"
 232                           " in parallel to [UN]LOAD_REQ. Aborting.\n",
 233                           cmd);
 234                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 235                 return ECORE_BUSY;
 236         }
 237
 238         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 239                 p_hwfn->mcp_info->block_mb_sending = true;
 240                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 241         }
 242
 243         return ECORE_SUCCESS;
 244 }
 245
 246 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 247 {
 248         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 249                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 250 }
 251
 252 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 253                                      struct ecore_ptt *p_ptt)
 254 {
 255         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 256         u32 delay = CHIP_MCP_RESP_ITER_US;
 257         u32 org_mcp_reset_seq, cnt = 0;
 258         enum _ecore_status_t rc = ECORE_SUCCESS;
 259
 260 #ifndef ASIC_ONLY
 261         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 262                 delay = EMUL_MCP_RESP_ITER_US;
 263 #endif
 264
 265         /* Ensure that only a single thread is accessing the mailbox at a
 266          * certain time.
 267          */
 268         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 269         if (rc != ECORE_SUCCESS)
 270                 return rc;
 271
 272         /* Set drv command along with the updated sequence */
 273         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 274         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 275
 276         do {
 277                 /* Wait for MFW response */
 278                 OSAL_UDELAY(delay);
 279                 /* Give the FW up to 500 second (50*1000*10usec) */
 280         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 281                                                 MISCS_REG_GENERIC_POR_0)) &&
 282                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 283
 284         if (org_mcp_reset_seq !=
 285             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 286                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 287                            "MCP was reset after %d usec\n", cnt * delay);
 288         } else {
 289                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 290                 rc = ECORE_AGAIN;
 291         }
 292
 293         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 294
 295         return rc;
 296 }
 297
 298 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 299                                              struct ecore_ptt *p_ptt,
 300                                              u32 cmd, u32 param,
 301                                              u32 *o_mcp_resp,
 302                                              u32 *o_mcp_param)
 303 {
 304         u32 delay = CHIP_MCP_RESP_ITER_US;
 305         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 306         u32 seq, cnt = 1, actual_mb_seq;
 307         enum _ecore_status_t rc = ECORE_SUCCESS;
 308
 309 #ifndef ASIC_ONLY
 310         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 311                 delay = EMUL_MCP_RESP_ITER_US;
 312         /* There is a built-in delay of 100usec in each MFW response read */
 313         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 314                 max_retries /= 10;
 315 #endif
 316
 317         /* Get actual driver mailbox sequence */
 318         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 319             DRV_MSG_SEQ_NUMBER_MASK;
 320
 321         /* Use MCP history register to check if MCP reset occurred between
 322          * init time and now.
 323          */
 324         if (p_hwfn->mcp_info->mcp_hist !=
 325             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 326                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 327                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 328                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 329         }
 330         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 331
 332         /* Set drv param */
 333         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 334
 335         /* Set drv command along with the updated sequence */
 336         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 337
 338         do {
 339                 /* Wait for MFW response */
 340                 OSAL_UDELAY(delay);
 341                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 342
 343                 /* Give the FW up to 5 second (500*10ms) */
 344         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 345                  (cnt++ < max_retries));
 346
 347         /* Is this a reply to our command? */
 348         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 349                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 350                 /* Get the MCP param */
 351                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 352         } else {
 353                 /* FW BUG! */
 354                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 355                        cmd, param);
 356                 *o_mcp_resp = 0;
 357                 rc = ECORE_AGAIN;
 358                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 359         }
 360         return rc;
 361 }
 362
 363 static enum _ecore_status_t
 364 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 365                         struct ecore_ptt *p_ptt,
 366                         struct ecore_mcp_mb_params *p_mb_params)
 367 {
 368         u32 union_data_addr;
 369         enum _ecore_status_t rc;
 370
 371         /* MCP not initialized */
 372         if (!ecore_mcp_is_init(p_hwfn)) {
 373                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 374                 return ECORE_BUSY;
 375         }
 376
 377         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 378                           OFFSETOF(struct public_drv_mb, union_data);
 379
 380         /* Ensure that only a single thread is accessing the mailbox at a
 381          * certain time.
 382          */
 383         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 384         if (rc != ECORE_SUCCESS)
 385                 return rc;
 386
 387         if (p_mb_params->p_data_src != OSAL_NULL)
 388                 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 389                                 p_mb_params->p_data_src,
 390                                 sizeof(*p_mb_params->p_data_src));
 391
 392         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 393                               p_mb_params->param, &p_mb_params->mcp_resp,
 394                               &p_mb_params->mcp_param);
 395
 396         if (p_mb_params->p_data_dst != OSAL_NULL)
 397                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 398                                   union_data_addr,
 399                                   sizeof(*p_mb_params->p_data_dst));
 400
 401         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 402
 403         return rc;
 404 }
 405
 406 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 407                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 408                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 409 {
 410         struct ecore_mcp_mb_params mb_params;
 411         enum _ecore_status_t rc;
 412
 413 #ifndef ASIC_ONLY
 414         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 415                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 416                         loaded--;
 417                         loaded_port[p_hwfn->port_id]--;
 418                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 419                                    loaded);
 420                 }
 421                 return ECORE_SUCCESS;
 422         }
 423 #endif
 424
 425         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 426         mb_params.cmd = cmd;
 427         mb_params.param = param;
 428         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 429         if (rc != ECORE_SUCCESS)
 430                 return rc;
 431
 432         *o_mcp_resp = mb_params.mcp_resp;
 433         *o_mcp_param = mb_params.mcp_param;
 434
 435         return ECORE_SUCCESS;
 436 }
 437
 438 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 439                                           struct ecore_ptt *p_ptt,
 440                                           u32 cmd,
 441                                           u32 param,
 442                                           u32 *o_mcp_resp,
 443                                           u32 *o_mcp_param,
 444                                           u32 i_txn_size, u32 *i_buf)
 445 {
 446         struct ecore_mcp_mb_params mb_params;
 447         union drv_union_data union_data;
 448         enum _ecore_status_t rc;
 449
 450         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 451         mb_params.cmd = cmd;
 452         mb_params.param = param;
 453         OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
 454         mb_params.p_data_src = &union_data;
 455         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 456         if (rc != ECORE_SUCCESS)
 457                 return rc;
 458
 459         *o_mcp_resp = mb_params.mcp_resp;
 460         *o_mcp_param = mb_params.mcp_param;
 461
 462         return ECORE_SUCCESS;
 463 }
 464
 465 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 466                                           struct ecore_ptt *p_ptt,
 467                                           u32 cmd,
 468                                           u32 param,
 469                                           u32 *o_mcp_resp,
 470                                           u32 *o_mcp_param,
 471                                           u32 *o_txn_size, u32 *o_buf)
 472 {
 473         struct ecore_mcp_mb_params mb_params;
 474         union drv_union_data union_data;
 475         enum _ecore_status_t rc;
 476
 477         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 478         mb_params.cmd = cmd;
 479         mb_params.param = param;
 480         mb_params.p_data_dst = &union_data;
 481         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 482         if (rc != ECORE_SUCCESS)
 483                 return rc;
 484
 485         *o_mcp_resp = mb_params.mcp_resp;
 486         *o_mcp_param = mb_params.mcp_param;
 487
 488         *o_txn_size = *o_mcp_param;
 489         OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
 490
 491         return ECORE_SUCCESS;
 492 }
 493
 494 #ifndef ASIC_ONLY
 495 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 496                                     u32 *p_load_code)
 497 {
 498         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 499
 500         if (!loaded)
 501                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 502         else if (!loaded_port[p_hwfn->port_id])
 503                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 504         else
 505                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 506
 507         /* On CMT, always tell that it's engine */
 508         if (p_hwfn->p_dev->num_hwfns > 1)
 509                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 510
 511         *p_load_code = load_phase;
 512         loaded++;
 513         loaded_port[p_hwfn->port_id]++;
 514
 515         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 516                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 517                    *p_load_code, loaded, p_hwfn->port_id,
 518                    loaded_port[p_hwfn->port_id]);
 519 }
 520 #endif
 521
 522 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 523                                         struct ecore_ptt *p_ptt,
 524                                         u32 *p_load_code)
 525 {
 526         struct ecore_dev *p_dev = p_hwfn->p_dev;
 527         struct ecore_mcp_mb_params mb_params;
 528         union drv_union_data union_data;
 529         enum _ecore_status_t rc;
 530
 531 #ifndef ASIC_ONLY
 532         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 533                 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
 534                 return ECORE_SUCCESS;
 535         }
 536 #endif
 537
 538         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 539         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 540         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 541                           p_dev->drv_type;
 542         OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
 543         mb_params.p_data_src = &union_data;
 544         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 545
 546         /* if mcp fails to respond we must abort */
 547         if (rc != ECORE_SUCCESS) {
 548                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 549                 return rc;
 550         }
 551
 552         *p_load_code = mb_params.mcp_resp;
 553
 554         /* If MFW refused (e.g. other port is in diagnostic mode) we
 555          * must abort. This can happen in the following cases:
 556          * - Other port is in diagnostic mode
 557          * - Previously loaded function on the engine is not compliant with
 558          *   the requester.
 559          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 560          *      -
 561          */
 562         if (!(*p_load_code) ||
 563             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 564             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 565             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 566                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 567                 return ECORE_BUSY;
 568         }
 569
 570         return ECORE_SUCCESS;
 571 }
 572
 573 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 574                                     struct ecore_ptt *p_ptt)
 575 {
 576         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 577                                         PUBLIC_PATH);
 578         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 579         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 580                                      ECORE_PATH_ID(p_hwfn));
 581         u32 disabled_vfs[VF_MAX_STATIC / 32];
 582         int i;
 583
 584         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 585                    "Reading Disabled VF information from [offset %08x],"
 586                    " path_addr %08x\n",
 587                    mfw_path_offsize, path_addr);
 588
 589         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 590                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 591                                            path_addr +
 592                                            OFFSETOF(struct public_path,
 593                                                     mcp_vf_disabled) +
 594                                            sizeof(u32) * i);
 595                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 596                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 597                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 598         }
 599
 600         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 601                 OSAL_VF_FLR_UPDATE(p_hwfn);
 602 }
 603
 604 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 605                                           struct ecore_ptt *p_ptt,
 606                                           u32 *vfs_to_ack)
 607 {
 608         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 609                                         PUBLIC_FUNC);
 610         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 611         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 612                                      MCP_PF_ID(p_hwfn));
 613         struct ecore_mcp_mb_params mb_params;
 614         union drv_union_data union_data;
 615         enum _ecore_status_t rc;
 616         int i;
 617
 618         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 619                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 620                            "Acking VFs [%08x,...,%08x] - %08x\n",
 621                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 622
 623         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 624         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 625         OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 626         mb_params.p_data_src = &union_data;
 627         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
 628                                      &mb_params);
 629         if (rc != ECORE_SUCCESS) {
 630                 DP_NOTICE(p_hwfn, false,
 631                           "Failed to pass ACK for VF flr to MFW\n");
 632                 return ECORE_TIMEOUT;
 633         }
 634
 635         /* TMP - clear the ACK bits; should be done by MFW */
 636         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 637                 ecore_wr(p_hwfn, p_ptt,
 638                          func_addr +
 639                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
 640                          i * sizeof(u32), 0);
 641
 642         return rc;
 643 }
 644
 645 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
 646                                                 struct ecore_ptt *p_ptt)
 647 {
 648         u32 transceiver_state;
 649
 650         transceiver_state = ecore_rd(p_hwfn, p_ptt,
 651                                      p_hwfn->mcp_info->port_addr +
 652                                      OFFSETOF(struct public_port,
 653                                               transceiver_data));
 654
 655         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
 656                    "Received transceiver state update [0x%08x] from mfw"
 657                    " [Addr 0x%x]\n",
 658                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
 659                                             OFFSETOF(struct public_port,
 660                                                      transceiver_data)));
 661
 662         transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
 663
 664         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
 665                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
 666         else
 667                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
 668 }
 669
 670 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
 671                                          struct ecore_ptt *p_ptt,
 672                                          bool b_reset)
 673 {
 674         struct ecore_mcp_link_state *p_link;
 675         u8 max_bw, min_bw;
 676         u32 status = 0;
 677
 678         p_link = &p_hwfn->mcp_info->link_output;
 679         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
 680         if (!b_reset) {
 681                 status = ecore_rd(p_hwfn, p_ptt,
 682                                   p_hwfn->mcp_info->port_addr +
 683                                   OFFSETOF(struct public_port, link_status));
 684                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
 685                            "Received link update [0x%08x] from mfw"
 686                            " [Addr 0x%x]\n",
 687                            status, (u32)(p_hwfn->mcp_info->port_addr +
 688                                           OFFSETOF(struct public_port,
 689                                                    link_status)));
 690         } else {
 691                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 692                            "Resetting link indications\n");
 693                 return;
 694         }
 695
 696         if (p_hwfn->b_drv_link_init)
 697                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 698         else
 699                 p_link->link_up = false;
 700
 701         p_link->full_duplex = true;
 702         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 703         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 704                 p_link->speed = 100000;
 705                 break;
 706         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 707                 p_link->speed = 50000;
 708                 break;
 709         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 710                 p_link->speed = 40000;
 711                 break;
 712         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 713                 p_link->speed = 25000;
 714                 break;
 715         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 716                 p_link->speed = 20000;
 717                 break;
 718         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 719                 p_link->speed = 10000;
 720                 break;
 721         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 722                 p_link->full_duplex = false;
 723                 /* Fall-through */
 724         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 725                 p_link->speed = 1000;
 726                 break;
 727         default:
 728                 p_link->speed = 0;
 729         }
 730
 731         /* We never store total line speed as p_link->speed is
 732          * again changes according to bandwidth allocation.
 733          */
 734         if (p_link->link_up && p_link->speed)
 735                 p_link->line_speed = p_link->speed;
 736         else
 737                 p_link->line_speed = 0;
 738
 739         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 740         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 741
 742         /* Max bandwidth configuration */
 743         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
 744                                            p_link, max_bw);
 745
 746         /* Mintz bandwidth configuration */
 747         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
 748                                            p_link, min_bw);
 749         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
 750                                               p_link->min_pf_rate);
 751
 752         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 753         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 754         p_link->parallel_detection = !!(status &
 755                                          LINK_STATUS_PARALLEL_DETECTION_USED);
 756         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 757
 758         p_link->partner_adv_speed |=
 759             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 760             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
 761         p_link->partner_adv_speed |=
 762             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 763             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
 764         p_link->partner_adv_speed |=
 765             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 766             ECORE_LINK_PARTNER_SPEED_10G : 0;
 767         p_link->partner_adv_speed |=
 768             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 769             ECORE_LINK_PARTNER_SPEED_20G : 0;
 770         p_link->partner_adv_speed |=
 771             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 772             ECORE_LINK_PARTNER_SPEED_25G : 0;
 773         p_link->partner_adv_speed |=
 774             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 775             ECORE_LINK_PARTNER_SPEED_40G : 0;
 776         p_link->partner_adv_speed |=
 777             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 778             ECORE_LINK_PARTNER_SPEED_50G : 0;
 779         p_link->partner_adv_speed |=
 780             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 781             ECORE_LINK_PARTNER_SPEED_100G : 0;
 782
 783         p_link->partner_tx_flow_ctrl_en =
 784             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 785         p_link->partner_rx_flow_ctrl_en =
 786             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 787
 788         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 789         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 790                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
 791                 break;
 792         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 793                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
 794                 break;
 795         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 796                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
 797                 break;
 798         default:
 799                 p_link->partner_adv_pause = 0;
 800         }
 801
 802         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 803
 804         if (p_link->link_up)
 805                 ecore_dcbx_eagle_workaround(p_hwfn, p_ptt, p_link->pfc_enabled);
 806
 807         OSAL_LINK_UPDATE(p_hwfn);
 808 }
 809
 810 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 811                                         struct ecore_ptt *p_ptt, bool b_up)
 812 {
 813         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 814         struct ecore_mcp_mb_params mb_params;
 815         union drv_union_data union_data;
 816         struct eth_phy_cfg *p_phy_cfg;
 817         enum _ecore_status_t rc = ECORE_SUCCESS;
 818         u32 cmd;
 819
 820 #ifndef ASIC_ONLY
 821         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 822                 return ECORE_SUCCESS;
 823 #endif
 824
 825         /* Set the shmem configuration according to params */
 826         p_phy_cfg = &union_data.drv_phy_cfg;
 827         OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
 828         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 829         if (!params->speed.autoneg)
 830                 p_phy_cfg->speed = params->speed.forced_speed;
 831         p_phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
 832         p_phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
 833         p_phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
 834         p_phy_cfg->adv_speed = params->speed.advertised_speeds;
 835         p_phy_cfg->loopback_mode = params->loopback_mode;
 836         p_hwfn->b_drv_link_init = b_up;
 837
 838         if (b_up)
 839                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 840                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
 841                            " adv_speed 0x%08x, loopback 0x%08x\n",
 842                            p_phy_cfg->speed, p_phy_cfg->pause,
 843                            p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode);
 844         else
 845                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
 846
 847         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 848         mb_params.cmd = cmd;
 849         mb_params.p_data_src = &union_data;
 850         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 851
 852         /* if mcp fails to respond we must abort */
 853         if (rc != ECORE_SUCCESS) {
 854                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 855                 return rc;
 856         }
 857
 858         /* Reset the link status if needed */
 859         if (!b_up)
 860                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
 861
 862         return rc;
 863 }
 864
 865 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
 866                                    struct ecore_ptt *p_ptt)
 867 {
 868         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
 869
 870         /* TODO - Add support for VFs */
 871         if (IS_VF(p_hwfn->p_dev))
 872                 return ECORE_INVAL;
 873
 874         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 875                                                  PUBLIC_PATH);
 876         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
 877         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
 878
 879         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
 880                                  path_addr +
 881                                  OFFSETOF(struct public_path, process_kill)) &
 882             PROCESS_KILL_COUNTER_MASK;
 883
 884         return proc_kill_cnt;
 885 }
 886
 887 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
 888                                           struct ecore_ptt *p_ptt)
 889 {
 890         struct ecore_dev *p_dev = p_hwfn->p_dev;
 891         u32 proc_kill_cnt;
 892
 893         /* Prevent possible attentions/interrupts during the recovery handling
 894          * and till its load phase, during which they will be re-enabled.
 895          */
 896         ecore_int_igu_disable_int(p_hwfn, p_ptt);
 897
 898         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
 899
 900         /* The following operations should be done once, and thus in CMT mode
 901          * are carried out by only the first HW function.
 902          */
 903         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
 904                 return;
 905
 906         if (p_dev->recov_in_prog) {
 907                 DP_NOTICE(p_hwfn, false,
 908                           "Ignoring the indication since a recovery"
 909                           " process is already in progress\n");
 910                 return;
 911         }
 912
 913         p_dev->recov_in_prog = true;
 914
 915         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
 916         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
 917
 918         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
 919 }
 920
 921 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
 922                                           struct ecore_ptt *p_ptt,
 923                                           enum MFW_DRV_MSG_TYPE type)
 924 {
 925         enum ecore_mcp_protocol_type stats_type;
 926         union ecore_mcp_protocol_stats stats;
 927         struct ecore_mcp_mb_params mb_params;
 928         union drv_union_data union_data;
 929         u32 hsi_param;
 930
 931         switch (type) {
 932         case MFW_DRV_MSG_GET_LAN_STATS:
 933                 stats_type = ECORE_MCP_LAN_STATS;
 934                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 935                 break;
 936         default:
 937                 DP_NOTICE(p_hwfn, false, "Invalid protocol type %d\n", type);
 938                 return;
 939         }
 940
 941         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
 942
 943         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 944         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 945         mb_params.param = hsi_param;
 946         OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
 947         mb_params.p_data_src = &union_data;
 948         ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 949 }
 950
 951 static void
 952 ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 953                         struct public_func *p_shmem_info)
 954 {
 955         struct ecore_mcp_function_info *p_info;
 956
 957         p_info = &p_hwfn->mcp_info->func_info;
 958
 959         /* TODO - bandwidth min/max should have valid values of 1-100,
 960          * as well as some indication that the feature is disabled.
 961          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
 962          * limit and correct value to min `1' and max `100' if limit isn't in
 963          * range.
 964          */
 965         p_info->bandwidth_min = (p_shmem_info->config &
 966                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 967             FUNC_MF_CFG_MIN_BW_SHIFT;
 968         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 969                 DP_INFO(p_hwfn,
 970                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 971                         p_info->bandwidth_min);
 972                 p_info->bandwidth_min = 1;
 973         }
 974
 975         p_info->bandwidth_max = (p_shmem_info->config &
 976                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 977             FUNC_MF_CFG_MAX_BW_SHIFT;
 978         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 979                 DP_INFO(p_hwfn,
 980                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 981                         p_info->bandwidth_max);
 982                 p_info->bandwidth_max = 100;
 983         }
 984 }
 985
 986 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
 987                                     struct ecore_ptt *p_ptt,
 988                                     struct public_func *p_data,
 989                                     int pfid)
 990 {
 991         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 992                                         PUBLIC_FUNC);
 993         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 994         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 995         u32 i, size;
 996
 997         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
 998
 999         size = OSAL_MIN_T(u32, sizeof(*p_data),
1000                           SECTION_SIZE(mfw_path_offsize));
1001         for (i = 0; i < size / sizeof(u32); i++)
1002                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1003                                               func_addr + (i << 2));
1004
1005         return size;
1006 }
1007
1008 static void
1009 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1010 {
1011         struct ecore_mcp_function_info *p_info;
1012         struct public_func shmem_info;
1013         u32 resp = 0, param = 0;
1014
1015         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1016
1017         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1018
1019         p_info = &p_hwfn->mcp_info->func_info;
1020
1021         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1022
1023         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1024
1025         /* Acknowledge the MFW */
1026         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1027                       &param);
1028 }
1029
1030 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1031                                          struct ecore_ptt *p_ptt)
1032 {
1033         /* A single notification should be sent to upper driver in CMT mode */
1034         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1035                 return;
1036
1037         DP_NOTICE(p_hwfn, false,
1038                   "Fan failure was detected on the network interface card"
1039                   " and it's going to be shut down.\n");
1040
1041         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1042 }
1043
1044 static enum _ecore_status_t
1045 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1046                     u32 mdump_cmd, union drv_union_data *p_data_src,
1047                     union drv_union_data *p_data_dst, u32 *p_mcp_resp)
1048 {
1049         struct ecore_mcp_mb_params mb_params;
1050         enum _ecore_status_t rc;
1051
1052         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1053         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1054         mb_params.param = mdump_cmd;
1055         mb_params.p_data_src = p_data_src;
1056         mb_params.p_data_dst = p_data_dst;
1057         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1058         if (rc != ECORE_SUCCESS)
1059                 return rc;
1060
1061         *p_mcp_resp = mb_params.mcp_resp;
1062         if (*p_mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1063                 DP_NOTICE(p_hwfn, false,
1064                           "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1065                           mdump_cmd);
1066                 rc = ECORE_INVAL;
1067         }
1068
1069         return rc;
1070 }
1071
1072 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1073                                                 struct ecore_ptt *p_ptt)
1074 {
1075         u32 mcp_resp;
1076
1077         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_ACK,
1078                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1079 }
1080
1081 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1082                                                 struct ecore_ptt *p_ptt,
1083                                                 u32 epoch)
1084 {
1085         union drv_union_data union_data;
1086         u32 mcp_resp;
1087
1088         OSAL_MEMCPY(&union_data.raw_data, &epoch, sizeof(epoch));
1089
1090         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_SET_VALUES,
1091                                    &union_data, OSAL_NULL, &mcp_resp);
1092 }
1093
1094 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1095                                              struct ecore_ptt *p_ptt)
1096 {
1097         u32 mcp_resp;
1098
1099         p_hwfn->p_dev->mdump_en = true;
1100
1101         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_TRIGGER,
1102                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1103 }
1104
1105 static enum _ecore_status_t
1106 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1107                            struct mdump_config_stc *p_mdump_config)
1108 {
1109         union drv_union_data union_data;
1110         u32 mcp_resp;
1111         enum _ecore_status_t rc;
1112
1113         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_GET_CONFIG,
1114                                  OSAL_NULL, &union_data, &mcp_resp);
1115         if (rc != ECORE_SUCCESS)
1116                 return rc;
1117
1118         /* A zero response implies that the mdump command is not supported */
1119         if (!mcp_resp)
1120                 return ECORE_NOTIMPL;
1121
1122         if (mcp_resp != FW_MSG_CODE_OK) {
1123                 DP_NOTICE(p_hwfn, false,
1124                           "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1125                           mcp_resp);
1126                 rc = ECORE_UNKNOWN_ERROR;
1127         }
1128
1129         OSAL_MEMCPY(p_mdump_config, &union_data.mdump_config,
1130                     sizeof(*p_mdump_config));
1131
1132         return rc;
1133 }
1134
1135 enum _ecore_status_t
1136 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1137                          struct ecore_mdump_info *p_mdump_info)
1138 {
1139         u32 addr, global_offsize, global_addr;
1140         struct mdump_config_stc mdump_config;
1141         enum _ecore_status_t rc;
1142
1143         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1144
1145         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1146                                     PUBLIC_GLOBAL);
1147         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1148         global_addr = SECTION_ADDR(global_offsize, 0);
1149         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1150                                         global_addr +
1151                                         OFFSETOF(struct public_global,
1152                                                  mdump_reason));
1153
1154         if (p_mdump_info->reason) {
1155                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1156                 if (rc != ECORE_SUCCESS)
1157                         return rc;
1158
1159                 p_mdump_info->version = mdump_config.version;
1160                 p_mdump_info->config = mdump_config.config;
1161                 p_mdump_info->epoch = mdump_config.epoc;
1162                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1163                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1164
1165                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1166                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1167                            p_mdump_info->reason, p_mdump_info->version,
1168                            p_mdump_info->config, p_mdump_info->epoch,
1169                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1170         } else {
1171                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1172                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1173         }
1174
1175         return ECORE_SUCCESS;
1176 }
1177
1178 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1179                                                 struct ecore_ptt *p_ptt)
1180 {
1181         u32 mcp_resp;
1182
1183         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_CLEAR_LOGS,
1184                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1185 }
1186
1187 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1188                                             struct ecore_ptt *p_ptt)
1189 {
1190         /* In CMT mode - no need for more than a single acknowledgment to the
1191          * MFW, and no more than a single notification to the upper driver.
1192          */
1193         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1194                 return;
1195
1196         DP_NOTICE(p_hwfn, false,
1197                   "Received a critical error notification from the MFW!\n");
1198
1199         if (p_hwfn->p_dev->mdump_en) {
1200                 DP_NOTICE(p_hwfn, false,
1201                           "Not acknowledging the notification to allow the MFW crash dump\n");
1202                 p_hwfn->p_dev->mdump_en = false;
1203                 return;
1204         }
1205
1206         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1207         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1208 }
1209
1210 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1211                                              struct ecore_ptt *p_ptt)
1212 {
1213         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1214         enum _ecore_status_t rc = ECORE_SUCCESS;
1215         bool found = false;
1216         u16 i;
1217
1218         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1219
1220         /* Read Messages from MFW */
1221         ecore_mcp_read_mb(p_hwfn, p_ptt);
1222
1223         /* Compare current messages to old ones */
1224         for (i = 0; i < info->mfw_mb_length; i++) {
1225                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1226                         continue;
1227
1228                 found = true;
1229
1230                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1231                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1232                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1233
1234                 switch (i) {
1235                 case MFW_DRV_MSG_LINK_CHANGE:
1236                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1237                         break;
1238                 case MFW_DRV_MSG_VF_DISABLED:
1239                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1240                         break;
1241                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1242                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1243                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1244                         break;
1245                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1246                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1247                                                     ECORE_DCBX_REMOTE_MIB);
1248                         break;
1249                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1250                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1251                                                     ECORE_DCBX_OPERATIONAL_MIB);
1252                         break;
1253                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1254                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1255                         break;
1256                 case MFW_DRV_MSG_ERROR_RECOVERY:
1257                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1258                         break;
1259                 case MFW_DRV_MSG_GET_LAN_STATS:
1260                 case MFW_DRV_MSG_GET_FCOE_STATS:
1261                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1262                 case MFW_DRV_MSG_GET_RDMA_STATS:
1263                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1264                         break;
1265                 case MFW_DRV_MSG_BW_UPDATE:
1266                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1267                         break;
1268                 case MFW_DRV_MSG_FAILURE_DETECTED:
1269                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1270                         break;
1271                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1272                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1273                         break;
1274                 default:
1275                         /* @DPDK */
1276                         DP_NOTICE(p_hwfn, false,
1277                                   "Unimplemented MFW message %d\n", i);
1278                         rc = ECORE_INVAL;
1279                 }
1280         }
1281
1282         /* ACK everything */
1283         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1284                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1285
1286                 /* MFW expect answer in BE, so we force write in that format */
1287                 ecore_wr(p_hwfn, p_ptt,
1288                          info->mfw_mb_addr + sizeof(u32) +
1289                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1290                          sizeof(u32) + i * sizeof(u32), val);
1291         }
1292
1293         if (!found) {
1294                 DP_NOTICE(p_hwfn, false,
1295                           "Received an MFW message indication but no"
1296                           " new message!\n");
1297                 rc = ECORE_INVAL;
1298         }
1299
1300         /* Copy the new mfw messages into the shadow */
1301         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1302
1303         return rc;
1304 }
1305
1306 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1307                                            struct ecore_ptt *p_ptt,
1308                                            u32 *p_mfw_ver,
1309                                            u32 *p_running_bundle_id)
1310 {
1311         u32 global_offsize;
1312
1313 #ifndef ASIC_ONLY
1314         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1315                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1316                 return ECORE_SUCCESS;
1317         }
1318 #endif
1319
1320         if (IS_VF(p_hwfn->p_dev)) {
1321                 if (p_hwfn->vf_iov_info) {
1322                         struct pfvf_acquire_resp_tlv *p_resp;
1323
1324                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1325                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1326                         return ECORE_SUCCESS;
1327                 } else {
1328                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1329                                    "VF requested MFW version prior to ACQUIRE\n");
1330                         return ECORE_INVAL;
1331                 }
1332         }
1333
1334         global_offsize = ecore_rd(p_hwfn, p_ptt,
1335                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1336                                                        public_base,
1337                                                        PUBLIC_GLOBAL));
1338         *p_mfw_ver =
1339             ecore_rd(p_hwfn, p_ptt,
1340                      SECTION_ADDR(global_offsize,
1341                                   0) + OFFSETOF(struct public_global, mfw_ver));
1342
1343         if (p_running_bundle_id != OSAL_NULL) {
1344                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1345                                                 SECTION_ADDR(global_offsize,
1346                                                              0) +
1347                                                 OFFSETOF(struct public_global,
1348                                                          running_bundle_id));
1349         }
1350
1351         return ECORE_SUCCESS;
1352 }
1353
1354 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1355                                               u32 *p_media_type)
1356 {
1357         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1358         struct ecore_ptt *p_ptt;
1359
1360         /* TODO - Add support for VFs */
1361         if (IS_VF(p_dev))
1362                 return ECORE_INVAL;
1363
1364         if (!ecore_mcp_is_init(p_hwfn)) {
1365                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1366                 return ECORE_BUSY;
1367         }
1368
1369         *p_media_type = MEDIA_UNSPECIFIED;
1370
1371         p_ptt = ecore_ptt_acquire(p_hwfn);
1372         if (!p_ptt)
1373                 return ECORE_BUSY;
1374
1375         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1376                                  OFFSETOF(struct public_port, media_type));
1377
1378         ecore_ptt_release(p_hwfn, p_ptt);
1379
1380         return ECORE_SUCCESS;
1381 }
1382
1383 static enum _ecore_status_t
1384 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1385                           struct public_func *p_info,
1386                           enum ecore_pci_personality *p_proto)
1387 {
1388         enum _ecore_status_t rc = ECORE_SUCCESS;
1389
1390         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1391         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1392                 *p_proto = ECORE_PCI_ETH;
1393                 break;
1394         default:
1395                 rc = ECORE_INVAL;
1396         }
1397
1398         return rc;
1399 }
1400
1401 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1402                                                     struct ecore_ptt *p_ptt)
1403 {
1404         struct ecore_mcp_function_info *info;
1405         struct public_func shmem_info;
1406
1407         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1408         info = &p_hwfn->mcp_info->func_info;
1409
1410         info->pause_on_host = (shmem_info.config &
1411                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1412
1413         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1414                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1415                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1416                 return ECORE_INVAL;
1417         }
1418
1419         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1420
1421         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1422                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1423                 info->mac[1] = (u8)(shmem_info.mac_upper);
1424                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1425                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1426                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1427                 info->mac[5] = (u8)(shmem_info.mac_lower);
1428         } else {
1429                 /* TODO - are there protocols for which there's no MAC? */
1430                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1431         }
1432
1433         /* TODO - are these calculations true for BE machine? */
1434         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1435                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1436         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1437                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1438
1439         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1440
1441         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1442                    "Read configuration from shmem: pause_on_host %02x"
1443                     " protocol %02x BW [%02x - %02x]"
1444                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1445                     " node %lx ovlan %04x\n",
1446                    info->pause_on_host, info->protocol,
1447                    info->bandwidth_min, info->bandwidth_max,
1448                    info->mac[0], info->mac[1], info->mac[2],
1449                    info->mac[3], info->mac[4], info->mac[5],
1450                    (unsigned long)info->wwn_port,
1451                    (unsigned long)info->wwn_node, info->ovlan);
1452
1453         return ECORE_SUCCESS;
1454 }
1455
1456 struct ecore_mcp_link_params
1457 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1458 {
1459         if (!p_hwfn || !p_hwfn->mcp_info)
1460                 return OSAL_NULL;
1461         return &p_hwfn->mcp_info->link_input;
1462 }
1463
1464 struct ecore_mcp_link_state
1465 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1466 {
1467         if (!p_hwfn || !p_hwfn->mcp_info)
1468                 return OSAL_NULL;
1469
1470 #ifndef ASIC_ONLY
1471         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1472                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1473                 p_hwfn->mcp_info->link_output.link_up = true;
1474         }
1475 #endif
1476
1477         return &p_hwfn->mcp_info->link_output;
1478 }
1479
1480 struct ecore_mcp_link_capabilities
1481 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1482 {
1483         if (!p_hwfn || !p_hwfn->mcp_info)
1484                 return OSAL_NULL;
1485         return &p_hwfn->mcp_info->link_capabilities;
1486 }
1487
1488 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1489                                      struct ecore_ptt *p_ptt)
1490 {
1491         u32 resp = 0, param = 0;
1492         enum _ecore_status_t rc;
1493
1494         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1495                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1496
1497         /* Wait for the drain to complete before returning */
1498         OSAL_MSLEEP(1020);
1499
1500         return rc;
1501 }
1502
1503 const struct ecore_mcp_function_info
1504 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1505 {
1506         if (!p_hwfn || !p_hwfn->mcp_info)
1507                 return OSAL_NULL;
1508         return &p_hwfn->mcp_info->func_info;
1509 }
1510
1511 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1512                                            struct ecore_ptt *p_ptt,
1513                                            struct ecore_mcp_nvm_params *params)
1514 {
1515         enum _ecore_status_t rc;
1516
1517         switch (params->type) {
1518         case ECORE_MCP_NVM_RD:
1519                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1520                                           params->nvm_common.offset,
1521                                           &params->nvm_common.resp,
1522                                           &params->nvm_common.param,
1523                                           params->nvm_rd.buf_size,
1524                                           params->nvm_rd.buf);
1525                 break;
1526         case ECORE_MCP_CMD:
1527                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1528                                    params->nvm_common.offset,
1529                                    &params->nvm_common.resp,
1530                                    &params->nvm_common.param);
1531                 break;
1532         case ECORE_MCP_NVM_WR:
1533                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1534                                           params->nvm_common.offset,
1535                                           &params->nvm_common.resp,
1536                                           &params->nvm_common.param,
1537                                           params->nvm_wr.buf_size,
1538                                           params->nvm_wr.buf);
1539                 break;
1540         default:
1541                 rc = ECORE_NOTIMPL;
1542                 break;
1543         }
1544         return rc;
1545 }
1546
1547 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1548                                   struct ecore_ptt *p_ptt, u32 personalities)
1549 {
1550         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1551         struct public_func shmem_info;
1552         int i, count = 0, num_pfs;
1553
1554         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1555
1556         for (i = 0; i < num_pfs; i++) {
1557                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1558                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1559                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1560                         continue;
1561
1562                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1563                                               &protocol) != ECORE_SUCCESS)
1564                         continue;
1565
1566                 if ((1 << ((u32)protocol)) & personalities)
1567                         count++;
1568         }
1569
1570         return count;
1571 }
1572
1573 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1574                                               struct ecore_ptt *p_ptt,
1575                                               u32 *p_flash_size)
1576 {
1577         u32 flash_size;
1578
1579 #ifndef ASIC_ONLY
1580         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1581                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1582                 return ECORE_INVAL;
1583         }
1584 #endif
1585
1586         if (IS_VF(p_hwfn->p_dev))
1587                 return ECORE_INVAL;
1588
1589         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1590         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1591             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1592         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1593
1594         *p_flash_size = flash_size;
1595
1596         return ECORE_SUCCESS;
1597 }
1598
1599 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1600                                                   struct ecore_ptt *p_ptt)
1601 {
1602         struct ecore_dev *p_dev = p_hwfn->p_dev;
1603
1604         if (p_dev->recov_in_prog) {
1605                 DP_NOTICE(p_hwfn, false,
1606                           "Avoid triggering a recovery since such a process"
1607                           " is already in progress\n");
1608                 return ECORE_AGAIN;
1609         }
1610
1611         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1612         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1613
1614         return ECORE_SUCCESS;
1615 }
1616
1617 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1618                                               struct ecore_ptt *p_ptt,
1619                                               u8 vf_id, u8 num)
1620 {
1621         u32 resp = 0, param = 0, rc_param = 0;
1622         enum _ecore_status_t rc;
1623
1624 /* Only Leader can configure MSIX, and need to take CMT into account */
1625
1626         if (!IS_LEAD_HWFN(p_hwfn))
1627                 return ECORE_SUCCESS;
1628         num *= p_hwfn->p_dev->num_hwfns;
1629
1630         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1631             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1632         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1633             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1634
1635         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1636                            &resp, &rc_param);
1637
1638         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1639                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1640                           vf_id);
1641                 rc = ECORE_INVAL;
1642         } else {
1643                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1644                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1645                             num, vf_id);
1646         }
1647
1648         return rc;
1649 }
1650
1651 enum _ecore_status_t
1652 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1653                            struct ecore_mcp_drv_version *p_ver)
1654 {
1655         struct drv_version_stc *p_drv_version;
1656         struct ecore_mcp_mb_params mb_params;
1657         union drv_union_data union_data;
1658         u32 num_words, i;
1659         void *p_name;
1660         OSAL_BE32 val;
1661         enum _ecore_status_t rc;
1662
1663 #ifndef ASIC_ONLY
1664         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1665                 return ECORE_SUCCESS;
1666 #endif
1667
1668         p_drv_version = &union_data.drv_version;
1669         p_drv_version->version = p_ver->version;
1670         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1671         for (i = 0; i < num_words; i++) {
1672                 p_name = &p_ver->name[i * sizeof(u32)];
1673                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1674                 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1675         }
1676
1677         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1678         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1679         mb_params.p_data_src = &union_data;
1680         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1681         if (rc != ECORE_SUCCESS)
1682                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1683
1684         return rc;
1685 }
1686
1687 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1688                                     struct ecore_ptt *p_ptt)
1689 {
1690         enum _ecore_status_t rc;
1691         u32 resp = 0, param = 0;
1692
1693         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1694                            &param);
1695         if (rc != ECORE_SUCCESS)
1696                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1697
1698         return rc;
1699 }
1700
1701 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1702                                       struct ecore_ptt *p_ptt)
1703 {
1704         u32 value, cpu_mode;
1705
1706         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1707
1708         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1709         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1710         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1711         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1712
1713         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1714 }
1715
1716 enum _ecore_status_t
1717 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1718                                    struct ecore_ptt *p_ptt,
1719                                    enum ecore_ov_config_method config,
1720                                    enum ecore_ov_client client)
1721 {
1722         enum _ecore_status_t rc;
1723         u32 resp = 0, param = 0;
1724         u32 drv_mb_param;
1725
1726         switch (config) {
1727         case ECORE_OV_CLIENT_DRV:
1728                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1729                 break;
1730         case ECORE_OV_CLIENT_USER:
1731                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1732                 break;
1733         default:
1734                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", config);
1735                 return ECORE_INVAL;
1736         }
1737
1738         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1739                            drv_mb_param, &resp, &param);
1740         if (rc != ECORE_SUCCESS)
1741                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1742
1743         return rc;
1744 }
1745
1746 enum _ecore_status_t
1747 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1748                                  struct ecore_ptt *p_ptt,
1749                                  enum ecore_ov_driver_state drv_state)
1750 {
1751         enum _ecore_status_t rc;
1752         u32 resp = 0, param = 0;
1753         u32 drv_mb_param;
1754
1755         switch (drv_state) {
1756         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1757                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1758                 break;
1759         case ECORE_OV_DRIVER_STATE_DISABLED:
1760                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1761                 break;
1762         case ECORE_OV_DRIVER_STATE_ACTIVE:
1763                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1764                 break;
1765         default:
1766                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1767                 return ECORE_INVAL;
1768         }
1769
1770         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1771                            drv_state, &resp, &param);
1772         if (rc != ECORE_SUCCESS)
1773                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1774
1775         return rc;
1776 }
1777
1778 enum _ecore_status_t
1779 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1780                          struct ecore_fc_npiv_tbl *p_table)
1781 {
1782         return 0;
1783 }
1784
1785 enum _ecore_status_t
1786 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1787                         struct ecore_ptt *p_ptt, u16 mtu)
1788 {
1789         return 0;
1790 }
1791
1792 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1793                                        struct ecore_ptt *p_ptt,
1794                                        enum ecore_led_mode mode)
1795 {
1796         u32 resp = 0, param = 0, drv_mb_param;
1797         enum _ecore_status_t rc;
1798
1799         switch (mode) {
1800         case ECORE_LED_MODE_ON:
1801                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1802                 break;
1803         case ECORE_LED_MODE_OFF:
1804                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1805                 break;
1806         case ECORE_LED_MODE_RESTORE:
1807                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1808                 break;
1809         default:
1810                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1811                 return ECORE_INVAL;
1812         }
1813
1814         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1815                            drv_mb_param, &resp, &param);
1816         if (rc != ECORE_SUCCESS)
1817                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1818
1819         return rc;
1820 }
1821
1822 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1823                                              struct ecore_ptt *p_ptt,
1824                                              u32 mask_parities)
1825 {
1826         enum _ecore_status_t rc;
1827         u32 resp = 0, param = 0;
1828
1829         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1830                            mask_parities, &resp, &param);
1831
1832         if (rc != ECORE_SUCCESS) {
1833                 DP_ERR(p_hwfn,
1834                        "MCP response failure for mask parities, aborting\n");
1835         } else if (resp != FW_MSG_CODE_OK) {
1836                 DP_ERR(p_hwfn,
1837                        "MCP did not ack mask parity request. Old MFW?\n");
1838                 rc = ECORE_INVAL;
1839         }
1840
1841         return rc;
1842 }
1843
1844 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1845                                         u8 *p_buf, u32 len)
1846 {
1847         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1848         u32 bytes_left, offset, bytes_to_copy, buf_size;
1849         struct ecore_mcp_nvm_params params;
1850         struct ecore_ptt *p_ptt;
1851         enum _ecore_status_t rc = ECORE_SUCCESS;
1852
1853         p_ptt = ecore_ptt_acquire(p_hwfn);
1854         if (!p_ptt)
1855                 return ECORE_BUSY;
1856
1857         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1858         bytes_left = len;
1859         offset = 0;
1860         params.type = ECORE_MCP_NVM_RD;
1861         params.nvm_rd.buf_size = &buf_size;
1862         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1863         while (bytes_left > 0) {
1864                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1865                                            MCP_DRV_NVM_BUF_LEN);
1866                 params.nvm_common.offset = (addr + offset) |
1867                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1868                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1869                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1870                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1871                                             FW_MSG_CODE_NVM_OK)) {
1872                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1873                         break;
1874                 }
1875
1876                 /* This can be a lengthy process, and it's possible scheduler
1877                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
1878                  */
1879                 if (bytes_left % 0x1000 <
1880                     (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
1881                         OSAL_MSLEEP(1);
1882
1883                 offset += *params.nvm_rd.buf_size;
1884                 bytes_left -= *params.nvm_rd.buf_size;
1885         }
1886
1887         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1888         ecore_ptt_release(p_hwfn, p_ptt);
1889
1890         return rc;
1891 }
1892
1893 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1894                                         u32 addr, u8 *p_buf, u32 len)
1895 {
1896         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1897         struct ecore_mcp_nvm_params params;
1898         struct ecore_ptt *p_ptt;
1899         enum _ecore_status_t rc;
1900
1901         p_ptt = ecore_ptt_acquire(p_hwfn);
1902         if (!p_ptt)
1903                 return ECORE_BUSY;
1904
1905         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1906         params.type = ECORE_MCP_NVM_RD;
1907         params.nvm_rd.buf_size = &len;
1908         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1909             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1910         params.nvm_common.offset = addr;
1911         params.nvm_rd.buf = (u32 *)p_buf;
1912         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1913         if (rc != ECORE_SUCCESS)
1914                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1915
1916         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1917         ecore_ptt_release(p_hwfn, p_ptt);
1918
1919         return rc;
1920 }
1921
1922 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1923 {
1924         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1925         struct ecore_mcp_nvm_params params;
1926         struct ecore_ptt *p_ptt;
1927
1928         p_ptt = ecore_ptt_acquire(p_hwfn);
1929         if (!p_ptt)
1930                 return ECORE_BUSY;
1931
1932         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1933         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1934         ecore_ptt_release(p_hwfn, p_ptt);
1935
1936         return ECORE_SUCCESS;
1937 }
1938
1939 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1940 {
1941         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1942         struct ecore_mcp_nvm_params params;
1943         struct ecore_ptt *p_ptt;
1944         enum _ecore_status_t rc;
1945
1946         p_ptt = ecore_ptt_acquire(p_hwfn);
1947         if (!p_ptt)
1948                 return ECORE_BUSY;
1949         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1950         params.type = ECORE_MCP_CMD;
1951         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1952         params.nvm_common.offset = addr;
1953         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1954         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1955         ecore_ptt_release(p_hwfn, p_ptt);
1956
1957         return rc;
1958 }
1959
1960 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1961                                                   u32 addr)
1962 {
1963         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1964         struct ecore_mcp_nvm_params params;
1965         struct ecore_ptt *p_ptt;
1966         enum _ecore_status_t rc;
1967
1968         p_ptt = ecore_ptt_acquire(p_hwfn);
1969         if (!p_ptt)
1970                 return ECORE_BUSY;
1971         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1972         params.type = ECORE_MCP_CMD;
1973         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1974         params.nvm_common.offset = addr;
1975         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1976         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1977         ecore_ptt_release(p_hwfn, p_ptt);
1978
1979         return rc;
1980 }
1981
1982 /* rc receives ECORE_INVAL as default parameter because
1983  * it might not enter the while loop if the len is 0
1984  */
1985 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1986                                          u32 addr, u8 *p_buf, u32 len)
1987 {
1988         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1989         enum _ecore_status_t rc = ECORE_INVAL;
1990         struct ecore_mcp_nvm_params params;
1991         struct ecore_ptt *p_ptt;
1992         u32 buf_idx, buf_size;
1993
1994         p_ptt = ecore_ptt_acquire(p_hwfn);
1995         if (!p_ptt)
1996                 return ECORE_BUSY;
1997
1998         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1999         params.type = ECORE_MCP_NVM_WR;
2000         if (cmd == ECORE_PUT_FILE_DATA)
2001                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2002         else
2003                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2004         buf_idx = 0;
2005         while (buf_idx < len) {
2006                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2007                                       MCP_DRV_NVM_BUF_LEN);
2008                 params.nvm_common.offset = ((buf_size <<
2009                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
2010                                             | addr) + buf_idx;
2011                 params.nvm_wr.buf_size = buf_size;
2012                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2013                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2014                 if (rc != ECORE_SUCCESS ||
2015                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2016                      (params.nvm_common.resp !=
2017                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2018                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2019
2020                 /* This can be a lengthy process, and it's possible scheduler
2021                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2022                  */
2023                 if (buf_idx % 0x1000 >
2024                     (buf_idx + buf_size) % 0x1000)
2025                         OSAL_MSLEEP(1);
2026
2027                 buf_idx += buf_size;
2028         }
2029
2030         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2031         ecore_ptt_release(p_hwfn, p_ptt);
2032
2033         return rc;
2034 }
2035
2036 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2037                                          u32 addr, u8 *p_buf, u32 len)
2038 {
2039         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2040         struct ecore_mcp_nvm_params params;
2041         struct ecore_ptt *p_ptt;
2042         enum _ecore_status_t rc;
2043
2044         p_ptt = ecore_ptt_acquire(p_hwfn);
2045         if (!p_ptt)
2046                 return ECORE_BUSY;
2047
2048         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2049         params.type = ECORE_MCP_NVM_WR;
2050         params.nvm_wr.buf_size = len;
2051         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2052             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2053         params.nvm_common.offset = addr;
2054         params.nvm_wr.buf = (u32 *)p_buf;
2055         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2056         if (rc != ECORE_SUCCESS)
2057                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2058         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2059         ecore_ptt_release(p_hwfn, p_ptt);
2060
2061         return rc;
2062 }
2063
2064 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2065                                                    u32 addr)
2066 {
2067         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2068         struct ecore_mcp_nvm_params params;
2069         struct ecore_ptt *p_ptt;
2070         enum _ecore_status_t rc;
2071
2072         p_ptt = ecore_ptt_acquire(p_hwfn);
2073         if (!p_ptt)
2074                 return ECORE_BUSY;
2075
2076         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2077         params.type = ECORE_MCP_CMD;
2078         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2079         params.nvm_common.offset = addr;
2080         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2081         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2082         ecore_ptt_release(p_hwfn, p_ptt);
2083
2084         return rc;
2085 }
2086
2087 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2088                                             struct ecore_ptt *p_ptt,
2089                                             u32 port, u32 addr, u32 offset,
2090                                             u32 len, u8 *p_buf)
2091 {
2092         struct ecore_mcp_nvm_params params;
2093         enum _ecore_status_t rc;
2094         u32 bytes_left, bytes_to_copy, buf_size;
2095
2096         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2097         params.nvm_common.offset =
2098                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2099                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2100         addr = offset;
2101         offset = 0;
2102         bytes_left = len;
2103         params.type = ECORE_MCP_NVM_RD;
2104         params.nvm_rd.buf_size = &buf_size;
2105         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2106         while (bytes_left > 0) {
2107                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2108                                            MAX_I2C_TRANSACTION_SIZE);
2109                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2110                 params.nvm_common.offset &=
2111                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2112                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2113                 params.nvm_common.offset |=
2114                         ((addr + offset) <<
2115                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2116                 params.nvm_common.offset |=
2117                         (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2118                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2119                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2120                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2121                         return ECORE_NODEV;
2122                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2123                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2124                         return ECORE_UNKNOWN_ERROR;
2125
2126                 offset += *params.nvm_rd.buf_size;
2127                 bytes_left -= *params.nvm_rd.buf_size;
2128         }
2129
2130         return ECORE_SUCCESS;
2131 }
2132
2133 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2134                                              struct ecore_ptt *p_ptt,
2135                                              u32 port, u32 addr, u32 offset,
2136                                              u32 len, u8 *p_buf)
2137 {
2138         struct ecore_mcp_nvm_params params;
2139         enum _ecore_status_t rc;
2140         u32 buf_idx, buf_size;
2141
2142         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2143         params.nvm_common.offset =
2144                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2145                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2146         params.type = ECORE_MCP_NVM_WR;
2147         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2148         buf_idx = 0;
2149         while (buf_idx < len) {
2150                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2151                                       MAX_I2C_TRANSACTION_SIZE);
2152                 params.nvm_common.offset &=
2153                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2154                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2155                 params.nvm_common.offset |=
2156                         ((offset + buf_idx) <<
2157                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2158                 params.nvm_common.offset |=
2159                         (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2160                 params.nvm_wr.buf_size = buf_size;
2161                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2162                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2163                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2164                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2165                         return ECORE_NODEV;
2166                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2167                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2168                         return ECORE_UNKNOWN_ERROR;
2169
2170                 buf_idx += buf_size;
2171         }
2172
2173         return ECORE_SUCCESS;
2174 }
2175
2176 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2177                                          struct ecore_ptt *p_ptt,
2178                                          u16 gpio, u32 *gpio_val)
2179 {
2180         enum _ecore_status_t rc = ECORE_SUCCESS;
2181         u32 drv_mb_param = 0, rsp;
2182
2183         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2184
2185         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2186                            drv_mb_param, &rsp, gpio_val);
2187
2188         if (rc != ECORE_SUCCESS)
2189                 return rc;
2190
2191         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2192                 return ECORE_UNKNOWN_ERROR;
2193
2194         return ECORE_SUCCESS;
2195 }
2196
2197 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2198                                           struct ecore_ptt *p_ptt,
2199                                           u16 gpio, u16 gpio_val)
2200 {
2201         enum _ecore_status_t rc = ECORE_SUCCESS;
2202         u32 drv_mb_param = 0, param, rsp;
2203
2204         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2205                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2206
2207         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2208                            drv_mb_param, &rsp, &param);
2209
2210         if (rc != ECORE_SUCCESS)
2211                 return rc;
2212
2213         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2214                 return ECORE_UNKNOWN_ERROR;
2215
2216         return ECORE_SUCCESS;
2217 }
2218
2219 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2220                                          struct ecore_ptt *p_ptt,
2221                                          u16 gpio, u32 *gpio_direction,
2222                                          u32 *gpio_ctrl)
2223 {
2224         u32 drv_mb_param = 0, rsp, val = 0;
2225         enum _ecore_status_t rc = ECORE_SUCCESS;
2226
2227         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2228
2229         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2230                            drv_mb_param, &rsp, &val);
2231         if (rc != ECORE_SUCCESS)
2232                 return rc;
2233
2234         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2235                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2236         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2237                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2238
2239         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2240                 return ECORE_UNKNOWN_ERROR;
2241
2242         return ECORE_SUCCESS;
2243 }
2244
2245 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2246                                                   struct ecore_ptt *p_ptt)
2247 {
2248         u32 drv_mb_param = 0, rsp, param;
2249         enum _ecore_status_t rc = ECORE_SUCCESS;
2250
2251         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2252                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2253
2254         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2255                            drv_mb_param, &rsp, &param);
2256
2257         if (rc != ECORE_SUCCESS)
2258                 return rc;
2259
2260         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2261             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2262                 rc = ECORE_UNKNOWN_ERROR;
2263
2264         return rc;
2265 }
2266
2267 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2268                                                struct ecore_ptt *p_ptt)
2269 {
2270         u32 drv_mb_param = 0, rsp, param;
2271         enum _ecore_status_t rc = ECORE_SUCCESS;
2272
2273         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2274                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2275
2276         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2277                            drv_mb_param, &rsp, &param);
2278
2279         if (rc != ECORE_SUCCESS)
2280                 return rc;
2281
2282         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2283             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2284                 rc = ECORE_UNKNOWN_ERROR;
2285
2286         return rc;
2287 }
2288
2289 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2290         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2291 {
2292         u32 drv_mb_param = 0, rsp;
2293         enum _ecore_status_t rc = ECORE_SUCCESS;
2294
2295         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2296                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2297
2298         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2299                            drv_mb_param, &rsp, num_images);
2300
2301         if (rc != ECORE_SUCCESS)
2302                 return rc;
2303
2304         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2305                 rc = ECORE_UNKNOWN_ERROR;
2306
2307         return rc;
2308 }
2309
2310 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2311         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2312         struct bist_nvm_image_att *p_image_att, u32 image_index)
2313 {
2314         struct ecore_mcp_nvm_params params;
2315         enum _ecore_status_t rc;
2316         u32 buf_size;
2317
2318         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2319         params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2320                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2321         params.nvm_common.offset |= (image_index <<
2322                                     DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2323
2324         params.type = ECORE_MCP_NVM_RD;
2325         params.nvm_rd.buf_size = &buf_size;
2326         params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2327         params.nvm_rd.buf = (u32 *)p_image_att;
2328
2329         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2330         if (rc != ECORE_SUCCESS)
2331                 return rc;
2332
2333         if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2334             (p_image_att->return_code != 1))
2335                 rc = ECORE_UNKNOWN_ERROR;
2336
2337         return rc;
2338 }
2339
2340 enum _ecore_status_t
2341 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2342                                struct ecore_ptt *p_ptt,
2343                                struct ecore_temperature_info *p_temp_info)
2344 {
2345         struct ecore_temperature_sensor *p_temp_sensor;
2346         struct temperature_status_stc *p_mfw_temp_info;
2347         struct ecore_mcp_mb_params mb_params;
2348         union drv_union_data union_data;
2349         u32 val;
2350         enum _ecore_status_t rc;
2351         u8 i;
2352
2353         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2354         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2355         mb_params.p_data_dst = &union_data;
2356         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2357         if (rc != ECORE_SUCCESS)
2358                 return rc;
2359
2360         p_mfw_temp_info = &union_data.temp_info;
2361
2362         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2363         p_temp_info->num_sensors = OSAL_MIN_T(u32,
2364                                               p_mfw_temp_info->num_of_sensors,
2365                                               ECORE_MAX_NUM_OF_SENSORS);
2366         for (i = 0; i < p_temp_info->num_sensors; i++) {
2367                 val = p_mfw_temp_info->sensor[i];
2368                 p_temp_sensor = &p_temp_info->sensors[i];
2369                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2370                                                  SENSOR_LOCATION_SHIFT;
2371                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2372                                                 THRESHOLD_HIGH_SHIFT;
2373                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2374                                           CRITICAL_TEMPERATURE_SHIFT;
2375                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2376                                               CURRENT_TEMP_SHIFT;
2377         }
2378
2379         return ECORE_SUCCESS;
2380 }
2381
2382 enum _ecore_status_t ecore_mcp_get_mba_versions(
2383         struct ecore_hwfn *p_hwfn,
2384         struct ecore_ptt *p_ptt,
2385         struct ecore_mba_vers *p_mba_vers)
2386 {
2387         struct ecore_mcp_nvm_params params;
2388         enum _ecore_status_t rc;
2389         u32 buf_size;
2390
2391         OSAL_MEM_ZERO(&params, sizeof(params));
2392         params.type = ECORE_MCP_NVM_RD;
2393         params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2394         params.nvm_common.offset = 0;
2395         params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2396         params.nvm_rd.buf_size = &buf_size;
2397         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2398
2399         if (rc != ECORE_SUCCESS)
2400                 return rc;
2401
2402         if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2403             FW_MSG_CODE_NVM_OK)
2404                 rc = ECORE_UNKNOWN_ERROR;
2405
2406         if (buf_size != MCP_DRV_NVM_BUF_LEN)
2407                 rc = ECORE_UNKNOWN_ERROR;
2408
2409         return rc;
2410 }
2411
2412 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2413                                               struct ecore_ptt *p_ptt,
2414                                               u64 *num_events)
2415 {
2416         u32 rsp;
2417
2418         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2419                              0, &rsp, (u32 *)num_events);
2420 }
2421
2422 #define ECORE_RESC_ALLOC_VERSION_MAJOR  1
2423 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
2424 #define ECORE_RESC_ALLOC_VERSION                                \
2425         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
2426           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
2427          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
2428           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2429
2430 enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
2431                                              struct ecore_ptt *p_ptt,
2432                                              struct resource_info *p_resc_info,
2433                                              u32 *p_mcp_resp, u32 *p_mcp_param)
2434 {
2435         struct ecore_mcp_mb_params mb_params;
2436         union drv_union_data *p_union_data;
2437         enum _ecore_status_t rc;
2438
2439         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2440         mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2441         mb_params.param = ECORE_RESC_ALLOC_VERSION;
2442         p_union_data = (union drv_union_data *)p_resc_info;
2443         mb_params.p_data_src = p_union_data;
2444         mb_params.p_data_dst = p_union_data;
2445         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2446         if (rc != ECORE_SUCCESS)
2447                 return rc;
2448
2449         *p_mcp_resp = mb_params.mcp_resp;
2450         *p_mcp_param = mb_params.mcp_param;
2451
2452         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2453                    "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
2454                    " offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
2455                    *p_mcp_param, p_resc_info->res_id, p_resc_info->size,
2456                    p_resc_info->offset, p_resc_info->vf_size,
2457                    p_resc_info->vf_offset, p_resc_info->flags);
2458
2459         return ECORE_SUCCESS;
2460 }
2461
2462 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
2463                                                struct ecore_ptt *p_ptt)
2464 {
2465         u32 mcp_resp, mcp_param;
2466
2467         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2468                              &mcp_resp, &mcp_param);
2469 }