drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_iov_api.h"
  19 #include "ecore_gtt_reg_addr.h"
  20 #include "ecore_iro.h"
  21 #include "ecore_dcbx.h"
  22
  23 #define CHIP_MCP_RESP_ITER_US 10
  24 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  25
  26 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  27 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  28
  29 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  30         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  31                  _val)
  32
  33 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  34         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  35
  36 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  37         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  38                      OFFSETOF(struct public_drv_mb, _field), _val)
  39
  40 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  41         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  42                      OFFSETOF(struct public_drv_mb, _field))
  43
  44 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  45         DRV_ID_PDA_COMP_VER_SHIFT)
  46
  47 #define MCP_BYTES_PER_MBIT_SHIFT 17
  48
  49 #ifndef ASIC_ONLY
  50 static int loaded;
  51 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  52 #endif
  53
  54 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  55 {
  56         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  57                 return false;
  58         return true;
  59 }
  60
  61 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  62 {
  63         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  64                                         PUBLIC_PORT);
  65         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  66
  67         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  68                                                    MFW_PORT(p_hwfn));
  69         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  70                    "port_addr = 0x%x, port_id 0x%02x\n",
  71                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  72 }
  73
  74 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  75 {
  76         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  77         OSAL_BE32 tmp;
  78         u32 i;
  79
  80 #ifndef ASIC_ONLY
  81         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  82                 return;
  83 #endif
  84
  85         if (!p_hwfn->mcp_info->public_base)
  86                 return;
  87
  88         for (i = 0; i < length; i++) {
  89                 tmp = ecore_rd(p_hwfn, p_ptt,
  90                                p_hwfn->mcp_info->mfw_mb_addr +
  91                                (i << 2) + sizeof(u32));
  92
  93                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  94                     OSAL_BE32_TO_CPU(tmp);
  95         }
  96 }
  97
  98 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
  99 {
 100         if (p_hwfn->mcp_info) {
 101                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 103                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 104         }
 105         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 106         p_hwfn->mcp_info = OSAL_NULL;
 107
 108         return ECORE_SUCCESS;
 109 }
 110
 111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 112                                                    struct ecore_ptt *p_ptt)
 113 {
 114         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 115         u32 drv_mb_offsize, mfw_mb_offsize;
 116         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 117
 118 #ifndef ASIC_ONLY
 119         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 120                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 121                 p_info->public_base = 0;
 122                 return ECORE_INVAL;
 123         }
 124 #endif
 125
 126         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 127         if (!p_info->public_base)
 128                 return ECORE_INVAL;
 129
 130         p_info->public_base |= GRCBASE_MCP;
 131
 132         /* Calculate the driver and MFW mailbox address */
 133         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 134                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 135                                                        PUBLIC_DRV_MB));
 136         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 137         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 138                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 139                    " mcp_pf_id = 0x%x\n",
 140                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 141
 142         /* Set the MFW MB address */
 143         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 144                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 145                                                        PUBLIC_MFW_MB));
 146         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 147         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 148                                                p_info->mfw_mb_addr);
 149
 150         /* Get the current driver mailbox sequence before sending
 151          * the first command
 152          */
 153         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 154             DRV_MSG_SEQ_NUMBER_MASK;
 155
 156         /* Get current FW pulse sequence */
 157         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 158             DRV_PULSE_SEQ_MASK;
 159
 160         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 161                                           MISCS_REG_GENERIC_POR_0);
 162
 163         return ECORE_SUCCESS;
 164 }
 165
 166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 167                                         struct ecore_ptt *p_ptt)
 168 {
 169         struct ecore_mcp_info *p_info;
 170         u32 size;
 171
 172         /* Allocate mcp_info structure */
 173         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 174                                        sizeof(*p_hwfn->mcp_info));
 175         if (!p_hwfn->mcp_info)
 176                 goto err;
 177         p_info = p_hwfn->mcp_info;
 178
 179         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 180                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 181                 /* Do not free mcp_info here, since public_base indicate that
 182                  * the MCP is not initialized
 183                  */
 184                 return ECORE_SUCCESS;
 185         }
 186
 187         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 188         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 189         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 191                 goto err;
 192
 193         /* Initialize the MFW spinlock */
 194         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 195         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 196
 197         return ECORE_SUCCESS;
 198
 199 err:
 200         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 201         ecore_mcp_free(p_hwfn);
 202         return ECORE_NOMEM;
 203 }
 204
 205 /* Locks the MFW mailbox of a PF to ensure a single access.
 206  * The lock is achieved in most cases by holding a spinlock, causing other
 207  * threads to wait till a previous access is done.
 208  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 209  * access is achieved by setting a blocking flag, which will fail other
 210  * competing contexts to send their mailboxes.
 211  */
 212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 213                                               u32 cmd)
 214 {
 215         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 216
 217         /* The spinlock shouldn't be acquired when the mailbox command is
 218          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 219          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 220          * (i.e. interrupts are disabled) - can lead to a deadlock.
 221          * It is assumed that for a single PF, no other mailbox commands can be
 222          * sent from another context while sending LOAD_REQ, and that any
 223          * parallel commands to UNLOAD_REQ can be cancelled.
 224          */
 225         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 226                 p_hwfn->mcp_info->block_mb_sending = false;
 227
 228         if (p_hwfn->mcp_info->block_mb_sending) {
 229                 DP_NOTICE(p_hwfn, false,
 230                           "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
 231                           cmd);
 232                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 233                 return ECORE_BUSY;
 234         }
 235
 236         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 237                 p_hwfn->mcp_info->block_mb_sending = true;
 238                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 239         }
 240
 241         return ECORE_SUCCESS;
 242 }
 243
 244 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 245 {
 246         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 247                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 248 }
 249
 250 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 251                                      struct ecore_ptt *p_ptt)
 252 {
 253         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 254         u32 delay = CHIP_MCP_RESP_ITER_US;
 255         u32 org_mcp_reset_seq, cnt = 0;
 256         enum _ecore_status_t rc = ECORE_SUCCESS;
 257
 258 #ifndef ASIC_ONLY
 259         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 260                 delay = EMUL_MCP_RESP_ITER_US;
 261 #endif
 262         /* Ensure that only a single thread is accessing the mailbox at a
 263          * certain time.
 264          */
 265         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 266         if (rc != ECORE_SUCCESS)
 267                 return rc;
 268
 269         /* Set drv command along with the updated sequence */
 270         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 271         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 272
 273         do {
 274                 /* Wait for MFW response */
 275                 OSAL_UDELAY(delay);
 276                 /* Give the FW up to 500 second (50*1000*10usec) */
 277         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 278                                                 MISCS_REG_GENERIC_POR_0)) &&
 279                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 280
 281         if (org_mcp_reset_seq !=
 282             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 283                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 284                            "MCP was reset after %d usec\n", cnt * delay);
 285         } else {
 286                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 287                 rc = ECORE_AGAIN;
 288         }
 289
 290         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 291
 292         return rc;
 293 }
 294
 295 /* Should be called while the dedicated spinlock is acquired */
 296 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 297                                              struct ecore_ptt *p_ptt,
 298                                              u32 cmd, u32 param,
 299                                              u32 *o_mcp_resp,
 300                                              u32 *o_mcp_param)
 301 {
 302         u32 delay = CHIP_MCP_RESP_ITER_US;
 303         u32 seq, cnt = 1, actual_mb_seq;
 304         enum _ecore_status_t rc = ECORE_SUCCESS;
 305
 306 #ifndef ASIC_ONLY
 307         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 308                 delay = EMUL_MCP_RESP_ITER_US;
 309 #endif
 310
 311         /* Get actual driver mailbox sequence */
 312         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 313             DRV_MSG_SEQ_NUMBER_MASK;
 314
 315         /* Use MCP history register to check if MCP reset occurred between
 316          * init time and now.
 317          */
 318         if (p_hwfn->mcp_info->mcp_hist !=
 319             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 320                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 321                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 322                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 323         }
 324         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 325
 326         /* Set drv param */
 327         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 328
 329         /* Set drv command along with the updated sequence */
 330         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 331
 332         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 333                    "wrote command (%x) to MFW MB param 0x%08x\n",
 334                    (cmd | seq), param);
 335
 336         do {
 337                 /* Wait for MFW response */
 338                 OSAL_UDELAY(delay);
 339                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 340
 341                 /* Give the FW up to 5 second (500*10ms) */
 342         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 343                  (cnt++ < ECORE_DRV_MB_MAX_RETRIES));
 344
 345         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 346                    "[after %d ms] read (%x) seq is (%x) from FW MB\n",
 347                    cnt * delay, *o_mcp_resp, seq);
 348
 349         /* Is this a reply to our command? */
 350         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 351                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 352                 /* Get the MCP param */
 353                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 354         } else {
 355                 /* FW BUG! */
 356                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 357                        cmd, param);
 358                 *o_mcp_resp = 0;
 359                 rc = ECORE_AGAIN;
 360                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 361         }
 362         return rc;
 363 }
 364
 365
 366 static enum _ecore_status_t
 367 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 368                         struct ecore_mcp_mb_params *p_mb_params)
 369 {
 370         u32 union_data_addr;
 371         enum _ecore_status_t rc;
 372
 373         /* MCP not initialized */
 374         if (!ecore_mcp_is_init(p_hwfn)) {
 375                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 376                 return ECORE_BUSY;
 377         }
 378
 379         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 380                           OFFSETOF(struct public_drv_mb, union_data);
 381
 382         /* Ensure that only a single thread is accessing the mailbox at a
 383          * certain time.
 384          */
 385         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 386         if (rc != ECORE_SUCCESS)
 387                 return rc;
 388
 389         if (p_mb_params->p_data_src != OSAL_NULL)
 390                 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 391                                 p_mb_params->p_data_src,
 392                                 sizeof(*p_mb_params->p_data_src));
 393
 394         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 395                               p_mb_params->param, &p_mb_params->mcp_resp,
 396                               &p_mb_params->mcp_param);
 397
 398         if (p_mb_params->p_data_dst != OSAL_NULL)
 399                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 400                                   union_data_addr,
 401                                   sizeof(*p_mb_params->p_data_dst));
 402
 403         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 404
 405         return rc;
 406 }
 407
 408 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 409                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 410                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 411 {
 412         struct ecore_mcp_mb_params mb_params;
 413         enum _ecore_status_t rc;
 414
 415 #ifndef ASIC_ONLY
 416         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 417                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 418                         loaded--;
 419                         loaded_port[p_hwfn->port_id]--;
 420                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 421                                    loaded);
 422                 }
 423                 return ECORE_SUCCESS;
 424         }
 425 #endif
 426         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 427         mb_params.cmd = cmd;
 428         mb_params.param = param;
 429         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 430         if (rc != ECORE_SUCCESS)
 431                 return rc;
 432
 433         *o_mcp_resp = mb_params.mcp_resp;
 434         *o_mcp_param = mb_params.mcp_param;
 435
 436         return ECORE_SUCCESS;
 437 }
 438
 439 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 440                                           struct ecore_ptt *p_ptt,
 441                                           u32 cmd,
 442                                           u32 param,
 443                                           u32 *o_mcp_resp,
 444                                           u32 *o_mcp_param,
 445                                           u32 i_txn_size, u32 *i_buf)
 446 {
 447         struct ecore_mcp_mb_params mb_params;
 448         union drv_union_data union_data;
 449         enum _ecore_status_t rc;
 450
 451         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 452         mb_params.cmd = cmd;
 453         mb_params.param = param;
 454         OSAL_MEMCPY(&union_data.raw_data, i_buf, i_txn_size);
 455         mb_params.p_data_src = &union_data;
 456         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 457         if (rc != ECORE_SUCCESS)
 458                 return rc;
 459
 460         *o_mcp_resp = mb_params.mcp_resp;
 461         *o_mcp_param = mb_params.mcp_param;
 462
 463         return ECORE_SUCCESS;
 464 }
 465
 466 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 467                                           struct ecore_ptt *p_ptt,
 468                                           u32 cmd,
 469                                           u32 param,
 470                                           u32 *o_mcp_resp,
 471                                           u32 *o_mcp_param,
 472                                           u32 *o_txn_size, u32 *o_buf)
 473 {
 474         enum _ecore_status_t rc;
 475         u32 i;
 476
 477         /* MCP not initialized */
 478         if (!ecore_mcp_is_init(p_hwfn)) {
 479                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 480                 return ECORE_BUSY;
 481         }
 482
 483         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 484         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, o_mcp_resp,
 485                               o_mcp_param);
 486         if (rc != ECORE_SUCCESS)
 487                 goto out;
 488
 489         /* Get payload after operation completes successfully */
 490         *o_txn_size = *o_mcp_param;
 491         for (i = 0; i < *o_txn_size; i += 4)
 492                 o_buf[i / sizeof(u32)] = DRV_MB_RD(p_hwfn, p_ptt,
 493                                                    union_data.raw_data[i]);
 494
 495 out:
 496         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 497         return rc;
 498 }
 499
 500 #ifndef ASIC_ONLY
 501 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 502                                     u32 *p_load_code)
 503 {
 504         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 505
 506         if (!loaded)
 507                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 508         else if (!loaded_port[p_hwfn->port_id])
 509                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 510         else
 511                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 512
 513         /* On CMT, always tell that it's engine */
 514         if (p_hwfn->p_dev->num_hwfns > 1)
 515                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 516
 517         *p_load_code = load_phase;
 518         loaded++;
 519         loaded_port[p_hwfn->port_id]++;
 520
 521         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 522                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 523                    *p_load_code, loaded, p_hwfn->port_id,
 524                    loaded_port[p_hwfn->port_id]);
 525 }
 526 #endif
 527
 528 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 529                                         struct ecore_ptt *p_ptt,
 530                                         u32 *p_load_code)
 531 {
 532         struct ecore_dev *p_dev = p_hwfn->p_dev;
 533         struct ecore_mcp_mb_params mb_params;
 534         union drv_union_data union_data;
 535         u32 param;
 536         enum _ecore_status_t rc;
 537
 538 #ifndef ASIC_ONLY
 539         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 540                 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
 541                 return ECORE_SUCCESS;
 542         }
 543 #endif
 544
 545         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 546         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 547         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 548                           p_dev->drv_type;
 549         OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
 550         mb_params.p_data_src = &union_data;
 551         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 552
 553         /* if mcp fails to respond we must abort */
 554         if (rc != ECORE_SUCCESS) {
 555                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 556                 return rc;
 557         }
 558
 559         /* If MFW refused (e.g. other port is in diagnostic mode) we
 560          * must abort. This can happen in the following cases:
 561          * - Other port is in diagnostic mode
 562          * - Previously loaded function on the engine is not compliant with
 563          *   the requester.
 564          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 565          *      -
 566          */
 567         if (!(*p_load_code) ||
 568             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 569             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 570             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 571                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 572                 return ECORE_BUSY;
 573         }
 574
 575         return ECORE_SUCCESS;
 576 }
 577
 578 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 579                                     struct ecore_ptt *p_ptt)
 580 {
 581         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 582                                         PUBLIC_PATH);
 583         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 584         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 585                                      ECORE_PATH_ID(p_hwfn));
 586         u32 disabled_vfs[VF_MAX_STATIC / 32];
 587         int i;
 588
 589         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 590                    "Reading Disabled VF information from [offset %08x],"
 591                    " path_addr %08x\n",
 592                    mfw_path_offsize, path_addr);
 593
 594         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 595                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 596                                            path_addr +
 597                                            OFFSETOF(struct public_path,
 598                                                     mcp_vf_disabled) +
 599                                            sizeof(u32) * i);
 600                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 601                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 602                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 603         }
 604
 605         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 606                 OSAL_VF_FLR_UPDATE(p_hwfn);
 607 }
 608
 609 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 610                                           struct ecore_ptt *p_ptt,
 611                                           u32 *vfs_to_ack)
 612 {
 613         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 614                                         PUBLIC_FUNC);
 615         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 616         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 617                                      MCP_PF_ID(p_hwfn));
 618         struct ecore_mcp_mb_params mb_params;
 619         union drv_union_data union_data;
 620         u32 resp, param;
 621         enum _ecore_status_t rc;
 622         int i;
 623
 624         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 625                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 626                            "Acking VFs [%08x,...,%08x] - %08x\n",
 627                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 628
 629         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 630         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 631         OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 632         mb_params.p_data_src = &union_data;
 633         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 634         if (rc != ECORE_SUCCESS) {
 635                 DP_NOTICE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 636                           "Failed to pass ACK for VF flr to MFW\n");
 637                 return ECORE_TIMEOUT;
 638         }
 639
 640         /* TMP - clear the ACK bits; should be done by MFW */
 641         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 642                 ecore_wr(p_hwfn, p_ptt,
 643                          func_addr +
 644                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
 645                          i * sizeof(u32), 0);
 646
 647         return rc;
 648 }
 649
 650 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
 651                                                 struct ecore_ptt *p_ptt)
 652 {
 653         u32 transceiver_state;
 654
 655         transceiver_state = ecore_rd(p_hwfn, p_ptt,
 656                                      p_hwfn->mcp_info->port_addr +
 657                                      OFFSETOF(struct public_port,
 658                                               transceiver_data));
 659
 660         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
 661                    "Received transceiver state update [0x%08x] from mfw"
 662                    " [Addr 0x%x]\n",
 663                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
 664                                             OFFSETOF(struct public_port,
 665                                                      transceiver_data)));
 666
 667         transceiver_state = GET_FIELD(transceiver_state, PMM_TRANSCEIVER_STATE);
 668
 669         if (transceiver_state == PMM_TRANSCEIVER_STATE_PRESENT)
 670                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
 671         else
 672                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
 673 }
 674
 675 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
 676                                          struct ecore_ptt *p_ptt, bool b_reset)
 677 {
 678         struct ecore_mcp_link_state *p_link;
 679         u32 status = 0;
 680
 681         p_link = &p_hwfn->mcp_info->link_output;
 682         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
 683         if (!b_reset) {
 684                 status = ecore_rd(p_hwfn, p_ptt,
 685                                   p_hwfn->mcp_info->port_addr +
 686                                   OFFSETOF(struct public_port, link_status));
 687                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
 688                            "Received link update [0x%08x] from mfw"
 689                            " [Addr 0x%x]\n",
 690                            status, (u32)(p_hwfn->mcp_info->port_addr +
 691                                           OFFSETOF(struct public_port,
 692                                                    link_status)));
 693         } else {
 694                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 695                            "Resetting link indications\n");
 696                 return;
 697         }
 698
 699         if (p_hwfn->b_drv_link_init)
 700                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 701         else
 702                 p_link->link_up = false;
 703
 704         p_link->full_duplex = true;
 705         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 706         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 707                 p_link->speed = 100000;
 708                 break;
 709         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 710                 p_link->speed = 50000;
 711                 break;
 712         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 713                 p_link->speed = 40000;
 714                 break;
 715         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 716                 p_link->speed = 25000;
 717                 break;
 718         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 719                 p_link->speed = 20000;
 720                 break;
 721         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 722                 p_link->speed = 10000;
 723                 break;
 724         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 725                 p_link->full_duplex = false;
 726                 /* Fall-through */
 727         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 728                 p_link->speed = 1000;
 729                 break;
 730         default:
 731                 p_link->speed = 0;
 732         }
 733
 734         /* We never store total line speed as p_link->speed is
 735          * again changes according to bandwidth allocation.
 736          */
 737         if (p_link->link_up && p_link->speed)
 738                 p_link->line_speed = p_link->speed;
 739         else
 740                 p_link->line_speed = 0;
 741
 742         /* Correct speed according to bandwidth allocation */
 743         if (p_hwfn->mcp_info->func_info.bandwidth_max && p_link->speed) {
 744                 u8 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 745
 746         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
 747                                            p_link, max_bw);
 748         }
 749
 750         if (p_hwfn->mcp_info->func_info.bandwidth_min && p_link->speed) {
 751                 u8 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 752
 753         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
 754                                            p_link, min_bw);
 755
 756         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
 757                                               p_link->min_pf_rate);
 758         }
 759
 760         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 761         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 762         p_link->parallel_detection = !!(status &
 763                                          LINK_STATUS_PARALLEL_DETECTION_USED);
 764         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 765
 766         p_link->partner_adv_speed |=
 767             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 768             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
 769         p_link->partner_adv_speed |=
 770             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 771             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
 772         p_link->partner_adv_speed |=
 773             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 774             ECORE_LINK_PARTNER_SPEED_10G : 0;
 775         p_link->partner_adv_speed |=
 776             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 777             ECORE_LINK_PARTNER_SPEED_20G : 0;
 778         p_link->partner_adv_speed |=
 779             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 780             ECORE_LINK_PARTNER_SPEED_25G : 0;
 781         p_link->partner_adv_speed |=
 782             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 783             ECORE_LINK_PARTNER_SPEED_40G : 0;
 784         p_link->partner_adv_speed |=
 785             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 786             ECORE_LINK_PARTNER_SPEED_50G : 0;
 787         p_link->partner_adv_speed |=
 788             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 789             ECORE_LINK_PARTNER_SPEED_100G : 0;
 790
 791         p_link->partner_tx_flow_ctrl_en =
 792             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 793         p_link->partner_rx_flow_ctrl_en =
 794             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 795
 796         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 797         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 798                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
 799                 break;
 800         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 801                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
 802                 break;
 803         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 804                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
 805                 break;
 806         default:
 807                 p_link->partner_adv_pause = 0;
 808         }
 809
 810         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 811
 812         if (p_link->link_up)
 813                 ecore_dcbx_eagle_workaround(p_hwfn, p_ptt, p_link->pfc_enabled);
 814
 815         OSAL_LINK_UPDATE(p_hwfn);
 816 }
 817
 818 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 819                                         struct ecore_ptt *p_ptt, bool b_up)
 820 {
 821         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 822         struct ecore_mcp_mb_params mb_params;
 823         union drv_union_data union_data;
 824         struct pmm_phy_cfg *p_phy_cfg;
 825         u32 param = 0, reply = 0, cmd;
 826         enum _ecore_status_t rc = ECORE_SUCCESS;
 827
 828 #ifndef ASIC_ONLY
 829         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 830                 return ECORE_SUCCESS;
 831 #endif
 832
 833         /* Set the shmem configuration according to params */
 834         p_phy_cfg = &union_data.drv_phy_cfg;
 835         OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
 836         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 837         if (!params->speed.autoneg)
 838                 p_phy_cfg->speed = params->speed.forced_speed;
 839         p_phy_cfg->pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0;
 840         p_phy_cfg->pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0;
 841         p_phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0;
 842         p_phy_cfg->adv_speed = params->speed.advertised_speeds;
 843         p_phy_cfg->loopback_mode = params->loopback_mode;
 844
 845 #ifndef ASIC_ONLY
 846         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 847                 DP_INFO(p_hwfn,
 848                         "Link on FPGA - Ask for loopback mode '5' at 10G\n");
 849                 p_phy_cfg->loopback_mode = 5;
 850                 p_phy_cfg->speed = 10000;
 851         }
 852 #endif
 853
 854         p_hwfn->b_drv_link_init = b_up;
 855
 856         if (b_up)
 857                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 858                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
 859                            " adv_speed 0x%08x, loopback 0x%08x,"
 860                            " features 0x%08x\n",
 861                            p_phy_cfg->speed, p_phy_cfg->pause,
 862                            p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode,
 863                            p_phy_cfg->feature_config_flags);
 864         else
 865                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
 866
 867         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 868         mb_params.cmd = cmd;
 869         mb_params.p_data_src = &union_data;
 870         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 871
 872         /* if mcp fails to respond we must abort */
 873         if (rc != ECORE_SUCCESS) {
 874                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 875                 return rc;
 876         }
 877
 878         /* Reset the link status if needed */
 879         if (!b_up)
 880                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
 881
 882         return rc;
 883 }
 884
 885 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
 886                                    struct ecore_ptt *p_ptt)
 887 {
 888         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
 889
 890         /* TODO - Add support for VFs */
 891         if (IS_VF(p_hwfn->p_dev))
 892                 return ECORE_INVAL;
 893
 894         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 895                                                  PUBLIC_PATH);
 896         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
 897         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
 898
 899         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
 900                                  path_addr +
 901                                  OFFSETOF(struct public_path, process_kill)) &
 902             PROCESS_KILL_COUNTER_MASK;
 903
 904         return proc_kill_cnt;
 905 }
 906
 907 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
 908                                           struct ecore_ptt *p_ptt)
 909 {
 910         struct ecore_dev *p_dev = p_hwfn->p_dev;
 911         u32 proc_kill_cnt;
 912
 913         /* Prevent possible attentions/interrupts during the recovery handling
 914          * and till its load phase, during which they will be re-enabled.
 915          */
 916         ecore_int_igu_disable_int(p_hwfn, p_ptt);
 917
 918         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
 919
 920         /* The following operations should be done once, and thus in CMT mode
 921          * are carried out by only the first HW function.
 922          */
 923         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
 924                 return;
 925
 926         if (p_dev->recov_in_prog) {
 927                 DP_NOTICE(p_hwfn, false,
 928                           "Ignoring the indication since a recovery"
 929                           " process is already in progress\n");
 930                 return;
 931         }
 932
 933         p_dev->recov_in_prog = true;
 934
 935         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
 936         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
 937
 938         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
 939 }
 940
 941 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
 942                                           struct ecore_ptt *p_ptt,
 943                                           enum MFW_DRV_MSG_TYPE type)
 944 {
 945         enum ecore_mcp_protocol_type stats_type;
 946         union ecore_mcp_protocol_stats stats;
 947         struct ecore_mcp_mb_params mb_params;
 948         u32 hsi_param, param = 0, reply = 0;
 949         union drv_union_data union_data;
 950
 951         switch (type) {
 952         case MFW_DRV_MSG_GET_LAN_STATS:
 953                 stats_type = ECORE_MCP_LAN_STATS;
 954                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 955                 break;
 956         default:
 957                 DP_NOTICE(p_hwfn, false, "Invalid protocol type %d\n", type);
 958                 return;
 959         }
 960
 961         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
 962
 963         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 964         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 965         mb_params.param = hsi_param;
 966         OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
 967         mb_params.p_data_src = &union_data;
 968         ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 969 }
 970
 971 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
 972                                     struct ecore_ptt *p_ptt,
 973                                     struct public_func *p_data, int pfid)
 974 {
 975         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 976                                         PUBLIC_FUNC);
 977         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 978         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 979         u32 i, size;
 980
 981         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
 982
 983         size = OSAL_MIN_T(u32, sizeof(*p_data), SECTION_SIZE(mfw_path_offsize));
 984         for (i = 0; i < size / sizeof(u32); i++)
 985                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
 986                                               func_addr + (i << 2));
 987
 988         return size;
 989 }
 990
 991 static void
 992 ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 993                         struct public_func *p_shmem_info)
 994 {
 995         struct ecore_mcp_function_info *p_info;
 996
 997         p_info = &p_hwfn->mcp_info->func_info;
 998
 999         /* TODO - bandwidth min/max should have valid values of 1-100,
1000          * as well as some indication that the feature is disabled.
1001          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1002          * limit and correct value to min `1' and max `100' if limit isn't in
1003          * range.
1004          */
1005         p_info->bandwidth_min = (p_shmem_info->config &
1006                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1007             FUNC_MF_CFG_MIN_BW_SHIFT;
1008         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1009                 DP_INFO(p_hwfn,
1010                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1011                         p_info->bandwidth_min);
1012                 p_info->bandwidth_min = 1;
1013         }
1014
1015         p_info->bandwidth_max = (p_shmem_info->config &
1016                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1017             FUNC_MF_CFG_MAX_BW_SHIFT;
1018         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1019                 DP_INFO(p_hwfn,
1020                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1021                         p_info->bandwidth_max);
1022                 p_info->bandwidth_max = 100;
1023         }
1024 }
1025
1026 static void
1027 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1028 {
1029         struct ecore_mcp_function_info *p_info;
1030         struct public_func shmem_info;
1031         u32 resp = 0, param = 0;
1032
1033         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1034
1035         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1036
1037         p_info = &p_hwfn->mcp_info->func_info;
1038
1039         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1040
1041         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1042
1043         /* Acknowledge the MFW */
1044         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1045                       &param);
1046 }
1047
1048 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1049                                          struct ecore_ptt *p_ptt)
1050 {
1051         /* A single notification should be sent to upper driver in CMT mode */
1052         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1053                 return;
1054
1055         DP_NOTICE(p_hwfn, false,
1056                   "Fan failure was detected on the network interface card"
1057                   " and it's going to be shut down.\n");
1058
1059         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1060 }
1061
1062 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1063                                              struct ecore_ptt *p_ptt)
1064 {
1065         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1066         enum _ecore_status_t rc = ECORE_SUCCESS;
1067         bool found = false;
1068         u16 i;
1069
1070         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1071
1072         /* Read Messages from MFW */
1073         ecore_mcp_read_mb(p_hwfn, p_ptt);
1074
1075         /* Compare current messages to old ones */
1076         for (i = 0; i < info->mfw_mb_length; i++) {
1077                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1078                         continue;
1079
1080                 found = true;
1081
1082                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1083                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1084                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1085
1086                 switch (i) {
1087                 case MFW_DRV_MSG_LINK_CHANGE:
1088                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1089                         break;
1090                 case MFW_DRV_MSG_VF_DISABLED:
1091                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1092                         break;
1093                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1094                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1095                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1096                         break;
1097                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1098                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1099                                                     ECORE_DCBX_REMOTE_MIB);
1100                         break;
1101                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1102                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1103                                                     ECORE_DCBX_OPERATIONAL_MIB);
1104                         break;
1105                 case MFW_DRV_MSG_ERROR_RECOVERY:
1106                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1107                         break;
1108                 case MFW_DRV_MSG_GET_LAN_STATS:
1109                 case MFW_DRV_MSG_GET_FCOE_STATS:
1110                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1111                 case MFW_DRV_MSG_GET_RDMA_STATS:
1112                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1113                         break;
1114                 case MFW_DRV_MSG_BW_UPDATE:
1115                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1116                         break;
1117                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1118                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1119                         break;
1120                 case MFW_DRV_MSG_FAILURE_DETECTED:
1121                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1122                         break;
1123                 default:
1124                         /* @DPDK */
1125                         DP_NOTICE(p_hwfn, false,
1126                                   "Unimplemented MFW message %d\n", i);
1127                         rc = ECORE_INVAL;
1128                 }
1129         }
1130
1131         /* ACK everything */
1132         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1133                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1134
1135                 /* MFW expect answer in BE, so we force write in that format */
1136                 ecore_wr(p_hwfn, p_ptt,
1137                          info->mfw_mb_addr + sizeof(u32) +
1138                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1139                          sizeof(u32) + i * sizeof(u32), val);
1140         }
1141
1142         if (!found) {
1143                 DP_NOTICE(p_hwfn, false,
1144                           "Received an MFW message indication but no"
1145                           " new message!\n");
1146                 rc = ECORE_INVAL;
1147         }
1148
1149         /* Copy the new mfw messages into the shadow */
1150         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1151
1152         return rc;
1153 }
1154
1155 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev,
1156                                            struct ecore_ptt *p_ptt,
1157                                            u32 *p_mfw_ver,
1158                                            u32 *p_running_bundle_id)
1159 {
1160         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1161         u32 global_offsize;
1162
1163 #ifndef ASIC_ONLY
1164         if (CHIP_REV_IS_EMUL(p_dev)) {
1165                 DP_NOTICE(p_dev, false, "Emulation - can't get MFW version\n");
1166                 return ECORE_SUCCESS;
1167         }
1168 #endif
1169
1170         if (IS_VF(p_dev)) {
1171                 if (p_hwfn->vf_iov_info) {
1172                         struct pfvf_acquire_resp_tlv *p_resp;
1173
1174                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1175                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1176                         return ECORE_SUCCESS;
1177                 }
1178
1179                 DP_VERBOSE(p_dev, ECORE_MSG_IOV,
1180                            "VF requested MFW vers prior to ACQUIRE\n");
1181                         return ECORE_INVAL;
1182                 }
1183
1184         global_offsize = ecore_rd(p_hwfn, p_ptt,
1185                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1186                                                        public_base,
1187                                                        PUBLIC_GLOBAL));
1188         *p_mfw_ver =
1189             ecore_rd(p_hwfn, p_ptt,
1190                      SECTION_ADDR(global_offsize,
1191                                   0) + OFFSETOF(struct public_global, mfw_ver));
1192
1193         if (p_running_bundle_id != OSAL_NULL) {
1194                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1195                                                 SECTION_ADDR(global_offsize,
1196                                                              0) +
1197                                                 OFFSETOF(struct public_global,
1198                                                          running_bundle_id));
1199         }
1200
1201         return ECORE_SUCCESS;
1202 }
1203
1204 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1205                                               u32 *p_media_type)
1206 {
1207         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1208         struct ecore_ptt *p_ptt;
1209
1210         /* TODO - Add support for VFs */
1211         if (IS_VF(p_dev))
1212                 return ECORE_INVAL;
1213
1214         if (!ecore_mcp_is_init(p_hwfn)) {
1215                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1216                 return ECORE_BUSY;
1217         }
1218
1219         *p_media_type = MEDIA_UNSPECIFIED;
1220
1221         p_ptt = ecore_ptt_acquire(p_hwfn);
1222         if (!p_ptt)
1223                 return ECORE_BUSY;
1224
1225         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1226                                  OFFSETOF(struct public_port, media_type));
1227
1228         ecore_ptt_release(p_hwfn, p_ptt);
1229
1230         return ECORE_SUCCESS;
1231 }
1232
1233 static enum _ecore_status_t
1234 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1235                           struct public_func *p_info,
1236                           enum ecore_pci_personality *p_proto)
1237 {
1238         enum _ecore_status_t rc = ECORE_SUCCESS;
1239
1240         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1241         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1242                 *p_proto = ECORE_PCI_ETH;
1243                 break;
1244         default:
1245                 rc = ECORE_INVAL;
1246         }
1247
1248         return rc;
1249 }
1250
1251 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1252                                                     struct ecore_ptt *p_ptt)
1253 {
1254         struct ecore_mcp_function_info *info;
1255         struct public_func shmem_info;
1256
1257         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1258         info = &p_hwfn->mcp_info->func_info;
1259
1260         info->pause_on_host = (shmem_info.config &
1261                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1262
1263         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1264                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1265                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1266                 return ECORE_INVAL;
1267         }
1268
1269         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1270
1271         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1272                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1273                 info->mac[1] = (u8)(shmem_info.mac_upper);
1274                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1275                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1276                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1277                 info->mac[5] = (u8)(shmem_info.mac_lower);
1278         } else {
1279                 /* TODO - are there protocols for which there's no MAC? */
1280                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1281         }
1282
1283         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1284
1285         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1286                    "Read configuration from shmem: pause_on_host %02x"
1287                     " protocol %02x BW [%02x - %02x]"
1288                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %" PRIx64
1289                     " node %" PRIx64 " ovlan %04x\n",
1290                    info->pause_on_host, info->protocol,
1291                    info->bandwidth_min, info->bandwidth_max,
1292                    info->mac[0], info->mac[1], info->mac[2],
1293                    info->mac[3], info->mac[4], info->mac[5],
1294                    info->wwn_port, info->wwn_node, info->ovlan);
1295
1296         return ECORE_SUCCESS;
1297 }
1298
1299 struct ecore_mcp_link_params
1300 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1301 {
1302         if (!p_hwfn || !p_hwfn->mcp_info)
1303                 return OSAL_NULL;
1304         return &p_hwfn->mcp_info->link_input;
1305 }
1306
1307 struct ecore_mcp_link_state
1308 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1309 {
1310         if (!p_hwfn || !p_hwfn->mcp_info)
1311                 return OSAL_NULL;
1312
1313 #ifndef ASIC_ONLY
1314         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1315                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1316                 p_hwfn->mcp_info->link_output.link_up = true;
1317         }
1318 #endif
1319
1320         return &p_hwfn->mcp_info->link_output;
1321 }
1322
1323 struct ecore_mcp_link_capabilities
1324 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1325 {
1326         if (!p_hwfn || !p_hwfn->mcp_info)
1327                 return OSAL_NULL;
1328         return &p_hwfn->mcp_info->link_capabilities;
1329 }
1330
1331 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1332                                      struct ecore_ptt *p_ptt)
1333 {
1334         enum _ecore_status_t rc;
1335         u32 resp = 0, param = 0;
1336
1337         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1338                            DRV_MSG_CODE_NIG_DRAIN, 100, &resp, &param);
1339
1340         /* Wait for the drain to complete before returning */
1341         OSAL_MSLEEP(120);
1342
1343         return rc;
1344 }
1345
1346 const struct ecore_mcp_function_info
1347 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1348 {
1349         if (!p_hwfn || !p_hwfn->mcp_info)
1350                 return OSAL_NULL;
1351         return &p_hwfn->mcp_info->func_info;
1352 }
1353
1354 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1355                                            struct ecore_ptt *p_ptt,
1356                                            struct ecore_mcp_nvm_params *params)
1357 {
1358         enum _ecore_status_t rc;
1359
1360         switch (params->type) {
1361         case ECORE_MCP_NVM_RD:
1362                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1363                                           params->nvm_common.offset,
1364                                           &params->nvm_common.resp,
1365                                           &params->nvm_common.param,
1366                                           params->nvm_rd.buf_size,
1367                                           params->nvm_rd.buf);
1368                 break;
1369         case ECORE_MCP_CMD:
1370                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1371                                    params->nvm_common.offset,
1372                                    &params->nvm_common.resp,
1373                                    &params->nvm_common.param);
1374                 break;
1375         case ECORE_MCP_NVM_WR:
1376                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1377                                           params->nvm_common.offset,
1378                                           &params->nvm_common.resp,
1379                                           &params->nvm_common.param,
1380                                           params->nvm_wr.buf_size,
1381                                           params->nvm_wr.buf);
1382                 break;
1383         default:
1384                 rc = ECORE_NOTIMPL;
1385                 break;
1386         }
1387         return rc;
1388 }
1389
1390 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1391                                   struct ecore_ptt *p_ptt, u32 personalities)
1392 {
1393         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1394         struct public_func shmem_info;
1395         int i, count = 0, num_pfs;
1396
1397         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1398
1399         for (i = 0; i < num_pfs; i++) {
1400                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1401                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1402                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1403                         continue;
1404
1405                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1406                                               &protocol) != ECORE_SUCCESS)
1407                         continue;
1408
1409                 if ((1 << ((u32)protocol)) & personalities)
1410                         count++;
1411         }
1412
1413         return count;
1414 }
1415
1416 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1417                                               struct ecore_ptt *p_ptt,
1418                                               u32 *p_flash_size)
1419 {
1420         u32 flash_size;
1421
1422 #ifndef ASIC_ONLY
1423         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1424                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1425                 return ECORE_INVAL;
1426         }
1427 #endif
1428
1429         if (IS_VF(p_hwfn->p_dev))
1430                 return ECORE_INVAL;
1431
1432         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1433         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1434             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1435         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1436
1437         *p_flash_size = flash_size;
1438
1439         return ECORE_SUCCESS;
1440 }
1441
1442 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1443                                                   struct ecore_ptt *p_ptt)
1444 {
1445         struct ecore_dev *p_dev = p_hwfn->p_dev;
1446
1447         if (p_dev->recov_in_prog) {
1448                 DP_NOTICE(p_hwfn, false,
1449                           "Avoid triggering a recovery since such a process"
1450                           " is already in progress\n");
1451                 return ECORE_AGAIN;
1452         }
1453
1454         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1455         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1456
1457         return ECORE_SUCCESS;
1458 }
1459
1460 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1461                                               struct ecore_ptt *p_ptt,
1462                                               u8 vf_id, u8 num)
1463 {
1464         u32 resp = 0, param = 0, rc_param = 0;
1465         enum _ecore_status_t rc;
1466
1467         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1468             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1469         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1470             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1471
1472         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1473                            &resp, &rc_param);
1474
1475         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1476                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1477                           vf_id);
1478                 rc = ECORE_INVAL;
1479         }
1480
1481         return rc;
1482 }
1483
1484 enum _ecore_status_t
1485 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1486                            struct ecore_mcp_drv_version *p_ver)
1487 {
1488         u32 param = 0, reply = 0, num_words, i;
1489         struct drv_version_stc *p_drv_version;
1490         struct ecore_mcp_mb_params mb_params;
1491         union drv_union_data union_data;
1492         void *p_name;
1493         OSAL_BE32 val;
1494         enum _ecore_status_t rc;
1495
1496 #ifndef ASIC_ONLY
1497         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1498                 return ECORE_SUCCESS;
1499 #endif
1500
1501         p_drv_version = &union_data.drv_version;
1502         p_drv_version->version = p_ver->version;
1503         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1504         for (i = 0; i < num_words; i++) {
1505                 p_name = &p_ver->name[i * sizeof(u32)];
1506                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1507                 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1508         }
1509
1510         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1511         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1512         mb_params.p_data_src = &union_data;
1513         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1514         if (rc != ECORE_SUCCESS)
1515                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1516
1517         return rc;
1518 }
1519
1520 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1521                                     struct ecore_ptt *p_ptt)
1522 {
1523         enum _ecore_status_t rc;
1524         u32 resp = 0, param = 0;
1525
1526         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1527                            &param);
1528         if (rc != ECORE_SUCCESS)
1529                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1530
1531         return rc;
1532 }
1533
1534 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1535                                       struct ecore_ptt *p_ptt)
1536 {
1537         u32 value, cpu_mode;
1538
1539         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1540
1541         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1542         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1543         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1544         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1545
1546         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1547 }
1548
1549 enum _ecore_status_t
1550 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1551                                    struct ecore_ptt *p_ptt,
1552                                    enum ecore_ov_config_method config,
1553                                    enum ecore_ov_client client)
1554 {
1555         enum _ecore_status_t rc;
1556         u32 resp = 0, param = 0;
1557         u32 drv_mb_param;
1558
1559         switch (config) {
1560         case ECORE_OV_CLIENT_DRV:
1561                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1562                 break;
1563         case ECORE_OV_CLIENT_USER:
1564                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1565                 break;
1566         default:
1567                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", config);
1568                 return ECORE_INVAL;
1569         }
1570
1571         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1572                            drv_mb_param, &resp, &param);
1573         if (rc != ECORE_SUCCESS)
1574                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1575
1576         return rc;
1577 }
1578
1579 enum _ecore_status_t
1580 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1581                                  struct ecore_ptt *p_ptt,
1582                                  enum ecore_ov_driver_state drv_state)
1583 {
1584         enum _ecore_status_t rc;
1585         u32 resp = 0, param = 0;
1586         u32 drv_mb_param;
1587
1588         switch (drv_state) {
1589         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1590                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1591                 break;
1592         case ECORE_OV_DRIVER_STATE_DISABLED:
1593                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1594                 break;
1595         case ECORE_OV_DRIVER_STATE_ACTIVE:
1596                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1597                 break;
1598         default:
1599                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1600                 return ECORE_INVAL;
1601         }
1602
1603         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1604                            drv_state, &resp, &param);
1605         if (rc != ECORE_SUCCESS)
1606                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1607
1608         return rc;
1609 }
1610
1611 enum _ecore_status_t
1612 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1613                          struct ecore_fc_npiv_tbl *p_table)
1614 {
1615         return 0;
1616 }
1617
1618 enum _ecore_status_t
1619 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1620                         struct ecore_ptt *p_ptt, u16 mtu)
1621 {
1622         return 0;
1623 }
1624
1625 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1626                                        struct ecore_ptt *p_ptt,
1627                                        enum ecore_led_mode mode)
1628 {
1629         u32 resp = 0, param = 0, drv_mb_param;
1630         enum _ecore_status_t rc;
1631
1632         switch (mode) {
1633         case ECORE_LED_MODE_ON:
1634                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1635                 break;
1636         case ECORE_LED_MODE_OFF:
1637                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1638                 break;
1639         case ECORE_LED_MODE_RESTORE:
1640                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1641                 break;
1642         default:
1643                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1644                 return ECORE_INVAL;
1645         }
1646
1647         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1648                            drv_mb_param, &resp, &param);
1649         if (rc != ECORE_SUCCESS)
1650                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1651
1652         return rc;
1653 }
1654
1655 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1656                                              struct ecore_ptt *p_ptt,
1657                                              u32 mask_parities)
1658 {
1659         enum _ecore_status_t rc;
1660         u32 resp = 0, param = 0;
1661
1662         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1663                            mask_parities, &resp, &param);
1664
1665         if (rc != ECORE_SUCCESS) {
1666                 DP_ERR(p_hwfn,
1667                        "MCP response failure for mask parities, aborting\n");
1668         } else if (resp != FW_MSG_CODE_OK) {
1669                 DP_ERR(p_hwfn,
1670                        "MCP did not ack mask parity request. Old MFW?\n");
1671                 rc = ECORE_INVAL;
1672         }
1673
1674         return rc;
1675 }
1676
1677 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1678                                         u8 *p_buf, u32 len)
1679 {
1680         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1681         u32 bytes_left, offset, bytes_to_copy, buf_size;
1682         struct ecore_mcp_nvm_params params;
1683         struct ecore_ptt *p_ptt;
1684         enum _ecore_status_t rc = ECORE_SUCCESS;
1685
1686         p_ptt = ecore_ptt_acquire(p_hwfn);
1687         if (!p_ptt)
1688                 return ECORE_BUSY;
1689
1690         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1691         bytes_left = len;
1692         offset = 0;
1693         params.type = ECORE_MCP_NVM_RD;
1694         params.nvm_rd.buf_size = &buf_size;
1695         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1696         while (bytes_left > 0) {
1697                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1698                                            MCP_DRV_NVM_BUF_LEN);
1699                 params.nvm_common.offset = (addr + offset) |
1700                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1701                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1702                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1703                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1704                                             FW_MSG_CODE_NVM_OK)) {
1705                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1706                         break;
1707                 }
1708                 offset += *params.nvm_rd.buf_size;
1709                 bytes_left -= *params.nvm_rd.buf_size;
1710         }
1711
1712         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1713         ecore_ptt_release(p_hwfn, p_ptt);
1714
1715         return rc;
1716 }
1717
1718 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1719                                         u32 addr, u8 *p_buf, u32 len)
1720 {
1721         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1722         struct ecore_mcp_nvm_params params;
1723         struct ecore_ptt *p_ptt;
1724         enum _ecore_status_t rc;
1725
1726         p_ptt = ecore_ptt_acquire(p_hwfn);
1727         if (!p_ptt)
1728                 return ECORE_BUSY;
1729
1730         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1731         params.type = ECORE_MCP_NVM_RD;
1732         params.nvm_rd.buf_size = &len;
1733         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1734             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1735         params.nvm_common.offset = addr;
1736         params.nvm_rd.buf = (u32 *)p_buf;
1737         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1738         if (rc != ECORE_SUCCESS)
1739                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1740
1741         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1742         ecore_ptt_release(p_hwfn, p_ptt);
1743
1744         return rc;
1745 }
1746
1747 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1748 {
1749         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1750         struct ecore_mcp_nvm_params params;
1751         struct ecore_ptt *p_ptt;
1752
1753         p_ptt = ecore_ptt_acquire(p_hwfn);
1754         if (!p_ptt)
1755                 return ECORE_BUSY;
1756
1757         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1758         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1759         ecore_ptt_release(p_hwfn, p_ptt);
1760
1761         return ECORE_SUCCESS;
1762 }
1763
1764 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1765 {
1766         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1767         struct ecore_mcp_nvm_params params;
1768         struct ecore_ptt *p_ptt;
1769         enum _ecore_status_t rc;
1770
1771         p_ptt = ecore_ptt_acquire(p_hwfn);
1772         if (!p_ptt)
1773                 return ECORE_BUSY;
1774         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1775         params.type = ECORE_MCP_CMD;
1776         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1777         params.nvm_common.offset = addr;
1778         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1779         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1780         ecore_ptt_release(p_hwfn, p_ptt);
1781
1782         return rc;
1783 }
1784
1785 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1786                                                   u32 addr)
1787 {
1788         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1789         struct ecore_mcp_nvm_params params;
1790         struct ecore_ptt *p_ptt;
1791         enum _ecore_status_t rc;
1792
1793         p_ptt = ecore_ptt_acquire(p_hwfn);
1794         if (!p_ptt)
1795                 return ECORE_BUSY;
1796         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1797         params.type = ECORE_MCP_CMD;
1798         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1799         params.nvm_common.offset = addr;
1800         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1801         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1802         ecore_ptt_release(p_hwfn, p_ptt);
1803
1804         return rc;
1805 }
1806
1807 /* rc receives ECORE_INVAL as default parameter because
1808  * it might not enter the while loop if the len is 0
1809  */
1810 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1811                                          u32 addr, u8 *p_buf, u32 len)
1812 {
1813         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1814         enum _ecore_status_t rc = ECORE_INVAL;
1815         struct ecore_mcp_nvm_params params;
1816         struct ecore_ptt *p_ptt;
1817         u32 buf_idx, buf_size;
1818
1819         p_ptt = ecore_ptt_acquire(p_hwfn);
1820         if (!p_ptt)
1821                 return ECORE_BUSY;
1822
1823         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1824         params.type = ECORE_MCP_NVM_WR;
1825         if (cmd == ECORE_PUT_FILE_DATA)
1826                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
1827         else
1828                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
1829         buf_idx = 0;
1830         while (buf_idx < len) {
1831                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
1832                                       MCP_DRV_NVM_BUF_LEN);
1833                 params.nvm_common.offset = ((buf_size <<
1834                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
1835                                             | addr) + buf_idx;
1836                 params.nvm_wr.buf_size = buf_size;
1837                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
1838                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1839                 if (rc != ECORE_SUCCESS ||
1840                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
1841                      (params.nvm_common.resp !=
1842                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
1843                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1844
1845                 buf_idx += buf_size;
1846         }
1847
1848         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1849         ecore_ptt_release(p_hwfn, p_ptt);
1850
1851         return rc;
1852 }
1853
1854 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
1855                                          u32 addr, u8 *p_buf, u32 len)
1856 {
1857         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1858         struct ecore_mcp_nvm_params params;
1859         struct ecore_ptt *p_ptt;
1860         enum _ecore_status_t rc;
1861
1862         p_ptt = ecore_ptt_acquire(p_hwfn);
1863         if (!p_ptt)
1864                 return ECORE_BUSY;
1865
1866         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1867         params.type = ECORE_MCP_NVM_WR;
1868         params.nvm_wr.buf_size = len;
1869         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
1870             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
1871         params.nvm_common.offset = addr;
1872         params.nvm_wr.buf = (u32 *)p_buf;
1873         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1874         if (rc != ECORE_SUCCESS)
1875                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1876         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1877         ecore_ptt_release(p_hwfn, p_ptt);
1878
1879         return rc;
1880 }
1881
1882 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
1883                                                    u32 addr)
1884 {
1885         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1886         struct ecore_mcp_nvm_params params;
1887         struct ecore_ptt *p_ptt;
1888         enum _ecore_status_t rc;
1889
1890         p_ptt = ecore_ptt_acquire(p_hwfn);
1891         if (!p_ptt)
1892                 return ECORE_BUSY;
1893
1894         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1895         params.type = ECORE_MCP_CMD;
1896         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
1897         params.nvm_common.offset = addr;
1898         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1899         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1900         ecore_ptt_release(p_hwfn, p_ptt);
1901
1902         return rc;
1903 }
1904
1905 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
1906                                             struct ecore_ptt *p_ptt,
1907                                             u32 port, u32 addr, u32 offset,
1908                                             u32 len, u8 *p_buf)
1909 {
1910         struct ecore_mcp_nvm_params params;
1911         enum _ecore_status_t rc;
1912         u32 bytes_left, bytes_to_copy, buf_size;
1913
1914         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1915         SET_FIELD(params.nvm_common.offset,
1916                   DRV_MB_PARAM_TRANSCEIVER_PORT, port);
1917         SET_FIELD(params.nvm_common.offset,
1918                   DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS, addr);
1919         addr = offset;
1920         offset = 0;
1921         bytes_left = len;
1922         params.type = ECORE_MCP_NVM_RD;
1923         params.nvm_rd.buf_size = &buf_size;
1924         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
1925         while (bytes_left > 0) {
1926                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1927                                            MAX_I2C_TRANSACTION_SIZE);
1928                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1929                 SET_FIELD(params.nvm_common.offset,
1930                           DRV_MB_PARAM_TRANSCEIVER_OFFSET, addr + offset);
1931                 SET_FIELD(params.nvm_common.offset,
1932                           DRV_MB_PARAM_TRANSCEIVER_SIZE, bytes_to_copy);
1933                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1934                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
1935                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
1936                         return ECORE_NODEV;
1937                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
1938                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
1939                         return ECORE_UNKNOWN_ERROR;
1940
1941                 offset += *params.nvm_rd.buf_size;
1942                 bytes_left -= *params.nvm_rd.buf_size;
1943         }
1944
1945         return ECORE_SUCCESS;
1946 }
1947
1948 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
1949                                              struct ecore_ptt *p_ptt,
1950                                              u32 port, u32 addr, u32 offset,
1951                                              u32 len, u8 *p_buf)
1952 {
1953         struct ecore_mcp_nvm_params params;
1954         enum _ecore_status_t rc;
1955         u32 buf_idx, buf_size;
1956
1957         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1958         SET_FIELD(params.nvm_common.offset,
1959                   DRV_MB_PARAM_TRANSCEIVER_PORT, port);
1960         SET_FIELD(params.nvm_common.offset,
1961                   DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS, addr);
1962         params.type = ECORE_MCP_NVM_WR;
1963         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
1964         buf_idx = 0;
1965         while (buf_idx < len) {
1966                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
1967                                       MAX_I2C_TRANSACTION_SIZE);
1968                 SET_FIELD(params.nvm_common.offset,
1969                           DRV_MB_PARAM_TRANSCEIVER_OFFSET, offset + buf_idx);
1970                 SET_FIELD(params.nvm_common.offset,
1971                           DRV_MB_PARAM_TRANSCEIVER_SIZE, buf_size);
1972                 params.nvm_wr.buf_size = buf_size;
1973                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
1974                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1975                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
1976                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
1977                         return ECORE_NODEV;
1978                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
1979                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
1980                         return ECORE_UNKNOWN_ERROR;
1981
1982                 buf_idx += buf_size;
1983         }
1984
1985         return ECORE_SUCCESS;
1986 }
1987
1988 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
1989                                          struct ecore_ptt *p_ptt,
1990                                          u16 gpio, u32 *gpio_val)
1991 {
1992         enum _ecore_status_t rc = ECORE_SUCCESS;
1993         u32 drv_mb_param = 0, rsp;
1994
1995         SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_NUMBER, gpio);
1996
1997         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
1998                            drv_mb_param, &rsp, gpio_val);
1999
2000         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2001                 return ECORE_UNKNOWN_ERROR;
2002
2003         return ECORE_SUCCESS;
2004 }
2005
2006 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2007                                           struct ecore_ptt *p_ptt,
2008                                           u16 gpio, u16 gpio_val)
2009 {
2010         enum _ecore_status_t rc = ECORE_SUCCESS;
2011         u32 drv_mb_param = 0, param, rsp;
2012
2013         SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_NUMBER, gpio);
2014         SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_VALUE, gpio_val);
2015
2016         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2017                            drv_mb_param, &rsp, &param);
2018
2019         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2020                 return ECORE_UNKNOWN_ERROR;
2021
2022         return ECORE_SUCCESS;
2023 }