2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
23 #include "ecore_sp_commands.h"
25 #define CHIP_MCP_RESP_ITER_US 10
26 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
28 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
29 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
31 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
32 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
35 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
36 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
38 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
39 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
40 OFFSETOF(struct public_drv_mb, _field), _val)
42 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
43 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
44 OFFSETOF(struct public_drv_mb, _field))
46 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
47 DRV_ID_PDA_COMP_VER_OFFSET)
49 #define MCP_BYTES_PER_MBIT_OFFSET 17
53 static int loaded_port[MAX_NUM_PORTS] = { 0 };
56 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
58 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
63 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
65 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
67 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
69 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
71 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
72 "port_addr = 0x%x, port_id 0x%02x\n",
73 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
76 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
78 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
83 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
87 if (!p_hwfn->mcp_info->public_base)
90 for (i = 0; i < length; i++) {
91 tmp = ecore_rd(p_hwfn, p_ptt,
92 p_hwfn->mcp_info->mfw_mb_addr +
93 (i << 2) + sizeof(u32));
95 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
96 OSAL_BE32_TO_CPU(tmp);
100 struct ecore_mcp_cmd_elem {
101 osal_list_entry_t list;
102 struct ecore_mcp_mb_params *p_mb_params;
103 u16 expected_seq_num;
107 /* Must be called while cmd_lock is acquired */
108 static struct ecore_mcp_cmd_elem *
109 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
110 struct ecore_mcp_mb_params *p_mb_params,
111 u16 expected_seq_num)
113 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
115 p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
116 sizeof(*p_cmd_elem));
118 DP_NOTICE(p_hwfn, false,
119 "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
123 p_cmd_elem->p_mb_params = p_mb_params;
124 p_cmd_elem->expected_seq_num = expected_seq_num;
125 OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
130 /* Must be called while cmd_lock is acquired */
131 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
132 struct ecore_mcp_cmd_elem *p_cmd_elem)
134 OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
135 OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
138 /* Must be called while cmd_lock is acquired */
139 static struct ecore_mcp_cmd_elem *
140 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
142 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
144 OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
145 struct ecore_mcp_cmd_elem) {
146 if (p_cmd_elem->expected_seq_num == seq_num)
153 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
155 if (p_hwfn->mcp_info) {
156 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
158 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
159 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
160 &p_hwfn->mcp_info->cmd_list, list,
161 struct ecore_mcp_cmd_elem) {
162 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
164 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
166 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
167 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
168 #ifdef CONFIG_ECORE_LOCK_ALLOC
169 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
170 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
174 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
176 return ECORE_SUCCESS;
179 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
180 struct ecore_ptt *p_ptt)
182 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
183 u32 drv_mb_offsize, mfw_mb_offsize;
184 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
187 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
188 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
189 p_info->public_base = 0;
194 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
195 if (!p_info->public_base)
198 p_info->public_base |= GRCBASE_MCP;
200 /* Calculate the driver and MFW mailbox address */
201 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
202 SECTION_OFFSIZE_ADDR(p_info->public_base,
204 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
205 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
206 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
207 " mcp_pf_id = 0x%x\n",
208 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
210 /* Set the MFW MB address */
211 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
212 SECTION_OFFSIZE_ADDR(p_info->public_base,
214 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
215 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
216 p_info->mfw_mb_addr);
218 /* Get the current driver mailbox sequence before sending
221 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
222 DRV_MSG_SEQ_NUMBER_MASK;
224 /* Get current FW pulse sequence */
225 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
228 p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
230 return ECORE_SUCCESS;
233 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
234 struct ecore_ptt *p_ptt)
236 struct ecore_mcp_info *p_info;
239 /* Allocate mcp_info structure */
240 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
241 sizeof(*p_hwfn->mcp_info));
242 if (!p_hwfn->mcp_info)
244 p_info = p_hwfn->mcp_info;
246 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
247 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
248 /* Do not free mcp_info here, since public_base indicate that
249 * the MCP is not initialized
251 return ECORE_SUCCESS;
254 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
255 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
256 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
257 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
260 /* Initialize the MFW spinlocks */
261 #ifdef CONFIG_ECORE_LOCK_ALLOC
262 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
263 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
265 OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
266 OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
268 OSAL_LIST_INIT(&p_info->cmd_list);
270 return ECORE_SUCCESS;
273 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
274 ecore_mcp_free(p_hwfn);
278 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
279 struct ecore_ptt *p_ptt)
281 u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
283 /* Use MCP history register to check if MCP reset occurred between init
286 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
287 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
288 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
289 p_hwfn->mcp_info->mcp_hist, generic_por_0);
291 ecore_load_mcp_offsets(p_hwfn, p_ptt);
292 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
296 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
297 struct ecore_ptt *p_ptt)
299 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
300 enum _ecore_status_t rc = ECORE_SUCCESS;
303 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
304 delay = EMUL_MCP_RESP_ITER_US;
307 /* Ensure that only a single thread is accessing the mailbox */
308 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
310 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
312 /* Set drv command along with the updated sequence */
313 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
314 seq = ++p_hwfn->mcp_info->drv_mb_seq;
315 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
318 /* Wait for MFW response */
320 /* Give the FW up to 500 second (50*1000*10usec) */
321 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
322 MISCS_REG_GENERIC_POR_0)) &&
323 (cnt++ < ECORE_MCP_RESET_RETRIES));
325 if (org_mcp_reset_seq !=
326 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
327 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
328 "MCP was reset after %d usec\n", cnt * delay);
330 DP_ERR(p_hwfn, "Failed to reset MCP\n");
334 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
339 /* Must be called while cmd_lock is acquired */
340 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
342 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
344 /* There is at most one pending command at a certain time, and if it
345 * exists - it is placed at the HEAD of the list.
347 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
348 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
349 struct ecore_mcp_cmd_elem,
351 return !p_cmd_elem->b_is_completed;
357 /* Must be called while cmd_lock is acquired */
358 static enum _ecore_status_t
359 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
361 struct ecore_mcp_mb_params *p_mb_params;
362 struct ecore_mcp_cmd_elem *p_cmd_elem;
366 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
367 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
369 /* Return if no new non-handled response has been received */
370 if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
373 p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
376 "Failed to find a pending mailbox cmd that expects sequence number %d\n",
378 return ECORE_UNKNOWN_ERROR;
381 p_mb_params = p_cmd_elem->p_mb_params;
383 /* Get the MFW response along with the sequence number */
384 p_mb_params->mcp_resp = mcp_resp;
386 /* Get the MFW param */
387 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
389 /* Get the union data */
390 if (p_mb_params->p_data_dst != OSAL_NULL &&
391 p_mb_params->data_dst_size) {
392 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
393 OFFSETOF(struct public_drv_mb,
395 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
396 union_data_addr, p_mb_params->data_dst_size);
399 p_cmd_elem->b_is_completed = true;
401 return ECORE_SUCCESS;
404 /* Must be called while cmd_lock is acquired */
405 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
406 struct ecore_ptt *p_ptt,
407 struct ecore_mcp_mb_params *p_mb_params,
410 union drv_union_data union_data;
413 /* Set the union data */
414 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
415 OFFSETOF(struct public_drv_mb, union_data);
416 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
417 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
418 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
419 p_mb_params->data_src_size);
420 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
423 /* Set the drv param */
424 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
426 /* Set the drv command along with the sequence number */
427 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
429 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
430 "MFW mailbox: command 0x%08x param 0x%08x\n",
431 (p_mb_params->cmd | seq_num), p_mb_params->param);
434 static enum _ecore_status_t
435 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
436 struct ecore_mcp_mb_params *p_mb_params,
437 u32 max_retries, u32 delay)
439 struct ecore_mcp_cmd_elem *p_cmd_elem;
442 enum _ecore_status_t rc = ECORE_SUCCESS;
444 /* Wait until the mailbox is non-occupied */
446 /* Exit the loop if there is no pending command, or if the
447 * pending command is completed during this iteration.
448 * The spinlock stays locked until the command is sent.
451 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
453 if (!ecore_mcp_has_pending_cmd(p_hwfn))
456 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
457 if (rc == ECORE_SUCCESS)
459 else if (rc != ECORE_AGAIN)
462 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
464 } while (++cnt < max_retries);
466 if (cnt >= max_retries) {
467 DP_NOTICE(p_hwfn, false,
468 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
469 p_mb_params->cmd, p_mb_params->param);
473 /* Send the mailbox command */
474 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
475 seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
476 p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
482 __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
483 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
485 /* Wait for the MFW response */
487 /* Exit the loop if the command is already completed, or if the
488 * command is completed during this iteration.
489 * The spinlock stays locked until the list element is removed.
493 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
495 if (p_cmd_elem->b_is_completed)
498 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
499 if (rc == ECORE_SUCCESS)
501 else if (rc != ECORE_AGAIN)
504 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
505 } while (++cnt < max_retries);
507 if (cnt >= max_retries) {
508 DP_NOTICE(p_hwfn, false,
509 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
510 p_mb_params->cmd, p_mb_params->param);
512 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
513 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
514 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
516 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
520 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
521 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
523 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
524 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
525 p_mb_params->mcp_resp, p_mb_params->mcp_param,
526 (cnt * delay) / 1000, (cnt * delay) % 1000);
528 /* Clear the sequence number from the MFW response */
529 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
531 return ECORE_SUCCESS;
534 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
538 static enum _ecore_status_t
539 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
540 struct ecore_ptt *p_ptt,
541 struct ecore_mcp_mb_params *p_mb_params)
543 osal_size_t union_data_size = sizeof(union drv_union_data);
544 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
545 u32 delay = CHIP_MCP_RESP_ITER_US;
548 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
549 delay = EMUL_MCP_RESP_ITER_US;
550 /* There is a built-in delay of 100usec in each MFW response read */
551 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
555 /* MCP not initialized */
556 if (!ecore_mcp_is_init(p_hwfn)) {
557 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
561 if (p_mb_params->data_src_size > union_data_size ||
562 p_mb_params->data_dst_size > union_data_size) {
564 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
565 p_mb_params->data_src_size, p_mb_params->data_dst_size,
570 return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
574 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
575 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
576 u32 *o_mcp_resp, u32 *o_mcp_param)
578 struct ecore_mcp_mb_params mb_params;
579 enum _ecore_status_t rc;
582 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
583 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
585 loaded_port[p_hwfn->port_id]--;
586 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
589 return ECORE_SUCCESS;
593 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
595 mb_params.param = param;
596 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
597 if (rc != ECORE_SUCCESS)
600 *o_mcp_resp = mb_params.mcp_resp;
601 *o_mcp_param = mb_params.mcp_param;
603 return ECORE_SUCCESS;
606 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
607 struct ecore_ptt *p_ptt,
612 u32 i_txn_size, u32 *i_buf)
614 struct ecore_mcp_mb_params mb_params;
615 enum _ecore_status_t rc;
617 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
619 mb_params.param = param;
620 mb_params.p_data_src = i_buf;
621 mb_params.data_src_size = (u8)i_txn_size;
622 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
623 if (rc != ECORE_SUCCESS)
626 *o_mcp_resp = mb_params.mcp_resp;
627 *o_mcp_param = mb_params.mcp_param;
629 return ECORE_SUCCESS;
632 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
633 struct ecore_ptt *p_ptt,
638 u32 *o_txn_size, u32 *o_buf)
640 struct ecore_mcp_mb_params mb_params;
641 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
642 enum _ecore_status_t rc;
644 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
646 mb_params.param = param;
647 mb_params.p_data_dst = raw_data;
649 /* Use the maximal value since the actual one is part of the response */
650 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
652 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
653 if (rc != ECORE_SUCCESS)
656 *o_mcp_resp = mb_params.mcp_resp;
657 *o_mcp_param = mb_params.mcp_param;
659 *o_txn_size = *o_mcp_param;
661 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
663 return ECORE_SUCCESS;
667 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
670 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
673 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
674 else if (!loaded_port[p_hwfn->port_id])
675 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
677 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
679 /* On CMT, always tell that it's engine */
680 if (p_hwfn->p_dev->num_hwfns > 1)
681 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
683 *p_load_code = load_phase;
685 loaded_port[p_hwfn->port_id]++;
687 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
688 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
689 *p_load_code, loaded, p_hwfn->port_id,
690 loaded_port[p_hwfn->port_id]);
695 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
696 enum ecore_override_force_load override_force_load)
698 bool can_force_load = false;
700 switch (override_force_load) {
701 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
702 can_force_load = true;
704 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
705 can_force_load = false;
708 can_force_load = (drv_role == DRV_ROLE_OS &&
709 exist_drv_role == DRV_ROLE_PREBOOT) ||
710 (drv_role == DRV_ROLE_KDUMP &&
711 exist_drv_role == DRV_ROLE_OS);
715 return can_force_load;
718 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
719 struct ecore_ptt *p_ptt)
721 u32 resp = 0, param = 0;
722 enum _ecore_status_t rc;
724 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
726 if (rc != ECORE_SUCCESS)
727 DP_NOTICE(p_hwfn, false,
728 "Failed to send cancel load request, rc = %d\n", rc);
733 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
734 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
735 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
736 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
737 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
738 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
739 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
741 static u32 ecore_get_config_bitmap(void)
743 u32 config_bitmap = 0x0;
745 #ifdef CONFIG_ECORE_L2
746 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
748 #ifdef CONFIG_ECORE_SRIOV
749 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
751 #ifdef CONFIG_ECORE_ROCE
752 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
754 #ifdef CONFIG_ECORE_IWARP
755 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
757 #ifdef CONFIG_ECORE_FCOE
758 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
760 #ifdef CONFIG_ECORE_ISCSI
761 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
763 #ifdef CONFIG_ECORE_LL2
764 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
767 return config_bitmap;
770 struct ecore_load_req_in_params {
772 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
773 #define ECORE_LOAD_REQ_HSI_VER_1 1
780 bool avoid_eng_reset;
783 struct ecore_load_req_out_params {
793 static enum _ecore_status_t
794 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
795 struct ecore_load_req_in_params *p_in_params,
796 struct ecore_load_req_out_params *p_out_params)
798 struct ecore_mcp_mb_params mb_params;
799 struct load_req_stc load_req;
800 struct load_rsp_stc load_rsp;
802 enum _ecore_status_t rc;
804 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
805 load_req.drv_ver_0 = p_in_params->drv_ver_0;
806 load_req.drv_ver_1 = p_in_params->drv_ver_1;
807 load_req.fw_ver = p_in_params->fw_ver;
808 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
809 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
810 p_in_params->timeout_val);
811 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
812 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
813 p_in_params->avoid_eng_reset);
815 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
816 DRV_ID_MCP_HSI_VER_CURRENT :
817 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
819 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
820 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
821 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
822 mb_params.p_data_src = &load_req;
823 mb_params.data_src_size = sizeof(load_req);
824 mb_params.p_data_dst = &load_rsp;
825 mb_params.data_dst_size = sizeof(load_rsp);
827 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
828 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
830 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
831 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
832 GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
833 GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
835 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
836 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
837 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
838 load_req.drv_ver_0, load_req.drv_ver_1,
839 load_req.fw_ver, load_req.misc0,
840 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
841 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
842 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
843 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
845 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
846 if (rc != ECORE_SUCCESS) {
847 DP_NOTICE(p_hwfn, false,
848 "Failed to send load request, rc = %d\n", rc);
852 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
853 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
854 p_out_params->load_code = mb_params.mcp_resp;
856 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
857 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
858 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
859 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
860 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
861 load_rsp.fw_ver, load_rsp.misc0,
862 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
863 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
864 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
866 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
867 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
868 p_out_params->exist_fw_ver = load_rsp.fw_ver;
869 p_out_params->exist_drv_role =
870 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
871 p_out_params->mfw_hsi_ver =
872 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
873 p_out_params->drv_exists =
874 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
875 LOAD_RSP_FLAGS0_DRV_EXISTS;
878 return ECORE_SUCCESS;
881 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
882 enum ecore_drv_role drv_role,
886 case ECORE_DRV_ROLE_OS:
887 *p_mfw_drv_role = DRV_ROLE_OS;
889 case ECORE_DRV_ROLE_KDUMP:
890 *p_mfw_drv_role = DRV_ROLE_KDUMP;
895 enum ecore_load_req_force {
896 ECORE_LOAD_REQ_FORCE_NONE,
897 ECORE_LOAD_REQ_FORCE_PF,
898 ECORE_LOAD_REQ_FORCE_ALL,
901 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
902 enum ecore_load_req_force force_cmd,
906 case ECORE_LOAD_REQ_FORCE_NONE:
907 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
909 case ECORE_LOAD_REQ_FORCE_PF:
910 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
912 case ECORE_LOAD_REQ_FORCE_ALL:
913 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
918 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
919 struct ecore_ptt *p_ptt,
920 struct ecore_load_req_params *p_params)
922 struct ecore_load_req_out_params out_params;
923 struct ecore_load_req_in_params in_params;
924 u8 mfw_drv_role = 0, mfw_force_cmd;
925 enum _ecore_status_t rc;
928 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
929 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
930 return ECORE_SUCCESS;
934 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
935 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
936 in_params.drv_ver_0 = ECORE_VERSION;
937 in_params.drv_ver_1 = ecore_get_config_bitmap();
938 in_params.fw_ver = STORM_FW_VERSION;
939 ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
940 in_params.drv_role = mfw_drv_role;
941 in_params.timeout_val = p_params->timeout_val;
942 ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
944 in_params.force_cmd = mfw_force_cmd;
945 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
947 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
948 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
949 if (rc != ECORE_SUCCESS)
952 /* First handle cases where another load request should/might be sent:
953 * - MFW expects the old interface [HSI version = 1]
954 * - MFW responds that a force load request is required
956 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
958 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
960 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
961 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
962 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
964 if (rc != ECORE_SUCCESS)
966 } else if (out_params.load_code ==
967 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
968 if (ecore_mcp_can_force_load(in_params.drv_role,
969 out_params.exist_drv_role,
970 p_params->override_force_load)) {
972 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
973 in_params.drv_role, in_params.fw_ver,
974 in_params.drv_ver_0, in_params.drv_ver_1,
975 out_params.exist_drv_role,
976 out_params.exist_fw_ver,
977 out_params.exist_drv_ver_0,
978 out_params.exist_drv_ver_1);
980 ecore_get_mfw_force_cmd(p_hwfn,
981 ECORE_LOAD_REQ_FORCE_ALL,
984 in_params.force_cmd = mfw_force_cmd;
985 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
986 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
988 if (rc != ECORE_SUCCESS)
991 DP_NOTICE(p_hwfn, false,
992 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
993 in_params.drv_role, in_params.fw_ver,
994 in_params.drv_ver_0, in_params.drv_ver_1,
995 out_params.exist_drv_role,
996 out_params.exist_fw_ver,
997 out_params.exist_drv_ver_0,
998 out_params.exist_drv_ver_1);
1000 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1005 /* Now handle the other types of responses.
1006 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1007 * expected here after the additional revised load requests were sent.
1009 switch (out_params.load_code) {
1010 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1011 case FW_MSG_CODE_DRV_LOAD_PORT:
1012 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1013 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1014 out_params.drv_exists) {
1015 /* The role and fw/driver version match, but the PF is
1016 * already loaded and has not been unloaded gracefully.
1017 * This is unexpected since a quasi-FLR request was
1018 * previously sent as part of ecore_hw_prepare().
1020 DP_NOTICE(p_hwfn, false,
1021 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1026 DP_NOTICE(p_hwfn, false,
1027 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1028 out_params.load_code);
1032 p_params->load_code = out_params.load_code;
1034 return ECORE_SUCCESS;
1037 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1038 struct ecore_ptt *p_ptt)
1040 u32 resp = 0, param = 0;
1041 enum _ecore_status_t rc;
1043 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1045 if (rc != ECORE_SUCCESS) {
1046 DP_NOTICE(p_hwfn, false,
1047 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1051 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
1053 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1054 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1055 DP_NOTICE(p_hwfn, false,
1056 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1058 return ECORE_SUCCESS;
1061 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1062 struct ecore_ptt *p_ptt)
1064 u32 wol_param, mcp_resp, mcp_param;
1067 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1069 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1070 &mcp_resp, &mcp_param);
1073 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1074 struct ecore_ptt *p_ptt)
1076 struct ecore_mcp_mb_params mb_params;
1077 struct mcp_mac wol_mac;
1079 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1080 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1082 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1085 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1086 struct ecore_ptt *p_ptt)
1088 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1090 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1091 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1092 ECORE_PATH_ID(p_hwfn));
1093 u32 disabled_vfs[VF_MAX_STATIC / 32];
1096 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1097 "Reading Disabled VF information from [offset %08x],"
1098 " path_addr %08x\n",
1099 mfw_path_offsize, path_addr);
1101 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1102 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1104 OFFSETOF(struct public_path,
1107 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1108 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1109 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1112 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1113 OSAL_VF_FLR_UPDATE(p_hwfn);
1116 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1117 struct ecore_ptt *p_ptt,
1120 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1122 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1123 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1125 struct ecore_mcp_mb_params mb_params;
1126 enum _ecore_status_t rc;
1129 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1130 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1131 "Acking VFs [%08x,...,%08x] - %08x\n",
1132 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1134 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1135 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1136 mb_params.p_data_src = vfs_to_ack;
1137 mb_params.data_src_size = VF_MAX_STATIC / 8;
1138 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1140 if (rc != ECORE_SUCCESS) {
1141 DP_NOTICE(p_hwfn, false,
1142 "Failed to pass ACK for VF flr to MFW\n");
1143 return ECORE_TIMEOUT;
1146 /* TMP - clear the ACK bits; should be done by MFW */
1147 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1148 ecore_wr(p_hwfn, p_ptt,
1150 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1151 i * sizeof(u32), 0);
1156 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1157 struct ecore_ptt *p_ptt)
1159 u32 transceiver_state;
1161 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1162 p_hwfn->mcp_info->port_addr +
1163 OFFSETOF(struct public_port,
1166 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1167 "Received transceiver state update [0x%08x] from mfw"
1169 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1170 OFFSETOF(struct public_port,
1171 transceiver_data)));
1173 transceiver_state = GET_MFW_FIELD(transceiver_state,
1174 ETH_TRANSCEIVER_STATE);
1176 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1177 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1179 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1182 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1183 struct ecore_ptt *p_ptt,
1184 struct ecore_mcp_link_state *p_link)
1186 u32 eee_status, val;
1188 p_link->eee_adv_caps = 0;
1189 p_link->eee_lp_adv_caps = 0;
1190 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1191 OFFSETOF(struct public_port, eee_status));
1192 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1193 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1194 if (val & EEE_1G_ADV)
1195 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1196 if (val & EEE_10G_ADV)
1197 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1198 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1199 if (val & EEE_1G_ADV)
1200 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1201 if (val & EEE_10G_ADV)
1202 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1205 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1206 struct ecore_ptt *p_ptt,
1209 struct ecore_mcp_link_state *p_link;
1213 /* Prevent SW/attentions from doing this at the same time */
1214 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1216 p_link = &p_hwfn->mcp_info->link_output;
1217 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1219 status = ecore_rd(p_hwfn, p_ptt,
1220 p_hwfn->mcp_info->port_addr +
1221 OFFSETOF(struct public_port, link_status));
1222 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1223 "Received link update [0x%08x] from mfw"
1225 status, (u32)(p_hwfn->mcp_info->port_addr +
1226 OFFSETOF(struct public_port,
1229 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1230 "Resetting link indications\n");
1234 if (p_hwfn->b_drv_link_init)
1235 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1237 p_link->link_up = false;
1239 p_link->full_duplex = true;
1240 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1241 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1242 p_link->speed = 100000;
1244 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1245 p_link->speed = 50000;
1247 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1248 p_link->speed = 40000;
1250 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1251 p_link->speed = 25000;
1253 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1254 p_link->speed = 20000;
1256 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1257 p_link->speed = 10000;
1259 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1260 p_link->full_duplex = false;
1262 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1263 p_link->speed = 1000;
1269 /* We never store total line speed as p_link->speed is
1270 * again changes according to bandwidth allocation.
1272 if (p_link->link_up && p_link->speed)
1273 p_link->line_speed = p_link->speed;
1275 p_link->line_speed = 0;
1277 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1278 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1280 /* Max bandwidth configuration */
1281 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1284 /* Mintz bandwidth configuration */
1285 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1287 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1288 p_link->min_pf_rate);
1290 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1291 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1292 p_link->parallel_detection = !!(status &
1293 LINK_STATUS_PARALLEL_DETECTION_USED);
1294 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1296 p_link->partner_adv_speed |=
1297 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1298 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1299 p_link->partner_adv_speed |=
1300 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1301 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1302 p_link->partner_adv_speed |=
1303 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1304 ECORE_LINK_PARTNER_SPEED_10G : 0;
1305 p_link->partner_adv_speed |=
1306 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1307 ECORE_LINK_PARTNER_SPEED_20G : 0;
1308 p_link->partner_adv_speed |=
1309 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1310 ECORE_LINK_PARTNER_SPEED_25G : 0;
1311 p_link->partner_adv_speed |=
1312 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1313 ECORE_LINK_PARTNER_SPEED_40G : 0;
1314 p_link->partner_adv_speed |=
1315 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1316 ECORE_LINK_PARTNER_SPEED_50G : 0;
1317 p_link->partner_adv_speed |=
1318 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1319 ECORE_LINK_PARTNER_SPEED_100G : 0;
1321 p_link->partner_tx_flow_ctrl_en =
1322 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1323 p_link->partner_rx_flow_ctrl_en =
1324 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1326 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1327 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1328 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1330 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1331 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1333 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1334 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1337 p_link->partner_adv_pause = 0;
1340 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1342 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1343 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1345 OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1347 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1350 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1351 struct ecore_ptt *p_ptt, bool b_up)
1353 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1354 struct ecore_mcp_mb_params mb_params;
1355 struct eth_phy_cfg phy_cfg;
1356 enum _ecore_status_t rc = ECORE_SUCCESS;
1360 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1361 return ECORE_SUCCESS;
1364 /* Set the shmem configuration according to params */
1365 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1366 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1367 if (!params->speed.autoneg)
1368 phy_cfg.speed = params->speed.forced_speed;
1369 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1370 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1371 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1372 phy_cfg.adv_speed = params->speed.advertised_speeds;
1373 phy_cfg.loopback_mode = params->loopback_mode;
1375 /* There are MFWs that share this capability regardless of whether
1376 * this is feasible or not. And given that at the very least adv_caps
1377 * would be set internally by ecore, we want to make sure LFA would
1380 if ((p_hwfn->mcp_info->capabilities &
1381 FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1382 params->eee.enable) {
1383 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1384 if (params->eee.tx_lpi_enable)
1385 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1386 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1387 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1388 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1389 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1390 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1391 EEE_TX_TIMER_USEC_OFFSET) &
1392 EEE_TX_TIMER_USEC_MASK;
1395 p_hwfn->b_drv_link_init = b_up;
1398 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1399 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1400 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1401 phy_cfg.loopback_mode);
1403 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1405 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1406 mb_params.cmd = cmd;
1407 mb_params.p_data_src = &phy_cfg;
1408 mb_params.data_src_size = sizeof(phy_cfg);
1409 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1411 /* if mcp fails to respond we must abort */
1412 if (rc != ECORE_SUCCESS) {
1413 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1417 /* Mimic link-change attention, done for several reasons:
1418 * - On reset, there's no guarantee MFW would trigger
1420 * - On initialization, older MFWs might not indicate link change
1421 * during LFA, so we'll never get an UP indication.
1423 ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1428 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1429 struct ecore_ptt *p_ptt)
1431 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1433 /* TODO - Add support for VFs */
1434 if (IS_VF(p_hwfn->p_dev))
1437 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1439 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1440 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1442 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1444 OFFSETOF(struct public_path, process_kill)) &
1445 PROCESS_KILL_COUNTER_MASK;
1447 return proc_kill_cnt;
1450 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1451 struct ecore_ptt *p_ptt)
1453 struct ecore_dev *p_dev = p_hwfn->p_dev;
1456 /* Prevent possible attentions/interrupts during the recovery handling
1457 * and till its load phase, during which they will be re-enabled.
1459 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1461 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1463 /* The following operations should be done once, and thus in CMT mode
1464 * are carried out by only the first HW function.
1466 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1469 if (p_dev->recov_in_prog) {
1470 DP_NOTICE(p_hwfn, false,
1471 "Ignoring the indication since a recovery"
1472 " process is already in progress\n");
1476 p_dev->recov_in_prog = true;
1478 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1479 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1481 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1484 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1485 struct ecore_ptt *p_ptt,
1486 enum MFW_DRV_MSG_TYPE type)
1488 enum ecore_mcp_protocol_type stats_type;
1489 union ecore_mcp_protocol_stats stats;
1490 struct ecore_mcp_mb_params mb_params;
1492 enum _ecore_status_t rc;
1495 case MFW_DRV_MSG_GET_LAN_STATS:
1496 stats_type = ECORE_MCP_LAN_STATS;
1497 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1500 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1504 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1506 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1507 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1508 mb_params.param = hsi_param;
1509 mb_params.p_data_src = &stats;
1510 mb_params.data_src_size = sizeof(stats);
1511 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1512 if (rc != ECORE_SUCCESS)
1513 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1516 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1517 struct public_func *p_shmem_info)
1519 struct ecore_mcp_function_info *p_info;
1521 p_info = &p_hwfn->mcp_info->func_info;
1523 /* TODO - bandwidth min/max should have valid values of 1-100,
1524 * as well as some indication that the feature is disabled.
1525 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1526 * limit and correct value to min `1' and max `100' if limit isn't in
1529 p_info->bandwidth_min = (p_shmem_info->config &
1530 FUNC_MF_CFG_MIN_BW_MASK) >>
1531 FUNC_MF_CFG_MIN_BW_OFFSET;
1532 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1534 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1535 p_info->bandwidth_min);
1536 p_info->bandwidth_min = 1;
1539 p_info->bandwidth_max = (p_shmem_info->config &
1540 FUNC_MF_CFG_MAX_BW_MASK) >>
1541 FUNC_MF_CFG_MAX_BW_OFFSET;
1542 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1544 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1545 p_info->bandwidth_max);
1546 p_info->bandwidth_max = 100;
1550 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1551 struct ecore_ptt *p_ptt,
1552 struct public_func *p_data,
1555 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1557 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1558 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1561 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1563 size = OSAL_MIN_T(u32, sizeof(*p_data),
1564 SECTION_SIZE(mfw_path_offsize));
1565 for (i = 0; i < size / sizeof(u32); i++)
1566 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1567 func_addr + (i << 2));
1573 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1575 struct ecore_mcp_function_info *p_info;
1576 struct public_func shmem_info;
1577 u32 resp = 0, param = 0;
1579 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1581 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1583 p_info = &p_hwfn->mcp_info->func_info;
1585 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1587 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1589 /* Acknowledge the MFW */
1590 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1594 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1595 struct ecore_ptt *p_ptt)
1597 /* A single notification should be sent to upper driver in CMT mode */
1598 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1601 DP_NOTICE(p_hwfn, false,
1602 "Fan failure was detected on the network interface card"
1603 " and it's going to be shut down.\n");
1605 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1608 struct ecore_mdump_cmd_params {
1617 static enum _ecore_status_t
1618 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1619 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1621 struct ecore_mcp_mb_params mb_params;
1622 enum _ecore_status_t rc;
1624 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1625 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1626 mb_params.param = p_mdump_cmd_params->cmd;
1627 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1628 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1629 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1630 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1631 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1632 if (rc != ECORE_SUCCESS)
1635 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1637 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1639 "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1640 p_mdump_cmd_params->cmd);
1642 } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1644 "The mdump command is not supported by the MFW\n");
1651 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1652 struct ecore_ptt *p_ptt)
1654 struct ecore_mdump_cmd_params mdump_cmd_params;
1656 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1657 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1659 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1662 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1663 struct ecore_ptt *p_ptt,
1666 struct ecore_mdump_cmd_params mdump_cmd_params;
1668 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1669 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1670 mdump_cmd_params.p_data_src = &epoch;
1671 mdump_cmd_params.data_src_size = sizeof(epoch);
1673 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1676 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1677 struct ecore_ptt *p_ptt)
1679 struct ecore_mdump_cmd_params mdump_cmd_params;
1681 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1682 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1684 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1687 static enum _ecore_status_t
1688 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1689 struct mdump_config_stc *p_mdump_config)
1691 struct ecore_mdump_cmd_params mdump_cmd_params;
1692 enum _ecore_status_t rc;
1694 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1695 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1696 mdump_cmd_params.p_data_dst = p_mdump_config;
1697 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1699 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1700 if (rc != ECORE_SUCCESS)
1703 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1705 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1706 mdump_cmd_params.mcp_resp);
1707 rc = ECORE_UNKNOWN_ERROR;
1713 enum _ecore_status_t
1714 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1715 struct ecore_mdump_info *p_mdump_info)
1717 u32 addr, global_offsize, global_addr;
1718 struct mdump_config_stc mdump_config;
1719 enum _ecore_status_t rc;
1721 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1723 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1725 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1726 global_addr = SECTION_ADDR(global_offsize, 0);
1727 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1729 OFFSETOF(struct public_global,
1732 if (p_mdump_info->reason) {
1733 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1734 if (rc != ECORE_SUCCESS)
1737 p_mdump_info->version = mdump_config.version;
1738 p_mdump_info->config = mdump_config.config;
1739 p_mdump_info->epoch = mdump_config.epoc;
1740 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1741 p_mdump_info->valid_logs = mdump_config.valid_logs;
1743 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1744 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1745 p_mdump_info->reason, p_mdump_info->version,
1746 p_mdump_info->config, p_mdump_info->epoch,
1747 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1749 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1750 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1753 return ECORE_SUCCESS;
1756 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1757 struct ecore_ptt *p_ptt)
1759 struct ecore_mdump_cmd_params mdump_cmd_params;
1761 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1762 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1764 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1767 enum _ecore_status_t
1768 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1769 struct ecore_mdump_retain_data *p_mdump_retain)
1771 struct ecore_mdump_cmd_params mdump_cmd_params;
1772 struct mdump_retain_data_stc mfw_mdump_retain;
1773 enum _ecore_status_t rc;
1775 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1776 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1777 mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1778 mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1780 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1781 if (rc != ECORE_SUCCESS)
1784 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1786 "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1787 mdump_cmd_params.mcp_resp);
1788 return ECORE_UNKNOWN_ERROR;
1791 p_mdump_retain->valid = mfw_mdump_retain.valid;
1792 p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1793 p_mdump_retain->pf = mfw_mdump_retain.pf;
1794 p_mdump_retain->status = mfw_mdump_retain.status;
1796 return ECORE_SUCCESS;
1799 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1800 struct ecore_ptt *p_ptt)
1802 struct ecore_mdump_cmd_params mdump_cmd_params;
1804 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1805 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1807 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1810 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1811 struct ecore_ptt *p_ptt)
1813 struct ecore_mdump_retain_data mdump_retain;
1814 enum _ecore_status_t rc;
1816 /* In CMT mode - no need for more than a single acknowledgment to the
1817 * MFW, and no more than a single notification to the upper driver.
1819 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1822 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1823 if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1824 DP_NOTICE(p_hwfn, false,
1825 "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1826 mdump_retain.epoch, mdump_retain.pf,
1827 mdump_retain.status);
1829 DP_NOTICE(p_hwfn, false,
1830 "The MFW notified that a critical error occurred in the device\n");
1833 if (p_hwfn->p_dev->allow_mdump) {
1834 DP_NOTICE(p_hwfn, false,
1835 "Not acknowledging the notification to allow the MFW crash dump\n");
1839 DP_NOTICE(p_hwfn, false,
1840 "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1841 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1842 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1845 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1846 struct ecore_ptt *p_ptt)
1848 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1849 enum _ecore_status_t rc = ECORE_SUCCESS;
1853 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1855 /* Read Messages from MFW */
1856 ecore_mcp_read_mb(p_hwfn, p_ptt);
1858 /* Compare current messages to old ones */
1859 for (i = 0; i < info->mfw_mb_length; i++) {
1860 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1865 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1866 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1867 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1870 case MFW_DRV_MSG_LINK_CHANGE:
1871 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1873 case MFW_DRV_MSG_VF_DISABLED:
1874 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1876 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1877 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1878 ECORE_DCBX_REMOTE_LLDP_MIB);
1880 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1881 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1882 ECORE_DCBX_REMOTE_MIB);
1884 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1885 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1886 ECORE_DCBX_OPERATIONAL_MIB);
1888 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1889 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1891 case MFW_DRV_MSG_ERROR_RECOVERY:
1892 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1894 case MFW_DRV_MSG_GET_LAN_STATS:
1895 case MFW_DRV_MSG_GET_FCOE_STATS:
1896 case MFW_DRV_MSG_GET_ISCSI_STATS:
1897 case MFW_DRV_MSG_GET_RDMA_STATS:
1898 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1900 case MFW_DRV_MSG_BW_UPDATE:
1901 ecore_mcp_update_bw(p_hwfn, p_ptt);
1903 case MFW_DRV_MSG_FAILURE_DETECTED:
1904 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1906 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1907 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1910 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1915 /* ACK everything */
1916 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1917 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1919 /* MFW expect answer in BE, so we force write in that format */
1920 ecore_wr(p_hwfn, p_ptt,
1921 info->mfw_mb_addr + sizeof(u32) +
1922 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1923 sizeof(u32) + i * sizeof(u32), val);
1927 DP_NOTICE(p_hwfn, false,
1928 "Received an MFW message indication but no"
1933 /* Copy the new mfw messages into the shadow */
1934 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1939 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1940 struct ecore_ptt *p_ptt,
1942 u32 *p_running_bundle_id)
1947 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1948 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1949 return ECORE_SUCCESS;
1953 if (IS_VF(p_hwfn->p_dev)) {
1954 if (p_hwfn->vf_iov_info) {
1955 struct pfvf_acquire_resp_tlv *p_resp;
1957 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1958 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1959 return ECORE_SUCCESS;
1961 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1962 "VF requested MFW version prior to ACQUIRE\n");
1967 global_offsize = ecore_rd(p_hwfn, p_ptt,
1968 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1972 ecore_rd(p_hwfn, p_ptt,
1973 SECTION_ADDR(global_offsize,
1974 0) + OFFSETOF(struct public_global, mfw_ver));
1976 if (p_running_bundle_id != OSAL_NULL) {
1977 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1978 SECTION_ADDR(global_offsize,
1980 OFFSETOF(struct public_global,
1981 running_bundle_id));
1984 return ECORE_SUCCESS;
1987 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
1988 struct ecore_ptt *p_ptt,
1992 /* TODO - Add support for VFs */
1993 if (IS_VF(p_hwfn->p_dev))
1996 if (!ecore_mcp_is_init(p_hwfn)) {
1997 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2002 *p_media_type = MEDIA_UNSPECIFIED;
2005 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2006 p_hwfn->mcp_info->port_addr +
2007 OFFSETOF(struct public_port,
2011 return ECORE_SUCCESS;
2015 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2017 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2018 enum ecore_pci_personality *p_proto)
2020 *p_proto = ECORE_PCI_ETH;
2022 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2023 "According to Legacy capabilities, L2 personality is %08x\n",
2028 static enum _ecore_status_t
2029 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2030 struct ecore_ptt *p_ptt,
2031 enum ecore_pci_personality *p_proto)
2033 u32 resp = 0, param = 0;
2034 enum _ecore_status_t rc;
2036 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2037 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2038 (u32)*p_proto, resp, param);
2039 return ECORE_SUCCESS;
2042 static enum _ecore_status_t
2043 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2044 struct public_func *p_info,
2045 struct ecore_ptt *p_ptt,
2046 enum ecore_pci_personality *p_proto)
2048 enum _ecore_status_t rc = ECORE_SUCCESS;
2050 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2051 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2052 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2054 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2063 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2064 struct ecore_ptt *p_ptt)
2066 struct ecore_mcp_function_info *info;
2067 struct public_func shmem_info;
2069 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2070 info = &p_hwfn->mcp_info->func_info;
2072 info->pause_on_host = (shmem_info.config &
2073 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2075 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2077 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2078 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2082 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2084 if (shmem_info.mac_upper || shmem_info.mac_lower) {
2085 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2086 info->mac[1] = (u8)(shmem_info.mac_upper);
2087 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2088 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2089 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2090 info->mac[5] = (u8)(shmem_info.mac_lower);
2092 /* TODO - are there protocols for which there's no MAC? */
2093 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2096 /* TODO - are these calculations true for BE machine? */
2097 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2098 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2099 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2100 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2102 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2104 info->mtu = (u16)shmem_info.mtu_size;
2109 info->mtu = (u16)shmem_info.mtu_size;
2111 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2112 "Read configuration from shmem: pause_on_host %02x"
2113 " protocol %02x BW [%02x - %02x]"
2114 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2115 " node %lx ovlan %04x\n",
2116 info->pause_on_host, info->protocol,
2117 info->bandwidth_min, info->bandwidth_max,
2118 info->mac[0], info->mac[1], info->mac[2],
2119 info->mac[3], info->mac[4], info->mac[5],
2120 (unsigned long)info->wwn_port,
2121 (unsigned long)info->wwn_node, info->ovlan);
2123 return ECORE_SUCCESS;
2126 struct ecore_mcp_link_params
2127 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2129 if (!p_hwfn || !p_hwfn->mcp_info)
2131 return &p_hwfn->mcp_info->link_input;
2134 struct ecore_mcp_link_state
2135 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2137 if (!p_hwfn || !p_hwfn->mcp_info)
2141 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2142 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2143 p_hwfn->mcp_info->link_output.link_up = true;
2147 return &p_hwfn->mcp_info->link_output;
2150 struct ecore_mcp_link_capabilities
2151 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2153 if (!p_hwfn || !p_hwfn->mcp_info)
2155 return &p_hwfn->mcp_info->link_capabilities;
2158 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2159 struct ecore_ptt *p_ptt)
2161 u32 resp = 0, param = 0;
2162 enum _ecore_status_t rc;
2164 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2165 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
2167 /* Wait for the drain to complete before returning */
2173 const struct ecore_mcp_function_info
2174 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2176 if (!p_hwfn || !p_hwfn->mcp_info)
2178 return &p_hwfn->mcp_info->func_info;
2181 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2182 struct ecore_ptt *p_ptt, u32 personalities)
2184 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2185 struct public_func shmem_info;
2186 int i, count = 0, num_pfs;
2188 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2190 for (i = 0; i < num_pfs; i++) {
2191 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2192 MCP_PF_ID_BY_REL(p_hwfn, i));
2193 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2196 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2201 if ((1 << ((u32)protocol)) & personalities)
2208 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2209 struct ecore_ptt *p_ptt,
2215 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2216 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2221 if (IS_VF(p_hwfn->p_dev))
2224 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2225 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2226 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2227 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2229 *p_flash_size = flash_size;
2231 return ECORE_SUCCESS;
2234 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2235 struct ecore_ptt *p_ptt)
2237 struct ecore_dev *p_dev = p_hwfn->p_dev;
2239 if (p_dev->recov_in_prog) {
2240 DP_NOTICE(p_hwfn, false,
2241 "Avoid triggering a recovery since such a process"
2242 " is already in progress\n");
2246 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2247 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2249 return ECORE_SUCCESS;
2252 static enum _ecore_status_t
2253 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2254 struct ecore_ptt *p_ptt,
2257 u32 resp = 0, param = 0, rc_param = 0;
2258 enum _ecore_status_t rc;
2260 /* Only Leader can configure MSIX, and need to take CMT into account */
2262 if (!IS_LEAD_HWFN(p_hwfn))
2263 return ECORE_SUCCESS;
2264 num *= p_hwfn->p_dev->num_hwfns;
2266 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2267 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2268 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2269 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2271 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2274 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2275 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2279 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2280 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2287 static enum _ecore_status_t
2288 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2289 struct ecore_ptt *p_ptt,
2292 u32 resp = 0, param = num, rc_param = 0;
2293 enum _ecore_status_t rc;
2295 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2296 param, &resp, &rc_param);
2298 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2299 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2302 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2303 "Requested 0x%02x MSI-x interrupts for VFs\n",
2310 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2311 struct ecore_ptt *p_ptt,
2314 if (ECORE_IS_BB(p_hwfn->p_dev))
2315 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2317 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2320 enum _ecore_status_t
2321 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2322 struct ecore_mcp_drv_version *p_ver)
2324 struct ecore_mcp_mb_params mb_params;
2325 struct drv_version_stc drv_version;
2329 enum _ecore_status_t rc;
2332 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2333 return ECORE_SUCCESS;
2336 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2337 drv_version.version = p_ver->version;
2338 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2339 for (i = 0; i < num_words; i++) {
2340 /* The driver name is expected to be in a big-endian format */
2341 p_name = &p_ver->name[i * sizeof(u32)];
2342 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2343 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2346 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2347 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2348 mb_params.p_data_src = &drv_version;
2349 mb_params.data_src_size = sizeof(drv_version);
2350 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2351 if (rc != ECORE_SUCCESS)
2352 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2357 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2358 struct ecore_ptt *p_ptt)
2360 enum _ecore_status_t rc;
2361 u32 resp = 0, param = 0;
2363 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2365 if (rc != ECORE_SUCCESS)
2366 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2371 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2372 struct ecore_ptt *p_ptt)
2374 u32 value, cpu_mode;
2376 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2378 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2379 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2380 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2381 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2383 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2386 enum _ecore_status_t
2387 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2388 struct ecore_ptt *p_ptt,
2389 enum ecore_ov_client client)
2391 enum _ecore_status_t rc;
2392 u32 resp = 0, param = 0;
2396 case ECORE_OV_CLIENT_DRV:
2397 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2399 case ECORE_OV_CLIENT_USER:
2400 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2402 case ECORE_OV_CLIENT_VENDOR_SPEC:
2403 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2406 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2410 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2411 drv_mb_param, &resp, ¶m);
2412 if (rc != ECORE_SUCCESS)
2413 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2418 enum _ecore_status_t
2419 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2420 struct ecore_ptt *p_ptt,
2421 enum ecore_ov_driver_state drv_state)
2423 enum _ecore_status_t rc;
2424 u32 resp = 0, param = 0;
2427 switch (drv_state) {
2428 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2429 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2431 case ECORE_OV_DRIVER_STATE_DISABLED:
2432 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2434 case ECORE_OV_DRIVER_STATE_ACTIVE:
2435 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2438 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2442 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2443 drv_mb_param, &resp, ¶m);
2444 if (rc != ECORE_SUCCESS)
2445 DP_ERR(p_hwfn, "Failed to send driver state\n");
2450 enum _ecore_status_t
2451 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2452 struct ecore_fc_npiv_tbl *p_table)
2457 enum _ecore_status_t
2458 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2459 struct ecore_ptt *p_ptt, u16 mtu)
2464 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2465 struct ecore_ptt *p_ptt,
2466 enum ecore_led_mode mode)
2468 u32 resp = 0, param = 0, drv_mb_param;
2469 enum _ecore_status_t rc;
2472 case ECORE_LED_MODE_ON:
2473 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2475 case ECORE_LED_MODE_OFF:
2476 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2478 case ECORE_LED_MODE_RESTORE:
2479 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2482 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2486 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2487 drv_mb_param, &resp, ¶m);
2488 if (rc != ECORE_SUCCESS)
2489 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2494 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2495 struct ecore_ptt *p_ptt,
2498 u32 resp = 0, param = 0;
2499 enum _ecore_status_t rc;
2501 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2502 mask_parities, &resp, ¶m);
2504 if (rc != ECORE_SUCCESS) {
2506 "MCP response failure for mask parities, aborting\n");
2507 } else if (resp != FW_MSG_CODE_OK) {
2509 "MCP did not ack mask parity request. Old MFW?\n");
2516 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2519 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2520 u32 bytes_left, offset, bytes_to_copy, buf_size;
2521 u32 nvm_offset, resp, param;
2522 struct ecore_ptt *p_ptt;
2523 enum _ecore_status_t rc = ECORE_SUCCESS;
2525 p_ptt = ecore_ptt_acquire(p_hwfn);
2531 while (bytes_left > 0) {
2532 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2533 MCP_DRV_NVM_BUF_LEN);
2534 nvm_offset = (addr + offset) | (bytes_to_copy <<
2535 DRV_MB_PARAM_NVM_LEN_OFFSET);
2536 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2537 DRV_MSG_CODE_NVM_READ_NVRAM,
2538 nvm_offset, &resp, ¶m, &buf_size,
2539 (u32 *)(p_buf + offset));
2540 if (rc != ECORE_SUCCESS) {
2541 DP_NOTICE(p_dev, false,
2542 "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2544 resp = FW_MSG_CODE_ERROR;
2548 if (resp != FW_MSG_CODE_NVM_OK) {
2549 DP_NOTICE(p_dev, false,
2550 "nvm read failed, resp = 0x%08x\n", resp);
2551 rc = ECORE_UNKNOWN_ERROR;
2555 /* This can be a lengthy process, and it's possible scheduler
2556 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2558 if (bytes_left % 0x1000 <
2559 (bytes_left - buf_size) % 0x1000)
2563 bytes_left -= buf_size;
2566 p_dev->mcp_nvm_resp = resp;
2567 ecore_ptt_release(p_hwfn, p_ptt);
2572 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2573 u32 addr, u8 *p_buf, u32 len)
2575 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2576 struct ecore_ptt *p_ptt;
2578 enum _ecore_status_t rc;
2580 p_ptt = ecore_ptt_acquire(p_hwfn);
2584 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2585 (cmd == ECORE_PHY_CORE_READ) ?
2586 DRV_MSG_CODE_PHY_CORE_READ :
2587 DRV_MSG_CODE_PHY_RAW_READ,
2588 addr, &resp, ¶m, &len, (u32 *)p_buf);
2589 if (rc != ECORE_SUCCESS)
2590 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2592 p_dev->mcp_nvm_resp = resp;
2593 ecore_ptt_release(p_hwfn, p_ptt);
2598 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2600 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2601 struct ecore_ptt *p_ptt;
2603 p_ptt = ecore_ptt_acquire(p_hwfn);
2607 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2608 ecore_ptt_release(p_hwfn, p_ptt);
2610 return ECORE_SUCCESS;
2613 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2615 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2616 struct ecore_ptt *p_ptt;
2618 enum _ecore_status_t rc;
2620 p_ptt = ecore_ptt_acquire(p_hwfn);
2623 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2625 p_dev->mcp_nvm_resp = resp;
2626 ecore_ptt_release(p_hwfn, p_ptt);
2631 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2634 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2635 struct ecore_ptt *p_ptt;
2637 enum _ecore_status_t rc;
2639 p_ptt = ecore_ptt_acquire(p_hwfn);
2642 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2644 p_dev->mcp_nvm_resp = resp;
2645 ecore_ptt_release(p_hwfn, p_ptt);
2650 /* rc receives ECORE_INVAL as default parameter because
2651 * it might not enter the while loop if the len is 0
2653 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2654 u32 addr, u8 *p_buf, u32 len)
2656 u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2657 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2658 enum _ecore_status_t rc = ECORE_INVAL;
2659 struct ecore_ptt *p_ptt;
2661 p_ptt = ecore_ptt_acquire(p_hwfn);
2666 case ECORE_PUT_FILE_DATA:
2667 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2669 case ECORE_NVM_WRITE_NVRAM:
2670 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2672 case ECORE_EXT_PHY_FW_UPGRADE:
2673 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2676 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2683 while (buf_idx < len) {
2684 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2685 MCP_DRV_NVM_BUF_LEN);
2686 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2689 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2690 &resp, ¶m, buf_size,
2691 (u32 *)&p_buf[buf_idx]);
2692 if (rc != ECORE_SUCCESS) {
2693 DP_NOTICE(p_dev, false,
2694 "ecore_mcp_nvm_write() failed, rc = %d\n",
2696 resp = FW_MSG_CODE_ERROR;
2700 if (resp != FW_MSG_CODE_OK &&
2701 resp != FW_MSG_CODE_NVM_OK &&
2702 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2703 DP_NOTICE(p_dev, false,
2704 "nvm write failed, resp = 0x%08x\n", resp);
2705 rc = ECORE_UNKNOWN_ERROR;
2709 /* This can be a lengthy process, and it's possible scheduler
2710 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2712 if (buf_idx % 0x1000 >
2713 (buf_idx + buf_size) % 0x1000)
2716 buf_idx += buf_size;
2719 p_dev->mcp_nvm_resp = resp;
2721 ecore_ptt_release(p_hwfn, p_ptt);
2726 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2727 u32 addr, u8 *p_buf, u32 len)
2729 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2730 struct ecore_ptt *p_ptt;
2731 u32 resp, param, nvm_cmd;
2732 enum _ecore_status_t rc;
2734 p_ptt = ecore_ptt_acquire(p_hwfn);
2738 nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ? DRV_MSG_CODE_PHY_CORE_WRITE :
2739 DRV_MSG_CODE_PHY_RAW_WRITE;
2740 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2741 &resp, ¶m, len, (u32 *)p_buf);
2742 if (rc != ECORE_SUCCESS)
2743 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2744 p_dev->mcp_nvm_resp = resp;
2745 ecore_ptt_release(p_hwfn, p_ptt);
2750 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2753 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2754 struct ecore_ptt *p_ptt;
2756 enum _ecore_status_t rc;
2758 p_ptt = ecore_ptt_acquire(p_hwfn);
2762 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2764 p_dev->mcp_nvm_resp = resp;
2765 ecore_ptt_release(p_hwfn, p_ptt);
2770 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2771 struct ecore_ptt *p_ptt,
2772 u32 port, u32 addr, u32 offset,
2775 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2777 enum _ecore_status_t rc;
2779 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2780 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2784 while (bytes_left > 0) {
2785 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2786 MAX_I2C_TRANSACTION_SIZE);
2787 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2788 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2789 nvm_offset |= ((addr + offset) <<
2790 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2791 nvm_offset |= (bytes_to_copy <<
2792 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2793 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2794 DRV_MSG_CODE_TRANSCEIVER_READ,
2795 nvm_offset, &resp, ¶m, &buf_size,
2796 (u32 *)(p_buf + offset));
2797 if ((resp & FW_MSG_CODE_MASK) ==
2798 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2800 } else if ((resp & FW_MSG_CODE_MASK) !=
2801 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2802 return ECORE_UNKNOWN_ERROR;
2805 bytes_left -= buf_size;
2808 return ECORE_SUCCESS;
2811 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2812 struct ecore_ptt *p_ptt,
2813 u32 port, u32 addr, u32 offset,
2816 u32 buf_idx, buf_size, nvm_offset, resp, param;
2817 enum _ecore_status_t rc;
2819 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2820 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2822 while (buf_idx < len) {
2823 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2824 MAX_I2C_TRANSACTION_SIZE);
2825 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2826 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2827 nvm_offset |= ((offset + buf_idx) <<
2828 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2829 nvm_offset |= (buf_size <<
2830 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2831 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2832 DRV_MSG_CODE_TRANSCEIVER_WRITE,
2833 nvm_offset, &resp, ¶m, buf_size,
2834 (u32 *)&p_buf[buf_idx]);
2835 if ((resp & FW_MSG_CODE_MASK) ==
2836 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2838 } else if ((resp & FW_MSG_CODE_MASK) !=
2839 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2840 return ECORE_UNKNOWN_ERROR;
2842 buf_idx += buf_size;
2845 return ECORE_SUCCESS;
2848 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2849 struct ecore_ptt *p_ptt,
2850 u16 gpio, u32 *gpio_val)
2852 enum _ecore_status_t rc = ECORE_SUCCESS;
2853 u32 drv_mb_param = 0, rsp;
2855 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2857 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2858 drv_mb_param, &rsp, gpio_val);
2860 if (rc != ECORE_SUCCESS)
2863 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2864 return ECORE_UNKNOWN_ERROR;
2866 return ECORE_SUCCESS;
2869 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2870 struct ecore_ptt *p_ptt,
2871 u16 gpio, u16 gpio_val)
2873 enum _ecore_status_t rc = ECORE_SUCCESS;
2874 u32 drv_mb_param = 0, param, rsp;
2876 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
2877 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
2879 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2880 drv_mb_param, &rsp, ¶m);
2882 if (rc != ECORE_SUCCESS)
2885 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2886 return ECORE_UNKNOWN_ERROR;
2888 return ECORE_SUCCESS;
2891 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2892 struct ecore_ptt *p_ptt,
2893 u16 gpio, u32 *gpio_direction,
2896 u32 drv_mb_param = 0, rsp, val = 0;
2897 enum _ecore_status_t rc = ECORE_SUCCESS;
2899 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
2901 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2902 drv_mb_param, &rsp, &val);
2903 if (rc != ECORE_SUCCESS)
2906 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2907 DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
2908 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2909 DRV_MB_PARAM_GPIO_CTRL_OFFSET;
2911 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2912 return ECORE_UNKNOWN_ERROR;
2914 return ECORE_SUCCESS;
2917 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2918 struct ecore_ptt *p_ptt)
2920 u32 drv_mb_param = 0, rsp, param;
2921 enum _ecore_status_t rc = ECORE_SUCCESS;
2923 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2924 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2926 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2927 drv_mb_param, &rsp, ¶m);
2929 if (rc != ECORE_SUCCESS)
2932 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2933 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2934 rc = ECORE_UNKNOWN_ERROR;
2939 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2940 struct ecore_ptt *p_ptt)
2942 u32 drv_mb_param, rsp, param;
2943 enum _ecore_status_t rc = ECORE_SUCCESS;
2945 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2946 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2948 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2949 drv_mb_param, &rsp, ¶m);
2951 if (rc != ECORE_SUCCESS)
2954 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2955 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2956 rc = ECORE_UNKNOWN_ERROR;
2961 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2962 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2964 u32 drv_mb_param = 0, rsp;
2965 enum _ecore_status_t rc = ECORE_SUCCESS;
2967 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2968 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2970 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2971 drv_mb_param, &rsp, num_images);
2973 if (rc != ECORE_SUCCESS)
2976 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2977 rc = ECORE_UNKNOWN_ERROR;
2982 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2983 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2984 struct bist_nvm_image_att *p_image_att, u32 image_index)
2986 u32 buf_size, nvm_offset, resp, param;
2987 enum _ecore_status_t rc;
2989 nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2990 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2991 nvm_offset |= (image_index <<
2992 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
2993 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2994 nvm_offset, &resp, ¶m, &buf_size,
2995 (u32 *)p_image_att);
2996 if (rc != ECORE_SUCCESS)
2999 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3000 (p_image_att->return_code != 1))
3001 rc = ECORE_UNKNOWN_ERROR;
3006 enum _ecore_status_t
3007 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3008 struct ecore_ptt *p_ptt,
3009 struct ecore_temperature_info *p_temp_info)
3011 struct ecore_temperature_sensor *p_temp_sensor;
3012 struct temperature_status_stc mfw_temp_info;
3013 struct ecore_mcp_mb_params mb_params;
3015 enum _ecore_status_t rc;
3018 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3019 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3020 mb_params.p_data_dst = &mfw_temp_info;
3021 mb_params.data_dst_size = sizeof(mfw_temp_info);
3022 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3023 if (rc != ECORE_SUCCESS)
3026 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3027 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3028 ECORE_MAX_NUM_OF_SENSORS);
3029 for (i = 0; i < p_temp_info->num_sensors; i++) {
3030 val = mfw_temp_info.sensor[i];
3031 p_temp_sensor = &p_temp_info->sensors[i];
3032 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3033 SENSOR_LOCATION_OFFSET;
3034 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3035 THRESHOLD_HIGH_OFFSET;
3036 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3037 CRITICAL_TEMPERATURE_OFFSET;
3038 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3039 CURRENT_TEMP_OFFSET;
3042 return ECORE_SUCCESS;
3045 enum _ecore_status_t ecore_mcp_get_mba_versions(
3046 struct ecore_hwfn *p_hwfn,
3047 struct ecore_ptt *p_ptt,
3048 struct ecore_mba_vers *p_mba_vers)
3050 u32 buf_size, resp, param;
3051 enum _ecore_status_t rc;
3053 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3054 0, &resp, ¶m, &buf_size,
3055 &p_mba_vers->mba_vers[0]);
3057 if (rc != ECORE_SUCCESS)
3060 if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3061 rc = ECORE_UNKNOWN_ERROR;
3063 if (buf_size != MCP_DRV_NVM_BUF_LEN)
3064 rc = ECORE_UNKNOWN_ERROR;
3069 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3070 struct ecore_ptt *p_ptt,
3075 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3076 0, &rsp, (u32 *)num_events);
3079 static enum resource_id_enum
3080 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3082 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3086 mfw_res_id = RESOURCE_NUM_SB_E;
3088 case ECORE_L2_QUEUE:
3089 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3092 mfw_res_id = RESOURCE_NUM_VPORT_E;
3095 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3098 mfw_res_id = RESOURCE_NUM_PQ_E;
3101 mfw_res_id = RESOURCE_NUM_RL_E;
3105 /* Each VFC resource can accommodate both a MAC and a VLAN */
3106 mfw_res_id = RESOURCE_VFC_FILTER_E;
3109 mfw_res_id = RESOURCE_ILT_E;
3111 case ECORE_LL2_QUEUE:
3112 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3114 case ECORE_RDMA_CNQ_RAM:
3115 case ECORE_CMDQS_CQS:
3116 /* CNQ/CMDQS are the same resource */
3117 mfw_res_id = RESOURCE_CQS_E;
3119 case ECORE_RDMA_STATS_QUEUE:
3120 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3123 mfw_res_id = RESOURCE_BDQ_E;
3132 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
3133 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
3134 #define ECORE_RESC_ALLOC_VERSION \
3135 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
3136 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) | \
3137 (ECORE_RESC_ALLOC_VERSION_MINOR << \
3138 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3140 struct ecore_resc_alloc_in_params {
3142 enum ecore_resources res_id;
3146 struct ecore_resc_alloc_out_params {
3156 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
3158 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3160 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3161 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3162 enum _ecore_status_t rc;
3164 /* Allow ongoing PCIe transactions to complete */
3165 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3167 /* Clear the PF's internal FID_enable in the PXP */
3168 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3169 if (rc != ECORE_SUCCESS)
3170 DP_NOTICE(p_hwfn, false,
3171 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3177 static enum _ecore_status_t
3178 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3179 struct ecore_ptt *p_ptt,
3180 struct ecore_resc_alloc_in_params *p_in_params,
3181 struct ecore_resc_alloc_out_params *p_out_params)
3183 struct ecore_mcp_mb_params mb_params;
3184 struct resource_info mfw_resc_info;
3185 enum _ecore_status_t rc;
3187 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3189 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3190 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3192 "Failed to match resource %d [%s] with the MFW resources\n",
3193 p_in_params->res_id,
3194 ecore_hw_get_resc_name(p_in_params->res_id));
3198 switch (p_in_params->cmd) {
3199 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3200 mfw_resc_info.size = p_in_params->resc_max_val;
3202 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3205 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3210 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3211 mb_params.cmd = p_in_params->cmd;
3212 mb_params.param = ECORE_RESC_ALLOC_VERSION;
3213 mb_params.p_data_src = &mfw_resc_info;
3214 mb_params.data_src_size = sizeof(mfw_resc_info);
3215 mb_params.p_data_dst = mb_params.p_data_src;
3216 mb_params.data_dst_size = mb_params.data_src_size;
3218 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3219 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3220 p_in_params->cmd, p_in_params->res_id,
3221 ecore_hw_get_resc_name(p_in_params->res_id),
3222 GET_MFW_FIELD(mb_params.param,
3223 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3224 GET_MFW_FIELD(mb_params.param,
3225 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3226 p_in_params->resc_max_val);
3228 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3229 if (rc != ECORE_SUCCESS)
3232 p_out_params->mcp_resp = mb_params.mcp_resp;
3233 p_out_params->mcp_param = mb_params.mcp_param;
3234 p_out_params->resc_num = mfw_resc_info.size;
3235 p_out_params->resc_start = mfw_resc_info.offset;
3236 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3237 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3238 p_out_params->flags = mfw_resc_info.flags;
3240 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3241 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3242 GET_MFW_FIELD(p_out_params->mcp_param,
3243 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3244 GET_MFW_FIELD(p_out_params->mcp_param,
3245 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3246 p_out_params->resc_num, p_out_params->resc_start,
3247 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3248 p_out_params->flags);
3250 return ECORE_SUCCESS;
3253 enum _ecore_status_t
3254 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3255 enum ecore_resources res_id, u32 resc_max_val,
3258 struct ecore_resc_alloc_out_params out_params;
3259 struct ecore_resc_alloc_in_params in_params;
3260 enum _ecore_status_t rc;
3262 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3263 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3264 in_params.res_id = res_id;
3265 in_params.resc_max_val = resc_max_val;
3266 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3267 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3269 if (rc != ECORE_SUCCESS)
3272 *p_mcp_resp = out_params.mcp_resp;
3274 return ECORE_SUCCESS;
3277 enum _ecore_status_t
3278 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3279 enum ecore_resources res_id, u32 *p_mcp_resp,
3280 u32 *p_resc_num, u32 *p_resc_start)
3282 struct ecore_resc_alloc_out_params out_params;
3283 struct ecore_resc_alloc_in_params in_params;
3284 enum _ecore_status_t rc;
3286 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3287 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3288 in_params.res_id = res_id;
3289 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3290 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3292 if (rc != ECORE_SUCCESS)
3295 *p_mcp_resp = out_params.mcp_resp;
3297 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3298 *p_resc_num = out_params.resc_num;
3299 *p_resc_start = out_params.resc_start;
3302 return ECORE_SUCCESS;
3305 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3306 struct ecore_ptt *p_ptt)
3308 u32 mcp_resp, mcp_param;
3310 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3311 &mcp_resp, &mcp_param);
3314 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3315 struct ecore_ptt *p_ptt,
3316 u32 param, u32 *p_mcp_resp,
3319 enum _ecore_status_t rc;
3321 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3322 p_mcp_resp, p_mcp_param);
3323 if (rc != ECORE_SUCCESS)
3326 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3328 "The resource command is unsupported by the MFW\n");
3329 return ECORE_NOTIMPL;
3332 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3333 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3335 DP_NOTICE(p_hwfn, false,
3336 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3344 enum _ecore_status_t
3345 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3346 struct ecore_resc_lock_params *p_params)
3348 u32 param = 0, mcp_resp, mcp_param;
3350 enum _ecore_status_t rc;
3352 switch (p_params->timeout) {
3353 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3354 opcode = RESOURCE_OPCODE_REQ;
3355 p_params->timeout = 0;
3357 case ECORE_MCP_RESC_LOCK_TO_NONE:
3358 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3359 p_params->timeout = 0;
3362 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3366 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3367 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3368 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3370 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3371 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3372 param, p_params->timeout, opcode, p_params->resource);
3374 /* Attempt to acquire the resource */
3375 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3377 if (rc != ECORE_SUCCESS)
3380 /* Analyze the response */
3381 p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3382 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3384 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3385 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3386 mcp_param, opcode, p_params->owner);
3389 case RESOURCE_OPCODE_GNT:
3390 p_params->b_granted = true;
3392 case RESOURCE_OPCODE_BUSY:
3393 p_params->b_granted = false;
3396 DP_NOTICE(p_hwfn, false,
3397 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3402 return ECORE_SUCCESS;
3405 enum _ecore_status_t
3406 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3407 struct ecore_resc_lock_params *p_params)
3410 enum _ecore_status_t rc;
3413 /* No need for an interval before the first iteration */
3415 if (p_params->sleep_b4_retry) {
3416 u16 retry_interval_in_ms =
3417 DIV_ROUND_UP(p_params->retry_interval,
3420 OSAL_MSLEEP(retry_interval_in_ms);
3422 OSAL_UDELAY(p_params->retry_interval);
3426 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3427 if (rc != ECORE_SUCCESS)
3430 if (p_params->b_granted)
3432 } while (retry_cnt++ < p_params->retry_num);
3434 return ECORE_SUCCESS;
3438 ecore_mcp_resc_lock_default_init(struct ecore_hwfn *p_hwfn,
3439 struct ecore_resc_lock_params *p_lock,
3440 struct ecore_resc_unlock_params *p_unlock,
3441 enum ecore_resc_lock resource,
3442 bool b_is_permanent)
3444 if (p_lock != OSAL_NULL) {
3445 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3447 /* Permanent resources don't require aging, and there's no
3448 * point in trying to acquire them more than once since it's
3449 * unexpected another entity would release them.
3451 if (b_is_permanent) {
3452 p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3454 p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3455 p_lock->retry_interval =
3456 ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3457 p_lock->sleep_b4_retry = true;
3460 p_lock->resource = resource;
3463 if (p_unlock != OSAL_NULL) {
3464 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3465 p_unlock->resource = resource;
3469 enum _ecore_status_t
3470 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3471 struct ecore_resc_unlock_params *p_params)
3473 u32 param = 0, mcp_resp, mcp_param;
3475 enum _ecore_status_t rc;
3477 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3478 : RESOURCE_OPCODE_RELEASE;
3479 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3480 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3482 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3483 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3484 param, opcode, p_params->resource);
3486 /* Attempt to release the resource */
3487 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3489 if (rc != ECORE_SUCCESS)
3492 /* Analyze the response */
3493 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3495 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3496 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3500 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3502 "Resource unlock request for an already released resource [%d]\n",
3503 p_params->resource);
3505 case RESOURCE_OPCODE_RELEASED:
3506 p_params->b_released = true;
3508 case RESOURCE_OPCODE_WRONG_OWNER:
3509 p_params->b_released = false;
3512 DP_NOTICE(p_hwfn, false,
3513 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3518 return ECORE_SUCCESS;
3521 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3523 return !!(p_hwfn->mcp_info->capabilities &
3524 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3527 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3528 struct ecore_ptt *p_ptt)
3531 enum _ecore_status_t rc;
3533 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3534 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3535 if (rc == ECORE_SUCCESS)
3536 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3537 "MFW supported features: %08x\n",
3538 p_hwfn->mcp_info->capabilities);
3543 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3544 struct ecore_ptt *p_ptt)
3546 u32 mcp_resp, mcp_param, features;
3548 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3549 DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3551 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3552 features, &mcp_resp, &mcp_param);