2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
24 #define CHIP_MCP_RESP_ITER_US 10
25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 OFFSETOF(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 OFFSETOF(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_SHIFT)
48 #define MCP_BYTES_PER_MBIT_SHIFT 17
52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
57 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
64 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
66 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
68 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
70 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
71 "port_addr = 0x%x, port_id 0x%02x\n",
72 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
77 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
82 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
86 if (!p_hwfn->mcp_info->public_base)
89 for (i = 0; i < length; i++) {
90 tmp = ecore_rd(p_hwfn, p_ptt,
91 p_hwfn->mcp_info->mfw_mb_addr +
92 (i << 2) + sizeof(u32));
94 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
95 OSAL_BE32_TO_CPU(tmp);
99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
101 if (p_hwfn->mcp_info) {
102 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
103 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
104 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
106 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
108 return ECORE_SUCCESS;
111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt)
114 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
115 u32 drv_mb_offsize, mfw_mb_offsize;
116 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
119 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
120 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
121 p_info->public_base = 0;
126 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
127 if (!p_info->public_base)
130 p_info->public_base |= GRCBASE_MCP;
132 /* Calculate the driver and MFW mailbox address */
133 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
134 SECTION_OFFSIZE_ADDR(p_info->public_base,
136 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
138 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
139 " mcp_pf_id = 0x%x\n",
140 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
142 /* Set the MFW MB address */
143 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
144 SECTION_OFFSIZE_ADDR(p_info->public_base,
146 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
147 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
148 p_info->mfw_mb_addr);
150 /* Get the current driver mailbox sequence before sending
153 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
154 DRV_MSG_SEQ_NUMBER_MASK;
156 /* Get current FW pulse sequence */
157 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
160 p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
161 MISCS_REG_GENERIC_POR_0);
163 return ECORE_SUCCESS;
166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
167 struct ecore_ptt *p_ptt)
169 struct ecore_mcp_info *p_info;
172 /* Allocate mcp_info structure */
173 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
174 sizeof(*p_hwfn->mcp_info));
175 if (!p_hwfn->mcp_info)
177 p_info = p_hwfn->mcp_info;
179 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
180 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
181 /* Do not free mcp_info here, since public_base indicate that
182 * the MCP is not initialized
184 return ECORE_SUCCESS;
187 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
188 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
189 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
190 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
193 /* Initialize the MFW spinlock */
194 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
195 OSAL_SPIN_LOCK_INIT(&p_info->lock);
197 return ECORE_SUCCESS;
200 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
201 ecore_mcp_free(p_hwfn);
205 /* Locks the MFW mailbox of a PF to ensure a single access.
206 * The lock is achieved in most cases by holding a spinlock, causing other
207 * threads to wait till a previous access is done.
208 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
209 * access is achieved by setting a blocking flag, which will fail other
210 * competing contexts to send their mailboxes.
212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
215 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
217 /* The spinlock shouldn't be acquired when the mailbox command is
218 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
219 * pending [UN]LOAD_REQ command of another PF together with a spinlock
220 * (i.e. interrupts are disabled) - can lead to a deadlock.
221 * It is assumed that for a single PF, no other mailbox commands can be
222 * sent from another context while sending LOAD_REQ, and that any
223 * parallel commands to UNLOAD_REQ can be cancelled.
225 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
226 p_hwfn->mcp_info->block_mb_sending = false;
228 /* There's at least a single command that is sent by ecore during the
229 * load sequence [expectation of MFW].
231 if ((p_hwfn->mcp_info->block_mb_sending) &&
232 (cmd != DRV_MSG_CODE_FEATURE_SUPPORT)) {
233 DP_NOTICE(p_hwfn, false,
234 "Trying to send a MFW mailbox command [0x%x]"
235 " in parallel to [UN]LOAD_REQ. Aborting.\n",
237 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
241 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
242 p_hwfn->mcp_info->block_mb_sending = true;
243 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
246 return ECORE_SUCCESS;
249 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
251 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
252 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
255 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
256 struct ecore_ptt *p_ptt)
258 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
259 u32 delay = CHIP_MCP_RESP_ITER_US;
260 u32 org_mcp_reset_seq, cnt = 0;
261 enum _ecore_status_t rc = ECORE_SUCCESS;
264 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
265 delay = EMUL_MCP_RESP_ITER_US;
268 /* Ensure that only a single thread is accessing the mailbox at a
271 rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
272 if (rc != ECORE_SUCCESS)
275 /* Set drv command along with the updated sequence */
276 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
277 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
280 /* Wait for MFW response */
282 /* Give the FW up to 500 second (50*1000*10usec) */
283 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
284 MISCS_REG_GENERIC_POR_0)) &&
285 (cnt++ < ECORE_MCP_RESET_RETRIES));
287 if (org_mcp_reset_seq !=
288 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
289 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
290 "MCP was reset after %d usec\n", cnt * delay);
292 DP_ERR(p_hwfn, "Failed to reset MCP\n");
296 ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
301 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
302 struct ecore_ptt *p_ptt,
307 u32 delay = CHIP_MCP_RESP_ITER_US;
308 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
309 u32 seq, cnt = 1, actual_mb_seq;
310 enum _ecore_status_t rc = ECORE_SUCCESS;
313 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
314 delay = EMUL_MCP_RESP_ITER_US;
315 /* There is a built-in delay of 100usec in each MFW response read */
316 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
320 /* Get actual driver mailbox sequence */
321 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
322 DRV_MSG_SEQ_NUMBER_MASK;
324 /* Use MCP history register to check if MCP reset occurred between
327 if (p_hwfn->mcp_info->mcp_hist !=
328 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
329 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
330 ecore_load_mcp_offsets(p_hwfn, p_ptt);
331 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
333 seq = ++p_hwfn->mcp_info->drv_mb_seq;
336 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
338 /* Set drv command along with the updated sequence */
339 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
342 /* Wait for MFW response */
344 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
346 /* Give the FW up to 5 second (500*10ms) */
347 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
348 (cnt++ < max_retries));
350 /* Is this a reply to our command? */
351 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
352 *o_mcp_resp &= FW_MSG_CODE_MASK;
353 /* Get the MCP param */
354 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
357 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
361 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
366 static enum _ecore_status_t
367 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
368 struct ecore_ptt *p_ptt,
369 struct ecore_mcp_mb_params *p_mb_params)
371 union drv_union_data union_data;
373 enum _ecore_status_t rc;
375 /* MCP not initialized */
376 if (!ecore_mcp_is_init(p_hwfn)) {
377 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
381 if (p_mb_params->data_src_size > sizeof(union_data) ||
382 p_mb_params->data_dst_size > sizeof(union_data)) {
384 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
385 p_mb_params->data_src_size, p_mb_params->data_dst_size,
390 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
391 OFFSETOF(struct public_drv_mb, union_data);
393 /* Ensure that only a single thread is accessing the mailbox at a
396 rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
397 if (rc != ECORE_SUCCESS)
400 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
401 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
402 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
403 p_mb_params->data_src_size);
404 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
407 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
408 p_mb_params->param, &p_mb_params->mcp_resp,
409 &p_mb_params->mcp_param);
411 if (p_mb_params->p_data_dst != OSAL_NULL &&
412 p_mb_params->data_dst_size)
413 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
414 union_data_addr, p_mb_params->data_dst_size);
416 ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
421 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
422 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
423 u32 *o_mcp_resp, u32 *o_mcp_param)
425 struct ecore_mcp_mb_params mb_params;
426 enum _ecore_status_t rc;
429 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
430 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
432 loaded_port[p_hwfn->port_id]--;
433 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
436 return ECORE_SUCCESS;
440 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
442 mb_params.param = param;
443 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
444 if (rc != ECORE_SUCCESS)
447 *o_mcp_resp = mb_params.mcp_resp;
448 *o_mcp_param = mb_params.mcp_param;
450 return ECORE_SUCCESS;
453 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
454 struct ecore_ptt *p_ptt,
459 u32 i_txn_size, u32 *i_buf)
461 struct ecore_mcp_mb_params mb_params;
462 enum _ecore_status_t rc;
464 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
466 mb_params.param = param;
467 mb_params.p_data_src = i_buf;
468 mb_params.data_src_size = (u8)i_txn_size;
469 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
470 if (rc != ECORE_SUCCESS)
473 *o_mcp_resp = mb_params.mcp_resp;
474 *o_mcp_param = mb_params.mcp_param;
476 return ECORE_SUCCESS;
479 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
480 struct ecore_ptt *p_ptt,
485 u32 *o_txn_size, u32 *o_buf)
487 struct ecore_mcp_mb_params mb_params;
488 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
489 enum _ecore_status_t rc;
491 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
493 mb_params.param = param;
494 mb_params.p_data_dst = raw_data;
496 /* Use the maximal value since the actual one is part of the response */
497 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
499 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
500 if (rc != ECORE_SUCCESS)
503 *o_mcp_resp = mb_params.mcp_resp;
504 *o_mcp_param = mb_params.mcp_param;
506 *o_txn_size = *o_mcp_param;
508 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
510 return ECORE_SUCCESS;
514 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
517 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
520 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
521 else if (!loaded_port[p_hwfn->port_id])
522 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
524 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
526 /* On CMT, always tell that it's engine */
527 if (p_hwfn->p_dev->num_hwfns > 1)
528 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
530 *p_load_code = load_phase;
532 loaded_port[p_hwfn->port_id]++;
534 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
535 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
536 *p_load_code, loaded, p_hwfn->port_id,
537 loaded_port[p_hwfn->port_id]);
542 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
543 enum ecore_override_force_load override_force_load)
545 bool can_force_load = false;
547 switch (override_force_load) {
548 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
549 can_force_load = true;
551 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
552 can_force_load = false;
555 can_force_load = (drv_role == DRV_ROLE_OS &&
556 exist_drv_role == DRV_ROLE_PREBOOT) ||
557 (drv_role == DRV_ROLE_KDUMP &&
558 exist_drv_role == DRV_ROLE_OS);
562 return can_force_load;
565 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
566 struct ecore_ptt *p_ptt)
568 u32 resp = 0, param = 0;
569 enum _ecore_status_t rc;
571 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
573 if (rc != ECORE_SUCCESS)
574 DP_NOTICE(p_hwfn, false,
575 "Failed to send cancel load request, rc = %d\n", rc);
580 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
581 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
582 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
583 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
584 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
585 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
586 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
588 static u32 ecore_get_config_bitmap(void)
590 u32 config_bitmap = 0x0;
592 #ifdef CONFIG_ECORE_L2
593 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
595 #ifdef CONFIG_ECORE_SRIOV
596 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
598 #ifdef CONFIG_ECORE_ROCE
599 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
601 #ifdef CONFIG_ECORE_IWARP
602 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
604 #ifdef CONFIG_ECORE_FCOE
605 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
607 #ifdef CONFIG_ECORE_ISCSI
608 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
610 #ifdef CONFIG_ECORE_LL2
611 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
614 return config_bitmap;
617 struct ecore_load_req_in_params {
619 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
620 #define ECORE_LOAD_REQ_HSI_VER_1 1
627 bool avoid_eng_reset;
630 struct ecore_load_req_out_params {
640 static enum _ecore_status_t
641 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
642 struct ecore_load_req_in_params *p_in_params,
643 struct ecore_load_req_out_params *p_out_params)
645 struct ecore_mcp_mb_params mb_params;
646 struct load_req_stc load_req;
647 struct load_rsp_stc load_rsp;
649 enum _ecore_status_t rc;
651 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
652 load_req.drv_ver_0 = p_in_params->drv_ver_0;
653 load_req.drv_ver_1 = p_in_params->drv_ver_1;
654 load_req.fw_ver = p_in_params->fw_ver;
655 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
656 p_in_params->drv_role);
657 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
658 p_in_params->timeout_val);
659 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
660 p_in_params->force_cmd);
661 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
662 p_in_params->avoid_eng_reset);
664 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
665 DRV_ID_MCP_HSI_VER_CURRENT :
666 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
668 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
669 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
670 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
671 mb_params.p_data_src = &load_req;
672 mb_params.data_src_size = sizeof(load_req);
673 mb_params.p_data_dst = &load_rsp;
674 mb_params.data_dst_size = sizeof(load_rsp);
676 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
677 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
679 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
680 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
681 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
682 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
684 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
685 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
686 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
687 load_req.drv_ver_0, load_req.drv_ver_1,
688 load_req.fw_ver, load_req.misc0,
689 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
690 ECORE_MFW_GET_FIELD(load_req.misc0,
692 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
693 ECORE_MFW_GET_FIELD(load_req.misc0,
696 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
697 if (rc != ECORE_SUCCESS) {
698 DP_NOTICE(p_hwfn, false,
699 "Failed to send load request, rc = %d\n", rc);
703 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
704 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
705 p_out_params->load_code = mb_params.mcp_resp;
707 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
708 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
709 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
710 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
711 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
712 load_rsp.fw_ver, load_rsp.misc0,
713 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
714 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
715 ECORE_MFW_GET_FIELD(load_rsp.misc0,
718 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
719 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
720 p_out_params->exist_fw_ver = load_rsp.fw_ver;
721 p_out_params->exist_drv_role =
722 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
723 p_out_params->mfw_hsi_ver =
724 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
725 p_out_params->drv_exists =
726 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
727 LOAD_RSP_FLAGS0_DRV_EXISTS;
730 return ECORE_SUCCESS;
733 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
734 enum ecore_drv_role drv_role,
738 case ECORE_DRV_ROLE_OS:
739 *p_mfw_drv_role = DRV_ROLE_OS;
741 case ECORE_DRV_ROLE_KDUMP:
742 *p_mfw_drv_role = DRV_ROLE_KDUMP;
747 enum ecore_load_req_force {
748 ECORE_LOAD_REQ_FORCE_NONE,
749 ECORE_LOAD_REQ_FORCE_PF,
750 ECORE_LOAD_REQ_FORCE_ALL,
753 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
754 enum ecore_load_req_force force_cmd,
758 case ECORE_LOAD_REQ_FORCE_NONE:
759 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
761 case ECORE_LOAD_REQ_FORCE_PF:
762 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
764 case ECORE_LOAD_REQ_FORCE_ALL:
765 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
770 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
771 struct ecore_ptt *p_ptt,
772 struct ecore_load_req_params *p_params)
774 struct ecore_load_req_out_params out_params;
775 struct ecore_load_req_in_params in_params;
776 u8 mfw_drv_role = 0, mfw_force_cmd;
777 enum _ecore_status_t rc;
780 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
781 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
782 return ECORE_SUCCESS;
786 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
787 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
788 in_params.drv_ver_0 = ECORE_VERSION;
789 in_params.drv_ver_1 = ecore_get_config_bitmap();
790 in_params.fw_ver = STORM_FW_VERSION;
791 ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
792 in_params.drv_role = mfw_drv_role;
793 in_params.timeout_val = p_params->timeout_val;
794 ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
796 in_params.force_cmd = mfw_force_cmd;
797 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
799 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
800 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
801 if (rc != ECORE_SUCCESS)
804 /* First handle cases where another load request should/might be sent:
805 * - MFW expects the old interface [HSI version = 1]
806 * - MFW responds that a force load request is required
808 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
810 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
812 /* The previous load request set the mailbox blocking */
813 p_hwfn->mcp_info->block_mb_sending = false;
815 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
816 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
817 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
819 if (rc != ECORE_SUCCESS)
821 } else if (out_params.load_code ==
822 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
823 /* The previous load request set the mailbox blocking */
824 p_hwfn->mcp_info->block_mb_sending = false;
826 if (ecore_mcp_can_force_load(in_params.drv_role,
827 out_params.exist_drv_role,
828 p_params->override_force_load)) {
830 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
831 in_params.drv_role, in_params.fw_ver,
832 in_params.drv_ver_0, in_params.drv_ver_1,
833 out_params.exist_drv_role,
834 out_params.exist_fw_ver,
835 out_params.exist_drv_ver_0,
836 out_params.exist_drv_ver_1);
838 ecore_get_mfw_force_cmd(p_hwfn,
839 ECORE_LOAD_REQ_FORCE_ALL,
842 in_params.force_cmd = mfw_force_cmd;
843 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
844 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
846 if (rc != ECORE_SUCCESS)
849 DP_NOTICE(p_hwfn, false,
850 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
851 in_params.drv_role, in_params.fw_ver,
852 in_params.drv_ver_0, in_params.drv_ver_1,
853 out_params.exist_drv_role,
854 out_params.exist_fw_ver,
855 out_params.exist_drv_ver_0,
856 out_params.exist_drv_ver_1);
858 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
863 /* Now handle the other types of responses.
864 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
865 * expected here after the additional revised load requests were sent.
867 switch (out_params.load_code) {
868 case FW_MSG_CODE_DRV_LOAD_ENGINE:
869 case FW_MSG_CODE_DRV_LOAD_PORT:
870 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
871 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
872 out_params.drv_exists) {
873 /* The role and fw/driver version match, but the PF is
874 * already loaded and has not been unloaded gracefully.
875 * This is unexpected since a quasi-FLR request was
876 * previously sent as part of ecore_hw_prepare().
878 DP_NOTICE(p_hwfn, false,
879 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
884 DP_NOTICE(p_hwfn, false,
885 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
886 out_params.load_code);
890 p_params->load_code = out_params.load_code;
892 return ECORE_SUCCESS;
895 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
896 struct ecore_ptt *p_ptt)
898 u32 resp = 0, param = 0;
899 enum _ecore_status_t rc;
901 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
903 if (rc != ECORE_SUCCESS) {
904 DP_NOTICE(p_hwfn, false,
905 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
909 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
911 /* Check if there is a DID mismatch between nvm-cfg/efuse */
912 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
913 DP_NOTICE(p_hwfn, false,
914 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
916 return ECORE_SUCCESS;
919 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
920 struct ecore_ptt *p_ptt)
922 u32 wol_param, mcp_resp, mcp_param;
925 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
927 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
928 &mcp_resp, &mcp_param);
931 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
932 struct ecore_ptt *p_ptt)
934 struct ecore_mcp_mb_params mb_params;
935 struct mcp_mac wol_mac;
937 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
938 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
940 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
943 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
944 struct ecore_ptt *p_ptt)
946 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
948 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
949 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
950 ECORE_PATH_ID(p_hwfn));
951 u32 disabled_vfs[VF_MAX_STATIC / 32];
954 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
955 "Reading Disabled VF information from [offset %08x],"
957 mfw_path_offsize, path_addr);
959 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
960 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
962 OFFSETOF(struct public_path,
965 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
966 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
967 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
970 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
971 OSAL_VF_FLR_UPDATE(p_hwfn);
974 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
975 struct ecore_ptt *p_ptt,
978 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
980 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
981 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
983 struct ecore_mcp_mb_params mb_params;
984 enum _ecore_status_t rc;
987 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
988 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
989 "Acking VFs [%08x,...,%08x] - %08x\n",
990 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
992 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
993 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
994 mb_params.p_data_src = vfs_to_ack;
995 mb_params.data_src_size = VF_MAX_STATIC / 8;
996 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
998 if (rc != ECORE_SUCCESS) {
999 DP_NOTICE(p_hwfn, false,
1000 "Failed to pass ACK for VF flr to MFW\n");
1001 return ECORE_TIMEOUT;
1004 /* TMP - clear the ACK bits; should be done by MFW */
1005 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1006 ecore_wr(p_hwfn, p_ptt,
1008 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1009 i * sizeof(u32), 0);
1014 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1015 struct ecore_ptt *p_ptt)
1017 u32 transceiver_state;
1019 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1020 p_hwfn->mcp_info->port_addr +
1021 OFFSETOF(struct public_port,
1024 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1025 "Received transceiver state update [0x%08x] from mfw"
1027 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1028 OFFSETOF(struct public_port,
1029 transceiver_data)));
1031 transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
1033 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1034 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1036 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1039 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1040 struct ecore_ptt *p_ptt,
1041 struct ecore_mcp_link_state *p_link)
1043 u32 eee_status, val;
1045 p_link->eee_adv_caps = 0;
1046 p_link->eee_lp_adv_caps = 0;
1047 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1048 OFFSETOF(struct public_port, eee_status));
1049 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1050 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_SHIFT;
1051 if (val & EEE_1G_ADV)
1052 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1053 if (val & EEE_10G_ADV)
1054 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1055 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_SHIFT;
1056 if (val & EEE_1G_ADV)
1057 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1058 if (val & EEE_10G_ADV)
1059 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1062 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1063 struct ecore_ptt *p_ptt,
1066 struct ecore_mcp_link_state *p_link;
1070 p_link = &p_hwfn->mcp_info->link_output;
1071 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1073 status = ecore_rd(p_hwfn, p_ptt,
1074 p_hwfn->mcp_info->port_addr +
1075 OFFSETOF(struct public_port, link_status));
1076 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1077 "Received link update [0x%08x] from mfw"
1079 status, (u32)(p_hwfn->mcp_info->port_addr +
1080 OFFSETOF(struct public_port,
1083 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1084 "Resetting link indications\n");
1088 if (p_hwfn->b_drv_link_init)
1089 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1091 p_link->link_up = false;
1093 p_link->full_duplex = true;
1094 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1095 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1096 p_link->speed = 100000;
1098 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1099 p_link->speed = 50000;
1101 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1102 p_link->speed = 40000;
1104 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1105 p_link->speed = 25000;
1107 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1108 p_link->speed = 20000;
1110 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1111 p_link->speed = 10000;
1113 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1114 p_link->full_duplex = false;
1116 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1117 p_link->speed = 1000;
1123 /* We never store total line speed as p_link->speed is
1124 * again changes according to bandwidth allocation.
1126 if (p_link->link_up && p_link->speed)
1127 p_link->line_speed = p_link->speed;
1129 p_link->line_speed = 0;
1131 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1132 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1134 /* Max bandwidth configuration */
1135 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1138 /* Mintz bandwidth configuration */
1139 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1141 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1142 p_link->min_pf_rate);
1144 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1145 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1146 p_link->parallel_detection = !!(status &
1147 LINK_STATUS_PARALLEL_DETECTION_USED);
1148 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1150 p_link->partner_adv_speed |=
1151 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1152 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1153 p_link->partner_adv_speed |=
1154 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1155 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1156 p_link->partner_adv_speed |=
1157 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1158 ECORE_LINK_PARTNER_SPEED_10G : 0;
1159 p_link->partner_adv_speed |=
1160 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1161 ECORE_LINK_PARTNER_SPEED_20G : 0;
1162 p_link->partner_adv_speed |=
1163 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1164 ECORE_LINK_PARTNER_SPEED_25G : 0;
1165 p_link->partner_adv_speed |=
1166 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1167 ECORE_LINK_PARTNER_SPEED_40G : 0;
1168 p_link->partner_adv_speed |=
1169 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1170 ECORE_LINK_PARTNER_SPEED_50G : 0;
1171 p_link->partner_adv_speed |=
1172 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1173 ECORE_LINK_PARTNER_SPEED_100G : 0;
1175 p_link->partner_tx_flow_ctrl_en =
1176 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1177 p_link->partner_rx_flow_ctrl_en =
1178 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1180 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1181 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1182 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1184 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1185 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1187 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1188 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1191 p_link->partner_adv_pause = 0;
1194 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1196 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1197 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1199 OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1202 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1203 struct ecore_ptt *p_ptt, bool b_up)
1205 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1206 struct ecore_mcp_mb_params mb_params;
1207 struct eth_phy_cfg phy_cfg;
1208 enum _ecore_status_t rc = ECORE_SUCCESS;
1212 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1213 return ECORE_SUCCESS;
1216 /* Set the shmem configuration according to params */
1217 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1218 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1219 if (!params->speed.autoneg)
1220 phy_cfg.speed = params->speed.forced_speed;
1221 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1222 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1223 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1224 phy_cfg.adv_speed = params->speed.advertised_speeds;
1225 phy_cfg.loopback_mode = params->loopback_mode;
1227 /* There are MFWs that share this capability regardless of whether
1228 * this is feasible or not. And given that at the very least adv_caps
1229 * would be set internally by ecore, we want to make sure LFA would
1232 if ((p_hwfn->mcp_info->capabilities &
1233 FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1234 params->eee.enable) {
1235 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1236 if (params->eee.tx_lpi_enable)
1237 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1238 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1239 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1240 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1241 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1242 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1243 EEE_TX_TIMER_USEC_SHIFT) &
1244 EEE_TX_TIMER_USEC_MASK;
1247 p_hwfn->b_drv_link_init = b_up;
1250 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1251 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1252 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1253 phy_cfg.loopback_mode);
1255 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1257 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1258 mb_params.cmd = cmd;
1259 mb_params.p_data_src = &phy_cfg;
1260 mb_params.data_src_size = sizeof(phy_cfg);
1261 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1263 /* if mcp fails to respond we must abort */
1264 if (rc != ECORE_SUCCESS) {
1265 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1269 /* Reset the link status if needed */
1271 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
1276 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1277 struct ecore_ptt *p_ptt)
1279 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1281 /* TODO - Add support for VFs */
1282 if (IS_VF(p_hwfn->p_dev))
1285 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1287 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1288 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1290 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1292 OFFSETOF(struct public_path, process_kill)) &
1293 PROCESS_KILL_COUNTER_MASK;
1295 return proc_kill_cnt;
1298 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1299 struct ecore_ptt *p_ptt)
1301 struct ecore_dev *p_dev = p_hwfn->p_dev;
1304 /* Prevent possible attentions/interrupts during the recovery handling
1305 * and till its load phase, during which they will be re-enabled.
1307 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1309 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1311 /* The following operations should be done once, and thus in CMT mode
1312 * are carried out by only the first HW function.
1314 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1317 if (p_dev->recov_in_prog) {
1318 DP_NOTICE(p_hwfn, false,
1319 "Ignoring the indication since a recovery"
1320 " process is already in progress\n");
1324 p_dev->recov_in_prog = true;
1326 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1327 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1329 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1332 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1333 struct ecore_ptt *p_ptt,
1334 enum MFW_DRV_MSG_TYPE type)
1336 enum ecore_mcp_protocol_type stats_type;
1337 union ecore_mcp_protocol_stats stats;
1338 struct ecore_mcp_mb_params mb_params;
1340 enum _ecore_status_t rc;
1343 case MFW_DRV_MSG_GET_LAN_STATS:
1344 stats_type = ECORE_MCP_LAN_STATS;
1345 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1348 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1352 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1354 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1355 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1356 mb_params.param = hsi_param;
1357 mb_params.p_data_src = &stats;
1358 mb_params.data_src_size = sizeof(stats);
1359 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1360 if (rc != ECORE_SUCCESS)
1361 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1364 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1365 struct public_func *p_shmem_info)
1367 struct ecore_mcp_function_info *p_info;
1369 p_info = &p_hwfn->mcp_info->func_info;
1371 /* TODO - bandwidth min/max should have valid values of 1-100,
1372 * as well as some indication that the feature is disabled.
1373 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1374 * limit and correct value to min `1' and max `100' if limit isn't in
1377 p_info->bandwidth_min = (p_shmem_info->config &
1378 FUNC_MF_CFG_MIN_BW_MASK) >>
1379 FUNC_MF_CFG_MIN_BW_SHIFT;
1380 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1382 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1383 p_info->bandwidth_min);
1384 p_info->bandwidth_min = 1;
1387 p_info->bandwidth_max = (p_shmem_info->config &
1388 FUNC_MF_CFG_MAX_BW_MASK) >>
1389 FUNC_MF_CFG_MAX_BW_SHIFT;
1390 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1392 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1393 p_info->bandwidth_max);
1394 p_info->bandwidth_max = 100;
1398 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1399 struct ecore_ptt *p_ptt,
1400 struct public_func *p_data,
1403 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1405 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1406 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1409 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1411 size = OSAL_MIN_T(u32, sizeof(*p_data),
1412 SECTION_SIZE(mfw_path_offsize));
1413 for (i = 0; i < size / sizeof(u32); i++)
1414 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1415 func_addr + (i << 2));
1421 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1423 struct ecore_mcp_function_info *p_info;
1424 struct public_func shmem_info;
1425 u32 resp = 0, param = 0;
1427 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1429 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1431 p_info = &p_hwfn->mcp_info->func_info;
1433 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1435 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1437 /* Acknowledge the MFW */
1438 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1442 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1443 struct ecore_ptt *p_ptt)
1445 /* A single notification should be sent to upper driver in CMT mode */
1446 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1449 DP_NOTICE(p_hwfn, false,
1450 "Fan failure was detected on the network interface card"
1451 " and it's going to be shut down.\n");
1453 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1456 struct ecore_mdump_cmd_params {
1465 static enum _ecore_status_t
1466 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1467 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1469 struct ecore_mcp_mb_params mb_params;
1470 enum _ecore_status_t rc;
1472 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1473 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1474 mb_params.param = p_mdump_cmd_params->cmd;
1475 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1476 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1477 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1478 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1479 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1480 if (rc != ECORE_SUCCESS)
1483 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1485 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1487 "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1488 p_mdump_cmd_params->cmd);
1490 } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1492 "The mdump command is not supported by the MFW\n");
1499 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1500 struct ecore_ptt *p_ptt)
1502 struct ecore_mdump_cmd_params mdump_cmd_params;
1504 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1505 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1507 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1510 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1511 struct ecore_ptt *p_ptt,
1514 struct ecore_mdump_cmd_params mdump_cmd_params;
1516 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1517 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1518 mdump_cmd_params.p_data_src = &epoch;
1519 mdump_cmd_params.data_src_size = sizeof(epoch);
1521 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1524 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1525 struct ecore_ptt *p_ptt)
1527 struct ecore_mdump_cmd_params mdump_cmd_params;
1529 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1530 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1532 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1535 static enum _ecore_status_t
1536 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1537 struct mdump_config_stc *p_mdump_config)
1539 struct ecore_mdump_cmd_params mdump_cmd_params;
1540 enum _ecore_status_t rc;
1542 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1543 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1544 mdump_cmd_params.p_data_dst = p_mdump_config;
1545 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1547 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1548 if (rc != ECORE_SUCCESS)
1551 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1553 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1554 mdump_cmd_params.mcp_resp);
1555 rc = ECORE_UNKNOWN_ERROR;
1561 enum _ecore_status_t
1562 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1563 struct ecore_mdump_info *p_mdump_info)
1565 u32 addr, global_offsize, global_addr;
1566 struct mdump_config_stc mdump_config;
1567 enum _ecore_status_t rc;
1569 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1571 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1573 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1574 global_addr = SECTION_ADDR(global_offsize, 0);
1575 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1577 OFFSETOF(struct public_global,
1580 if (p_mdump_info->reason) {
1581 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1582 if (rc != ECORE_SUCCESS)
1585 p_mdump_info->version = mdump_config.version;
1586 p_mdump_info->config = mdump_config.config;
1587 p_mdump_info->epoch = mdump_config.epoc;
1588 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1589 p_mdump_info->valid_logs = mdump_config.valid_logs;
1591 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1592 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1593 p_mdump_info->reason, p_mdump_info->version,
1594 p_mdump_info->config, p_mdump_info->epoch,
1595 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1597 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1598 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1601 return ECORE_SUCCESS;
1604 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1605 struct ecore_ptt *p_ptt)
1607 struct ecore_mdump_cmd_params mdump_cmd_params;
1609 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1610 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1612 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1615 enum _ecore_status_t
1616 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1617 struct ecore_mdump_retain_data *p_mdump_retain)
1619 struct ecore_mdump_cmd_params mdump_cmd_params;
1620 struct mdump_retain_data_stc mfw_mdump_retain;
1621 enum _ecore_status_t rc;
1623 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1624 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1625 mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1626 mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1628 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1629 if (rc != ECORE_SUCCESS)
1632 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1634 "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1635 mdump_cmd_params.mcp_resp);
1636 return ECORE_UNKNOWN_ERROR;
1639 p_mdump_retain->valid = mfw_mdump_retain.valid;
1640 p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1641 p_mdump_retain->pf = mfw_mdump_retain.pf;
1642 p_mdump_retain->status = mfw_mdump_retain.status;
1644 return ECORE_SUCCESS;
1647 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1648 struct ecore_ptt *p_ptt)
1650 struct ecore_mdump_cmd_params mdump_cmd_params;
1652 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1653 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1655 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1658 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1659 struct ecore_ptt *p_ptt)
1661 struct ecore_mdump_retain_data mdump_retain;
1662 enum _ecore_status_t rc;
1664 /* In CMT mode - no need for more than a single acknowledgment to the
1665 * MFW, and no more than a single notification to the upper driver.
1667 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1670 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1671 if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1672 DP_NOTICE(p_hwfn, false,
1673 "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1674 mdump_retain.epoch, mdump_retain.pf,
1675 mdump_retain.status);
1677 DP_NOTICE(p_hwfn, false,
1678 "The MFW notified that a critical error occurred in the device\n");
1681 if (p_hwfn->p_dev->allow_mdump) {
1682 DP_NOTICE(p_hwfn, false,
1683 "Not acknowledging the notification to allow the MFW crash dump\n");
1687 DP_NOTICE(p_hwfn, false,
1688 "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1689 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1690 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1693 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1694 struct ecore_ptt *p_ptt)
1696 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1697 enum _ecore_status_t rc = ECORE_SUCCESS;
1701 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1703 /* Read Messages from MFW */
1704 ecore_mcp_read_mb(p_hwfn, p_ptt);
1706 /* Compare current messages to old ones */
1707 for (i = 0; i < info->mfw_mb_length; i++) {
1708 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1713 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1714 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1715 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1718 case MFW_DRV_MSG_LINK_CHANGE:
1719 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1721 case MFW_DRV_MSG_VF_DISABLED:
1722 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1724 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1725 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1726 ECORE_DCBX_REMOTE_LLDP_MIB);
1728 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1729 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1730 ECORE_DCBX_REMOTE_MIB);
1732 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1733 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1734 ECORE_DCBX_OPERATIONAL_MIB);
1736 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1737 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1739 case MFW_DRV_MSG_ERROR_RECOVERY:
1740 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1742 case MFW_DRV_MSG_GET_LAN_STATS:
1743 case MFW_DRV_MSG_GET_FCOE_STATS:
1744 case MFW_DRV_MSG_GET_ISCSI_STATS:
1745 case MFW_DRV_MSG_GET_RDMA_STATS:
1746 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1748 case MFW_DRV_MSG_BW_UPDATE:
1749 ecore_mcp_update_bw(p_hwfn, p_ptt);
1751 case MFW_DRV_MSG_FAILURE_DETECTED:
1752 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1754 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1755 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1758 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1763 /* ACK everything */
1764 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1765 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1767 /* MFW expect answer in BE, so we force write in that format */
1768 ecore_wr(p_hwfn, p_ptt,
1769 info->mfw_mb_addr + sizeof(u32) +
1770 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1771 sizeof(u32) + i * sizeof(u32), val);
1775 DP_NOTICE(p_hwfn, false,
1776 "Received an MFW message indication but no"
1781 /* Copy the new mfw messages into the shadow */
1782 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1787 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1788 struct ecore_ptt *p_ptt,
1790 u32 *p_running_bundle_id)
1795 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1796 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1797 return ECORE_SUCCESS;
1801 if (IS_VF(p_hwfn->p_dev)) {
1802 if (p_hwfn->vf_iov_info) {
1803 struct pfvf_acquire_resp_tlv *p_resp;
1805 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1806 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1807 return ECORE_SUCCESS;
1809 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1810 "VF requested MFW version prior to ACQUIRE\n");
1815 global_offsize = ecore_rd(p_hwfn, p_ptt,
1816 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1820 ecore_rd(p_hwfn, p_ptt,
1821 SECTION_ADDR(global_offsize,
1822 0) + OFFSETOF(struct public_global, mfw_ver));
1824 if (p_running_bundle_id != OSAL_NULL) {
1825 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1826 SECTION_ADDR(global_offsize,
1828 OFFSETOF(struct public_global,
1829 running_bundle_id));
1832 return ECORE_SUCCESS;
1835 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
1836 struct ecore_ptt *p_ptt,
1840 /* TODO - Add support for VFs */
1841 if (IS_VF(p_hwfn->p_dev))
1844 if (!ecore_mcp_is_init(p_hwfn)) {
1845 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1850 *p_media_type = MEDIA_UNSPECIFIED;
1853 *p_media_type = ecore_rd(p_hwfn, p_ptt,
1854 p_hwfn->mcp_info->port_addr +
1855 OFFSETOF(struct public_port,
1859 return ECORE_SUCCESS;
1863 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1865 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
1866 enum ecore_pci_personality *p_proto)
1868 *p_proto = ECORE_PCI_ETH;
1870 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1871 "According to Legacy capabilities, L2 personality is %08x\n",
1876 static enum _ecore_status_t
1877 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
1878 struct ecore_ptt *p_ptt,
1879 enum ecore_pci_personality *p_proto)
1881 u32 resp = 0, param = 0;
1882 enum _ecore_status_t rc;
1884 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1885 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1886 (u32)*p_proto, resp, param);
1887 return ECORE_SUCCESS;
1890 static enum _ecore_status_t
1891 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1892 struct public_func *p_info,
1893 struct ecore_ptt *p_ptt,
1894 enum ecore_pci_personality *p_proto)
1896 enum _ecore_status_t rc = ECORE_SUCCESS;
1898 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1899 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1900 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
1902 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1911 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1912 struct ecore_ptt *p_ptt)
1914 struct ecore_mcp_function_info *info;
1915 struct public_func shmem_info;
1917 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1918 info = &p_hwfn->mcp_info->func_info;
1920 info->pause_on_host = (shmem_info.config &
1921 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1923 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1925 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1926 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1930 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1932 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1933 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1934 info->mac[1] = (u8)(shmem_info.mac_upper);
1935 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1936 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1937 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1938 info->mac[5] = (u8)(shmem_info.mac_lower);
1940 /* TODO - are there protocols for which there's no MAC? */
1941 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1944 /* TODO - are these calculations true for BE machine? */
1945 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1946 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1947 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1948 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1950 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1952 info->mtu = (u16)shmem_info.mtu_size;
1957 info->mtu = (u16)shmem_info.mtu_size;
1959 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1960 "Read configuration from shmem: pause_on_host %02x"
1961 " protocol %02x BW [%02x - %02x]"
1962 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1963 " node %lx ovlan %04x\n",
1964 info->pause_on_host, info->protocol,
1965 info->bandwidth_min, info->bandwidth_max,
1966 info->mac[0], info->mac[1], info->mac[2],
1967 info->mac[3], info->mac[4], info->mac[5],
1968 (unsigned long)info->wwn_port,
1969 (unsigned long)info->wwn_node, info->ovlan);
1971 return ECORE_SUCCESS;
1974 struct ecore_mcp_link_params
1975 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1977 if (!p_hwfn || !p_hwfn->mcp_info)
1979 return &p_hwfn->mcp_info->link_input;
1982 struct ecore_mcp_link_state
1983 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1985 if (!p_hwfn || !p_hwfn->mcp_info)
1989 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1990 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1991 p_hwfn->mcp_info->link_output.link_up = true;
1995 return &p_hwfn->mcp_info->link_output;
1998 struct ecore_mcp_link_capabilities
1999 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2001 if (!p_hwfn || !p_hwfn->mcp_info)
2003 return &p_hwfn->mcp_info->link_capabilities;
2006 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2007 struct ecore_ptt *p_ptt)
2009 u32 resp = 0, param = 0;
2010 enum _ecore_status_t rc;
2012 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2013 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
2015 /* Wait for the drain to complete before returning */
2021 const struct ecore_mcp_function_info
2022 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2024 if (!p_hwfn || !p_hwfn->mcp_info)
2026 return &p_hwfn->mcp_info->func_info;
2029 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
2030 struct ecore_ptt *p_ptt,
2031 struct ecore_mcp_nvm_params *params)
2033 enum _ecore_status_t rc;
2035 switch (params->type) {
2036 case ECORE_MCP_NVM_RD:
2037 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
2038 params->nvm_common.offset,
2039 ¶ms->nvm_common.resp,
2040 ¶ms->nvm_common.param,
2041 params->nvm_rd.buf_size,
2042 params->nvm_rd.buf);
2045 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
2046 params->nvm_common.offset,
2047 ¶ms->nvm_common.resp,
2048 ¶ms->nvm_common.param);
2050 case ECORE_MCP_NVM_WR:
2051 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
2052 params->nvm_common.offset,
2053 ¶ms->nvm_common.resp,
2054 ¶ms->nvm_common.param,
2055 params->nvm_wr.buf_size,
2056 params->nvm_wr.buf);
2065 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2066 struct ecore_ptt *p_ptt, u32 personalities)
2068 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2069 struct public_func shmem_info;
2070 int i, count = 0, num_pfs;
2072 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2074 for (i = 0; i < num_pfs; i++) {
2075 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2076 MCP_PF_ID_BY_REL(p_hwfn, i));
2077 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2080 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2085 if ((1 << ((u32)protocol)) & personalities)
2092 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2093 struct ecore_ptt *p_ptt,
2099 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2100 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2105 if (IS_VF(p_hwfn->p_dev))
2108 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2109 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2110 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2111 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2113 *p_flash_size = flash_size;
2115 return ECORE_SUCCESS;
2118 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2119 struct ecore_ptt *p_ptt)
2121 struct ecore_dev *p_dev = p_hwfn->p_dev;
2123 if (p_dev->recov_in_prog) {
2124 DP_NOTICE(p_hwfn, false,
2125 "Avoid triggering a recovery since such a process"
2126 " is already in progress\n");
2130 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2131 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2133 return ECORE_SUCCESS;
2136 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2137 struct ecore_ptt *p_ptt,
2140 u32 resp = 0, param = 0, rc_param = 0;
2141 enum _ecore_status_t rc;
2143 /* Only Leader can configure MSIX, and need to take CMT into account */
2145 if (!IS_LEAD_HWFN(p_hwfn))
2146 return ECORE_SUCCESS;
2147 num *= p_hwfn->p_dev->num_hwfns;
2149 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2150 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2151 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2152 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2154 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2157 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2158 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2162 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2163 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2170 enum _ecore_status_t
2171 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2172 struct ecore_mcp_drv_version *p_ver)
2174 struct ecore_mcp_mb_params mb_params;
2175 struct drv_version_stc drv_version;
2179 enum _ecore_status_t rc;
2182 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2183 return ECORE_SUCCESS;
2186 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2187 drv_version.version = p_ver->version;
2188 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2189 for (i = 0; i < num_words; i++) {
2190 /* The driver name is expected to be in a big-endian format */
2191 p_name = &p_ver->name[i * sizeof(u32)];
2192 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2193 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2196 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2197 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2198 mb_params.p_data_src = &drv_version;
2199 mb_params.data_src_size = sizeof(drv_version);
2200 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2201 if (rc != ECORE_SUCCESS)
2202 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2207 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2208 struct ecore_ptt *p_ptt)
2210 enum _ecore_status_t rc;
2211 u32 resp = 0, param = 0;
2213 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2215 if (rc != ECORE_SUCCESS)
2216 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2221 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2222 struct ecore_ptt *p_ptt)
2224 u32 value, cpu_mode;
2226 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2228 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2229 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2230 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2231 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2233 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2236 enum _ecore_status_t
2237 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2238 struct ecore_ptt *p_ptt,
2239 enum ecore_ov_client client)
2241 enum _ecore_status_t rc;
2242 u32 resp = 0, param = 0;
2246 case ECORE_OV_CLIENT_DRV:
2247 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2249 case ECORE_OV_CLIENT_USER:
2250 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2252 case ECORE_OV_CLIENT_VENDOR_SPEC:
2253 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2256 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2260 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2261 drv_mb_param, &resp, ¶m);
2262 if (rc != ECORE_SUCCESS)
2263 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2268 enum _ecore_status_t
2269 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2270 struct ecore_ptt *p_ptt,
2271 enum ecore_ov_driver_state drv_state)
2273 enum _ecore_status_t rc;
2274 u32 resp = 0, param = 0;
2277 switch (drv_state) {
2278 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2279 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2281 case ECORE_OV_DRIVER_STATE_DISABLED:
2282 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2284 case ECORE_OV_DRIVER_STATE_ACTIVE:
2285 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2288 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2292 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2293 drv_mb_param, &resp, ¶m);
2294 if (rc != ECORE_SUCCESS)
2295 DP_ERR(p_hwfn, "Failed to send driver state\n");
2300 enum _ecore_status_t
2301 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2302 struct ecore_fc_npiv_tbl *p_table)
2307 enum _ecore_status_t
2308 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2309 struct ecore_ptt *p_ptt, u16 mtu)
2314 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2315 struct ecore_ptt *p_ptt,
2316 enum ecore_led_mode mode)
2318 u32 resp = 0, param = 0, drv_mb_param;
2319 enum _ecore_status_t rc;
2322 case ECORE_LED_MODE_ON:
2323 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2325 case ECORE_LED_MODE_OFF:
2326 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2328 case ECORE_LED_MODE_RESTORE:
2329 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2332 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2336 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2337 drv_mb_param, &resp, ¶m);
2338 if (rc != ECORE_SUCCESS)
2339 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2344 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2345 struct ecore_ptt *p_ptt,
2348 u32 resp = 0, param = 0;
2349 enum _ecore_status_t rc;
2351 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2352 mask_parities, &resp, ¶m);
2354 if (rc != ECORE_SUCCESS) {
2356 "MCP response failure for mask parities, aborting\n");
2357 } else if (resp != FW_MSG_CODE_OK) {
2359 "MCP did not ack mask parity request. Old MFW?\n");
2366 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2369 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2370 u32 bytes_left, offset, bytes_to_copy, buf_size;
2371 struct ecore_mcp_nvm_params params;
2372 struct ecore_ptt *p_ptt;
2373 enum _ecore_status_t rc = ECORE_SUCCESS;
2375 p_ptt = ecore_ptt_acquire(p_hwfn);
2379 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2382 params.type = ECORE_MCP_NVM_RD;
2383 params.nvm_rd.buf_size = &buf_size;
2384 params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
2385 while (bytes_left > 0) {
2386 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2387 MCP_DRV_NVM_BUF_LEN);
2388 params.nvm_common.offset = (addr + offset) |
2389 (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
2390 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2391 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2392 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
2393 FW_MSG_CODE_NVM_OK)) {
2394 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2398 /* This can be a lengthy process, and it's possible scheduler
2399 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2401 if (bytes_left % 0x1000 <
2402 (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
2405 offset += *params.nvm_rd.buf_size;
2406 bytes_left -= *params.nvm_rd.buf_size;
2409 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2410 ecore_ptt_release(p_hwfn, p_ptt);
2415 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2416 u32 addr, u8 *p_buf, u32 len)
2418 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2419 struct ecore_mcp_nvm_params params;
2420 struct ecore_ptt *p_ptt;
2421 enum _ecore_status_t rc;
2423 p_ptt = ecore_ptt_acquire(p_hwfn);
2427 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2428 params.type = ECORE_MCP_NVM_RD;
2429 params.nvm_rd.buf_size = &len;
2430 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
2431 DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
2432 params.nvm_common.offset = addr;
2433 params.nvm_rd.buf = (u32 *)p_buf;
2434 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2435 if (rc != ECORE_SUCCESS)
2436 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2438 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2439 ecore_ptt_release(p_hwfn, p_ptt);
2444 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2446 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2447 struct ecore_mcp_nvm_params params;
2448 struct ecore_ptt *p_ptt;
2450 p_ptt = ecore_ptt_acquire(p_hwfn);
2454 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2455 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2456 ecore_ptt_release(p_hwfn, p_ptt);
2458 return ECORE_SUCCESS;
2461 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2463 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2464 struct ecore_mcp_nvm_params params;
2465 struct ecore_ptt *p_ptt;
2466 enum _ecore_status_t rc;
2468 p_ptt = ecore_ptt_acquire(p_hwfn);
2471 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2472 params.type = ECORE_MCP_CMD;
2473 params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
2474 params.nvm_common.offset = addr;
2475 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2476 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2477 ecore_ptt_release(p_hwfn, p_ptt);
2482 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2485 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2486 struct ecore_mcp_nvm_params params;
2487 struct ecore_ptt *p_ptt;
2488 enum _ecore_status_t rc;
2490 p_ptt = ecore_ptt_acquire(p_hwfn);
2493 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2494 params.type = ECORE_MCP_CMD;
2495 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
2496 params.nvm_common.offset = addr;
2497 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2498 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2499 ecore_ptt_release(p_hwfn, p_ptt);
2504 /* rc receives ECORE_INVAL as default parameter because
2505 * it might not enter the while loop if the len is 0
2507 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2508 u32 addr, u8 *p_buf, u32 len)
2510 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2511 enum _ecore_status_t rc = ECORE_INVAL;
2512 struct ecore_mcp_nvm_params params;
2513 struct ecore_ptt *p_ptt;
2514 u32 buf_idx, buf_size;
2516 p_ptt = ecore_ptt_acquire(p_hwfn);
2520 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2521 params.type = ECORE_MCP_NVM_WR;
2522 if (cmd == ECORE_PUT_FILE_DATA)
2523 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2525 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2527 while (buf_idx < len) {
2528 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2529 MCP_DRV_NVM_BUF_LEN);
2530 params.nvm_common.offset = ((buf_size <<
2531 DRV_MB_PARAM_NVM_LEN_SHIFT)
2533 params.nvm_wr.buf_size = buf_size;
2534 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2535 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2536 if (rc != ECORE_SUCCESS ||
2537 ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2538 (params.nvm_common.resp !=
2539 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2540 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2542 /* This can be a lengthy process, and it's possible scheduler
2543 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2545 if (buf_idx % 0x1000 >
2546 (buf_idx + buf_size) % 0x1000)
2549 buf_idx += buf_size;
2552 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2553 ecore_ptt_release(p_hwfn, p_ptt);
2558 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2559 u32 addr, u8 *p_buf, u32 len)
2561 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2562 struct ecore_mcp_nvm_params params;
2563 struct ecore_ptt *p_ptt;
2564 enum _ecore_status_t rc;
2566 p_ptt = ecore_ptt_acquire(p_hwfn);
2570 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2571 params.type = ECORE_MCP_NVM_WR;
2572 params.nvm_wr.buf_size = len;
2573 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2574 DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2575 params.nvm_common.offset = addr;
2576 params.nvm_wr.buf = (u32 *)p_buf;
2577 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2578 if (rc != ECORE_SUCCESS)
2579 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2580 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2581 ecore_ptt_release(p_hwfn, p_ptt);
2586 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2589 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2590 struct ecore_mcp_nvm_params params;
2591 struct ecore_ptt *p_ptt;
2592 enum _ecore_status_t rc;
2594 p_ptt = ecore_ptt_acquire(p_hwfn);
2598 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2599 params.type = ECORE_MCP_CMD;
2600 params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2601 params.nvm_common.offset = addr;
2602 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2603 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2604 ecore_ptt_release(p_hwfn, p_ptt);
2609 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2610 struct ecore_ptt *p_ptt,
2611 u32 port, u32 addr, u32 offset,
2614 struct ecore_mcp_nvm_params params;
2615 enum _ecore_status_t rc;
2616 u32 bytes_left, bytes_to_copy, buf_size;
2618 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2619 params.nvm_common.offset =
2620 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2621 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2625 params.type = ECORE_MCP_NVM_RD;
2626 params.nvm_rd.buf_size = &buf_size;
2627 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2628 while (bytes_left > 0) {
2629 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2630 MAX_I2C_TRANSACTION_SIZE);
2631 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2632 params.nvm_common.offset &=
2633 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2634 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2635 params.nvm_common.offset |=
2637 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2638 params.nvm_common.offset |=
2639 (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2640 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2641 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2642 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2644 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2645 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2646 return ECORE_UNKNOWN_ERROR;
2648 offset += *params.nvm_rd.buf_size;
2649 bytes_left -= *params.nvm_rd.buf_size;
2652 return ECORE_SUCCESS;
2655 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2656 struct ecore_ptt *p_ptt,
2657 u32 port, u32 addr, u32 offset,
2660 struct ecore_mcp_nvm_params params;
2661 enum _ecore_status_t rc;
2662 u32 buf_idx, buf_size;
2664 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2665 params.nvm_common.offset =
2666 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2667 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2668 params.type = ECORE_MCP_NVM_WR;
2669 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2671 while (buf_idx < len) {
2672 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2673 MAX_I2C_TRANSACTION_SIZE);
2674 params.nvm_common.offset &=
2675 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2676 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2677 params.nvm_common.offset |=
2678 ((offset + buf_idx) <<
2679 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2680 params.nvm_common.offset |=
2681 (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2682 params.nvm_wr.buf_size = buf_size;
2683 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2684 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2685 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2686 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2688 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2689 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2690 return ECORE_UNKNOWN_ERROR;
2692 buf_idx += buf_size;
2695 return ECORE_SUCCESS;
2698 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2699 struct ecore_ptt *p_ptt,
2700 u16 gpio, u32 *gpio_val)
2702 enum _ecore_status_t rc = ECORE_SUCCESS;
2703 u32 drv_mb_param = 0, rsp;
2705 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2707 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2708 drv_mb_param, &rsp, gpio_val);
2710 if (rc != ECORE_SUCCESS)
2713 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2714 return ECORE_UNKNOWN_ERROR;
2716 return ECORE_SUCCESS;
2719 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2720 struct ecore_ptt *p_ptt,
2721 u16 gpio, u16 gpio_val)
2723 enum _ecore_status_t rc = ECORE_SUCCESS;
2724 u32 drv_mb_param = 0, param, rsp;
2726 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2727 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2729 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2730 drv_mb_param, &rsp, ¶m);
2732 if (rc != ECORE_SUCCESS)
2735 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2736 return ECORE_UNKNOWN_ERROR;
2738 return ECORE_SUCCESS;
2741 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2742 struct ecore_ptt *p_ptt,
2743 u16 gpio, u32 *gpio_direction,
2746 u32 drv_mb_param = 0, rsp, val = 0;
2747 enum _ecore_status_t rc = ECORE_SUCCESS;
2749 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2751 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2752 drv_mb_param, &rsp, &val);
2753 if (rc != ECORE_SUCCESS)
2756 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2757 DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2758 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2759 DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2761 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2762 return ECORE_UNKNOWN_ERROR;
2764 return ECORE_SUCCESS;
2767 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2768 struct ecore_ptt *p_ptt)
2770 u32 drv_mb_param = 0, rsp, param;
2771 enum _ecore_status_t rc = ECORE_SUCCESS;
2773 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2774 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2776 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2777 drv_mb_param, &rsp, ¶m);
2779 if (rc != ECORE_SUCCESS)
2782 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2783 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2784 rc = ECORE_UNKNOWN_ERROR;
2789 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2790 struct ecore_ptt *p_ptt)
2792 u32 drv_mb_param, rsp, param;
2793 enum _ecore_status_t rc = ECORE_SUCCESS;
2795 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2796 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2798 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2799 drv_mb_param, &rsp, ¶m);
2801 if (rc != ECORE_SUCCESS)
2804 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2805 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2806 rc = ECORE_UNKNOWN_ERROR;
2811 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2812 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2814 u32 drv_mb_param = 0, rsp;
2815 enum _ecore_status_t rc = ECORE_SUCCESS;
2817 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2818 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2820 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2821 drv_mb_param, &rsp, num_images);
2823 if (rc != ECORE_SUCCESS)
2826 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2827 rc = ECORE_UNKNOWN_ERROR;
2832 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2833 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2834 struct bist_nvm_image_att *p_image_att, u32 image_index)
2836 struct ecore_mcp_nvm_params params;
2837 enum _ecore_status_t rc;
2840 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2841 params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2842 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2843 params.nvm_common.offset |= (image_index <<
2844 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2846 params.type = ECORE_MCP_NVM_RD;
2847 params.nvm_rd.buf_size = &buf_size;
2848 params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2849 params.nvm_rd.buf = (u32 *)p_image_att;
2851 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2852 if (rc != ECORE_SUCCESS)
2855 if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2856 (p_image_att->return_code != 1))
2857 rc = ECORE_UNKNOWN_ERROR;
2862 enum _ecore_status_t
2863 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2864 struct ecore_ptt *p_ptt,
2865 struct ecore_temperature_info *p_temp_info)
2867 struct ecore_temperature_sensor *p_temp_sensor;
2868 struct temperature_status_stc mfw_temp_info;
2869 struct ecore_mcp_mb_params mb_params;
2871 enum _ecore_status_t rc;
2874 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2875 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2876 mb_params.p_data_dst = &mfw_temp_info;
2877 mb_params.data_dst_size = sizeof(mfw_temp_info);
2878 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2879 if (rc != ECORE_SUCCESS)
2882 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2883 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2884 ECORE_MAX_NUM_OF_SENSORS);
2885 for (i = 0; i < p_temp_info->num_sensors; i++) {
2886 val = mfw_temp_info.sensor[i];
2887 p_temp_sensor = &p_temp_info->sensors[i];
2888 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2889 SENSOR_LOCATION_SHIFT;
2890 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2891 THRESHOLD_HIGH_SHIFT;
2892 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2893 CRITICAL_TEMPERATURE_SHIFT;
2894 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2898 return ECORE_SUCCESS;
2901 enum _ecore_status_t ecore_mcp_get_mba_versions(
2902 struct ecore_hwfn *p_hwfn,
2903 struct ecore_ptt *p_ptt,
2904 struct ecore_mba_vers *p_mba_vers)
2906 struct ecore_mcp_nvm_params params;
2907 enum _ecore_status_t rc;
2910 OSAL_MEM_ZERO(¶ms, sizeof(params));
2911 params.type = ECORE_MCP_NVM_RD;
2912 params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2913 params.nvm_common.offset = 0;
2914 params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2915 params.nvm_rd.buf_size = &buf_size;
2916 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2918 if (rc != ECORE_SUCCESS)
2921 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2923 rc = ECORE_UNKNOWN_ERROR;
2925 if (buf_size != MCP_DRV_NVM_BUF_LEN)
2926 rc = ECORE_UNKNOWN_ERROR;
2931 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2932 struct ecore_ptt *p_ptt,
2937 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2938 0, &rsp, (u32 *)num_events);
2941 static enum resource_id_enum
2942 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
2944 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2948 mfw_res_id = RESOURCE_NUM_SB_E;
2950 case ECORE_L2_QUEUE:
2951 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2954 mfw_res_id = RESOURCE_NUM_VPORT_E;
2957 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2960 mfw_res_id = RESOURCE_NUM_PQ_E;
2963 mfw_res_id = RESOURCE_NUM_RL_E;
2967 /* Each VFC resource can accommodate both a MAC and a VLAN */
2968 mfw_res_id = RESOURCE_VFC_FILTER_E;
2971 mfw_res_id = RESOURCE_ILT_E;
2973 case ECORE_LL2_QUEUE:
2974 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2976 case ECORE_RDMA_CNQ_RAM:
2977 case ECORE_CMDQS_CQS:
2978 /* CNQ/CMDQS are the same resource */
2979 mfw_res_id = RESOURCE_CQS_E;
2981 case ECORE_RDMA_STATS_QUEUE:
2982 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2985 mfw_res_id = RESOURCE_BDQ_E;
2994 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
2995 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
2996 #define ECORE_RESC_ALLOC_VERSION \
2997 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
2998 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2999 (ECORE_RESC_ALLOC_VERSION_MINOR << \
3000 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
3002 struct ecore_resc_alloc_in_params {
3004 enum ecore_resources res_id;
3008 struct ecore_resc_alloc_out_params {
3018 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
3020 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3022 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3023 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3024 enum _ecore_status_t rc;
3026 /* Allow ongoing PCIe transactions to complete */
3027 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3029 /* Clear the PF's internal FID_enable in the PXP */
3030 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3031 if (rc != ECORE_SUCCESS)
3032 DP_NOTICE(p_hwfn, false,
3033 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3039 static enum _ecore_status_t
3040 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3041 struct ecore_ptt *p_ptt,
3042 struct ecore_resc_alloc_in_params *p_in_params,
3043 struct ecore_resc_alloc_out_params *p_out_params)
3045 struct ecore_mcp_mb_params mb_params;
3046 struct resource_info mfw_resc_info;
3047 enum _ecore_status_t rc;
3049 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3051 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3052 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3054 "Failed to match resource %d [%s] with the MFW resources\n",
3055 p_in_params->res_id,
3056 ecore_hw_get_resc_name(p_in_params->res_id));
3060 switch (p_in_params->cmd) {
3061 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3062 mfw_resc_info.size = p_in_params->resc_max_val;
3064 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3067 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3072 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3073 mb_params.cmd = p_in_params->cmd;
3074 mb_params.param = ECORE_RESC_ALLOC_VERSION;
3075 mb_params.p_data_src = &mfw_resc_info;
3076 mb_params.data_src_size = sizeof(mfw_resc_info);
3077 mb_params.p_data_dst = mb_params.p_data_src;
3078 mb_params.data_dst_size = mb_params.data_src_size;
3080 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3081 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3082 p_in_params->cmd, p_in_params->res_id,
3083 ecore_hw_get_resc_name(p_in_params->res_id),
3084 ECORE_MFW_GET_FIELD(mb_params.param,
3085 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3086 ECORE_MFW_GET_FIELD(mb_params.param,
3087 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3088 p_in_params->resc_max_val);
3090 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3091 if (rc != ECORE_SUCCESS)
3094 p_out_params->mcp_resp = mb_params.mcp_resp;
3095 p_out_params->mcp_param = mb_params.mcp_param;
3096 p_out_params->resc_num = mfw_resc_info.size;
3097 p_out_params->resc_start = mfw_resc_info.offset;
3098 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3099 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3100 p_out_params->flags = mfw_resc_info.flags;
3102 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3103 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3104 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3105 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3106 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3107 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3108 p_out_params->resc_num, p_out_params->resc_start,
3109 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3110 p_out_params->flags);
3112 return ECORE_SUCCESS;
3115 enum _ecore_status_t
3116 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3117 enum ecore_resources res_id, u32 resc_max_val,
3120 struct ecore_resc_alloc_out_params out_params;
3121 struct ecore_resc_alloc_in_params in_params;
3122 enum _ecore_status_t rc;
3124 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3125 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3126 in_params.res_id = res_id;
3127 in_params.resc_max_val = resc_max_val;
3128 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3129 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3131 if (rc != ECORE_SUCCESS)
3134 *p_mcp_resp = out_params.mcp_resp;
3136 return ECORE_SUCCESS;
3139 enum _ecore_status_t
3140 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3141 enum ecore_resources res_id, u32 *p_mcp_resp,
3142 u32 *p_resc_num, u32 *p_resc_start)
3144 struct ecore_resc_alloc_out_params out_params;
3145 struct ecore_resc_alloc_in_params in_params;
3146 enum _ecore_status_t rc;
3148 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3149 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3150 in_params.res_id = res_id;
3151 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3152 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3154 if (rc != ECORE_SUCCESS)
3157 *p_mcp_resp = out_params.mcp_resp;
3159 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3160 *p_resc_num = out_params.resc_num;
3161 *p_resc_start = out_params.resc_start;
3164 return ECORE_SUCCESS;
3167 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3168 struct ecore_ptt *p_ptt)
3170 u32 mcp_resp, mcp_param;
3172 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3173 &mcp_resp, &mcp_param);
3176 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3177 struct ecore_ptt *p_ptt,
3178 u32 param, u32 *p_mcp_resp,
3181 enum _ecore_status_t rc;
3183 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3184 p_mcp_resp, p_mcp_param);
3185 if (rc != ECORE_SUCCESS)
3188 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3190 "The resource command is unsupported by the MFW\n");
3191 return ECORE_NOTIMPL;
3194 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3195 u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3197 DP_NOTICE(p_hwfn, false,
3198 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3206 enum _ecore_status_t
3207 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3208 struct ecore_resc_lock_params *p_params)
3210 u32 param = 0, mcp_resp, mcp_param;
3212 enum _ecore_status_t rc;
3214 switch (p_params->timeout) {
3215 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3216 opcode = RESOURCE_OPCODE_REQ;
3217 p_params->timeout = 0;
3219 case ECORE_MCP_RESC_LOCK_TO_NONE:
3220 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3221 p_params->timeout = 0;
3224 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3228 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3229 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3230 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3232 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3233 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3234 param, p_params->timeout, opcode, p_params->resource);
3236 /* Attempt to acquire the resource */
3237 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3239 if (rc != ECORE_SUCCESS)
3242 /* Analyze the response */
3243 p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
3244 RESOURCE_CMD_RSP_OWNER);
3245 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3247 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3248 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3249 mcp_param, opcode, p_params->owner);
3252 case RESOURCE_OPCODE_GNT:
3253 p_params->b_granted = true;
3255 case RESOURCE_OPCODE_BUSY:
3256 p_params->b_granted = false;
3259 DP_NOTICE(p_hwfn, false,
3260 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3265 return ECORE_SUCCESS;
3268 enum _ecore_status_t
3269 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3270 struct ecore_resc_lock_params *p_params)
3273 enum _ecore_status_t rc;
3276 /* No need for an interval before the first iteration */
3278 if (p_params->sleep_b4_retry) {
3279 u16 retry_interval_in_ms =
3280 DIV_ROUND_UP(p_params->retry_interval,
3283 OSAL_MSLEEP(retry_interval_in_ms);
3285 OSAL_UDELAY(p_params->retry_interval);
3289 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3290 if (rc != ECORE_SUCCESS)
3293 if (p_params->b_granted)
3295 } while (retry_cnt++ < p_params->retry_num);
3297 return ECORE_SUCCESS;
3300 enum _ecore_status_t
3301 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3302 struct ecore_resc_unlock_params *p_params)
3304 u32 param = 0, mcp_resp, mcp_param;
3306 enum _ecore_status_t rc;
3308 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3309 : RESOURCE_OPCODE_RELEASE;
3310 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3311 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3313 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3314 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3315 param, opcode, p_params->resource);
3317 /* Attempt to release the resource */
3318 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3320 if (rc != ECORE_SUCCESS)
3323 /* Analyze the response */
3324 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3326 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3327 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3331 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3333 "Resource unlock request for an already released resource [%d]\n",
3334 p_params->resource);
3336 case RESOURCE_OPCODE_RELEASED:
3337 p_params->b_released = true;
3339 case RESOURCE_OPCODE_WRONG_OWNER:
3340 p_params->b_released = false;
3343 DP_NOTICE(p_hwfn, false,
3344 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3349 return ECORE_SUCCESS;
3352 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3354 return !!(p_hwfn->mcp_info->capabilities &
3355 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3358 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3359 struct ecore_ptt *p_ptt)
3362 enum _ecore_status_t rc;
3364 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3365 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3366 if (rc == ECORE_SUCCESS)
3367 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3368 "MFW supported features: %08x\n",
3369 p_hwfn->mcp_info->capabilities);
3374 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3375 struct ecore_ptt *p_ptt)
3377 u32 mcp_resp, mcp_param, features;
3379 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3380 DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3382 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3383 features, &mcp_resp, &mcp_param);