2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
24 #define CHIP_MCP_RESP_ITER_US 10
25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 OFFSETOF(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 OFFSETOF(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_SHIFT)
48 #define MCP_BYTES_PER_MBIT_SHIFT 17
52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
57 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
64 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
66 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
68 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
70 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
71 "port_addr = 0x%x, port_id 0x%02x\n",
72 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
77 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
82 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
86 if (!p_hwfn->mcp_info->public_base)
89 for (i = 0; i < length; i++) {
90 tmp = ecore_rd(p_hwfn, p_ptt,
91 p_hwfn->mcp_info->mfw_mb_addr +
92 (i << 2) + sizeof(u32));
94 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
95 OSAL_BE32_TO_CPU(tmp);
99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
101 if (p_hwfn->mcp_info) {
102 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
103 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
104 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
106 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
108 return ECORE_SUCCESS;
111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt)
114 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
115 u32 drv_mb_offsize, mfw_mb_offsize;
116 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
119 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
120 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
121 p_info->public_base = 0;
126 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
127 if (!p_info->public_base)
130 p_info->public_base |= GRCBASE_MCP;
132 /* Calculate the driver and MFW mailbox address */
133 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
134 SECTION_OFFSIZE_ADDR(p_info->public_base,
136 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
138 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
139 " mcp_pf_id = 0x%x\n",
140 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
142 /* Set the MFW MB address */
143 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
144 SECTION_OFFSIZE_ADDR(p_info->public_base,
146 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
147 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
148 p_info->mfw_mb_addr);
150 /* Get the current driver mailbox sequence before sending
153 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
154 DRV_MSG_SEQ_NUMBER_MASK;
156 /* Get current FW pulse sequence */
157 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
160 p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
161 MISCS_REG_GENERIC_POR_0);
163 return ECORE_SUCCESS;
166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
167 struct ecore_ptt *p_ptt)
169 struct ecore_mcp_info *p_info;
172 /* Allocate mcp_info structure */
173 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
174 sizeof(*p_hwfn->mcp_info));
175 if (!p_hwfn->mcp_info)
177 p_info = p_hwfn->mcp_info;
179 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
180 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
181 /* Do not free mcp_info here, since public_base indicate that
182 * the MCP is not initialized
184 return ECORE_SUCCESS;
187 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
188 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
189 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
190 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
193 /* Initialize the MFW spinlock */
194 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
195 OSAL_SPIN_LOCK_INIT(&p_info->lock);
197 return ECORE_SUCCESS;
200 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
201 ecore_mcp_free(p_hwfn);
205 /* Locks the MFW mailbox of a PF to ensure a single access.
206 * The lock is achieved in most cases by holding a spinlock, causing other
207 * threads to wait till a previous access is done.
208 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
209 * access is achieved by setting a blocking flag, which will fail other
210 * competing contexts to send their mailboxes.
212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
215 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
217 /* The spinlock shouldn't be acquired when the mailbox command is
218 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
219 * pending [UN]LOAD_REQ command of another PF together with a spinlock
220 * (i.e. interrupts are disabled) - can lead to a deadlock.
221 * It is assumed that for a single PF, no other mailbox commands can be
222 * sent from another context while sending LOAD_REQ, and that any
223 * parallel commands to UNLOAD_REQ can be cancelled.
225 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
226 p_hwfn->mcp_info->block_mb_sending = false;
228 /* There's at least a single command that is sent by ecore during the
229 * load sequence [expectation of MFW].
231 if ((p_hwfn->mcp_info->block_mb_sending) &&
232 (cmd != DRV_MSG_CODE_FEATURE_SUPPORT)) {
233 DP_NOTICE(p_hwfn, false,
234 "Trying to send a MFW mailbox command [0x%x]"
235 " in parallel to [UN]LOAD_REQ. Aborting.\n",
237 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
241 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
242 p_hwfn->mcp_info->block_mb_sending = true;
243 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
246 return ECORE_SUCCESS;
249 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
251 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
252 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
255 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
256 struct ecore_ptt *p_ptt)
258 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
259 u32 delay = CHIP_MCP_RESP_ITER_US;
260 u32 org_mcp_reset_seq, cnt = 0;
261 enum _ecore_status_t rc = ECORE_SUCCESS;
264 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
265 delay = EMUL_MCP_RESP_ITER_US;
268 /* Ensure that only a single thread is accessing the mailbox at a
271 rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
272 if (rc != ECORE_SUCCESS)
275 /* Set drv command along with the updated sequence */
276 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
277 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
280 /* Wait for MFW response */
282 /* Give the FW up to 500 second (50*1000*10usec) */
283 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
284 MISCS_REG_GENERIC_POR_0)) &&
285 (cnt++ < ECORE_MCP_RESET_RETRIES));
287 if (org_mcp_reset_seq !=
288 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
289 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
290 "MCP was reset after %d usec\n", cnt * delay);
292 DP_ERR(p_hwfn, "Failed to reset MCP\n");
296 ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
301 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
302 struct ecore_ptt *p_ptt,
307 u32 delay = CHIP_MCP_RESP_ITER_US;
308 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
309 u32 seq, cnt = 1, actual_mb_seq;
310 enum _ecore_status_t rc = ECORE_SUCCESS;
313 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
314 delay = EMUL_MCP_RESP_ITER_US;
315 /* There is a built-in delay of 100usec in each MFW response read */
316 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
320 /* Get actual driver mailbox sequence */
321 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
322 DRV_MSG_SEQ_NUMBER_MASK;
324 /* Use MCP history register to check if MCP reset occurred between
327 if (p_hwfn->mcp_info->mcp_hist !=
328 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
329 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
330 ecore_load_mcp_offsets(p_hwfn, p_ptt);
331 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
333 seq = ++p_hwfn->mcp_info->drv_mb_seq;
336 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
338 /* Set drv command along with the updated sequence */
339 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
342 /* Wait for MFW response */
344 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
346 /* Give the FW up to 5 second (500*10ms) */
347 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
348 (cnt++ < max_retries));
350 /* Is this a reply to our command? */
351 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
352 *o_mcp_resp &= FW_MSG_CODE_MASK;
353 /* Get the MCP param */
354 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
357 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
361 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
366 static enum _ecore_status_t
367 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
368 struct ecore_ptt *p_ptt,
369 struct ecore_mcp_mb_params *p_mb_params)
371 union drv_union_data union_data;
373 enum _ecore_status_t rc;
375 /* MCP not initialized */
376 if (!ecore_mcp_is_init(p_hwfn)) {
377 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
381 if (p_mb_params->data_src_size > sizeof(union_data) ||
382 p_mb_params->data_dst_size > sizeof(union_data)) {
384 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
385 p_mb_params->data_src_size, p_mb_params->data_dst_size,
390 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
391 OFFSETOF(struct public_drv_mb, union_data);
393 /* Ensure that only a single thread is accessing the mailbox at a
396 rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
397 if (rc != ECORE_SUCCESS)
400 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
401 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
402 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
403 p_mb_params->data_src_size);
404 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
407 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
408 p_mb_params->param, &p_mb_params->mcp_resp,
409 &p_mb_params->mcp_param);
411 if (p_mb_params->p_data_dst != OSAL_NULL &&
412 p_mb_params->data_dst_size)
413 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
414 union_data_addr, p_mb_params->data_dst_size);
416 ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
421 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
422 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
423 u32 *o_mcp_resp, u32 *o_mcp_param)
425 struct ecore_mcp_mb_params mb_params;
426 enum _ecore_status_t rc;
429 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
430 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
432 loaded_port[p_hwfn->port_id]--;
433 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
436 return ECORE_SUCCESS;
440 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
442 mb_params.param = param;
443 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
444 if (rc != ECORE_SUCCESS)
447 *o_mcp_resp = mb_params.mcp_resp;
448 *o_mcp_param = mb_params.mcp_param;
450 return ECORE_SUCCESS;
453 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
454 struct ecore_ptt *p_ptt,
459 u32 i_txn_size, u32 *i_buf)
461 struct ecore_mcp_mb_params mb_params;
462 enum _ecore_status_t rc;
464 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
466 mb_params.param = param;
467 mb_params.p_data_src = i_buf;
468 mb_params.data_src_size = (u8)i_txn_size;
469 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
470 if (rc != ECORE_SUCCESS)
473 *o_mcp_resp = mb_params.mcp_resp;
474 *o_mcp_param = mb_params.mcp_param;
476 return ECORE_SUCCESS;
479 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
480 struct ecore_ptt *p_ptt,
485 u32 *o_txn_size, u32 *o_buf)
487 struct ecore_mcp_mb_params mb_params;
488 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
489 enum _ecore_status_t rc;
491 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
493 mb_params.param = param;
494 mb_params.p_data_dst = raw_data;
496 /* Use the maximal value since the actual one is part of the response */
497 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
499 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
500 if (rc != ECORE_SUCCESS)
503 *o_mcp_resp = mb_params.mcp_resp;
504 *o_mcp_param = mb_params.mcp_param;
506 *o_txn_size = *o_mcp_param;
508 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
510 return ECORE_SUCCESS;
514 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
517 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
520 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
521 else if (!loaded_port[p_hwfn->port_id])
522 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
524 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
526 /* On CMT, always tell that it's engine */
527 if (p_hwfn->p_dev->num_hwfns > 1)
528 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
530 *p_load_code = load_phase;
532 loaded_port[p_hwfn->port_id]++;
534 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
535 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
536 *p_load_code, loaded, p_hwfn->port_id,
537 loaded_port[p_hwfn->port_id]);
542 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
543 enum ecore_override_force_load override_force_load)
545 bool can_force_load = false;
547 switch (override_force_load) {
548 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
549 can_force_load = true;
551 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
552 can_force_load = false;
555 can_force_load = (drv_role == DRV_ROLE_OS &&
556 exist_drv_role == DRV_ROLE_PREBOOT) ||
557 (drv_role == DRV_ROLE_KDUMP &&
558 exist_drv_role == DRV_ROLE_OS);
562 return can_force_load;
565 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
566 struct ecore_ptt *p_ptt)
568 u32 resp = 0, param = 0;
569 enum _ecore_status_t rc;
571 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
573 if (rc != ECORE_SUCCESS)
574 DP_NOTICE(p_hwfn, false,
575 "Failed to send cancel load request, rc = %d\n", rc);
580 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
581 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
582 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
583 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
584 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
585 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
586 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
588 static u32 ecore_get_config_bitmap(void)
590 u32 config_bitmap = 0x0;
592 #ifdef CONFIG_ECORE_L2
593 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
595 #ifdef CONFIG_ECORE_SRIOV
596 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
598 #ifdef CONFIG_ECORE_ROCE
599 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
601 #ifdef CONFIG_ECORE_IWARP
602 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
604 #ifdef CONFIG_ECORE_FCOE
605 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
607 #ifdef CONFIG_ECORE_ISCSI
608 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
610 #ifdef CONFIG_ECORE_LL2
611 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
614 return config_bitmap;
617 struct ecore_load_req_in_params {
619 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
620 #define ECORE_LOAD_REQ_HSI_VER_1 1
627 bool avoid_eng_reset;
630 struct ecore_load_req_out_params {
640 static enum _ecore_status_t
641 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
642 struct ecore_load_req_in_params *p_in_params,
643 struct ecore_load_req_out_params *p_out_params)
645 struct ecore_mcp_mb_params mb_params;
646 struct load_req_stc load_req;
647 struct load_rsp_stc load_rsp;
649 enum _ecore_status_t rc;
651 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
652 load_req.drv_ver_0 = p_in_params->drv_ver_0;
653 load_req.drv_ver_1 = p_in_params->drv_ver_1;
654 load_req.fw_ver = p_in_params->fw_ver;
655 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
656 p_in_params->drv_role);
657 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
658 p_in_params->timeout_val);
659 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
660 p_in_params->force_cmd);
661 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
662 p_in_params->avoid_eng_reset);
664 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
665 DRV_ID_MCP_HSI_VER_CURRENT :
666 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
668 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
669 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
670 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
671 mb_params.p_data_src = &load_req;
672 mb_params.data_src_size = sizeof(load_req);
673 mb_params.p_data_dst = &load_rsp;
674 mb_params.data_dst_size = sizeof(load_rsp);
676 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
677 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
679 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
680 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
681 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
682 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
684 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
685 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
686 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
687 load_req.drv_ver_0, load_req.drv_ver_1,
688 load_req.fw_ver, load_req.misc0,
689 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
690 ECORE_MFW_GET_FIELD(load_req.misc0,
692 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
693 ECORE_MFW_GET_FIELD(load_req.misc0,
696 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
697 if (rc != ECORE_SUCCESS) {
698 DP_NOTICE(p_hwfn, false,
699 "Failed to send load request, rc = %d\n", rc);
703 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
704 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
705 p_out_params->load_code = mb_params.mcp_resp;
707 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
708 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
709 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
710 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
711 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
712 load_rsp.fw_ver, load_rsp.misc0,
713 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
714 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
715 ECORE_MFW_GET_FIELD(load_rsp.misc0,
718 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
719 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
720 p_out_params->exist_fw_ver = load_rsp.fw_ver;
721 p_out_params->exist_drv_role =
722 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
723 p_out_params->mfw_hsi_ver =
724 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
725 p_out_params->drv_exists =
726 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
727 LOAD_RSP_FLAGS0_DRV_EXISTS;
730 return ECORE_SUCCESS;
733 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
734 enum ecore_drv_role drv_role,
738 case ECORE_DRV_ROLE_OS:
739 *p_mfw_drv_role = DRV_ROLE_OS;
741 case ECORE_DRV_ROLE_KDUMP:
742 *p_mfw_drv_role = DRV_ROLE_KDUMP;
747 enum ecore_load_req_force {
748 ECORE_LOAD_REQ_FORCE_NONE,
749 ECORE_LOAD_REQ_FORCE_PF,
750 ECORE_LOAD_REQ_FORCE_ALL,
753 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
754 enum ecore_load_req_force force_cmd,
758 case ECORE_LOAD_REQ_FORCE_NONE:
759 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
761 case ECORE_LOAD_REQ_FORCE_PF:
762 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
764 case ECORE_LOAD_REQ_FORCE_ALL:
765 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
770 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
771 struct ecore_ptt *p_ptt,
772 struct ecore_load_req_params *p_params)
774 struct ecore_load_req_out_params out_params;
775 struct ecore_load_req_in_params in_params;
776 u8 mfw_drv_role = 0, mfw_force_cmd;
777 enum _ecore_status_t rc;
780 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
781 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
782 return ECORE_SUCCESS;
786 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
787 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
788 in_params.drv_ver_0 = ECORE_VERSION;
789 in_params.drv_ver_1 = ecore_get_config_bitmap();
790 in_params.fw_ver = STORM_FW_VERSION;
791 ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
792 in_params.drv_role = mfw_drv_role;
793 in_params.timeout_val = p_params->timeout_val;
794 ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
796 in_params.force_cmd = mfw_force_cmd;
797 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
799 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
800 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
801 if (rc != ECORE_SUCCESS)
804 /* First handle cases where another load request should/might be sent:
805 * - MFW expects the old interface [HSI version = 1]
806 * - MFW responds that a force load request is required
808 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
810 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
812 /* The previous load request set the mailbox blocking */
813 p_hwfn->mcp_info->block_mb_sending = false;
815 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
816 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
817 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
819 if (rc != ECORE_SUCCESS)
821 } else if (out_params.load_code ==
822 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
823 /* The previous load request set the mailbox blocking */
824 p_hwfn->mcp_info->block_mb_sending = false;
826 if (ecore_mcp_can_force_load(in_params.drv_role,
827 out_params.exist_drv_role,
828 p_params->override_force_load)) {
830 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
831 in_params.drv_role, in_params.fw_ver,
832 in_params.drv_ver_0, in_params.drv_ver_1,
833 out_params.exist_drv_role,
834 out_params.exist_fw_ver,
835 out_params.exist_drv_ver_0,
836 out_params.exist_drv_ver_1);
838 ecore_get_mfw_force_cmd(p_hwfn,
839 ECORE_LOAD_REQ_FORCE_ALL,
842 in_params.force_cmd = mfw_force_cmd;
843 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
844 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
846 if (rc != ECORE_SUCCESS)
849 DP_NOTICE(p_hwfn, false,
850 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
851 in_params.drv_role, in_params.fw_ver,
852 in_params.drv_ver_0, in_params.drv_ver_1,
853 out_params.exist_drv_role,
854 out_params.exist_fw_ver,
855 out_params.exist_drv_ver_0,
856 out_params.exist_drv_ver_1);
858 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
863 /* Now handle the other types of responses.
864 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
865 * expected here after the additional revised load requests were sent.
867 switch (out_params.load_code) {
868 case FW_MSG_CODE_DRV_LOAD_ENGINE:
869 case FW_MSG_CODE_DRV_LOAD_PORT:
870 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
871 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
872 out_params.drv_exists) {
873 /* The role and fw/driver version match, but the PF is
874 * already loaded and has not been unloaded gracefully.
875 * This is unexpected since a quasi-FLR request was
876 * previously sent as part of ecore_hw_prepare().
878 DP_NOTICE(p_hwfn, false,
879 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
884 DP_NOTICE(p_hwfn, false,
885 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
886 out_params.load_code);
890 p_params->load_code = out_params.load_code;
892 return ECORE_SUCCESS;
895 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
896 struct ecore_ptt *p_ptt)
898 u32 resp = 0, param = 0;
899 enum _ecore_status_t rc;
901 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
903 if (rc != ECORE_SUCCESS) {
904 DP_NOTICE(p_hwfn, false,
905 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
909 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
911 /* Check if there is a DID mismatch between nvm-cfg/efuse */
912 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
913 DP_NOTICE(p_hwfn, false,
914 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
916 return ECORE_SUCCESS;
919 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
920 struct ecore_ptt *p_ptt)
922 u32 wol_param, mcp_resp, mcp_param;
925 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
927 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
928 &mcp_resp, &mcp_param);
931 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
932 struct ecore_ptt *p_ptt)
934 struct ecore_mcp_mb_params mb_params;
935 struct mcp_mac wol_mac;
937 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
938 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
940 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
943 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
944 struct ecore_ptt *p_ptt)
946 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
948 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
949 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
950 ECORE_PATH_ID(p_hwfn));
951 u32 disabled_vfs[VF_MAX_STATIC / 32];
954 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
955 "Reading Disabled VF information from [offset %08x],"
957 mfw_path_offsize, path_addr);
959 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
960 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
962 OFFSETOF(struct public_path,
965 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
966 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
967 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
970 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
971 OSAL_VF_FLR_UPDATE(p_hwfn);
974 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
975 struct ecore_ptt *p_ptt,
978 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
980 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
981 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
983 struct ecore_mcp_mb_params mb_params;
984 enum _ecore_status_t rc;
987 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
988 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
989 "Acking VFs [%08x,...,%08x] - %08x\n",
990 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
992 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
993 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
994 mb_params.p_data_src = vfs_to_ack;
995 mb_params.data_src_size = VF_MAX_STATIC / 8;
996 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
998 if (rc != ECORE_SUCCESS) {
999 DP_NOTICE(p_hwfn, false,
1000 "Failed to pass ACK for VF flr to MFW\n");
1001 return ECORE_TIMEOUT;
1004 /* TMP - clear the ACK bits; should be done by MFW */
1005 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1006 ecore_wr(p_hwfn, p_ptt,
1008 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1009 i * sizeof(u32), 0);
1014 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1015 struct ecore_ptt *p_ptt)
1017 u32 transceiver_state;
1019 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1020 p_hwfn->mcp_info->port_addr +
1021 OFFSETOF(struct public_port,
1024 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1025 "Received transceiver state update [0x%08x] from mfw"
1027 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1028 OFFSETOF(struct public_port,
1029 transceiver_data)));
1031 transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
1033 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1034 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1036 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1039 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1040 struct ecore_ptt *p_ptt,
1043 struct ecore_mcp_link_state *p_link;
1047 p_link = &p_hwfn->mcp_info->link_output;
1048 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1050 status = ecore_rd(p_hwfn, p_ptt,
1051 p_hwfn->mcp_info->port_addr +
1052 OFFSETOF(struct public_port, link_status));
1053 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1054 "Received link update [0x%08x] from mfw"
1056 status, (u32)(p_hwfn->mcp_info->port_addr +
1057 OFFSETOF(struct public_port,
1060 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1061 "Resetting link indications\n");
1065 if (p_hwfn->b_drv_link_init)
1066 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1068 p_link->link_up = false;
1070 p_link->full_duplex = true;
1071 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1072 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1073 p_link->speed = 100000;
1075 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1076 p_link->speed = 50000;
1078 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1079 p_link->speed = 40000;
1081 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1082 p_link->speed = 25000;
1084 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1085 p_link->speed = 20000;
1087 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1088 p_link->speed = 10000;
1090 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1091 p_link->full_duplex = false;
1093 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1094 p_link->speed = 1000;
1100 /* We never store total line speed as p_link->speed is
1101 * again changes according to bandwidth allocation.
1103 if (p_link->link_up && p_link->speed)
1104 p_link->line_speed = p_link->speed;
1106 p_link->line_speed = 0;
1108 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1109 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1111 /* Max bandwidth configuration */
1112 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1115 /* Mintz bandwidth configuration */
1116 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1118 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1119 p_link->min_pf_rate);
1121 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1122 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1123 p_link->parallel_detection = !!(status &
1124 LINK_STATUS_PARALLEL_DETECTION_USED);
1125 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1127 p_link->partner_adv_speed |=
1128 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1129 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1130 p_link->partner_adv_speed |=
1131 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1132 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1133 p_link->partner_adv_speed |=
1134 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1135 ECORE_LINK_PARTNER_SPEED_10G : 0;
1136 p_link->partner_adv_speed |=
1137 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1138 ECORE_LINK_PARTNER_SPEED_20G : 0;
1139 p_link->partner_adv_speed |=
1140 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1141 ECORE_LINK_PARTNER_SPEED_25G : 0;
1142 p_link->partner_adv_speed |=
1143 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1144 ECORE_LINK_PARTNER_SPEED_40G : 0;
1145 p_link->partner_adv_speed |=
1146 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1147 ECORE_LINK_PARTNER_SPEED_50G : 0;
1148 p_link->partner_adv_speed |=
1149 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1150 ECORE_LINK_PARTNER_SPEED_100G : 0;
1152 p_link->partner_tx_flow_ctrl_en =
1153 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1154 p_link->partner_rx_flow_ctrl_en =
1155 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1157 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1158 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1159 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1161 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1162 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1164 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1165 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1168 p_link->partner_adv_pause = 0;
1171 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1173 OSAL_LINK_UPDATE(p_hwfn);
1176 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1177 struct ecore_ptt *p_ptt, bool b_up)
1179 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1180 struct ecore_mcp_mb_params mb_params;
1181 struct eth_phy_cfg phy_cfg;
1182 enum _ecore_status_t rc = ECORE_SUCCESS;
1186 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1187 return ECORE_SUCCESS;
1190 /* Set the shmem configuration according to params */
1191 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1192 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1193 if (!params->speed.autoneg)
1194 phy_cfg.speed = params->speed.forced_speed;
1195 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1196 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1197 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1198 phy_cfg.adv_speed = params->speed.advertised_speeds;
1199 phy_cfg.loopback_mode = params->loopback_mode;
1200 p_hwfn->b_drv_link_init = b_up;
1203 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1204 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1205 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1206 phy_cfg.loopback_mode);
1208 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1210 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1211 mb_params.cmd = cmd;
1212 mb_params.p_data_src = &phy_cfg;
1213 mb_params.data_src_size = sizeof(phy_cfg);
1214 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1216 /* if mcp fails to respond we must abort */
1217 if (rc != ECORE_SUCCESS) {
1218 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1222 /* Reset the link status if needed */
1224 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
1229 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1230 struct ecore_ptt *p_ptt)
1232 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1234 /* TODO - Add support for VFs */
1235 if (IS_VF(p_hwfn->p_dev))
1238 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1240 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1241 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1243 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1245 OFFSETOF(struct public_path, process_kill)) &
1246 PROCESS_KILL_COUNTER_MASK;
1248 return proc_kill_cnt;
1251 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1252 struct ecore_ptt *p_ptt)
1254 struct ecore_dev *p_dev = p_hwfn->p_dev;
1257 /* Prevent possible attentions/interrupts during the recovery handling
1258 * and till its load phase, during which they will be re-enabled.
1260 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1262 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1264 /* The following operations should be done once, and thus in CMT mode
1265 * are carried out by only the first HW function.
1267 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1270 if (p_dev->recov_in_prog) {
1271 DP_NOTICE(p_hwfn, false,
1272 "Ignoring the indication since a recovery"
1273 " process is already in progress\n");
1277 p_dev->recov_in_prog = true;
1279 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1280 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1282 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1285 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1286 struct ecore_ptt *p_ptt,
1287 enum MFW_DRV_MSG_TYPE type)
1289 enum ecore_mcp_protocol_type stats_type;
1290 union ecore_mcp_protocol_stats stats;
1291 struct ecore_mcp_mb_params mb_params;
1293 enum _ecore_status_t rc;
1296 case MFW_DRV_MSG_GET_LAN_STATS:
1297 stats_type = ECORE_MCP_LAN_STATS;
1298 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1301 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1305 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1307 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1308 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1309 mb_params.param = hsi_param;
1310 mb_params.p_data_src = &stats;
1311 mb_params.data_src_size = sizeof(stats);
1312 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1313 if (rc != ECORE_SUCCESS)
1314 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1317 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1318 struct public_func *p_shmem_info)
1320 struct ecore_mcp_function_info *p_info;
1322 p_info = &p_hwfn->mcp_info->func_info;
1324 /* TODO - bandwidth min/max should have valid values of 1-100,
1325 * as well as some indication that the feature is disabled.
1326 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1327 * limit and correct value to min `1' and max `100' if limit isn't in
1330 p_info->bandwidth_min = (p_shmem_info->config &
1331 FUNC_MF_CFG_MIN_BW_MASK) >>
1332 FUNC_MF_CFG_MIN_BW_SHIFT;
1333 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1335 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1336 p_info->bandwidth_min);
1337 p_info->bandwidth_min = 1;
1340 p_info->bandwidth_max = (p_shmem_info->config &
1341 FUNC_MF_CFG_MAX_BW_MASK) >>
1342 FUNC_MF_CFG_MAX_BW_SHIFT;
1343 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1345 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1346 p_info->bandwidth_max);
1347 p_info->bandwidth_max = 100;
1351 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1352 struct ecore_ptt *p_ptt,
1353 struct public_func *p_data,
1356 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1358 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1359 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1362 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1364 size = OSAL_MIN_T(u32, sizeof(*p_data),
1365 SECTION_SIZE(mfw_path_offsize));
1366 for (i = 0; i < size / sizeof(u32); i++)
1367 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1368 func_addr + (i << 2));
1374 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1376 struct ecore_mcp_function_info *p_info;
1377 struct public_func shmem_info;
1378 u32 resp = 0, param = 0;
1380 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1382 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1384 p_info = &p_hwfn->mcp_info->func_info;
1386 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1388 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1390 /* Acknowledge the MFW */
1391 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1395 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1396 struct ecore_ptt *p_ptt)
1398 /* A single notification should be sent to upper driver in CMT mode */
1399 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1402 DP_NOTICE(p_hwfn, false,
1403 "Fan failure was detected on the network interface card"
1404 " and it's going to be shut down.\n");
1406 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1409 struct ecore_mdump_cmd_params {
1418 static enum _ecore_status_t
1419 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1420 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1422 struct ecore_mcp_mb_params mb_params;
1423 enum _ecore_status_t rc;
1425 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1426 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1427 mb_params.param = p_mdump_cmd_params->cmd;
1428 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1429 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1430 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1431 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1432 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1433 if (rc != ECORE_SUCCESS)
1436 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1438 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1440 "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1441 p_mdump_cmd_params->cmd);
1443 } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1445 "The mdump command is not supported by the MFW\n");
1452 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1453 struct ecore_ptt *p_ptt)
1455 struct ecore_mdump_cmd_params mdump_cmd_params;
1457 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1458 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1460 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1463 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1464 struct ecore_ptt *p_ptt,
1467 struct ecore_mdump_cmd_params mdump_cmd_params;
1469 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1470 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1471 mdump_cmd_params.p_data_src = &epoch;
1472 mdump_cmd_params.data_src_size = sizeof(epoch);
1474 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1477 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1478 struct ecore_ptt *p_ptt)
1480 struct ecore_mdump_cmd_params mdump_cmd_params;
1482 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1483 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1485 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1488 static enum _ecore_status_t
1489 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1490 struct mdump_config_stc *p_mdump_config)
1492 struct ecore_mdump_cmd_params mdump_cmd_params;
1493 enum _ecore_status_t rc;
1495 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1496 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1497 mdump_cmd_params.p_data_dst = p_mdump_config;
1498 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1500 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1501 if (rc != ECORE_SUCCESS)
1504 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1506 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1507 mdump_cmd_params.mcp_resp);
1508 rc = ECORE_UNKNOWN_ERROR;
1514 enum _ecore_status_t
1515 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1516 struct ecore_mdump_info *p_mdump_info)
1518 u32 addr, global_offsize, global_addr;
1519 struct mdump_config_stc mdump_config;
1520 enum _ecore_status_t rc;
1522 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1524 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1526 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1527 global_addr = SECTION_ADDR(global_offsize, 0);
1528 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1530 OFFSETOF(struct public_global,
1533 if (p_mdump_info->reason) {
1534 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1535 if (rc != ECORE_SUCCESS)
1538 p_mdump_info->version = mdump_config.version;
1539 p_mdump_info->config = mdump_config.config;
1540 p_mdump_info->epoch = mdump_config.epoc;
1541 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1542 p_mdump_info->valid_logs = mdump_config.valid_logs;
1544 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1545 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1546 p_mdump_info->reason, p_mdump_info->version,
1547 p_mdump_info->config, p_mdump_info->epoch,
1548 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1550 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1551 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1554 return ECORE_SUCCESS;
1557 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1558 struct ecore_ptt *p_ptt)
1560 struct ecore_mdump_cmd_params mdump_cmd_params;
1562 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1563 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1565 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1568 enum _ecore_status_t
1569 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1570 struct ecore_mdump_retain_data *p_mdump_retain)
1572 struct ecore_mdump_cmd_params mdump_cmd_params;
1573 struct mdump_retain_data_stc mfw_mdump_retain;
1574 enum _ecore_status_t rc;
1576 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1577 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1578 mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1579 mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1581 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1582 if (rc != ECORE_SUCCESS)
1585 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1587 "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1588 mdump_cmd_params.mcp_resp);
1589 return ECORE_UNKNOWN_ERROR;
1592 p_mdump_retain->valid = mfw_mdump_retain.valid;
1593 p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1594 p_mdump_retain->pf = mfw_mdump_retain.pf;
1595 p_mdump_retain->status = mfw_mdump_retain.status;
1597 return ECORE_SUCCESS;
1600 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1601 struct ecore_ptt *p_ptt)
1603 struct ecore_mdump_cmd_params mdump_cmd_params;
1605 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1606 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1608 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1611 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1612 struct ecore_ptt *p_ptt)
1614 struct ecore_mdump_retain_data mdump_retain;
1615 enum _ecore_status_t rc;
1617 /* In CMT mode - no need for more than a single acknowledgment to the
1618 * MFW, and no more than a single notification to the upper driver.
1620 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1623 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1624 if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1625 DP_NOTICE(p_hwfn, false,
1626 "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1627 mdump_retain.epoch, mdump_retain.pf,
1628 mdump_retain.status);
1630 DP_NOTICE(p_hwfn, false,
1631 "The MFW notified that a critical error occurred in the device\n");
1634 if (p_hwfn->p_dev->allow_mdump) {
1635 DP_NOTICE(p_hwfn, false,
1636 "Not acknowledging the notification to allow the MFW crash dump\n");
1640 DP_NOTICE(p_hwfn, false,
1641 "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1642 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1643 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1646 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1647 struct ecore_ptt *p_ptt)
1649 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1650 enum _ecore_status_t rc = ECORE_SUCCESS;
1654 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1656 /* Read Messages from MFW */
1657 ecore_mcp_read_mb(p_hwfn, p_ptt);
1659 /* Compare current messages to old ones */
1660 for (i = 0; i < info->mfw_mb_length; i++) {
1661 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1666 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1667 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1668 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1671 case MFW_DRV_MSG_LINK_CHANGE:
1672 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1674 case MFW_DRV_MSG_VF_DISABLED:
1675 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1677 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1678 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1679 ECORE_DCBX_REMOTE_LLDP_MIB);
1681 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1682 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1683 ECORE_DCBX_REMOTE_MIB);
1685 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1686 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1687 ECORE_DCBX_OPERATIONAL_MIB);
1689 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1690 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1692 case MFW_DRV_MSG_ERROR_RECOVERY:
1693 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1695 case MFW_DRV_MSG_GET_LAN_STATS:
1696 case MFW_DRV_MSG_GET_FCOE_STATS:
1697 case MFW_DRV_MSG_GET_ISCSI_STATS:
1698 case MFW_DRV_MSG_GET_RDMA_STATS:
1699 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1701 case MFW_DRV_MSG_BW_UPDATE:
1702 ecore_mcp_update_bw(p_hwfn, p_ptt);
1704 case MFW_DRV_MSG_FAILURE_DETECTED:
1705 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1707 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1708 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1711 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1716 /* ACK everything */
1717 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1718 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1720 /* MFW expect answer in BE, so we force write in that format */
1721 ecore_wr(p_hwfn, p_ptt,
1722 info->mfw_mb_addr + sizeof(u32) +
1723 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1724 sizeof(u32) + i * sizeof(u32), val);
1728 DP_NOTICE(p_hwfn, false,
1729 "Received an MFW message indication but no"
1734 /* Copy the new mfw messages into the shadow */
1735 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1740 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1741 struct ecore_ptt *p_ptt,
1743 u32 *p_running_bundle_id)
1748 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1749 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1750 return ECORE_SUCCESS;
1754 if (IS_VF(p_hwfn->p_dev)) {
1755 if (p_hwfn->vf_iov_info) {
1756 struct pfvf_acquire_resp_tlv *p_resp;
1758 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1759 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1760 return ECORE_SUCCESS;
1762 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1763 "VF requested MFW version prior to ACQUIRE\n");
1768 global_offsize = ecore_rd(p_hwfn, p_ptt,
1769 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1773 ecore_rd(p_hwfn, p_ptt,
1774 SECTION_ADDR(global_offsize,
1775 0) + OFFSETOF(struct public_global, mfw_ver));
1777 if (p_running_bundle_id != OSAL_NULL) {
1778 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1779 SECTION_ADDR(global_offsize,
1781 OFFSETOF(struct public_global,
1782 running_bundle_id));
1785 return ECORE_SUCCESS;
1788 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1791 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1792 struct ecore_ptt *p_ptt;
1794 /* TODO - Add support for VFs */
1798 if (!ecore_mcp_is_init(p_hwfn)) {
1799 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1803 *p_media_type = MEDIA_UNSPECIFIED;
1805 p_ptt = ecore_ptt_acquire(p_hwfn);
1809 *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1810 OFFSETOF(struct public_port, media_type));
1812 ecore_ptt_release(p_hwfn, p_ptt);
1814 return ECORE_SUCCESS;
1818 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1820 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
1821 enum ecore_pci_personality *p_proto)
1823 *p_proto = ECORE_PCI_ETH;
1825 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1826 "According to Legacy capabilities, L2 personality is %08x\n",
1831 static enum _ecore_status_t
1832 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
1833 struct ecore_ptt *p_ptt,
1834 enum ecore_pci_personality *p_proto)
1836 u32 resp = 0, param = 0;
1837 enum _ecore_status_t rc;
1839 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1840 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1841 (u32)*p_proto, resp, param);
1842 return ECORE_SUCCESS;
1845 static enum _ecore_status_t
1846 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1847 struct public_func *p_info,
1848 struct ecore_ptt *p_ptt,
1849 enum ecore_pci_personality *p_proto)
1851 enum _ecore_status_t rc = ECORE_SUCCESS;
1853 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1854 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1855 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
1857 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1866 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1867 struct ecore_ptt *p_ptt)
1869 struct ecore_mcp_function_info *info;
1870 struct public_func shmem_info;
1872 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1873 info = &p_hwfn->mcp_info->func_info;
1875 info->pause_on_host = (shmem_info.config &
1876 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1878 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1880 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1881 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1885 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1887 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1888 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1889 info->mac[1] = (u8)(shmem_info.mac_upper);
1890 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1891 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1892 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1893 info->mac[5] = (u8)(shmem_info.mac_lower);
1895 /* TODO - are there protocols for which there's no MAC? */
1896 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1899 /* TODO - are these calculations true for BE machine? */
1900 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1901 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1902 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1903 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1905 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1907 info->mtu = (u16)shmem_info.mtu_size;
1912 info->mtu = (u16)shmem_info.mtu_size;
1914 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1915 "Read configuration from shmem: pause_on_host %02x"
1916 " protocol %02x BW [%02x - %02x]"
1917 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1918 " node %lx ovlan %04x\n",
1919 info->pause_on_host, info->protocol,
1920 info->bandwidth_min, info->bandwidth_max,
1921 info->mac[0], info->mac[1], info->mac[2],
1922 info->mac[3], info->mac[4], info->mac[5],
1923 (unsigned long)info->wwn_port,
1924 (unsigned long)info->wwn_node, info->ovlan);
1926 return ECORE_SUCCESS;
1929 struct ecore_mcp_link_params
1930 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1932 if (!p_hwfn || !p_hwfn->mcp_info)
1934 return &p_hwfn->mcp_info->link_input;
1937 struct ecore_mcp_link_state
1938 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1940 if (!p_hwfn || !p_hwfn->mcp_info)
1944 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1945 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1946 p_hwfn->mcp_info->link_output.link_up = true;
1950 return &p_hwfn->mcp_info->link_output;
1953 struct ecore_mcp_link_capabilities
1954 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1956 if (!p_hwfn || !p_hwfn->mcp_info)
1958 return &p_hwfn->mcp_info->link_capabilities;
1961 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1962 struct ecore_ptt *p_ptt)
1964 u32 resp = 0, param = 0;
1965 enum _ecore_status_t rc;
1967 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1968 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
1970 /* Wait for the drain to complete before returning */
1976 const struct ecore_mcp_function_info
1977 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1979 if (!p_hwfn || !p_hwfn->mcp_info)
1981 return &p_hwfn->mcp_info->func_info;
1984 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1985 struct ecore_ptt *p_ptt,
1986 struct ecore_mcp_nvm_params *params)
1988 enum _ecore_status_t rc;
1990 switch (params->type) {
1991 case ECORE_MCP_NVM_RD:
1992 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1993 params->nvm_common.offset,
1994 ¶ms->nvm_common.resp,
1995 ¶ms->nvm_common.param,
1996 params->nvm_rd.buf_size,
1997 params->nvm_rd.buf);
2000 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
2001 params->nvm_common.offset,
2002 ¶ms->nvm_common.resp,
2003 ¶ms->nvm_common.param);
2005 case ECORE_MCP_NVM_WR:
2006 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
2007 params->nvm_common.offset,
2008 ¶ms->nvm_common.resp,
2009 ¶ms->nvm_common.param,
2010 params->nvm_wr.buf_size,
2011 params->nvm_wr.buf);
2020 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2021 struct ecore_ptt *p_ptt, u32 personalities)
2023 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2024 struct public_func shmem_info;
2025 int i, count = 0, num_pfs;
2027 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2029 for (i = 0; i < num_pfs; i++) {
2030 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2031 MCP_PF_ID_BY_REL(p_hwfn, i));
2032 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2035 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2040 if ((1 << ((u32)protocol)) & personalities)
2047 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2048 struct ecore_ptt *p_ptt,
2054 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2055 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2060 if (IS_VF(p_hwfn->p_dev))
2063 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2064 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2065 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2066 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2068 *p_flash_size = flash_size;
2070 return ECORE_SUCCESS;
2073 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2074 struct ecore_ptt *p_ptt)
2076 struct ecore_dev *p_dev = p_hwfn->p_dev;
2078 if (p_dev->recov_in_prog) {
2079 DP_NOTICE(p_hwfn, false,
2080 "Avoid triggering a recovery since such a process"
2081 " is already in progress\n");
2085 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2086 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2088 return ECORE_SUCCESS;
2091 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2092 struct ecore_ptt *p_ptt,
2095 u32 resp = 0, param = 0, rc_param = 0;
2096 enum _ecore_status_t rc;
2098 /* Only Leader can configure MSIX, and need to take CMT into account */
2100 if (!IS_LEAD_HWFN(p_hwfn))
2101 return ECORE_SUCCESS;
2102 num *= p_hwfn->p_dev->num_hwfns;
2104 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2105 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2106 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2107 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2109 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2112 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2113 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2117 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2118 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2125 enum _ecore_status_t
2126 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2127 struct ecore_mcp_drv_version *p_ver)
2129 struct ecore_mcp_mb_params mb_params;
2130 struct drv_version_stc drv_version;
2134 enum _ecore_status_t rc;
2137 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2138 return ECORE_SUCCESS;
2141 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2142 drv_version.version = p_ver->version;
2143 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2144 for (i = 0; i < num_words; i++) {
2145 /* The driver name is expected to be in a big-endian format */
2146 p_name = &p_ver->name[i * sizeof(u32)];
2147 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2148 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2151 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2152 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2153 mb_params.p_data_src = &drv_version;
2154 mb_params.data_src_size = sizeof(drv_version);
2155 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2156 if (rc != ECORE_SUCCESS)
2157 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2162 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2163 struct ecore_ptt *p_ptt)
2165 enum _ecore_status_t rc;
2166 u32 resp = 0, param = 0;
2168 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2170 if (rc != ECORE_SUCCESS)
2171 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2176 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2177 struct ecore_ptt *p_ptt)
2179 u32 value, cpu_mode;
2181 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2183 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2184 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2185 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2186 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2188 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2191 enum _ecore_status_t
2192 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2193 struct ecore_ptt *p_ptt,
2194 enum ecore_ov_client client)
2196 enum _ecore_status_t rc;
2197 u32 resp = 0, param = 0;
2201 case ECORE_OV_CLIENT_DRV:
2202 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2204 case ECORE_OV_CLIENT_USER:
2205 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2207 case ECORE_OV_CLIENT_VENDOR_SPEC:
2208 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2211 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2215 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2216 drv_mb_param, &resp, ¶m);
2217 if (rc != ECORE_SUCCESS)
2218 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2223 enum _ecore_status_t
2224 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2225 struct ecore_ptt *p_ptt,
2226 enum ecore_ov_driver_state drv_state)
2228 enum _ecore_status_t rc;
2229 u32 resp = 0, param = 0;
2232 switch (drv_state) {
2233 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2234 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2236 case ECORE_OV_DRIVER_STATE_DISABLED:
2237 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2239 case ECORE_OV_DRIVER_STATE_ACTIVE:
2240 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2243 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2247 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2248 drv_mb_param, &resp, ¶m);
2249 if (rc != ECORE_SUCCESS)
2250 DP_ERR(p_hwfn, "Failed to send driver state\n");
2255 enum _ecore_status_t
2256 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2257 struct ecore_fc_npiv_tbl *p_table)
2262 enum _ecore_status_t
2263 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2264 struct ecore_ptt *p_ptt, u16 mtu)
2269 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2270 struct ecore_ptt *p_ptt,
2271 enum ecore_led_mode mode)
2273 u32 resp = 0, param = 0, drv_mb_param;
2274 enum _ecore_status_t rc;
2277 case ECORE_LED_MODE_ON:
2278 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2280 case ECORE_LED_MODE_OFF:
2281 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2283 case ECORE_LED_MODE_RESTORE:
2284 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2287 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2291 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2292 drv_mb_param, &resp, ¶m);
2293 if (rc != ECORE_SUCCESS)
2294 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2299 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2300 struct ecore_ptt *p_ptt,
2303 u32 resp = 0, param = 0;
2304 enum _ecore_status_t rc;
2306 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2307 mask_parities, &resp, ¶m);
2309 if (rc != ECORE_SUCCESS) {
2311 "MCP response failure for mask parities, aborting\n");
2312 } else if (resp != FW_MSG_CODE_OK) {
2314 "MCP did not ack mask parity request. Old MFW?\n");
2321 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2324 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2325 u32 bytes_left, offset, bytes_to_copy, buf_size;
2326 struct ecore_mcp_nvm_params params;
2327 struct ecore_ptt *p_ptt;
2328 enum _ecore_status_t rc = ECORE_SUCCESS;
2330 p_ptt = ecore_ptt_acquire(p_hwfn);
2334 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2337 params.type = ECORE_MCP_NVM_RD;
2338 params.nvm_rd.buf_size = &buf_size;
2339 params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
2340 while (bytes_left > 0) {
2341 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2342 MCP_DRV_NVM_BUF_LEN);
2343 params.nvm_common.offset = (addr + offset) |
2344 (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
2345 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2346 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2347 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
2348 FW_MSG_CODE_NVM_OK)) {
2349 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2353 /* This can be a lengthy process, and it's possible scheduler
2354 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2356 if (bytes_left % 0x1000 <
2357 (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
2360 offset += *params.nvm_rd.buf_size;
2361 bytes_left -= *params.nvm_rd.buf_size;
2364 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2365 ecore_ptt_release(p_hwfn, p_ptt);
2370 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2371 u32 addr, u8 *p_buf, u32 len)
2373 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2374 struct ecore_mcp_nvm_params params;
2375 struct ecore_ptt *p_ptt;
2376 enum _ecore_status_t rc;
2378 p_ptt = ecore_ptt_acquire(p_hwfn);
2382 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2383 params.type = ECORE_MCP_NVM_RD;
2384 params.nvm_rd.buf_size = &len;
2385 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
2386 DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
2387 params.nvm_common.offset = addr;
2388 params.nvm_rd.buf = (u32 *)p_buf;
2389 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2390 if (rc != ECORE_SUCCESS)
2391 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2393 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2394 ecore_ptt_release(p_hwfn, p_ptt);
2399 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2401 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2402 struct ecore_mcp_nvm_params params;
2403 struct ecore_ptt *p_ptt;
2405 p_ptt = ecore_ptt_acquire(p_hwfn);
2409 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2410 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2411 ecore_ptt_release(p_hwfn, p_ptt);
2413 return ECORE_SUCCESS;
2416 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2418 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2419 struct ecore_mcp_nvm_params params;
2420 struct ecore_ptt *p_ptt;
2421 enum _ecore_status_t rc;
2423 p_ptt = ecore_ptt_acquire(p_hwfn);
2426 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2427 params.type = ECORE_MCP_CMD;
2428 params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
2429 params.nvm_common.offset = addr;
2430 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2431 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2432 ecore_ptt_release(p_hwfn, p_ptt);
2437 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2440 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2441 struct ecore_mcp_nvm_params params;
2442 struct ecore_ptt *p_ptt;
2443 enum _ecore_status_t rc;
2445 p_ptt = ecore_ptt_acquire(p_hwfn);
2448 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2449 params.type = ECORE_MCP_CMD;
2450 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
2451 params.nvm_common.offset = addr;
2452 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2453 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2454 ecore_ptt_release(p_hwfn, p_ptt);
2459 /* rc receives ECORE_INVAL as default parameter because
2460 * it might not enter the while loop if the len is 0
2462 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2463 u32 addr, u8 *p_buf, u32 len)
2465 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2466 enum _ecore_status_t rc = ECORE_INVAL;
2467 struct ecore_mcp_nvm_params params;
2468 struct ecore_ptt *p_ptt;
2469 u32 buf_idx, buf_size;
2471 p_ptt = ecore_ptt_acquire(p_hwfn);
2475 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2476 params.type = ECORE_MCP_NVM_WR;
2477 if (cmd == ECORE_PUT_FILE_DATA)
2478 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2480 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2482 while (buf_idx < len) {
2483 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2484 MCP_DRV_NVM_BUF_LEN);
2485 params.nvm_common.offset = ((buf_size <<
2486 DRV_MB_PARAM_NVM_LEN_SHIFT)
2488 params.nvm_wr.buf_size = buf_size;
2489 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2490 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2491 if (rc != ECORE_SUCCESS ||
2492 ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2493 (params.nvm_common.resp !=
2494 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2495 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2497 /* This can be a lengthy process, and it's possible scheduler
2498 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2500 if (buf_idx % 0x1000 >
2501 (buf_idx + buf_size) % 0x1000)
2504 buf_idx += buf_size;
2507 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2508 ecore_ptt_release(p_hwfn, p_ptt);
2513 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2514 u32 addr, u8 *p_buf, u32 len)
2516 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2517 struct ecore_mcp_nvm_params params;
2518 struct ecore_ptt *p_ptt;
2519 enum _ecore_status_t rc;
2521 p_ptt = ecore_ptt_acquire(p_hwfn);
2525 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2526 params.type = ECORE_MCP_NVM_WR;
2527 params.nvm_wr.buf_size = len;
2528 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2529 DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2530 params.nvm_common.offset = addr;
2531 params.nvm_wr.buf = (u32 *)p_buf;
2532 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2533 if (rc != ECORE_SUCCESS)
2534 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2535 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2536 ecore_ptt_release(p_hwfn, p_ptt);
2541 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2544 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2545 struct ecore_mcp_nvm_params params;
2546 struct ecore_ptt *p_ptt;
2547 enum _ecore_status_t rc;
2549 p_ptt = ecore_ptt_acquire(p_hwfn);
2553 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2554 params.type = ECORE_MCP_CMD;
2555 params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2556 params.nvm_common.offset = addr;
2557 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2558 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2559 ecore_ptt_release(p_hwfn, p_ptt);
2564 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2565 struct ecore_ptt *p_ptt,
2566 u32 port, u32 addr, u32 offset,
2569 struct ecore_mcp_nvm_params params;
2570 enum _ecore_status_t rc;
2571 u32 bytes_left, bytes_to_copy, buf_size;
2573 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2574 params.nvm_common.offset =
2575 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2576 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2580 params.type = ECORE_MCP_NVM_RD;
2581 params.nvm_rd.buf_size = &buf_size;
2582 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2583 while (bytes_left > 0) {
2584 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2585 MAX_I2C_TRANSACTION_SIZE);
2586 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2587 params.nvm_common.offset &=
2588 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2589 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2590 params.nvm_common.offset |=
2592 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2593 params.nvm_common.offset |=
2594 (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2595 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2596 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2597 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2599 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2600 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2601 return ECORE_UNKNOWN_ERROR;
2603 offset += *params.nvm_rd.buf_size;
2604 bytes_left -= *params.nvm_rd.buf_size;
2607 return ECORE_SUCCESS;
2610 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2611 struct ecore_ptt *p_ptt,
2612 u32 port, u32 addr, u32 offset,
2615 struct ecore_mcp_nvm_params params;
2616 enum _ecore_status_t rc;
2617 u32 buf_idx, buf_size;
2619 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2620 params.nvm_common.offset =
2621 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2622 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2623 params.type = ECORE_MCP_NVM_WR;
2624 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2626 while (buf_idx < len) {
2627 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2628 MAX_I2C_TRANSACTION_SIZE);
2629 params.nvm_common.offset &=
2630 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2631 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2632 params.nvm_common.offset |=
2633 ((offset + buf_idx) <<
2634 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2635 params.nvm_common.offset |=
2636 (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2637 params.nvm_wr.buf_size = buf_size;
2638 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2639 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2640 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2641 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2643 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2644 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2645 return ECORE_UNKNOWN_ERROR;
2647 buf_idx += buf_size;
2650 return ECORE_SUCCESS;
2653 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2654 struct ecore_ptt *p_ptt,
2655 u16 gpio, u32 *gpio_val)
2657 enum _ecore_status_t rc = ECORE_SUCCESS;
2658 u32 drv_mb_param = 0, rsp;
2660 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2662 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2663 drv_mb_param, &rsp, gpio_val);
2665 if (rc != ECORE_SUCCESS)
2668 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2669 return ECORE_UNKNOWN_ERROR;
2671 return ECORE_SUCCESS;
2674 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2675 struct ecore_ptt *p_ptt,
2676 u16 gpio, u16 gpio_val)
2678 enum _ecore_status_t rc = ECORE_SUCCESS;
2679 u32 drv_mb_param = 0, param, rsp;
2681 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2682 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2684 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2685 drv_mb_param, &rsp, ¶m);
2687 if (rc != ECORE_SUCCESS)
2690 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2691 return ECORE_UNKNOWN_ERROR;
2693 return ECORE_SUCCESS;
2696 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2697 struct ecore_ptt *p_ptt,
2698 u16 gpio, u32 *gpio_direction,
2701 u32 drv_mb_param = 0, rsp, val = 0;
2702 enum _ecore_status_t rc = ECORE_SUCCESS;
2704 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2706 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2707 drv_mb_param, &rsp, &val);
2708 if (rc != ECORE_SUCCESS)
2711 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2712 DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2713 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2714 DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2716 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2717 return ECORE_UNKNOWN_ERROR;
2719 return ECORE_SUCCESS;
2722 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2723 struct ecore_ptt *p_ptt)
2725 u32 drv_mb_param = 0, rsp, param;
2726 enum _ecore_status_t rc = ECORE_SUCCESS;
2728 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2729 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2731 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2732 drv_mb_param, &rsp, ¶m);
2734 if (rc != ECORE_SUCCESS)
2737 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2738 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2739 rc = ECORE_UNKNOWN_ERROR;
2744 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2745 struct ecore_ptt *p_ptt)
2747 u32 drv_mb_param, rsp, param;
2748 enum _ecore_status_t rc = ECORE_SUCCESS;
2750 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2751 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2753 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2754 drv_mb_param, &rsp, ¶m);
2756 if (rc != ECORE_SUCCESS)
2759 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2760 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2761 rc = ECORE_UNKNOWN_ERROR;
2766 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2767 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2769 u32 drv_mb_param = 0, rsp;
2770 enum _ecore_status_t rc = ECORE_SUCCESS;
2772 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2773 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2775 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2776 drv_mb_param, &rsp, num_images);
2778 if (rc != ECORE_SUCCESS)
2781 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2782 rc = ECORE_UNKNOWN_ERROR;
2787 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2788 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2789 struct bist_nvm_image_att *p_image_att, u32 image_index)
2791 struct ecore_mcp_nvm_params params;
2792 enum _ecore_status_t rc;
2795 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2796 params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2797 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2798 params.nvm_common.offset |= (image_index <<
2799 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2801 params.type = ECORE_MCP_NVM_RD;
2802 params.nvm_rd.buf_size = &buf_size;
2803 params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2804 params.nvm_rd.buf = (u32 *)p_image_att;
2806 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2807 if (rc != ECORE_SUCCESS)
2810 if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2811 (p_image_att->return_code != 1))
2812 rc = ECORE_UNKNOWN_ERROR;
2817 enum _ecore_status_t
2818 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2819 struct ecore_ptt *p_ptt,
2820 struct ecore_temperature_info *p_temp_info)
2822 struct ecore_temperature_sensor *p_temp_sensor;
2823 struct temperature_status_stc mfw_temp_info;
2824 struct ecore_mcp_mb_params mb_params;
2826 enum _ecore_status_t rc;
2829 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2830 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2831 mb_params.p_data_dst = &mfw_temp_info;
2832 mb_params.data_dst_size = sizeof(mfw_temp_info);
2833 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2834 if (rc != ECORE_SUCCESS)
2837 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2838 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2839 ECORE_MAX_NUM_OF_SENSORS);
2840 for (i = 0; i < p_temp_info->num_sensors; i++) {
2841 val = mfw_temp_info.sensor[i];
2842 p_temp_sensor = &p_temp_info->sensors[i];
2843 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2844 SENSOR_LOCATION_SHIFT;
2845 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2846 THRESHOLD_HIGH_SHIFT;
2847 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2848 CRITICAL_TEMPERATURE_SHIFT;
2849 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2853 return ECORE_SUCCESS;
2856 enum _ecore_status_t ecore_mcp_get_mba_versions(
2857 struct ecore_hwfn *p_hwfn,
2858 struct ecore_ptt *p_ptt,
2859 struct ecore_mba_vers *p_mba_vers)
2861 struct ecore_mcp_nvm_params params;
2862 enum _ecore_status_t rc;
2865 OSAL_MEM_ZERO(¶ms, sizeof(params));
2866 params.type = ECORE_MCP_NVM_RD;
2867 params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2868 params.nvm_common.offset = 0;
2869 params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2870 params.nvm_rd.buf_size = &buf_size;
2871 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2873 if (rc != ECORE_SUCCESS)
2876 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2878 rc = ECORE_UNKNOWN_ERROR;
2880 if (buf_size != MCP_DRV_NVM_BUF_LEN)
2881 rc = ECORE_UNKNOWN_ERROR;
2886 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2887 struct ecore_ptt *p_ptt,
2892 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2893 0, &rsp, (u32 *)num_events);
2896 static enum resource_id_enum
2897 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
2899 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2903 mfw_res_id = RESOURCE_NUM_SB_E;
2905 case ECORE_L2_QUEUE:
2906 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2909 mfw_res_id = RESOURCE_NUM_VPORT_E;
2912 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2915 mfw_res_id = RESOURCE_NUM_PQ_E;
2918 mfw_res_id = RESOURCE_NUM_RL_E;
2922 /* Each VFC resource can accommodate both a MAC and a VLAN */
2923 mfw_res_id = RESOURCE_VFC_FILTER_E;
2926 mfw_res_id = RESOURCE_ILT_E;
2928 case ECORE_LL2_QUEUE:
2929 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2931 case ECORE_RDMA_CNQ_RAM:
2932 case ECORE_CMDQS_CQS:
2933 /* CNQ/CMDQS are the same resource */
2934 mfw_res_id = RESOURCE_CQS_E;
2936 case ECORE_RDMA_STATS_QUEUE:
2937 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2940 mfw_res_id = RESOURCE_BDQ_E;
2949 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
2950 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
2951 #define ECORE_RESC_ALLOC_VERSION \
2952 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
2953 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2954 (ECORE_RESC_ALLOC_VERSION_MINOR << \
2955 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2957 struct ecore_resc_alloc_in_params {
2959 enum ecore_resources res_id;
2963 struct ecore_resc_alloc_out_params {
2973 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
2975 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
2977 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2978 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2979 enum _ecore_status_t rc;
2981 /* Allow ongoing PCIe transactions to complete */
2982 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
2984 /* Clear the PF's internal FID_enable in the PXP */
2985 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2986 if (rc != ECORE_SUCCESS)
2987 DP_NOTICE(p_hwfn, false,
2988 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2994 static enum _ecore_status_t
2995 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
2996 struct ecore_ptt *p_ptt,
2997 struct ecore_resc_alloc_in_params *p_in_params,
2998 struct ecore_resc_alloc_out_params *p_out_params)
3000 struct ecore_mcp_mb_params mb_params;
3001 struct resource_info mfw_resc_info;
3002 enum _ecore_status_t rc;
3004 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3006 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3007 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3009 "Failed to match resource %d [%s] with the MFW resources\n",
3010 p_in_params->res_id,
3011 ecore_hw_get_resc_name(p_in_params->res_id));
3015 switch (p_in_params->cmd) {
3016 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3017 mfw_resc_info.size = p_in_params->resc_max_val;
3019 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3022 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3027 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3028 mb_params.cmd = p_in_params->cmd;
3029 mb_params.param = ECORE_RESC_ALLOC_VERSION;
3030 mb_params.p_data_src = &mfw_resc_info;
3031 mb_params.data_src_size = sizeof(mfw_resc_info);
3032 mb_params.p_data_dst = mb_params.p_data_src;
3033 mb_params.data_dst_size = mb_params.data_src_size;
3035 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3036 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3037 p_in_params->cmd, p_in_params->res_id,
3038 ecore_hw_get_resc_name(p_in_params->res_id),
3039 ECORE_MFW_GET_FIELD(mb_params.param,
3040 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3041 ECORE_MFW_GET_FIELD(mb_params.param,
3042 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3043 p_in_params->resc_max_val);
3045 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3046 if (rc != ECORE_SUCCESS)
3049 p_out_params->mcp_resp = mb_params.mcp_resp;
3050 p_out_params->mcp_param = mb_params.mcp_param;
3051 p_out_params->resc_num = mfw_resc_info.size;
3052 p_out_params->resc_start = mfw_resc_info.offset;
3053 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3054 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3055 p_out_params->flags = mfw_resc_info.flags;
3057 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3058 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3059 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3060 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3061 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3062 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3063 p_out_params->resc_num, p_out_params->resc_start,
3064 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3065 p_out_params->flags);
3067 return ECORE_SUCCESS;
3070 enum _ecore_status_t
3071 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3072 enum ecore_resources res_id, u32 resc_max_val,
3075 struct ecore_resc_alloc_out_params out_params;
3076 struct ecore_resc_alloc_in_params in_params;
3077 enum _ecore_status_t rc;
3079 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3080 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3081 in_params.res_id = res_id;
3082 in_params.resc_max_val = resc_max_val;
3083 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3084 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3086 if (rc != ECORE_SUCCESS)
3089 *p_mcp_resp = out_params.mcp_resp;
3091 return ECORE_SUCCESS;
3094 enum _ecore_status_t
3095 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3096 enum ecore_resources res_id, u32 *p_mcp_resp,
3097 u32 *p_resc_num, u32 *p_resc_start)
3099 struct ecore_resc_alloc_out_params out_params;
3100 struct ecore_resc_alloc_in_params in_params;
3101 enum _ecore_status_t rc;
3103 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3104 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3105 in_params.res_id = res_id;
3106 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3107 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3109 if (rc != ECORE_SUCCESS)
3112 *p_mcp_resp = out_params.mcp_resp;
3114 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3115 *p_resc_num = out_params.resc_num;
3116 *p_resc_start = out_params.resc_start;
3119 return ECORE_SUCCESS;
3122 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3123 struct ecore_ptt *p_ptt)
3125 u32 mcp_resp, mcp_param;
3127 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3128 &mcp_resp, &mcp_param);
3131 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3132 struct ecore_ptt *p_ptt,
3133 u32 param, u32 *p_mcp_resp,
3136 enum _ecore_status_t rc;
3138 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3139 p_mcp_resp, p_mcp_param);
3140 if (rc != ECORE_SUCCESS)
3143 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3145 "The resource command is unsupported by the MFW\n");
3146 return ECORE_NOTIMPL;
3149 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3150 u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3152 DP_NOTICE(p_hwfn, false,
3153 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3161 enum _ecore_status_t
3162 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3163 struct ecore_resc_lock_params *p_params)
3165 u32 param = 0, mcp_resp, mcp_param;
3167 enum _ecore_status_t rc;
3169 switch (p_params->timeout) {
3170 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3171 opcode = RESOURCE_OPCODE_REQ;
3172 p_params->timeout = 0;
3174 case ECORE_MCP_RESC_LOCK_TO_NONE:
3175 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3176 p_params->timeout = 0;
3179 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3183 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3184 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3185 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3187 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3188 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3189 param, p_params->timeout, opcode, p_params->resource);
3191 /* Attempt to acquire the resource */
3192 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3194 if (rc != ECORE_SUCCESS)
3197 /* Analyze the response */
3198 p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
3199 RESOURCE_CMD_RSP_OWNER);
3200 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3202 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3203 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3204 mcp_param, opcode, p_params->owner);
3207 case RESOURCE_OPCODE_GNT:
3208 p_params->b_granted = true;
3210 case RESOURCE_OPCODE_BUSY:
3211 p_params->b_granted = false;
3214 DP_NOTICE(p_hwfn, false,
3215 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3220 return ECORE_SUCCESS;
3223 enum _ecore_status_t
3224 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3225 struct ecore_resc_lock_params *p_params)
3228 enum _ecore_status_t rc;
3231 /* No need for an interval before the first iteration */
3233 if (p_params->sleep_b4_retry) {
3234 u16 retry_interval_in_ms =
3235 DIV_ROUND_UP(p_params->retry_interval,
3238 OSAL_MSLEEP(retry_interval_in_ms);
3240 OSAL_UDELAY(p_params->retry_interval);
3244 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3245 if (rc != ECORE_SUCCESS)
3248 if (p_params->b_granted)
3250 } while (retry_cnt++ < p_params->retry_num);
3252 return ECORE_SUCCESS;
3255 enum _ecore_status_t
3256 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3257 struct ecore_resc_unlock_params *p_params)
3259 u32 param = 0, mcp_resp, mcp_param;
3261 enum _ecore_status_t rc;
3263 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3264 : RESOURCE_OPCODE_RELEASE;
3265 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3266 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3268 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3269 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3270 param, opcode, p_params->resource);
3272 /* Attempt to release the resource */
3273 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3275 if (rc != ECORE_SUCCESS)
3278 /* Analyze the response */
3279 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3281 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3282 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3286 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3288 "Resource unlock request for an already released resource [%d]\n",
3289 p_params->resource);
3291 case RESOURCE_OPCODE_RELEASED:
3292 p_params->b_released = true;
3294 case RESOURCE_OPCODE_WRONG_OWNER:
3295 p_params->b_released = false;
3298 DP_NOTICE(p_hwfn, false,
3299 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3304 return ECORE_SUCCESS;
3307 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3309 return !!(p_hwfn->mcp_info->capabilities &
3310 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3313 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3314 struct ecore_ptt *p_ptt)
3317 enum _ecore_status_t rc;
3319 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3320 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3321 if (rc == ECORE_SUCCESS)
3322 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3323 "MFW supported features: %08x\n",
3324 p_hwfn->mcp_info->capabilities);
3329 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3330 struct ecore_ptt *p_ptt)
3332 u32 mcp_resp, mcp_param, features;
3334 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ;
3336 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3337 features, &mcp_resp, &mcp_param);