2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
24 #define CHIP_MCP_RESP_ITER_US 10
25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 OFFSETOF(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 OFFSETOF(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_OFFSET)
48 #define MCP_BYTES_PER_MBIT_OFFSET 17
52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
57 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
64 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
66 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
68 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
70 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
71 "port_addr = 0x%x, port_id 0x%02x\n",
72 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
77 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
82 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
86 if (!p_hwfn->mcp_info->public_base)
89 for (i = 0; i < length; i++) {
90 tmp = ecore_rd(p_hwfn, p_ptt,
91 p_hwfn->mcp_info->mfw_mb_addr +
92 (i << 2) + sizeof(u32));
94 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
95 OSAL_BE32_TO_CPU(tmp);
99 struct ecore_mcp_cmd_elem {
100 osal_list_entry_t list;
101 struct ecore_mcp_mb_params *p_mb_params;
102 u16 expected_seq_num;
106 /* Must be called while cmd_lock is acquired */
107 static struct ecore_mcp_cmd_elem *
108 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
109 struct ecore_mcp_mb_params *p_mb_params,
110 u16 expected_seq_num)
112 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
114 p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
115 sizeof(*p_cmd_elem));
117 DP_NOTICE(p_hwfn, false,
118 "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
122 p_cmd_elem->p_mb_params = p_mb_params;
123 p_cmd_elem->expected_seq_num = expected_seq_num;
124 OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
129 /* Must be called while cmd_lock is acquired */
130 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
131 struct ecore_mcp_cmd_elem *p_cmd_elem)
133 OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
134 OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
137 /* Must be called while cmd_lock is acquired */
138 static struct ecore_mcp_cmd_elem *
139 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
141 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
143 OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
144 struct ecore_mcp_cmd_elem) {
145 if (p_cmd_elem->expected_seq_num == seq_num)
152 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
154 if (p_hwfn->mcp_info) {
155 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
157 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
158 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
159 &p_hwfn->mcp_info->cmd_list, list,
160 struct ecore_mcp_cmd_elem) {
161 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
163 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
165 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
166 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
167 #ifdef CONFIG_ECORE_LOCK_ALLOC
168 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
169 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
173 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
175 return ECORE_SUCCESS;
178 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
179 struct ecore_ptt *p_ptt)
181 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
182 u32 drv_mb_offsize, mfw_mb_offsize;
183 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
186 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
187 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
188 p_info->public_base = 0;
193 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
194 if (!p_info->public_base)
197 p_info->public_base |= GRCBASE_MCP;
199 /* Calculate the driver and MFW mailbox address */
200 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
201 SECTION_OFFSIZE_ADDR(p_info->public_base,
203 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
204 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
205 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
206 " mcp_pf_id = 0x%x\n",
207 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
209 /* Set the MFW MB address */
210 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
211 SECTION_OFFSIZE_ADDR(p_info->public_base,
213 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
214 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
215 p_info->mfw_mb_addr);
217 /* Get the current driver mailbox sequence before sending
220 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
221 DRV_MSG_SEQ_NUMBER_MASK;
223 /* Get current FW pulse sequence */
224 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
227 p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
229 return ECORE_SUCCESS;
232 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
233 struct ecore_ptt *p_ptt)
235 struct ecore_mcp_info *p_info;
238 /* Allocate mcp_info structure */
239 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
240 sizeof(*p_hwfn->mcp_info));
241 if (!p_hwfn->mcp_info)
243 p_info = p_hwfn->mcp_info;
245 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
246 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
247 /* Do not free mcp_info here, since public_base indicate that
248 * the MCP is not initialized
250 return ECORE_SUCCESS;
253 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
254 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
255 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
256 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
259 /* Initialize the MFW spinlocks */
260 #ifdef CONFIG_ECORE_LOCK_ALLOC
261 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
262 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
264 OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
265 OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
267 OSAL_LIST_INIT(&p_info->cmd_list);
269 return ECORE_SUCCESS;
272 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
273 ecore_mcp_free(p_hwfn);
277 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
278 struct ecore_ptt *p_ptt)
280 u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
282 /* Use MCP history register to check if MCP reset occurred between init
285 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
286 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
287 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
288 p_hwfn->mcp_info->mcp_hist, generic_por_0);
290 ecore_load_mcp_offsets(p_hwfn, p_ptt);
291 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
295 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
296 struct ecore_ptt *p_ptt)
298 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
299 enum _ecore_status_t rc = ECORE_SUCCESS;
302 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
303 delay = EMUL_MCP_RESP_ITER_US;
306 /* Ensure that only a single thread is accessing the mailbox */
307 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
309 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
311 /* Set drv command along with the updated sequence */
312 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
313 seq = ++p_hwfn->mcp_info->drv_mb_seq;
314 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
317 /* Wait for MFW response */
319 /* Give the FW up to 500 second (50*1000*10usec) */
320 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
321 MISCS_REG_GENERIC_POR_0)) &&
322 (cnt++ < ECORE_MCP_RESET_RETRIES));
324 if (org_mcp_reset_seq !=
325 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
326 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
327 "MCP was reset after %d usec\n", cnt * delay);
329 DP_ERR(p_hwfn, "Failed to reset MCP\n");
333 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
338 /* Must be called while cmd_lock is acquired */
339 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
341 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
343 /* There is at most one pending command at a certain time, and if it
344 * exists - it is placed at the HEAD of the list.
346 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
347 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
348 struct ecore_mcp_cmd_elem,
350 return !p_cmd_elem->b_is_completed;
356 /* Must be called while cmd_lock is acquired */
357 static enum _ecore_status_t
358 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
360 struct ecore_mcp_mb_params *p_mb_params;
361 struct ecore_mcp_cmd_elem *p_cmd_elem;
365 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
366 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
368 /* Return if no new non-handled response has been received */
369 if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
372 p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
375 "Failed to find a pending mailbox cmd that expects sequence number %d\n",
377 return ECORE_UNKNOWN_ERROR;
380 p_mb_params = p_cmd_elem->p_mb_params;
382 /* Get the MFW response along with the sequence number */
383 p_mb_params->mcp_resp = mcp_resp;
385 /* Get the MFW param */
386 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
388 /* Get the union data */
389 if (p_mb_params->p_data_dst != OSAL_NULL &&
390 p_mb_params->data_dst_size) {
391 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
392 OFFSETOF(struct public_drv_mb,
394 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
395 union_data_addr, p_mb_params->data_dst_size);
398 p_cmd_elem->b_is_completed = true;
400 return ECORE_SUCCESS;
403 /* Must be called while cmd_lock is acquired */
404 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
405 struct ecore_ptt *p_ptt,
406 struct ecore_mcp_mb_params *p_mb_params,
409 union drv_union_data union_data;
412 /* Set the union data */
413 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
414 OFFSETOF(struct public_drv_mb, union_data);
415 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
416 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
417 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
418 p_mb_params->data_src_size);
419 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
422 /* Set the drv param */
423 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
425 /* Set the drv command along with the sequence number */
426 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
428 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
429 "MFW mailbox: command 0x%08x param 0x%08x\n",
430 (p_mb_params->cmd | seq_num), p_mb_params->param);
433 static enum _ecore_status_t
434 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
435 struct ecore_mcp_mb_params *p_mb_params,
436 u32 max_retries, u32 delay)
438 struct ecore_mcp_cmd_elem *p_cmd_elem;
441 enum _ecore_status_t rc = ECORE_SUCCESS;
443 /* Wait until the mailbox is non-occupied */
445 /* Exit the loop if there is no pending command, or if the
446 * pending command is completed during this iteration.
447 * The spinlock stays locked until the command is sent.
450 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
452 if (!ecore_mcp_has_pending_cmd(p_hwfn))
455 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
456 if (rc == ECORE_SUCCESS)
458 else if (rc != ECORE_AGAIN)
461 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
463 } while (++cnt < max_retries);
465 if (cnt >= max_retries) {
466 DP_NOTICE(p_hwfn, false,
467 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
468 p_mb_params->cmd, p_mb_params->param);
472 /* Send the mailbox command */
473 ecore_mcp_reread_offsets(p_hwfn, p_ptt);
474 seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
475 p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
481 __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
482 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
484 /* Wait for the MFW response */
486 /* Exit the loop if the command is already completed, or if the
487 * command is completed during this iteration.
488 * The spinlock stays locked until the list element is removed.
492 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
494 if (p_cmd_elem->b_is_completed)
497 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
498 if (rc == ECORE_SUCCESS)
500 else if (rc != ECORE_AGAIN)
503 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
504 } while (++cnt < max_retries);
506 if (cnt >= max_retries) {
507 DP_NOTICE(p_hwfn, false,
508 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
509 p_mb_params->cmd, p_mb_params->param);
511 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
512 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
513 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
515 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
519 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
520 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
522 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
523 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
524 p_mb_params->mcp_resp, p_mb_params->mcp_param,
525 (cnt * delay) / 1000, (cnt * delay) % 1000);
527 /* Clear the sequence number from the MFW response */
528 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
530 return ECORE_SUCCESS;
533 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
537 static enum _ecore_status_t
538 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
539 struct ecore_ptt *p_ptt,
540 struct ecore_mcp_mb_params *p_mb_params)
542 osal_size_t union_data_size = sizeof(union drv_union_data);
543 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
544 u32 delay = CHIP_MCP_RESP_ITER_US;
547 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
548 delay = EMUL_MCP_RESP_ITER_US;
549 /* There is a built-in delay of 100usec in each MFW response read */
550 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
554 /* MCP not initialized */
555 if (!ecore_mcp_is_init(p_hwfn)) {
556 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
560 if (p_mb_params->data_src_size > union_data_size ||
561 p_mb_params->data_dst_size > union_data_size) {
563 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
564 p_mb_params->data_src_size, p_mb_params->data_dst_size,
569 return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
573 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
574 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
575 u32 *o_mcp_resp, u32 *o_mcp_param)
577 struct ecore_mcp_mb_params mb_params;
578 enum _ecore_status_t rc;
581 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
582 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
584 loaded_port[p_hwfn->port_id]--;
585 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
588 return ECORE_SUCCESS;
592 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
594 mb_params.param = param;
595 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
596 if (rc != ECORE_SUCCESS)
599 *o_mcp_resp = mb_params.mcp_resp;
600 *o_mcp_param = mb_params.mcp_param;
602 return ECORE_SUCCESS;
605 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
606 struct ecore_ptt *p_ptt,
611 u32 i_txn_size, u32 *i_buf)
613 struct ecore_mcp_mb_params mb_params;
614 enum _ecore_status_t rc;
616 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
618 mb_params.param = param;
619 mb_params.p_data_src = i_buf;
620 mb_params.data_src_size = (u8)i_txn_size;
621 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
622 if (rc != ECORE_SUCCESS)
625 *o_mcp_resp = mb_params.mcp_resp;
626 *o_mcp_param = mb_params.mcp_param;
628 return ECORE_SUCCESS;
631 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
632 struct ecore_ptt *p_ptt,
637 u32 *o_txn_size, u32 *o_buf)
639 struct ecore_mcp_mb_params mb_params;
640 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
641 enum _ecore_status_t rc;
643 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
645 mb_params.param = param;
646 mb_params.p_data_dst = raw_data;
648 /* Use the maximal value since the actual one is part of the response */
649 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
651 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
652 if (rc != ECORE_SUCCESS)
655 *o_mcp_resp = mb_params.mcp_resp;
656 *o_mcp_param = mb_params.mcp_param;
658 *o_txn_size = *o_mcp_param;
660 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
662 return ECORE_SUCCESS;
666 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
669 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
672 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
673 else if (!loaded_port[p_hwfn->port_id])
674 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
676 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
678 /* On CMT, always tell that it's engine */
679 if (p_hwfn->p_dev->num_hwfns > 1)
680 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
682 *p_load_code = load_phase;
684 loaded_port[p_hwfn->port_id]++;
686 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
687 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
688 *p_load_code, loaded, p_hwfn->port_id,
689 loaded_port[p_hwfn->port_id]);
694 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
695 enum ecore_override_force_load override_force_load)
697 bool can_force_load = false;
699 switch (override_force_load) {
700 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
701 can_force_load = true;
703 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
704 can_force_load = false;
707 can_force_load = (drv_role == DRV_ROLE_OS &&
708 exist_drv_role == DRV_ROLE_PREBOOT) ||
709 (drv_role == DRV_ROLE_KDUMP &&
710 exist_drv_role == DRV_ROLE_OS);
714 return can_force_load;
717 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
718 struct ecore_ptt *p_ptt)
720 u32 resp = 0, param = 0;
721 enum _ecore_status_t rc;
723 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
725 if (rc != ECORE_SUCCESS)
726 DP_NOTICE(p_hwfn, false,
727 "Failed to send cancel load request, rc = %d\n", rc);
732 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
733 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
734 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
735 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
736 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
737 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
738 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
740 static u32 ecore_get_config_bitmap(void)
742 u32 config_bitmap = 0x0;
744 #ifdef CONFIG_ECORE_L2
745 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
747 #ifdef CONFIG_ECORE_SRIOV
748 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
750 #ifdef CONFIG_ECORE_ROCE
751 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
753 #ifdef CONFIG_ECORE_IWARP
754 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
756 #ifdef CONFIG_ECORE_FCOE
757 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
759 #ifdef CONFIG_ECORE_ISCSI
760 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
762 #ifdef CONFIG_ECORE_LL2
763 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
766 return config_bitmap;
769 struct ecore_load_req_in_params {
771 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
772 #define ECORE_LOAD_REQ_HSI_VER_1 1
779 bool avoid_eng_reset;
782 struct ecore_load_req_out_params {
792 static enum _ecore_status_t
793 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
794 struct ecore_load_req_in_params *p_in_params,
795 struct ecore_load_req_out_params *p_out_params)
797 struct ecore_mcp_mb_params mb_params;
798 struct load_req_stc load_req;
799 struct load_rsp_stc load_rsp;
801 enum _ecore_status_t rc;
803 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
804 load_req.drv_ver_0 = p_in_params->drv_ver_0;
805 load_req.drv_ver_1 = p_in_params->drv_ver_1;
806 load_req.fw_ver = p_in_params->fw_ver;
807 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
808 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
809 p_in_params->timeout_val);
810 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
811 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
812 p_in_params->avoid_eng_reset);
814 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
815 DRV_ID_MCP_HSI_VER_CURRENT :
816 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
818 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
819 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
820 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
821 mb_params.p_data_src = &load_req;
822 mb_params.data_src_size = sizeof(load_req);
823 mb_params.p_data_dst = &load_rsp;
824 mb_params.data_dst_size = sizeof(load_rsp);
826 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
827 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
829 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
830 GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
831 GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
832 GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
834 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
835 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
836 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
837 load_req.drv_ver_0, load_req.drv_ver_1,
838 load_req.fw_ver, load_req.misc0,
839 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
840 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
841 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
842 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
844 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
845 if (rc != ECORE_SUCCESS) {
846 DP_NOTICE(p_hwfn, false,
847 "Failed to send load request, rc = %d\n", rc);
851 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
852 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
853 p_out_params->load_code = mb_params.mcp_resp;
855 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
856 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
857 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
858 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
859 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
860 load_rsp.fw_ver, load_rsp.misc0,
861 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
862 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
863 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
865 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
866 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
867 p_out_params->exist_fw_ver = load_rsp.fw_ver;
868 p_out_params->exist_drv_role =
869 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
870 p_out_params->mfw_hsi_ver =
871 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
872 p_out_params->drv_exists =
873 GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
874 LOAD_RSP_FLAGS0_DRV_EXISTS;
877 return ECORE_SUCCESS;
880 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
881 enum ecore_drv_role drv_role,
885 case ECORE_DRV_ROLE_OS:
886 *p_mfw_drv_role = DRV_ROLE_OS;
888 case ECORE_DRV_ROLE_KDUMP:
889 *p_mfw_drv_role = DRV_ROLE_KDUMP;
894 enum ecore_load_req_force {
895 ECORE_LOAD_REQ_FORCE_NONE,
896 ECORE_LOAD_REQ_FORCE_PF,
897 ECORE_LOAD_REQ_FORCE_ALL,
900 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
901 enum ecore_load_req_force force_cmd,
905 case ECORE_LOAD_REQ_FORCE_NONE:
906 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
908 case ECORE_LOAD_REQ_FORCE_PF:
909 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
911 case ECORE_LOAD_REQ_FORCE_ALL:
912 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
917 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
918 struct ecore_ptt *p_ptt,
919 struct ecore_load_req_params *p_params)
921 struct ecore_load_req_out_params out_params;
922 struct ecore_load_req_in_params in_params;
923 u8 mfw_drv_role = 0, mfw_force_cmd;
924 enum _ecore_status_t rc;
927 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
928 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
929 return ECORE_SUCCESS;
933 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
934 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
935 in_params.drv_ver_0 = ECORE_VERSION;
936 in_params.drv_ver_1 = ecore_get_config_bitmap();
937 in_params.fw_ver = STORM_FW_VERSION;
938 ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
939 in_params.drv_role = mfw_drv_role;
940 in_params.timeout_val = p_params->timeout_val;
941 ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
943 in_params.force_cmd = mfw_force_cmd;
944 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
946 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
947 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
948 if (rc != ECORE_SUCCESS)
951 /* First handle cases where another load request should/might be sent:
952 * - MFW expects the old interface [HSI version = 1]
953 * - MFW responds that a force load request is required
955 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
957 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
959 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
960 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
961 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
963 if (rc != ECORE_SUCCESS)
965 } else if (out_params.load_code ==
966 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
967 if (ecore_mcp_can_force_load(in_params.drv_role,
968 out_params.exist_drv_role,
969 p_params->override_force_load)) {
971 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
972 in_params.drv_role, in_params.fw_ver,
973 in_params.drv_ver_0, in_params.drv_ver_1,
974 out_params.exist_drv_role,
975 out_params.exist_fw_ver,
976 out_params.exist_drv_ver_0,
977 out_params.exist_drv_ver_1);
979 ecore_get_mfw_force_cmd(p_hwfn,
980 ECORE_LOAD_REQ_FORCE_ALL,
983 in_params.force_cmd = mfw_force_cmd;
984 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
985 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
987 if (rc != ECORE_SUCCESS)
990 DP_NOTICE(p_hwfn, false,
991 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
992 in_params.drv_role, in_params.fw_ver,
993 in_params.drv_ver_0, in_params.drv_ver_1,
994 out_params.exist_drv_role,
995 out_params.exist_fw_ver,
996 out_params.exist_drv_ver_0,
997 out_params.exist_drv_ver_1);
999 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1004 /* Now handle the other types of responses.
1005 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1006 * expected here after the additional revised load requests were sent.
1008 switch (out_params.load_code) {
1009 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1010 case FW_MSG_CODE_DRV_LOAD_PORT:
1011 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1012 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1013 out_params.drv_exists) {
1014 /* The role and fw/driver version match, but the PF is
1015 * already loaded and has not been unloaded gracefully.
1016 * This is unexpected since a quasi-FLR request was
1017 * previously sent as part of ecore_hw_prepare().
1019 DP_NOTICE(p_hwfn, false,
1020 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1025 DP_NOTICE(p_hwfn, false,
1026 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1027 out_params.load_code);
1031 p_params->load_code = out_params.load_code;
1033 return ECORE_SUCCESS;
1036 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1037 struct ecore_ptt *p_ptt)
1039 u32 resp = 0, param = 0;
1040 enum _ecore_status_t rc;
1042 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1044 if (rc != ECORE_SUCCESS) {
1045 DP_NOTICE(p_hwfn, false,
1046 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1050 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
1052 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1053 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1054 DP_NOTICE(p_hwfn, false,
1055 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1057 return ECORE_SUCCESS;
1060 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1061 struct ecore_ptt *p_ptt)
1063 u32 wol_param, mcp_resp, mcp_param;
1066 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1068 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1069 &mcp_resp, &mcp_param);
1072 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1073 struct ecore_ptt *p_ptt)
1075 struct ecore_mcp_mb_params mb_params;
1076 struct mcp_mac wol_mac;
1078 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1079 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1081 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1084 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1085 struct ecore_ptt *p_ptt)
1087 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1089 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1090 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1091 ECORE_PATH_ID(p_hwfn));
1092 u32 disabled_vfs[VF_MAX_STATIC / 32];
1095 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1096 "Reading Disabled VF information from [offset %08x],"
1097 " path_addr %08x\n",
1098 mfw_path_offsize, path_addr);
1100 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1101 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1103 OFFSETOF(struct public_path,
1106 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1107 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1108 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1111 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1112 OSAL_VF_FLR_UPDATE(p_hwfn);
1115 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1116 struct ecore_ptt *p_ptt,
1119 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1121 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1122 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1124 struct ecore_mcp_mb_params mb_params;
1125 enum _ecore_status_t rc;
1128 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1129 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1130 "Acking VFs [%08x,...,%08x] - %08x\n",
1131 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1133 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1134 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1135 mb_params.p_data_src = vfs_to_ack;
1136 mb_params.data_src_size = VF_MAX_STATIC / 8;
1137 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1139 if (rc != ECORE_SUCCESS) {
1140 DP_NOTICE(p_hwfn, false,
1141 "Failed to pass ACK for VF flr to MFW\n");
1142 return ECORE_TIMEOUT;
1145 /* TMP - clear the ACK bits; should be done by MFW */
1146 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1147 ecore_wr(p_hwfn, p_ptt,
1149 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1150 i * sizeof(u32), 0);
1155 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1156 struct ecore_ptt *p_ptt)
1158 u32 transceiver_state;
1160 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1161 p_hwfn->mcp_info->port_addr +
1162 OFFSETOF(struct public_port,
1165 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1166 "Received transceiver state update [0x%08x] from mfw"
1168 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1169 OFFSETOF(struct public_port,
1170 transceiver_data)));
1172 transceiver_state = GET_MFW_FIELD(transceiver_state,
1173 ETH_TRANSCEIVER_STATE);
1175 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1176 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1178 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1181 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1182 struct ecore_ptt *p_ptt,
1183 struct ecore_mcp_link_state *p_link)
1185 u32 eee_status, val;
1187 p_link->eee_adv_caps = 0;
1188 p_link->eee_lp_adv_caps = 0;
1189 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1190 OFFSETOF(struct public_port, eee_status));
1191 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1192 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1193 if (val & EEE_1G_ADV)
1194 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1195 if (val & EEE_10G_ADV)
1196 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1197 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1198 if (val & EEE_1G_ADV)
1199 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1200 if (val & EEE_10G_ADV)
1201 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1204 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1205 struct ecore_ptt *p_ptt,
1208 struct ecore_mcp_link_state *p_link;
1212 /* Prevent SW/attentions from doing this at the same time */
1213 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1215 p_link = &p_hwfn->mcp_info->link_output;
1216 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1218 status = ecore_rd(p_hwfn, p_ptt,
1219 p_hwfn->mcp_info->port_addr +
1220 OFFSETOF(struct public_port, link_status));
1221 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1222 "Received link update [0x%08x] from mfw"
1224 status, (u32)(p_hwfn->mcp_info->port_addr +
1225 OFFSETOF(struct public_port,
1228 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1229 "Resetting link indications\n");
1233 if (p_hwfn->b_drv_link_init)
1234 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1236 p_link->link_up = false;
1238 p_link->full_duplex = true;
1239 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1240 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1241 p_link->speed = 100000;
1243 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1244 p_link->speed = 50000;
1246 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1247 p_link->speed = 40000;
1249 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1250 p_link->speed = 25000;
1252 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1253 p_link->speed = 20000;
1255 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1256 p_link->speed = 10000;
1258 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1259 p_link->full_duplex = false;
1261 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1262 p_link->speed = 1000;
1268 /* We never store total line speed as p_link->speed is
1269 * again changes according to bandwidth allocation.
1271 if (p_link->link_up && p_link->speed)
1272 p_link->line_speed = p_link->speed;
1274 p_link->line_speed = 0;
1276 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1277 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1279 /* Max bandwidth configuration */
1280 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1283 /* Mintz bandwidth configuration */
1284 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1286 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1287 p_link->min_pf_rate);
1289 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1290 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1291 p_link->parallel_detection = !!(status &
1292 LINK_STATUS_PARALLEL_DETECTION_USED);
1293 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1295 p_link->partner_adv_speed |=
1296 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1297 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1298 p_link->partner_adv_speed |=
1299 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1300 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1301 p_link->partner_adv_speed |=
1302 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1303 ECORE_LINK_PARTNER_SPEED_10G : 0;
1304 p_link->partner_adv_speed |=
1305 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1306 ECORE_LINK_PARTNER_SPEED_20G : 0;
1307 p_link->partner_adv_speed |=
1308 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1309 ECORE_LINK_PARTNER_SPEED_25G : 0;
1310 p_link->partner_adv_speed |=
1311 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1312 ECORE_LINK_PARTNER_SPEED_40G : 0;
1313 p_link->partner_adv_speed |=
1314 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1315 ECORE_LINK_PARTNER_SPEED_50G : 0;
1316 p_link->partner_adv_speed |=
1317 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1318 ECORE_LINK_PARTNER_SPEED_100G : 0;
1320 p_link->partner_tx_flow_ctrl_en =
1321 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1322 p_link->partner_rx_flow_ctrl_en =
1323 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1325 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1326 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1327 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1329 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1330 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1332 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1333 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1336 p_link->partner_adv_pause = 0;
1339 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1341 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1342 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1344 OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1346 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1349 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1350 struct ecore_ptt *p_ptt, bool b_up)
1352 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1353 struct ecore_mcp_mb_params mb_params;
1354 struct eth_phy_cfg phy_cfg;
1355 enum _ecore_status_t rc = ECORE_SUCCESS;
1359 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1360 return ECORE_SUCCESS;
1363 /* Set the shmem configuration according to params */
1364 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1365 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1366 if (!params->speed.autoneg)
1367 phy_cfg.speed = params->speed.forced_speed;
1368 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1369 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1370 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1371 phy_cfg.adv_speed = params->speed.advertised_speeds;
1372 phy_cfg.loopback_mode = params->loopback_mode;
1374 /* There are MFWs that share this capability regardless of whether
1375 * this is feasible or not. And given that at the very least adv_caps
1376 * would be set internally by ecore, we want to make sure LFA would
1379 if ((p_hwfn->mcp_info->capabilities &
1380 FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1381 params->eee.enable) {
1382 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1383 if (params->eee.tx_lpi_enable)
1384 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1385 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1386 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1387 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1388 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1389 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1390 EEE_TX_TIMER_USEC_OFFSET) &
1391 EEE_TX_TIMER_USEC_MASK;
1394 p_hwfn->b_drv_link_init = b_up;
1397 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1398 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1399 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1400 phy_cfg.loopback_mode);
1402 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1404 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1405 mb_params.cmd = cmd;
1406 mb_params.p_data_src = &phy_cfg;
1407 mb_params.data_src_size = sizeof(phy_cfg);
1408 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1410 /* if mcp fails to respond we must abort */
1411 if (rc != ECORE_SUCCESS) {
1412 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1416 /* Mimic link-change attention, done for several reasons:
1417 * - On reset, there's no guarantee MFW would trigger
1419 * - On initialization, older MFWs might not indicate link change
1420 * during LFA, so we'll never get an UP indication.
1422 ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1427 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1428 struct ecore_ptt *p_ptt)
1430 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1432 /* TODO - Add support for VFs */
1433 if (IS_VF(p_hwfn->p_dev))
1436 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1438 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1439 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1441 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1443 OFFSETOF(struct public_path, process_kill)) &
1444 PROCESS_KILL_COUNTER_MASK;
1446 return proc_kill_cnt;
1449 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1450 struct ecore_ptt *p_ptt)
1452 struct ecore_dev *p_dev = p_hwfn->p_dev;
1455 /* Prevent possible attentions/interrupts during the recovery handling
1456 * and till its load phase, during which they will be re-enabled.
1458 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1460 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1462 /* The following operations should be done once, and thus in CMT mode
1463 * are carried out by only the first HW function.
1465 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1468 if (p_dev->recov_in_prog) {
1469 DP_NOTICE(p_hwfn, false,
1470 "Ignoring the indication since a recovery"
1471 " process is already in progress\n");
1475 p_dev->recov_in_prog = true;
1477 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1478 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1480 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1483 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1484 struct ecore_ptt *p_ptt,
1485 enum MFW_DRV_MSG_TYPE type)
1487 enum ecore_mcp_protocol_type stats_type;
1488 union ecore_mcp_protocol_stats stats;
1489 struct ecore_mcp_mb_params mb_params;
1491 enum _ecore_status_t rc;
1494 case MFW_DRV_MSG_GET_LAN_STATS:
1495 stats_type = ECORE_MCP_LAN_STATS;
1496 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1499 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1503 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1505 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1506 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1507 mb_params.param = hsi_param;
1508 mb_params.p_data_src = &stats;
1509 mb_params.data_src_size = sizeof(stats);
1510 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1511 if (rc != ECORE_SUCCESS)
1512 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1515 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1516 struct public_func *p_shmem_info)
1518 struct ecore_mcp_function_info *p_info;
1520 p_info = &p_hwfn->mcp_info->func_info;
1522 /* TODO - bandwidth min/max should have valid values of 1-100,
1523 * as well as some indication that the feature is disabled.
1524 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1525 * limit and correct value to min `1' and max `100' if limit isn't in
1528 p_info->bandwidth_min = (p_shmem_info->config &
1529 FUNC_MF_CFG_MIN_BW_MASK) >>
1530 FUNC_MF_CFG_MIN_BW_OFFSET;
1531 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1533 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1534 p_info->bandwidth_min);
1535 p_info->bandwidth_min = 1;
1538 p_info->bandwidth_max = (p_shmem_info->config &
1539 FUNC_MF_CFG_MAX_BW_MASK) >>
1540 FUNC_MF_CFG_MAX_BW_OFFSET;
1541 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1543 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1544 p_info->bandwidth_max);
1545 p_info->bandwidth_max = 100;
1549 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1550 struct ecore_ptt *p_ptt,
1551 struct public_func *p_data,
1554 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1556 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1557 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1560 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1562 size = OSAL_MIN_T(u32, sizeof(*p_data),
1563 SECTION_SIZE(mfw_path_offsize));
1564 for (i = 0; i < size / sizeof(u32); i++)
1565 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1566 func_addr + (i << 2));
1572 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1574 struct ecore_mcp_function_info *p_info;
1575 struct public_func shmem_info;
1576 u32 resp = 0, param = 0;
1578 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1580 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1582 p_info = &p_hwfn->mcp_info->func_info;
1584 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1586 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1588 /* Acknowledge the MFW */
1589 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1593 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1594 struct ecore_ptt *p_ptt)
1596 /* A single notification should be sent to upper driver in CMT mode */
1597 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1600 DP_NOTICE(p_hwfn, false,
1601 "Fan failure was detected on the network interface card"
1602 " and it's going to be shut down.\n");
1604 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1607 struct ecore_mdump_cmd_params {
1616 static enum _ecore_status_t
1617 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1618 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1620 struct ecore_mcp_mb_params mb_params;
1621 enum _ecore_status_t rc;
1623 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1624 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1625 mb_params.param = p_mdump_cmd_params->cmd;
1626 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1627 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1628 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1629 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1630 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1631 if (rc != ECORE_SUCCESS)
1634 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1636 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1638 "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1639 p_mdump_cmd_params->cmd);
1641 } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1643 "The mdump command is not supported by the MFW\n");
1650 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1651 struct ecore_ptt *p_ptt)
1653 struct ecore_mdump_cmd_params mdump_cmd_params;
1655 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1656 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1658 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1661 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1662 struct ecore_ptt *p_ptt,
1665 struct ecore_mdump_cmd_params mdump_cmd_params;
1667 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1668 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1669 mdump_cmd_params.p_data_src = &epoch;
1670 mdump_cmd_params.data_src_size = sizeof(epoch);
1672 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1675 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1676 struct ecore_ptt *p_ptt)
1678 struct ecore_mdump_cmd_params mdump_cmd_params;
1680 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1681 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1683 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1686 static enum _ecore_status_t
1687 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1688 struct mdump_config_stc *p_mdump_config)
1690 struct ecore_mdump_cmd_params mdump_cmd_params;
1691 enum _ecore_status_t rc;
1693 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1694 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1695 mdump_cmd_params.p_data_dst = p_mdump_config;
1696 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1698 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1699 if (rc != ECORE_SUCCESS)
1702 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1704 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1705 mdump_cmd_params.mcp_resp);
1706 rc = ECORE_UNKNOWN_ERROR;
1712 enum _ecore_status_t
1713 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1714 struct ecore_mdump_info *p_mdump_info)
1716 u32 addr, global_offsize, global_addr;
1717 struct mdump_config_stc mdump_config;
1718 enum _ecore_status_t rc;
1720 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1722 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1724 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1725 global_addr = SECTION_ADDR(global_offsize, 0);
1726 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1728 OFFSETOF(struct public_global,
1731 if (p_mdump_info->reason) {
1732 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1733 if (rc != ECORE_SUCCESS)
1736 p_mdump_info->version = mdump_config.version;
1737 p_mdump_info->config = mdump_config.config;
1738 p_mdump_info->epoch = mdump_config.epoc;
1739 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1740 p_mdump_info->valid_logs = mdump_config.valid_logs;
1742 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1743 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1744 p_mdump_info->reason, p_mdump_info->version,
1745 p_mdump_info->config, p_mdump_info->epoch,
1746 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1748 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1749 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1752 return ECORE_SUCCESS;
1755 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1756 struct ecore_ptt *p_ptt)
1758 struct ecore_mdump_cmd_params mdump_cmd_params;
1760 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1761 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1763 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1766 enum _ecore_status_t
1767 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1768 struct ecore_mdump_retain_data *p_mdump_retain)
1770 struct ecore_mdump_cmd_params mdump_cmd_params;
1771 struct mdump_retain_data_stc mfw_mdump_retain;
1772 enum _ecore_status_t rc;
1774 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1775 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1776 mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1777 mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1779 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1780 if (rc != ECORE_SUCCESS)
1783 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1785 "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1786 mdump_cmd_params.mcp_resp);
1787 return ECORE_UNKNOWN_ERROR;
1790 p_mdump_retain->valid = mfw_mdump_retain.valid;
1791 p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1792 p_mdump_retain->pf = mfw_mdump_retain.pf;
1793 p_mdump_retain->status = mfw_mdump_retain.status;
1795 return ECORE_SUCCESS;
1798 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1799 struct ecore_ptt *p_ptt)
1801 struct ecore_mdump_cmd_params mdump_cmd_params;
1803 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1804 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1806 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1809 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1810 struct ecore_ptt *p_ptt)
1812 struct ecore_mdump_retain_data mdump_retain;
1813 enum _ecore_status_t rc;
1815 /* In CMT mode - no need for more than a single acknowledgment to the
1816 * MFW, and no more than a single notification to the upper driver.
1818 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1821 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1822 if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1823 DP_NOTICE(p_hwfn, false,
1824 "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1825 mdump_retain.epoch, mdump_retain.pf,
1826 mdump_retain.status);
1828 DP_NOTICE(p_hwfn, false,
1829 "The MFW notified that a critical error occurred in the device\n");
1832 if (p_hwfn->p_dev->allow_mdump) {
1833 DP_NOTICE(p_hwfn, false,
1834 "Not acknowledging the notification to allow the MFW crash dump\n");
1838 DP_NOTICE(p_hwfn, false,
1839 "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1840 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1841 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1844 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1845 struct ecore_ptt *p_ptt)
1847 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1848 enum _ecore_status_t rc = ECORE_SUCCESS;
1852 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1854 /* Read Messages from MFW */
1855 ecore_mcp_read_mb(p_hwfn, p_ptt);
1857 /* Compare current messages to old ones */
1858 for (i = 0; i < info->mfw_mb_length; i++) {
1859 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1864 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1865 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1866 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1869 case MFW_DRV_MSG_LINK_CHANGE:
1870 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1872 case MFW_DRV_MSG_VF_DISABLED:
1873 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1875 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1876 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1877 ECORE_DCBX_REMOTE_LLDP_MIB);
1879 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1880 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1881 ECORE_DCBX_REMOTE_MIB);
1883 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1884 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1885 ECORE_DCBX_OPERATIONAL_MIB);
1887 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1888 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1890 case MFW_DRV_MSG_ERROR_RECOVERY:
1891 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1893 case MFW_DRV_MSG_GET_LAN_STATS:
1894 case MFW_DRV_MSG_GET_FCOE_STATS:
1895 case MFW_DRV_MSG_GET_ISCSI_STATS:
1896 case MFW_DRV_MSG_GET_RDMA_STATS:
1897 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1899 case MFW_DRV_MSG_BW_UPDATE:
1900 ecore_mcp_update_bw(p_hwfn, p_ptt);
1902 case MFW_DRV_MSG_FAILURE_DETECTED:
1903 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1905 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1906 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1909 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1914 /* ACK everything */
1915 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1916 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1918 /* MFW expect answer in BE, so we force write in that format */
1919 ecore_wr(p_hwfn, p_ptt,
1920 info->mfw_mb_addr + sizeof(u32) +
1921 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1922 sizeof(u32) + i * sizeof(u32), val);
1926 DP_NOTICE(p_hwfn, false,
1927 "Received an MFW message indication but no"
1932 /* Copy the new mfw messages into the shadow */
1933 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1938 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1939 struct ecore_ptt *p_ptt,
1941 u32 *p_running_bundle_id)
1946 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1947 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1948 return ECORE_SUCCESS;
1952 if (IS_VF(p_hwfn->p_dev)) {
1953 if (p_hwfn->vf_iov_info) {
1954 struct pfvf_acquire_resp_tlv *p_resp;
1956 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1957 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1958 return ECORE_SUCCESS;
1960 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1961 "VF requested MFW version prior to ACQUIRE\n");
1966 global_offsize = ecore_rd(p_hwfn, p_ptt,
1967 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1971 ecore_rd(p_hwfn, p_ptt,
1972 SECTION_ADDR(global_offsize,
1973 0) + OFFSETOF(struct public_global, mfw_ver));
1975 if (p_running_bundle_id != OSAL_NULL) {
1976 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1977 SECTION_ADDR(global_offsize,
1979 OFFSETOF(struct public_global,
1980 running_bundle_id));
1983 return ECORE_SUCCESS;
1986 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
1987 struct ecore_ptt *p_ptt,
1991 /* TODO - Add support for VFs */
1992 if (IS_VF(p_hwfn->p_dev))
1995 if (!ecore_mcp_is_init(p_hwfn)) {
1996 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2001 *p_media_type = MEDIA_UNSPECIFIED;
2004 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2005 p_hwfn->mcp_info->port_addr +
2006 OFFSETOF(struct public_port,
2010 return ECORE_SUCCESS;
2014 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2016 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2017 enum ecore_pci_personality *p_proto)
2019 *p_proto = ECORE_PCI_ETH;
2021 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2022 "According to Legacy capabilities, L2 personality is %08x\n",
2027 static enum _ecore_status_t
2028 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2029 struct ecore_ptt *p_ptt,
2030 enum ecore_pci_personality *p_proto)
2032 u32 resp = 0, param = 0;
2033 enum _ecore_status_t rc;
2035 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2036 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2037 (u32)*p_proto, resp, param);
2038 return ECORE_SUCCESS;
2041 static enum _ecore_status_t
2042 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2043 struct public_func *p_info,
2044 struct ecore_ptt *p_ptt,
2045 enum ecore_pci_personality *p_proto)
2047 enum _ecore_status_t rc = ECORE_SUCCESS;
2049 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2050 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2051 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2053 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2062 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2063 struct ecore_ptt *p_ptt)
2065 struct ecore_mcp_function_info *info;
2066 struct public_func shmem_info;
2068 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2069 info = &p_hwfn->mcp_info->func_info;
2071 info->pause_on_host = (shmem_info.config &
2072 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2074 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2076 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2077 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2081 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2083 if (shmem_info.mac_upper || shmem_info.mac_lower) {
2084 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2085 info->mac[1] = (u8)(shmem_info.mac_upper);
2086 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2087 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2088 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2089 info->mac[5] = (u8)(shmem_info.mac_lower);
2091 /* TODO - are there protocols for which there's no MAC? */
2092 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2095 /* TODO - are these calculations true for BE machine? */
2096 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2097 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2098 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2099 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2101 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2103 info->mtu = (u16)shmem_info.mtu_size;
2108 info->mtu = (u16)shmem_info.mtu_size;
2110 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2111 "Read configuration from shmem: pause_on_host %02x"
2112 " protocol %02x BW [%02x - %02x]"
2113 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2114 " node %lx ovlan %04x\n",
2115 info->pause_on_host, info->protocol,
2116 info->bandwidth_min, info->bandwidth_max,
2117 info->mac[0], info->mac[1], info->mac[2],
2118 info->mac[3], info->mac[4], info->mac[5],
2119 (unsigned long)info->wwn_port,
2120 (unsigned long)info->wwn_node, info->ovlan);
2122 return ECORE_SUCCESS;
2125 struct ecore_mcp_link_params
2126 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2128 if (!p_hwfn || !p_hwfn->mcp_info)
2130 return &p_hwfn->mcp_info->link_input;
2133 struct ecore_mcp_link_state
2134 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2136 if (!p_hwfn || !p_hwfn->mcp_info)
2140 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2141 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2142 p_hwfn->mcp_info->link_output.link_up = true;
2146 return &p_hwfn->mcp_info->link_output;
2149 struct ecore_mcp_link_capabilities
2150 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2152 if (!p_hwfn || !p_hwfn->mcp_info)
2154 return &p_hwfn->mcp_info->link_capabilities;
2157 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2158 struct ecore_ptt *p_ptt)
2160 u32 resp = 0, param = 0;
2161 enum _ecore_status_t rc;
2163 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2164 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
2166 /* Wait for the drain to complete before returning */
2172 const struct ecore_mcp_function_info
2173 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2175 if (!p_hwfn || !p_hwfn->mcp_info)
2177 return &p_hwfn->mcp_info->func_info;
2180 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2181 struct ecore_ptt *p_ptt, u32 personalities)
2183 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2184 struct public_func shmem_info;
2185 int i, count = 0, num_pfs;
2187 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2189 for (i = 0; i < num_pfs; i++) {
2190 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2191 MCP_PF_ID_BY_REL(p_hwfn, i));
2192 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2195 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2200 if ((1 << ((u32)protocol)) & personalities)
2207 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2208 struct ecore_ptt *p_ptt,
2214 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2215 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2220 if (IS_VF(p_hwfn->p_dev))
2223 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2224 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2225 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2226 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2228 *p_flash_size = flash_size;
2230 return ECORE_SUCCESS;
2233 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2234 struct ecore_ptt *p_ptt)
2236 struct ecore_dev *p_dev = p_hwfn->p_dev;
2238 if (p_dev->recov_in_prog) {
2239 DP_NOTICE(p_hwfn, false,
2240 "Avoid triggering a recovery since such a process"
2241 " is already in progress\n");
2245 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2246 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2248 return ECORE_SUCCESS;
2251 static enum _ecore_status_t
2252 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2253 struct ecore_ptt *p_ptt,
2256 u32 resp = 0, param = 0, rc_param = 0;
2257 enum _ecore_status_t rc;
2259 /* Only Leader can configure MSIX, and need to take CMT into account */
2261 if (!IS_LEAD_HWFN(p_hwfn))
2262 return ECORE_SUCCESS;
2263 num *= p_hwfn->p_dev->num_hwfns;
2265 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2266 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2267 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2268 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2270 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2273 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2274 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2278 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2279 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2286 static enum _ecore_status_t
2287 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2288 struct ecore_ptt *p_ptt,
2291 u32 resp = 0, param = num, rc_param = 0;
2292 enum _ecore_status_t rc;
2294 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2295 param, &resp, &rc_param);
2297 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2298 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2301 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2302 "Requested 0x%02x MSI-x interrupts for VFs\n",
2309 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2310 struct ecore_ptt *p_ptt,
2313 if (ECORE_IS_BB(p_hwfn->p_dev))
2314 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2316 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2319 enum _ecore_status_t
2320 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2321 struct ecore_mcp_drv_version *p_ver)
2323 struct ecore_mcp_mb_params mb_params;
2324 struct drv_version_stc drv_version;
2328 enum _ecore_status_t rc;
2331 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2332 return ECORE_SUCCESS;
2335 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2336 drv_version.version = p_ver->version;
2337 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2338 for (i = 0; i < num_words; i++) {
2339 /* The driver name is expected to be in a big-endian format */
2340 p_name = &p_ver->name[i * sizeof(u32)];
2341 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2342 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2345 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2346 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2347 mb_params.p_data_src = &drv_version;
2348 mb_params.data_src_size = sizeof(drv_version);
2349 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2350 if (rc != ECORE_SUCCESS)
2351 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2356 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2357 struct ecore_ptt *p_ptt)
2359 enum _ecore_status_t rc;
2360 u32 resp = 0, param = 0;
2362 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2364 if (rc != ECORE_SUCCESS)
2365 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2370 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2371 struct ecore_ptt *p_ptt)
2373 u32 value, cpu_mode;
2375 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2377 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2378 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2379 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2380 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2382 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2385 enum _ecore_status_t
2386 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2387 struct ecore_ptt *p_ptt,
2388 enum ecore_ov_client client)
2390 enum _ecore_status_t rc;
2391 u32 resp = 0, param = 0;
2395 case ECORE_OV_CLIENT_DRV:
2396 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2398 case ECORE_OV_CLIENT_USER:
2399 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2401 case ECORE_OV_CLIENT_VENDOR_SPEC:
2402 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2405 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2409 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2410 drv_mb_param, &resp, ¶m);
2411 if (rc != ECORE_SUCCESS)
2412 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2417 enum _ecore_status_t
2418 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2419 struct ecore_ptt *p_ptt,
2420 enum ecore_ov_driver_state drv_state)
2422 enum _ecore_status_t rc;
2423 u32 resp = 0, param = 0;
2426 switch (drv_state) {
2427 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2428 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2430 case ECORE_OV_DRIVER_STATE_DISABLED:
2431 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2433 case ECORE_OV_DRIVER_STATE_ACTIVE:
2434 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2437 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2441 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2442 drv_mb_param, &resp, ¶m);
2443 if (rc != ECORE_SUCCESS)
2444 DP_ERR(p_hwfn, "Failed to send driver state\n");
2449 enum _ecore_status_t
2450 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2451 struct ecore_fc_npiv_tbl *p_table)
2456 enum _ecore_status_t
2457 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2458 struct ecore_ptt *p_ptt, u16 mtu)
2463 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2464 struct ecore_ptt *p_ptt,
2465 enum ecore_led_mode mode)
2467 u32 resp = 0, param = 0, drv_mb_param;
2468 enum _ecore_status_t rc;
2471 case ECORE_LED_MODE_ON:
2472 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2474 case ECORE_LED_MODE_OFF:
2475 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2477 case ECORE_LED_MODE_RESTORE:
2478 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2481 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2485 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2486 drv_mb_param, &resp, ¶m);
2487 if (rc != ECORE_SUCCESS)
2488 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2493 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2494 struct ecore_ptt *p_ptt,
2497 u32 resp = 0, param = 0;
2498 enum _ecore_status_t rc;
2500 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2501 mask_parities, &resp, ¶m);
2503 if (rc != ECORE_SUCCESS) {
2505 "MCP response failure for mask parities, aborting\n");
2506 } else if (resp != FW_MSG_CODE_OK) {
2508 "MCP did not ack mask parity request. Old MFW?\n");
2515 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2518 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2519 u32 bytes_left, offset, bytes_to_copy, buf_size;
2520 u32 nvm_offset, resp, param;
2521 struct ecore_ptt *p_ptt;
2522 enum _ecore_status_t rc = ECORE_SUCCESS;
2524 p_ptt = ecore_ptt_acquire(p_hwfn);
2530 while (bytes_left > 0) {
2531 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2532 MCP_DRV_NVM_BUF_LEN);
2533 nvm_offset = (addr + offset) | (bytes_to_copy <<
2534 DRV_MB_PARAM_NVM_LEN_OFFSET);
2535 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2536 DRV_MSG_CODE_NVM_READ_NVRAM,
2537 nvm_offset, &resp, ¶m, &buf_size,
2538 (u32 *)(p_buf + offset));
2539 if (rc != ECORE_SUCCESS) {
2540 DP_NOTICE(p_dev, false,
2541 "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2543 resp = FW_MSG_CODE_ERROR;
2547 if (resp != FW_MSG_CODE_NVM_OK) {
2548 DP_NOTICE(p_dev, false,
2549 "nvm read failed, resp = 0x%08x\n", resp);
2550 rc = ECORE_UNKNOWN_ERROR;
2554 /* This can be a lengthy process, and it's possible scheduler
2555 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2557 if (bytes_left % 0x1000 <
2558 (bytes_left - buf_size) % 0x1000)
2562 bytes_left -= buf_size;
2565 p_dev->mcp_nvm_resp = resp;
2566 ecore_ptt_release(p_hwfn, p_ptt);
2571 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2572 u32 addr, u8 *p_buf, u32 len)
2574 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2575 struct ecore_ptt *p_ptt;
2577 enum _ecore_status_t rc;
2579 p_ptt = ecore_ptt_acquire(p_hwfn);
2583 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2584 (cmd == ECORE_PHY_CORE_READ) ?
2585 DRV_MSG_CODE_PHY_CORE_READ :
2586 DRV_MSG_CODE_PHY_RAW_READ,
2587 addr, &resp, ¶m, &len, (u32 *)p_buf);
2588 if (rc != ECORE_SUCCESS)
2589 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2591 p_dev->mcp_nvm_resp = resp;
2592 ecore_ptt_release(p_hwfn, p_ptt);
2597 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2599 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2600 struct ecore_ptt *p_ptt;
2602 p_ptt = ecore_ptt_acquire(p_hwfn);
2606 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2607 ecore_ptt_release(p_hwfn, p_ptt);
2609 return ECORE_SUCCESS;
2612 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2614 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2615 struct ecore_ptt *p_ptt;
2617 enum _ecore_status_t rc;
2619 p_ptt = ecore_ptt_acquire(p_hwfn);
2622 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2624 p_dev->mcp_nvm_resp = resp;
2625 ecore_ptt_release(p_hwfn, p_ptt);
2630 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2633 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2634 struct ecore_ptt *p_ptt;
2636 enum _ecore_status_t rc;
2638 p_ptt = ecore_ptt_acquire(p_hwfn);
2641 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2643 p_dev->mcp_nvm_resp = resp;
2644 ecore_ptt_release(p_hwfn, p_ptt);
2649 /* rc receives ECORE_INVAL as default parameter because
2650 * it might not enter the while loop if the len is 0
2652 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2653 u32 addr, u8 *p_buf, u32 len)
2655 u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2656 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2657 enum _ecore_status_t rc = ECORE_INVAL;
2658 struct ecore_ptt *p_ptt;
2660 p_ptt = ecore_ptt_acquire(p_hwfn);
2665 case ECORE_PUT_FILE_DATA:
2666 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2668 case ECORE_NVM_WRITE_NVRAM:
2669 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2671 case ECORE_EXT_PHY_FW_UPGRADE:
2672 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2675 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2682 while (buf_idx < len) {
2683 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2684 MCP_DRV_NVM_BUF_LEN);
2685 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2688 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2689 &resp, ¶m, buf_size,
2690 (u32 *)&p_buf[buf_idx]);
2691 if (rc != ECORE_SUCCESS) {
2692 DP_NOTICE(p_dev, false,
2693 "ecore_mcp_nvm_write() failed, rc = %d\n",
2695 resp = FW_MSG_CODE_ERROR;
2699 if (resp != FW_MSG_CODE_OK &&
2700 resp != FW_MSG_CODE_NVM_OK &&
2701 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2702 DP_NOTICE(p_dev, false,
2703 "nvm write failed, resp = 0x%08x\n", resp);
2704 rc = ECORE_UNKNOWN_ERROR;
2708 /* This can be a lengthy process, and it's possible scheduler
2709 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2711 if (buf_idx % 0x1000 >
2712 (buf_idx + buf_size) % 0x1000)
2715 buf_idx += buf_size;
2718 p_dev->mcp_nvm_resp = resp;
2720 ecore_ptt_release(p_hwfn, p_ptt);
2725 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2726 u32 addr, u8 *p_buf, u32 len)
2728 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2729 struct ecore_ptt *p_ptt;
2730 u32 resp, param, nvm_cmd;
2731 enum _ecore_status_t rc;
2733 p_ptt = ecore_ptt_acquire(p_hwfn);
2737 nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ? DRV_MSG_CODE_PHY_CORE_WRITE :
2738 DRV_MSG_CODE_PHY_RAW_WRITE;
2739 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2740 &resp, ¶m, len, (u32 *)p_buf);
2741 if (rc != ECORE_SUCCESS)
2742 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2743 p_dev->mcp_nvm_resp = resp;
2744 ecore_ptt_release(p_hwfn, p_ptt);
2749 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2752 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2753 struct ecore_ptt *p_ptt;
2755 enum _ecore_status_t rc;
2757 p_ptt = ecore_ptt_acquire(p_hwfn);
2761 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2763 p_dev->mcp_nvm_resp = resp;
2764 ecore_ptt_release(p_hwfn, p_ptt);
2769 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2770 struct ecore_ptt *p_ptt,
2771 u32 port, u32 addr, u32 offset,
2774 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2776 enum _ecore_status_t rc;
2778 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2779 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2783 while (bytes_left > 0) {
2784 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2785 MAX_I2C_TRANSACTION_SIZE);
2786 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2787 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2788 nvm_offset |= ((addr + offset) <<
2789 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2790 nvm_offset |= (bytes_to_copy <<
2791 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2792 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2793 DRV_MSG_CODE_TRANSCEIVER_READ,
2794 nvm_offset, &resp, ¶m, &buf_size,
2795 (u32 *)(p_buf + offset));
2796 if ((resp & FW_MSG_CODE_MASK) ==
2797 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2799 } else if ((resp & FW_MSG_CODE_MASK) !=
2800 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2801 return ECORE_UNKNOWN_ERROR;
2804 bytes_left -= buf_size;
2807 return ECORE_SUCCESS;
2810 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2811 struct ecore_ptt *p_ptt,
2812 u32 port, u32 addr, u32 offset,
2815 u32 buf_idx, buf_size, nvm_offset, resp, param;
2816 enum _ecore_status_t rc;
2818 nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2819 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2821 while (buf_idx < len) {
2822 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2823 MAX_I2C_TRANSACTION_SIZE);
2824 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2825 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2826 nvm_offset |= ((offset + buf_idx) <<
2827 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2828 nvm_offset |= (buf_size <<
2829 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2830 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2831 DRV_MSG_CODE_TRANSCEIVER_WRITE,
2832 nvm_offset, &resp, ¶m, buf_size,
2833 (u32 *)&p_buf[buf_idx]);
2834 if ((resp & FW_MSG_CODE_MASK) ==
2835 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2837 } else if ((resp & FW_MSG_CODE_MASK) !=
2838 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2839 return ECORE_UNKNOWN_ERROR;
2841 buf_idx += buf_size;
2844 return ECORE_SUCCESS;
2847 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2848 struct ecore_ptt *p_ptt,
2849 u16 gpio, u32 *gpio_val)
2851 enum _ecore_status_t rc = ECORE_SUCCESS;
2852 u32 drv_mb_param = 0, rsp;
2854 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2856 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2857 drv_mb_param, &rsp, gpio_val);
2859 if (rc != ECORE_SUCCESS)
2862 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2863 return ECORE_UNKNOWN_ERROR;
2865 return ECORE_SUCCESS;
2868 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2869 struct ecore_ptt *p_ptt,
2870 u16 gpio, u16 gpio_val)
2872 enum _ecore_status_t rc = ECORE_SUCCESS;
2873 u32 drv_mb_param = 0, param, rsp;
2875 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
2876 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
2878 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2879 drv_mb_param, &rsp, ¶m);
2881 if (rc != ECORE_SUCCESS)
2884 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2885 return ECORE_UNKNOWN_ERROR;
2887 return ECORE_SUCCESS;
2890 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2891 struct ecore_ptt *p_ptt,
2892 u16 gpio, u32 *gpio_direction,
2895 u32 drv_mb_param = 0, rsp, val = 0;
2896 enum _ecore_status_t rc = ECORE_SUCCESS;
2898 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
2900 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2901 drv_mb_param, &rsp, &val);
2902 if (rc != ECORE_SUCCESS)
2905 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2906 DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
2907 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2908 DRV_MB_PARAM_GPIO_CTRL_OFFSET;
2910 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2911 return ECORE_UNKNOWN_ERROR;
2913 return ECORE_SUCCESS;
2916 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2917 struct ecore_ptt *p_ptt)
2919 u32 drv_mb_param = 0, rsp, param;
2920 enum _ecore_status_t rc = ECORE_SUCCESS;
2922 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2923 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2925 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2926 drv_mb_param, &rsp, ¶m);
2928 if (rc != ECORE_SUCCESS)
2931 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2932 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2933 rc = ECORE_UNKNOWN_ERROR;
2938 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2939 struct ecore_ptt *p_ptt)
2941 u32 drv_mb_param, rsp, param;
2942 enum _ecore_status_t rc = ECORE_SUCCESS;
2944 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2945 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2947 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2948 drv_mb_param, &rsp, ¶m);
2950 if (rc != ECORE_SUCCESS)
2953 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2954 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2955 rc = ECORE_UNKNOWN_ERROR;
2960 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2961 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2963 u32 drv_mb_param = 0, rsp;
2964 enum _ecore_status_t rc = ECORE_SUCCESS;
2966 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2967 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2969 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2970 drv_mb_param, &rsp, num_images);
2972 if (rc != ECORE_SUCCESS)
2975 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2976 rc = ECORE_UNKNOWN_ERROR;
2981 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2982 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2983 struct bist_nvm_image_att *p_image_att, u32 image_index)
2985 u32 buf_size, nvm_offset, resp, param;
2986 enum _ecore_status_t rc;
2988 nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2989 DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2990 nvm_offset |= (image_index <<
2991 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
2992 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2993 nvm_offset, &resp, ¶m, &buf_size,
2994 (u32 *)p_image_att);
2995 if (rc != ECORE_SUCCESS)
2998 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2999 (p_image_att->return_code != 1))
3000 rc = ECORE_UNKNOWN_ERROR;
3005 enum _ecore_status_t
3006 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3007 struct ecore_ptt *p_ptt,
3008 struct ecore_temperature_info *p_temp_info)
3010 struct ecore_temperature_sensor *p_temp_sensor;
3011 struct temperature_status_stc mfw_temp_info;
3012 struct ecore_mcp_mb_params mb_params;
3014 enum _ecore_status_t rc;
3017 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3018 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3019 mb_params.p_data_dst = &mfw_temp_info;
3020 mb_params.data_dst_size = sizeof(mfw_temp_info);
3021 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3022 if (rc != ECORE_SUCCESS)
3025 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3026 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3027 ECORE_MAX_NUM_OF_SENSORS);
3028 for (i = 0; i < p_temp_info->num_sensors; i++) {
3029 val = mfw_temp_info.sensor[i];
3030 p_temp_sensor = &p_temp_info->sensors[i];
3031 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3032 SENSOR_LOCATION_OFFSET;
3033 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3034 THRESHOLD_HIGH_OFFSET;
3035 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3036 CRITICAL_TEMPERATURE_OFFSET;
3037 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3038 CURRENT_TEMP_OFFSET;
3041 return ECORE_SUCCESS;
3044 enum _ecore_status_t ecore_mcp_get_mba_versions(
3045 struct ecore_hwfn *p_hwfn,
3046 struct ecore_ptt *p_ptt,
3047 struct ecore_mba_vers *p_mba_vers)
3049 u32 buf_size, resp, param;
3050 enum _ecore_status_t rc;
3052 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3053 0, &resp, ¶m, &buf_size,
3054 &p_mba_vers->mba_vers[0]);
3056 if (rc != ECORE_SUCCESS)
3059 if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3060 rc = ECORE_UNKNOWN_ERROR;
3062 if (buf_size != MCP_DRV_NVM_BUF_LEN)
3063 rc = ECORE_UNKNOWN_ERROR;
3068 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3069 struct ecore_ptt *p_ptt,
3074 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3075 0, &rsp, (u32 *)num_events);
3078 static enum resource_id_enum
3079 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3081 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3085 mfw_res_id = RESOURCE_NUM_SB_E;
3087 case ECORE_L2_QUEUE:
3088 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3091 mfw_res_id = RESOURCE_NUM_VPORT_E;
3094 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3097 mfw_res_id = RESOURCE_NUM_PQ_E;
3100 mfw_res_id = RESOURCE_NUM_RL_E;
3104 /* Each VFC resource can accommodate both a MAC and a VLAN */
3105 mfw_res_id = RESOURCE_VFC_FILTER_E;
3108 mfw_res_id = RESOURCE_ILT_E;
3110 case ECORE_LL2_QUEUE:
3111 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3113 case ECORE_RDMA_CNQ_RAM:
3114 case ECORE_CMDQS_CQS:
3115 /* CNQ/CMDQS are the same resource */
3116 mfw_res_id = RESOURCE_CQS_E;
3118 case ECORE_RDMA_STATS_QUEUE:
3119 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3122 mfw_res_id = RESOURCE_BDQ_E;
3131 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
3132 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
3133 #define ECORE_RESC_ALLOC_VERSION \
3134 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
3135 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) | \
3136 (ECORE_RESC_ALLOC_VERSION_MINOR << \
3137 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3139 struct ecore_resc_alloc_in_params {
3141 enum ecore_resources res_id;
3145 struct ecore_resc_alloc_out_params {
3155 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
3157 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3159 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3160 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3161 enum _ecore_status_t rc;
3163 /* Allow ongoing PCIe transactions to complete */
3164 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3166 /* Clear the PF's internal FID_enable in the PXP */
3167 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3168 if (rc != ECORE_SUCCESS)
3169 DP_NOTICE(p_hwfn, false,
3170 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3176 static enum _ecore_status_t
3177 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3178 struct ecore_ptt *p_ptt,
3179 struct ecore_resc_alloc_in_params *p_in_params,
3180 struct ecore_resc_alloc_out_params *p_out_params)
3182 struct ecore_mcp_mb_params mb_params;
3183 struct resource_info mfw_resc_info;
3184 enum _ecore_status_t rc;
3186 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3188 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3189 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3191 "Failed to match resource %d [%s] with the MFW resources\n",
3192 p_in_params->res_id,
3193 ecore_hw_get_resc_name(p_in_params->res_id));
3197 switch (p_in_params->cmd) {
3198 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3199 mfw_resc_info.size = p_in_params->resc_max_val;
3201 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3204 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3209 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3210 mb_params.cmd = p_in_params->cmd;
3211 mb_params.param = ECORE_RESC_ALLOC_VERSION;
3212 mb_params.p_data_src = &mfw_resc_info;
3213 mb_params.data_src_size = sizeof(mfw_resc_info);
3214 mb_params.p_data_dst = mb_params.p_data_src;
3215 mb_params.data_dst_size = mb_params.data_src_size;
3217 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3218 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3219 p_in_params->cmd, p_in_params->res_id,
3220 ecore_hw_get_resc_name(p_in_params->res_id),
3221 GET_MFW_FIELD(mb_params.param,
3222 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3223 GET_MFW_FIELD(mb_params.param,
3224 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3225 p_in_params->resc_max_val);
3227 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3228 if (rc != ECORE_SUCCESS)
3231 p_out_params->mcp_resp = mb_params.mcp_resp;
3232 p_out_params->mcp_param = mb_params.mcp_param;
3233 p_out_params->resc_num = mfw_resc_info.size;
3234 p_out_params->resc_start = mfw_resc_info.offset;
3235 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3236 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3237 p_out_params->flags = mfw_resc_info.flags;
3239 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3240 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3241 GET_MFW_FIELD(p_out_params->mcp_param,
3242 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3243 GET_MFW_FIELD(p_out_params->mcp_param,
3244 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3245 p_out_params->resc_num, p_out_params->resc_start,
3246 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3247 p_out_params->flags);
3249 return ECORE_SUCCESS;
3252 enum _ecore_status_t
3253 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3254 enum ecore_resources res_id, u32 resc_max_val,
3257 struct ecore_resc_alloc_out_params out_params;
3258 struct ecore_resc_alloc_in_params in_params;
3259 enum _ecore_status_t rc;
3261 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3262 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3263 in_params.res_id = res_id;
3264 in_params.resc_max_val = resc_max_val;
3265 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3266 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3268 if (rc != ECORE_SUCCESS)
3271 *p_mcp_resp = out_params.mcp_resp;
3273 return ECORE_SUCCESS;
3276 enum _ecore_status_t
3277 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3278 enum ecore_resources res_id, u32 *p_mcp_resp,
3279 u32 *p_resc_num, u32 *p_resc_start)
3281 struct ecore_resc_alloc_out_params out_params;
3282 struct ecore_resc_alloc_in_params in_params;
3283 enum _ecore_status_t rc;
3285 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3286 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3287 in_params.res_id = res_id;
3288 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3289 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3291 if (rc != ECORE_SUCCESS)
3294 *p_mcp_resp = out_params.mcp_resp;
3296 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3297 *p_resc_num = out_params.resc_num;
3298 *p_resc_start = out_params.resc_start;
3301 return ECORE_SUCCESS;
3304 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3305 struct ecore_ptt *p_ptt)
3307 u32 mcp_resp, mcp_param;
3309 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3310 &mcp_resp, &mcp_param);
3313 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3314 struct ecore_ptt *p_ptt,
3315 u32 param, u32 *p_mcp_resp,
3318 enum _ecore_status_t rc;
3320 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3321 p_mcp_resp, p_mcp_param);
3322 if (rc != ECORE_SUCCESS)
3325 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3327 "The resource command is unsupported by the MFW\n");
3328 return ECORE_NOTIMPL;
3331 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3332 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3334 DP_NOTICE(p_hwfn, false,
3335 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3343 enum _ecore_status_t
3344 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3345 struct ecore_resc_lock_params *p_params)
3347 u32 param = 0, mcp_resp, mcp_param;
3349 enum _ecore_status_t rc;
3351 switch (p_params->timeout) {
3352 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3353 opcode = RESOURCE_OPCODE_REQ;
3354 p_params->timeout = 0;
3356 case ECORE_MCP_RESC_LOCK_TO_NONE:
3357 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3358 p_params->timeout = 0;
3361 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3365 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3366 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3367 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3369 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3370 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3371 param, p_params->timeout, opcode, p_params->resource);
3373 /* Attempt to acquire the resource */
3374 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3376 if (rc != ECORE_SUCCESS)
3379 /* Analyze the response */
3380 p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3381 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3383 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3384 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3385 mcp_param, opcode, p_params->owner);
3388 case RESOURCE_OPCODE_GNT:
3389 p_params->b_granted = true;
3391 case RESOURCE_OPCODE_BUSY:
3392 p_params->b_granted = false;
3395 DP_NOTICE(p_hwfn, false,
3396 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3401 return ECORE_SUCCESS;
3404 enum _ecore_status_t
3405 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3406 struct ecore_resc_lock_params *p_params)
3409 enum _ecore_status_t rc;
3412 /* No need for an interval before the first iteration */
3414 if (p_params->sleep_b4_retry) {
3415 u16 retry_interval_in_ms =
3416 DIV_ROUND_UP(p_params->retry_interval,
3419 OSAL_MSLEEP(retry_interval_in_ms);
3421 OSAL_UDELAY(p_params->retry_interval);
3425 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3426 if (rc != ECORE_SUCCESS)
3429 if (p_params->b_granted)
3431 } while (retry_cnt++ < p_params->retry_num);
3433 return ECORE_SUCCESS;
3437 ecore_mcp_resc_lock_default_init(struct ecore_hwfn *p_hwfn,
3438 struct ecore_resc_lock_params *p_lock,
3439 struct ecore_resc_unlock_params *p_unlock,
3440 enum ecore_resc_lock resource,
3441 bool b_is_permanent)
3443 if (p_lock != OSAL_NULL) {
3444 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3446 /* Permanent resources don't require aging, and there's no
3447 * point in trying to acquire them more than once since it's
3448 * unexpected another entity would release them.
3450 if (b_is_permanent) {
3451 p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3453 p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3454 p_lock->retry_interval =
3455 ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3456 p_lock->sleep_b4_retry = true;
3459 p_lock->resource = resource;
3462 if (p_unlock != OSAL_NULL) {
3463 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3464 p_unlock->resource = resource;
3468 enum _ecore_status_t
3469 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3470 struct ecore_resc_unlock_params *p_params)
3472 u32 param = 0, mcp_resp, mcp_param;
3474 enum _ecore_status_t rc;
3476 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3477 : RESOURCE_OPCODE_RELEASE;
3478 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3479 SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3481 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3482 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3483 param, opcode, p_params->resource);
3485 /* Attempt to release the resource */
3486 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3488 if (rc != ECORE_SUCCESS)
3491 /* Analyze the response */
3492 opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3494 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3495 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3499 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3501 "Resource unlock request for an already released resource [%d]\n",
3502 p_params->resource);
3504 case RESOURCE_OPCODE_RELEASED:
3505 p_params->b_released = true;
3507 case RESOURCE_OPCODE_WRONG_OWNER:
3508 p_params->b_released = false;
3511 DP_NOTICE(p_hwfn, false,
3512 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3517 return ECORE_SUCCESS;
3520 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3522 return !!(p_hwfn->mcp_info->capabilities &
3523 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3526 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3527 struct ecore_ptt *p_ptt)
3530 enum _ecore_status_t rc;
3532 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3533 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3534 if (rc == ECORE_SUCCESS)
3535 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3536 "MFW supported features: %08x\n",
3537 p_hwfn->mcp_info->capabilities);
3542 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3543 struct ecore_ptt *p_ptt)
3545 u32 mcp_resp, mcp_param, features;
3547 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3548 DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3550 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3551 features, &mcp_resp, &mcp_param);