drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 100 {
 101         if (p_hwfn->mcp_info) {
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 103                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 104                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 105         }
 106         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 107         p_hwfn->mcp_info = OSAL_NULL;
 108
 109         return ECORE_SUCCESS;
 110 }
 111
 112 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 113                                                    struct ecore_ptt *p_ptt)
 114 {
 115         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 116         u32 drv_mb_offsize, mfw_mb_offsize;
 117         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 118
 119 #ifndef ASIC_ONLY
 120         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 121                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 122                 p_info->public_base = 0;
 123                 return ECORE_INVAL;
 124         }
 125 #endif
 126
 127         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 128         if (!p_info->public_base)
 129                 return ECORE_INVAL;
 130
 131         p_info->public_base |= GRCBASE_MCP;
 132
 133         /* Calculate the driver and MFW mailbox address */
 134         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 135                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 136                                                        PUBLIC_DRV_MB));
 137         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 138         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 139                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 140                    " mcp_pf_id = 0x%x\n",
 141                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 142
 143         /* Set the MFW MB address */
 144         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 145                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 146                                                        PUBLIC_MFW_MB));
 147         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 148         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 149                                                p_info->mfw_mb_addr);
 150
 151         /* Get the current driver mailbox sequence before sending
 152          * the first command
 153          */
 154         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 155             DRV_MSG_SEQ_NUMBER_MASK;
 156
 157         /* Get current FW pulse sequence */
 158         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 159             DRV_PULSE_SEQ_MASK;
 160
 161         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 162                                           MISCS_REG_GENERIC_POR_0);
 163
 164         return ECORE_SUCCESS;
 165 }
 166
 167 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 168                                         struct ecore_ptt *p_ptt)
 169 {
 170         struct ecore_mcp_info *p_info;
 171         u32 size;
 172
 173         /* Allocate mcp_info structure */
 174         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 175                                        sizeof(*p_hwfn->mcp_info));
 176         if (!p_hwfn->mcp_info)
 177                 goto err;
 178         p_info = p_hwfn->mcp_info;
 179
 180         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 181                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 182                 /* Do not free mcp_info here, since public_base indicate that
 183                  * the MCP is not initialized
 184                  */
 185                 return ECORE_SUCCESS;
 186         }
 187
 188         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 189         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 191         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 192                 goto err;
 193
 194         /* Initialize the MFW spinlock */
 195         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 196         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 197
 198         return ECORE_SUCCESS;
 199
 200 err:
 201         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 202         ecore_mcp_free(p_hwfn);
 203         return ECORE_NOMEM;
 204 }
 205
 206 /* Locks the MFW mailbox of a PF to ensure a single access.
 207  * The lock is achieved in most cases by holding a spinlock, causing other
 208  * threads to wait till a previous access is done.
 209  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 210  * access is achieved by setting a blocking flag, which will fail other
 211  * competing contexts to send their mailboxes.
 212  */
 213 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 214                                               u32 cmd)
 215 {
 216         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 217
 218         /* The spinlock shouldn't be acquired when the mailbox command is
 219          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 220          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 221          * (i.e. interrupts are disabled) - can lead to a deadlock.
 222          * It is assumed that for a single PF, no other mailbox commands can be
 223          * sent from another context while sending LOAD_REQ, and that any
 224          * parallel commands to UNLOAD_REQ can be cancelled.
 225          */
 226         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 227                 p_hwfn->mcp_info->block_mb_sending = false;
 228
 229         if (p_hwfn->mcp_info->block_mb_sending) {
 230                 DP_NOTICE(p_hwfn, false,
 231                           "Trying to send a MFW mailbox command [0x%x]"
 232                           " in parallel to [UN]LOAD_REQ. Aborting.\n",
 233                           cmd);
 234                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 235                 return ECORE_BUSY;
 236         }
 237
 238         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 239                 p_hwfn->mcp_info->block_mb_sending = true;
 240                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 241         }
 242
 243         return ECORE_SUCCESS;
 244 }
 245
 246 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 247 {
 248         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 249                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 250 }
 251
 252 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 253                                      struct ecore_ptt *p_ptt)
 254 {
 255         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 256         u32 delay = CHIP_MCP_RESP_ITER_US;
 257         u32 org_mcp_reset_seq, cnt = 0;
 258         enum _ecore_status_t rc = ECORE_SUCCESS;
 259
 260 #ifndef ASIC_ONLY
 261         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 262                 delay = EMUL_MCP_RESP_ITER_US;
 263 #endif
 264
 265         /* Ensure that only a single thread is accessing the mailbox at a
 266          * certain time.
 267          */
 268         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 269         if (rc != ECORE_SUCCESS)
 270                 return rc;
 271
 272         /* Set drv command along with the updated sequence */
 273         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 274         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 275
 276         do {
 277                 /* Wait for MFW response */
 278                 OSAL_UDELAY(delay);
 279                 /* Give the FW up to 500 second (50*1000*10usec) */
 280         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 281                                                 MISCS_REG_GENERIC_POR_0)) &&
 282                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 283
 284         if (org_mcp_reset_seq !=
 285             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 286                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 287                            "MCP was reset after %d usec\n", cnt * delay);
 288         } else {
 289                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 290                 rc = ECORE_AGAIN;
 291         }
 292
 293         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 294
 295         return rc;
 296 }
 297
 298 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 299                                              struct ecore_ptt *p_ptt,
 300                                              u32 cmd, u32 param,
 301                                              u32 *o_mcp_resp,
 302                                              u32 *o_mcp_param)
 303 {
 304         u32 delay = CHIP_MCP_RESP_ITER_US;
 305         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 306         u32 seq, cnt = 1, actual_mb_seq;
 307         enum _ecore_status_t rc = ECORE_SUCCESS;
 308
 309 #ifndef ASIC_ONLY
 310         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 311                 delay = EMUL_MCP_RESP_ITER_US;
 312         /* There is a built-in delay of 100usec in each MFW response read */
 313         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 314                 max_retries /= 10;
 315 #endif
 316
 317         /* Get actual driver mailbox sequence */
 318         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 319             DRV_MSG_SEQ_NUMBER_MASK;
 320
 321         /* Use MCP history register to check if MCP reset occurred between
 322          * init time and now.
 323          */
 324         if (p_hwfn->mcp_info->mcp_hist !=
 325             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 326                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 327                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 328                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 329         }
 330         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 331
 332         /* Set drv param */
 333         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 334
 335         /* Set drv command along with the updated sequence */
 336         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 337
 338         do {
 339                 /* Wait for MFW response */
 340                 OSAL_UDELAY(delay);
 341                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 342
 343                 /* Give the FW up to 5 second (500*10ms) */
 344         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 345                  (cnt++ < max_retries));
 346
 347         /* Is this a reply to our command? */
 348         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 349                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 350                 /* Get the MCP param */
 351                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 352         } else {
 353                 /* FW BUG! */
 354                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 355                        cmd, param);
 356                 *o_mcp_resp = 0;
 357                 rc = ECORE_AGAIN;
 358                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 359         }
 360         return rc;
 361 }
 362
 363 static enum _ecore_status_t
 364 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 365                         struct ecore_ptt *p_ptt,
 366                         struct ecore_mcp_mb_params *p_mb_params)
 367 {
 368         u32 union_data_addr;
 369         enum _ecore_status_t rc;
 370
 371         /* MCP not initialized */
 372         if (!ecore_mcp_is_init(p_hwfn)) {
 373                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 374                 return ECORE_BUSY;
 375         }
 376
 377         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 378                           OFFSETOF(struct public_drv_mb, union_data);
 379
 380         /* Ensure that only a single thread is accessing the mailbox at a
 381          * certain time.
 382          */
 383         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 384         if (rc != ECORE_SUCCESS)
 385                 return rc;
 386
 387         if (p_mb_params->p_data_src != OSAL_NULL)
 388                 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 389                                 p_mb_params->p_data_src,
 390                                 sizeof(*p_mb_params->p_data_src));
 391
 392         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 393                               p_mb_params->param, &p_mb_params->mcp_resp,
 394                               &p_mb_params->mcp_param);
 395
 396         if (p_mb_params->p_data_dst != OSAL_NULL)
 397                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 398                                   union_data_addr,
 399                                   sizeof(*p_mb_params->p_data_dst));
 400
 401         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 402
 403         return rc;
 404 }
 405
 406 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 407                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 408                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 409 {
 410         struct ecore_mcp_mb_params mb_params;
 411         enum _ecore_status_t rc;
 412
 413 #ifndef ASIC_ONLY
 414         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 415                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 416                         loaded--;
 417                         loaded_port[p_hwfn->port_id]--;
 418                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 419                                    loaded);
 420                 }
 421                 return ECORE_SUCCESS;
 422         }
 423 #endif
 424
 425         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 426         mb_params.cmd = cmd;
 427         mb_params.param = param;
 428         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 429         if (rc != ECORE_SUCCESS)
 430                 return rc;
 431
 432         *o_mcp_resp = mb_params.mcp_resp;
 433         *o_mcp_param = mb_params.mcp_param;
 434
 435         return ECORE_SUCCESS;
 436 }
 437
 438 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 439                                           struct ecore_ptt *p_ptt,
 440                                           u32 cmd,
 441                                           u32 param,
 442                                           u32 *o_mcp_resp,
 443                                           u32 *o_mcp_param,
 444                                           u32 i_txn_size, u32 *i_buf)
 445 {
 446         struct ecore_mcp_mb_params mb_params;
 447         union drv_union_data union_data;
 448         enum _ecore_status_t rc;
 449
 450         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 451         mb_params.cmd = cmd;
 452         mb_params.param = param;
 453         OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
 454         mb_params.p_data_src = &union_data;
 455         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 456         if (rc != ECORE_SUCCESS)
 457                 return rc;
 458
 459         *o_mcp_resp = mb_params.mcp_resp;
 460         *o_mcp_param = mb_params.mcp_param;
 461
 462         return ECORE_SUCCESS;
 463 }
 464
 465 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 466                                           struct ecore_ptt *p_ptt,
 467                                           u32 cmd,
 468                                           u32 param,
 469                                           u32 *o_mcp_resp,
 470                                           u32 *o_mcp_param,
 471                                           u32 *o_txn_size, u32 *o_buf)
 472 {
 473         struct ecore_mcp_mb_params mb_params;
 474         union drv_union_data union_data;
 475         enum _ecore_status_t rc;
 476
 477         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 478         mb_params.cmd = cmd;
 479         mb_params.param = param;
 480         mb_params.p_data_dst = &union_data;
 481         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 482         if (rc != ECORE_SUCCESS)
 483                 return rc;
 484
 485         *o_mcp_resp = mb_params.mcp_resp;
 486         *o_mcp_param = mb_params.mcp_param;
 487
 488         *o_txn_size = *o_mcp_param;
 489         OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
 490
 491         return ECORE_SUCCESS;
 492 }
 493
 494 #ifndef ASIC_ONLY
 495 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 496                                     u32 *p_load_code)
 497 {
 498         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 499
 500         if (!loaded)
 501                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 502         else if (!loaded_port[p_hwfn->port_id])
 503                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 504         else
 505                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 506
 507         /* On CMT, always tell that it's engine */
 508         if (p_hwfn->p_dev->num_hwfns > 1)
 509                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 510
 511         *p_load_code = load_phase;
 512         loaded++;
 513         loaded_port[p_hwfn->port_id]++;
 514
 515         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 516                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 517                    *p_load_code, loaded, p_hwfn->port_id,
 518                    loaded_port[p_hwfn->port_id]);
 519 }
 520 #endif
 521
 522 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 523                                         struct ecore_ptt *p_ptt,
 524                                         u32 *p_load_code)
 525 {
 526         struct ecore_dev *p_dev = p_hwfn->p_dev;
 527         struct ecore_mcp_mb_params mb_params;
 528         union drv_union_data union_data;
 529         enum _ecore_status_t rc;
 530
 531 #ifndef ASIC_ONLY
 532         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 533                 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
 534                 return ECORE_SUCCESS;
 535         }
 536 #endif
 537
 538         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 539         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 540         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 541                           p_dev->drv_type;
 542         OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
 543         mb_params.p_data_src = &union_data;
 544         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 545
 546         /* if mcp fails to respond we must abort */
 547         if (rc != ECORE_SUCCESS) {
 548                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 549                 return rc;
 550         }
 551
 552         *p_load_code = mb_params.mcp_resp;
 553
 554         /* If MFW refused (e.g. other port is in diagnostic mode) we
 555          * must abort. This can happen in the following cases:
 556          * - Other port is in diagnostic mode
 557          * - Previously loaded function on the engine is not compliant with
 558          *   the requester.
 559          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 560          *      -
 561          */
 562         if (!(*p_load_code) ||
 563             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 564             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 565             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 566                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 567                 return ECORE_BUSY;
 568         }
 569
 570         return ECORE_SUCCESS;
 571 }
 572
 573 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 574                                     struct ecore_ptt *p_ptt)
 575 {
 576         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 577                                         PUBLIC_PATH);
 578         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 579         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 580                                      ECORE_PATH_ID(p_hwfn));
 581         u32 disabled_vfs[VF_MAX_STATIC / 32];
 582         int i;
 583
 584         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 585                    "Reading Disabled VF information from [offset %08x],"
 586                    " path_addr %08x\n",
 587                    mfw_path_offsize, path_addr);
 588
 589         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 590                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 591                                            path_addr +
 592                                            OFFSETOF(struct public_path,
 593                                                     mcp_vf_disabled) +
 594                                            sizeof(u32) * i);
 595                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 596                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 597                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 598         }
 599
 600         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 601                 OSAL_VF_FLR_UPDATE(p_hwfn);
 602 }
 603
 604 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 605                                           struct ecore_ptt *p_ptt,
 606                                           u32 *vfs_to_ack)
 607 {
 608         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 609                                         PUBLIC_FUNC);
 610         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 611         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 612                                      MCP_PF_ID(p_hwfn));
 613         struct ecore_mcp_mb_params mb_params;
 614         union drv_union_data union_data;
 615         enum _ecore_status_t rc;
 616         int i;
 617
 618         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 619                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 620                            "Acking VFs [%08x,...,%08x] - %08x\n",
 621                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 622
 623         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 624         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 625         OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 626         mb_params.p_data_src = &union_data;
 627         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
 628                                      &mb_params);
 629         if (rc != ECORE_SUCCESS) {
 630                 DP_NOTICE(p_hwfn, false,
 631                           "Failed to pass ACK for VF flr to MFW\n");
 632                 return ECORE_TIMEOUT;
 633         }
 634
 635         /* TMP - clear the ACK bits; should be done by MFW */
 636         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 637                 ecore_wr(p_hwfn, p_ptt,
 638                          func_addr +
 639                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
 640                          i * sizeof(u32), 0);
 641
 642         return rc;
 643 }
 644
 645 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
 646                                                 struct ecore_ptt *p_ptt)
 647 {
 648         u32 transceiver_state;
 649
 650         transceiver_state = ecore_rd(p_hwfn, p_ptt,
 651                                      p_hwfn->mcp_info->port_addr +
 652                                      OFFSETOF(struct public_port,
 653                                               transceiver_data));
 654
 655         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
 656                    "Received transceiver state update [0x%08x] from mfw"
 657                    " [Addr 0x%x]\n",
 658                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
 659                                             OFFSETOF(struct public_port,
 660                                                      transceiver_data)));
 661
 662         transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
 663
 664         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
 665                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
 666         else
 667                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
 668 }
 669
 670 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
 671                                          struct ecore_ptt *p_ptt,
 672                                          bool b_reset)
 673 {
 674         struct ecore_mcp_link_state *p_link;
 675         u8 max_bw, min_bw;
 676         u32 status = 0;
 677
 678         p_link = &p_hwfn->mcp_info->link_output;
 679         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
 680         if (!b_reset) {
 681                 status = ecore_rd(p_hwfn, p_ptt,
 682                                   p_hwfn->mcp_info->port_addr +
 683                                   OFFSETOF(struct public_port, link_status));
 684                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
 685                            "Received link update [0x%08x] from mfw"
 686                            " [Addr 0x%x]\n",
 687                            status, (u32)(p_hwfn->mcp_info->port_addr +
 688                                           OFFSETOF(struct public_port,
 689                                                    link_status)));
 690         } else {
 691                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 692                            "Resetting link indications\n");
 693                 return;
 694         }
 695
 696         if (p_hwfn->b_drv_link_init)
 697                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 698         else
 699                 p_link->link_up = false;
 700
 701         p_link->full_duplex = true;
 702         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 703         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 704                 p_link->speed = 100000;
 705                 break;
 706         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 707                 p_link->speed = 50000;
 708                 break;
 709         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 710                 p_link->speed = 40000;
 711                 break;
 712         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 713                 p_link->speed = 25000;
 714                 break;
 715         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 716                 p_link->speed = 20000;
 717                 break;
 718         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 719                 p_link->speed = 10000;
 720                 break;
 721         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 722                 p_link->full_duplex = false;
 723                 /* Fall-through */
 724         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 725                 p_link->speed = 1000;
 726                 break;
 727         default:
 728                 p_link->speed = 0;
 729         }
 730
 731         /* We never store total line speed as p_link->speed is
 732          * again changes according to bandwidth allocation.
 733          */
 734         if (p_link->link_up && p_link->speed)
 735                 p_link->line_speed = p_link->speed;
 736         else
 737                 p_link->line_speed = 0;
 738
 739         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 740         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 741
 742         /* Max bandwidth configuration */
 743         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
 744                                            p_link, max_bw);
 745
 746         /* Mintz bandwidth configuration */
 747         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
 748                                            p_link, min_bw);
 749         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
 750                                               p_link->min_pf_rate);
 751
 752         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 753         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 754         p_link->parallel_detection = !!(status &
 755                                          LINK_STATUS_PARALLEL_DETECTION_USED);
 756         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 757
 758         p_link->partner_adv_speed |=
 759             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 760             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
 761         p_link->partner_adv_speed |=
 762             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 763             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
 764         p_link->partner_adv_speed |=
 765             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 766             ECORE_LINK_PARTNER_SPEED_10G : 0;
 767         p_link->partner_adv_speed |=
 768             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 769             ECORE_LINK_PARTNER_SPEED_20G : 0;
 770         p_link->partner_adv_speed |=
 771             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 772             ECORE_LINK_PARTNER_SPEED_25G : 0;
 773         p_link->partner_adv_speed |=
 774             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 775             ECORE_LINK_PARTNER_SPEED_40G : 0;
 776         p_link->partner_adv_speed |=
 777             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 778             ECORE_LINK_PARTNER_SPEED_50G : 0;
 779         p_link->partner_adv_speed |=
 780             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 781             ECORE_LINK_PARTNER_SPEED_100G : 0;
 782
 783         p_link->partner_tx_flow_ctrl_en =
 784             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 785         p_link->partner_rx_flow_ctrl_en =
 786             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 787
 788         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 789         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 790                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
 791                 break;
 792         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 793                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
 794                 break;
 795         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 796                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
 797                 break;
 798         default:
 799                 p_link->partner_adv_pause = 0;
 800         }
 801
 802         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 803
 804         if (p_link->link_up)
 805                 ecore_dcbx_eagle_workaround(p_hwfn, p_ptt, p_link->pfc_enabled);
 806
 807         OSAL_LINK_UPDATE(p_hwfn);
 808 }
 809
 810 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 811                                         struct ecore_ptt *p_ptt, bool b_up)
 812 {
 813         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 814         struct ecore_mcp_mb_params mb_params;
 815         union drv_union_data union_data;
 816         struct eth_phy_cfg *p_phy_cfg;
 817         enum _ecore_status_t rc = ECORE_SUCCESS;
 818         u32 cmd;
 819
 820 #ifndef ASIC_ONLY
 821         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 822                 return ECORE_SUCCESS;
 823 #endif
 824
 825         /* Set the shmem configuration according to params */
 826         p_phy_cfg = &union_data.drv_phy_cfg;
 827         OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
 828         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 829         if (!params->speed.autoneg)
 830                 p_phy_cfg->speed = params->speed.forced_speed;
 831         p_phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
 832         p_phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
 833         p_phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
 834         p_phy_cfg->adv_speed = params->speed.advertised_speeds;
 835         p_phy_cfg->loopback_mode = params->loopback_mode;
 836         p_hwfn->b_drv_link_init = b_up;
 837
 838         if (b_up)
 839                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 840                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
 841                            " adv_speed 0x%08x, loopback 0x%08x,"
 842                            " features 0x%08x\n",
 843                            p_phy_cfg->speed, p_phy_cfg->pause,
 844                            p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode,
 845                            p_phy_cfg->feature_config_flags);
 846         else
 847                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
 848
 849         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 850         mb_params.cmd = cmd;
 851         mb_params.p_data_src = &union_data;
 852         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 853
 854         /* if mcp fails to respond we must abort */
 855         if (rc != ECORE_SUCCESS) {
 856                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 857                 return rc;
 858         }
 859
 860         /* Reset the link status if needed */
 861         if (!b_up)
 862                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
 863
 864         return rc;
 865 }
 866
 867 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
 868                                    struct ecore_ptt *p_ptt)
 869 {
 870         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
 871
 872         /* TODO - Add support for VFs */
 873         if (IS_VF(p_hwfn->p_dev))
 874                 return ECORE_INVAL;
 875
 876         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 877                                                  PUBLIC_PATH);
 878         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
 879         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
 880
 881         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
 882                                  path_addr +
 883                                  OFFSETOF(struct public_path, process_kill)) &
 884             PROCESS_KILL_COUNTER_MASK;
 885
 886         return proc_kill_cnt;
 887 }
 888
 889 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
 890                                           struct ecore_ptt *p_ptt)
 891 {
 892         struct ecore_dev *p_dev = p_hwfn->p_dev;
 893         u32 proc_kill_cnt;
 894
 895         /* Prevent possible attentions/interrupts during the recovery handling
 896          * and till its load phase, during which they will be re-enabled.
 897          */
 898         ecore_int_igu_disable_int(p_hwfn, p_ptt);
 899
 900         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
 901
 902         /* The following operations should be done once, and thus in CMT mode
 903          * are carried out by only the first HW function.
 904          */
 905         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
 906                 return;
 907
 908         if (p_dev->recov_in_prog) {
 909                 DP_NOTICE(p_hwfn, false,
 910                           "Ignoring the indication since a recovery"
 911                           " process is already in progress\n");
 912                 return;
 913         }
 914
 915         p_dev->recov_in_prog = true;
 916
 917         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
 918         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
 919
 920         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
 921 }
 922
 923 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
 924                                           struct ecore_ptt *p_ptt,
 925                                           enum MFW_DRV_MSG_TYPE type)
 926 {
 927         enum ecore_mcp_protocol_type stats_type;
 928         union ecore_mcp_protocol_stats stats;
 929         struct ecore_mcp_mb_params mb_params;
 930         union drv_union_data union_data;
 931         u32 hsi_param;
 932
 933         switch (type) {
 934         case MFW_DRV_MSG_GET_LAN_STATS:
 935                 stats_type = ECORE_MCP_LAN_STATS;
 936                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 937                 break;
 938         default:
 939                 DP_NOTICE(p_hwfn, false, "Invalid protocol type %d\n", type);
 940                 return;
 941         }
 942
 943         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
 944
 945         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 946         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 947         mb_params.param = hsi_param;
 948         OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
 949         mb_params.p_data_src = &union_data;
 950         ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 951 }
 952
 953 static void
 954 ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 955                         struct public_func *p_shmem_info)
 956 {
 957         struct ecore_mcp_function_info *p_info;
 958
 959         p_info = &p_hwfn->mcp_info->func_info;
 960
 961         /* TODO - bandwidth min/max should have valid values of 1-100,
 962          * as well as some indication that the feature is disabled.
 963          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
 964          * limit and correct value to min `1' and max `100' if limit isn't in
 965          * range.
 966          */
 967         p_info->bandwidth_min = (p_shmem_info->config &
 968                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 969             FUNC_MF_CFG_MIN_BW_SHIFT;
 970         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 971                 DP_INFO(p_hwfn,
 972                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 973                         p_info->bandwidth_min);
 974                 p_info->bandwidth_min = 1;
 975         }
 976
 977         p_info->bandwidth_max = (p_shmem_info->config &
 978                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 979             FUNC_MF_CFG_MAX_BW_SHIFT;
 980         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 981                 DP_INFO(p_hwfn,
 982                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 983                         p_info->bandwidth_max);
 984                 p_info->bandwidth_max = 100;
 985         }
 986 }
 987
 988 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
 989                                     struct ecore_ptt *p_ptt,
 990                                     struct public_func *p_data,
 991                                     int pfid)
 992 {
 993         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 994                                         PUBLIC_FUNC);
 995         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 996         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 997         u32 i, size;
 998
 999         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1000
1001         size = OSAL_MIN_T(u32, sizeof(*p_data),
1002                           SECTION_SIZE(mfw_path_offsize));
1003         for (i = 0; i < size / sizeof(u32); i++)
1004                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1005                                               func_addr + (i << 2));
1006
1007         return size;
1008 }
1009
1010 static void
1011 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1012 {
1013         struct ecore_mcp_function_info *p_info;
1014         struct public_func shmem_info;
1015         u32 resp = 0, param = 0;
1016
1017         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1018
1019         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1020
1021         p_info = &p_hwfn->mcp_info->func_info;
1022
1023         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1024
1025         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1026
1027         /* Acknowledge the MFW */
1028         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1029                       &param);
1030 }
1031
1032 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1033                                          struct ecore_ptt *p_ptt)
1034 {
1035         /* A single notification should be sent to upper driver in CMT mode */
1036         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1037                 return;
1038
1039         DP_NOTICE(p_hwfn, false,
1040                   "Fan failure was detected on the network interface card"
1041                   " and it's going to be shut down.\n");
1042
1043         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1044 }
1045
1046 static enum _ecore_status_t
1047 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1048                     u32 mdump_cmd, union drv_union_data *p_data_src,
1049                     union drv_union_data *p_data_dst, u32 *p_mcp_resp)
1050 {
1051         struct ecore_mcp_mb_params mb_params;
1052         enum _ecore_status_t rc;
1053
1054         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1055         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1056         mb_params.param = mdump_cmd;
1057         mb_params.p_data_src = p_data_src;
1058         mb_params.p_data_dst = p_data_dst;
1059         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1060         if (rc != ECORE_SUCCESS)
1061                 return rc;
1062
1063         *p_mcp_resp = mb_params.mcp_resp;
1064         if (*p_mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1065                 DP_NOTICE(p_hwfn, false,
1066                           "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1067                           mdump_cmd);
1068                 rc = ECORE_INVAL;
1069         }
1070
1071         return rc;
1072 }
1073
1074 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1075                                                 struct ecore_ptt *p_ptt)
1076 {
1077         u32 mcp_resp;
1078
1079         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_ACK,
1080                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1081 }
1082
1083 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1084                                                 struct ecore_ptt *p_ptt,
1085                                                 u32 epoch)
1086 {
1087         union drv_union_data union_data;
1088         u32 mcp_resp;
1089
1090         OSAL_MEMCPY(&union_data.raw_data, &epoch, sizeof(epoch));
1091
1092         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_SET_VALUES,
1093                                    &union_data, OSAL_NULL, &mcp_resp);
1094 }
1095
1096 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1097                                              struct ecore_ptt *p_ptt)
1098 {
1099         u32 mcp_resp;
1100
1101         p_hwfn->p_dev->mdump_en = true;
1102
1103         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_TRIGGER,
1104                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1105 }
1106
1107 static enum _ecore_status_t
1108 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1109                            struct mdump_config_stc *p_mdump_config)
1110 {
1111         union drv_union_data union_data;
1112         u32 mcp_resp;
1113         enum _ecore_status_t rc;
1114
1115         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_GET_CONFIG,
1116                                  OSAL_NULL, &union_data, &mcp_resp);
1117         if (rc != ECORE_SUCCESS)
1118                 return rc;
1119
1120         /* A zero response implies that the mdump command is not supported */
1121         if (!mcp_resp)
1122                 return ECORE_NOTIMPL;
1123
1124         if (mcp_resp != FW_MSG_CODE_OK) {
1125                 DP_NOTICE(p_hwfn, false,
1126                           "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1127                           mcp_resp);
1128                 rc = ECORE_UNKNOWN_ERROR;
1129         }
1130
1131         OSAL_MEMCPY(p_mdump_config, &union_data.mdump_config,
1132                     sizeof(*p_mdump_config));
1133
1134         return rc;
1135 }
1136
1137 enum _ecore_status_t
1138 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1139                          struct ecore_mdump_info *p_mdump_info)
1140 {
1141         u32 addr, global_offsize, global_addr;
1142         struct mdump_config_stc mdump_config;
1143         enum _ecore_status_t rc;
1144
1145         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1146
1147         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1148                                     PUBLIC_GLOBAL);
1149         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1150         global_addr = SECTION_ADDR(global_offsize, 0);
1151         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1152                                         global_addr +
1153                                         OFFSETOF(struct public_global,
1154                                                  mdump_reason));
1155
1156         if (p_mdump_info->reason) {
1157                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1158                 if (rc != ECORE_SUCCESS)
1159                         return rc;
1160
1161                 p_mdump_info->version = mdump_config.version;
1162                 p_mdump_info->config = mdump_config.config;
1163                 p_mdump_info->epoch = mdump_config.epoc;
1164                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1165                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1166
1167                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1168                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1169                            p_mdump_info->reason, p_mdump_info->version,
1170                            p_mdump_info->config, p_mdump_info->epoch,
1171                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1172         } else {
1173                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1174                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1175         }
1176
1177         return ECORE_SUCCESS;
1178 }
1179
1180 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1181                                                 struct ecore_ptt *p_ptt)
1182 {
1183         u32 mcp_resp;
1184
1185         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_CLEAR_LOGS,
1186                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1187 }
1188
1189 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1190                                             struct ecore_ptt *p_ptt)
1191 {
1192         /* In CMT mode - no need for more than a single acknowledgment to the
1193          * MFW, and no more than a single notification to the upper driver.
1194          */
1195         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1196                 return;
1197
1198         DP_NOTICE(p_hwfn, false,
1199                   "Received a critical error notification from the MFW!\n");
1200
1201         if (p_hwfn->p_dev->mdump_en) {
1202                 DP_NOTICE(p_hwfn, false,
1203                           "Not acknowledging the notification to allow the MFW crash dump\n");
1204                 p_hwfn->p_dev->mdump_en = false;
1205                 return;
1206         }
1207
1208         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1209         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1210 }
1211
1212 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1213                                              struct ecore_ptt *p_ptt)
1214 {
1215         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1216         enum _ecore_status_t rc = ECORE_SUCCESS;
1217         bool found = false;
1218         u16 i;
1219
1220         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1221
1222         /* Read Messages from MFW */
1223         ecore_mcp_read_mb(p_hwfn, p_ptt);
1224
1225         /* Compare current messages to old ones */
1226         for (i = 0; i < info->mfw_mb_length; i++) {
1227                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1228                         continue;
1229
1230                 found = true;
1231
1232                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1233                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1234                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1235
1236                 switch (i) {
1237                 case MFW_DRV_MSG_LINK_CHANGE:
1238                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1239                         break;
1240                 case MFW_DRV_MSG_VF_DISABLED:
1241                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1242                         break;
1243                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1244                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1245                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1246                         break;
1247                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1248                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1249                                                     ECORE_DCBX_REMOTE_MIB);
1250                         break;
1251                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1252                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1253                                                     ECORE_DCBX_OPERATIONAL_MIB);
1254                         break;
1255                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1256                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1257                         break;
1258                 case MFW_DRV_MSG_ERROR_RECOVERY:
1259                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1260                         break;
1261                 case MFW_DRV_MSG_GET_LAN_STATS:
1262                 case MFW_DRV_MSG_GET_FCOE_STATS:
1263                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1264                 case MFW_DRV_MSG_GET_RDMA_STATS:
1265                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1266                         break;
1267                 case MFW_DRV_MSG_BW_UPDATE:
1268                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1269                         break;
1270                 case MFW_DRV_MSG_FAILURE_DETECTED:
1271                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1272                         break;
1273                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1274                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1275                         break;
1276                 default:
1277                         /* @DPDK */
1278                         DP_NOTICE(p_hwfn, false,
1279                                   "Unimplemented MFW message %d\n", i);
1280                         rc = ECORE_INVAL;
1281                 }
1282         }
1283
1284         /* ACK everything */
1285         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1286                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1287
1288                 /* MFW expect answer in BE, so we force write in that format */
1289                 ecore_wr(p_hwfn, p_ptt,
1290                          info->mfw_mb_addr + sizeof(u32) +
1291                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1292                          sizeof(u32) + i * sizeof(u32), val);
1293         }
1294
1295         if (!found) {
1296                 DP_NOTICE(p_hwfn, false,
1297                           "Received an MFW message indication but no"
1298                           " new message!\n");
1299                 rc = ECORE_INVAL;
1300         }
1301
1302         /* Copy the new mfw messages into the shadow */
1303         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1304
1305         return rc;
1306 }
1307
1308 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1309                                            struct ecore_ptt *p_ptt,
1310                                            u32 *p_mfw_ver,
1311                                            u32 *p_running_bundle_id)
1312 {
1313         u32 global_offsize;
1314
1315 #ifndef ASIC_ONLY
1316         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1317                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1318                 return ECORE_SUCCESS;
1319         }
1320 #endif
1321
1322         if (IS_VF(p_hwfn->p_dev)) {
1323                 if (p_hwfn->vf_iov_info) {
1324                         struct pfvf_acquire_resp_tlv *p_resp;
1325
1326                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1327                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1328                         return ECORE_SUCCESS;
1329                 } else {
1330                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1331                                    "VF requested MFW version prior to ACQUIRE\n");
1332                         return ECORE_INVAL;
1333                 }
1334         }
1335
1336         global_offsize = ecore_rd(p_hwfn, p_ptt,
1337                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1338                                                        public_base,
1339                                                        PUBLIC_GLOBAL));
1340         *p_mfw_ver =
1341             ecore_rd(p_hwfn, p_ptt,
1342                      SECTION_ADDR(global_offsize,
1343                                   0) + OFFSETOF(struct public_global, mfw_ver));
1344
1345         if (p_running_bundle_id != OSAL_NULL) {
1346                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1347                                                 SECTION_ADDR(global_offsize,
1348                                                              0) +
1349                                                 OFFSETOF(struct public_global,
1350                                                          running_bundle_id));
1351         }
1352
1353         return ECORE_SUCCESS;
1354 }
1355
1356 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1357                                               u32 *p_media_type)
1358 {
1359         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1360         struct ecore_ptt *p_ptt;
1361
1362         /* TODO - Add support for VFs */
1363         if (IS_VF(p_dev))
1364                 return ECORE_INVAL;
1365
1366         if (!ecore_mcp_is_init(p_hwfn)) {
1367                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1368                 return ECORE_BUSY;
1369         }
1370
1371         *p_media_type = MEDIA_UNSPECIFIED;
1372
1373         p_ptt = ecore_ptt_acquire(p_hwfn);
1374         if (!p_ptt)
1375                 return ECORE_BUSY;
1376
1377         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1378                                  OFFSETOF(struct public_port, media_type));
1379
1380         ecore_ptt_release(p_hwfn, p_ptt);
1381
1382         return ECORE_SUCCESS;
1383 }
1384
1385 static enum _ecore_status_t
1386 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1387                           struct public_func *p_info,
1388                           enum ecore_pci_personality *p_proto)
1389 {
1390         enum _ecore_status_t rc = ECORE_SUCCESS;
1391
1392         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1393         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1394                 *p_proto = ECORE_PCI_ETH;
1395                 break;
1396         default:
1397                 rc = ECORE_INVAL;
1398         }
1399
1400         return rc;
1401 }
1402
1403 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1404                                                     struct ecore_ptt *p_ptt)
1405 {
1406         struct ecore_mcp_function_info *info;
1407         struct public_func shmem_info;
1408
1409         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1410         info = &p_hwfn->mcp_info->func_info;
1411
1412         info->pause_on_host = (shmem_info.config &
1413                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1414
1415         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1416                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1417                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1418                 return ECORE_INVAL;
1419         }
1420
1421         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1422
1423         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1424                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1425                 info->mac[1] = (u8)(shmem_info.mac_upper);
1426                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1427                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1428                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1429                 info->mac[5] = (u8)(shmem_info.mac_lower);
1430         } else {
1431                 /* TODO - are there protocols for which there's no MAC? */
1432                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1433         }
1434
1435         /* TODO - are these calculations true for BE machine? */
1436         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1437                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1438         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1439                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1440
1441         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1442
1443         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1444                    "Read configuration from shmem: pause_on_host %02x"
1445                     " protocol %02x BW [%02x - %02x]"
1446                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1447                     " node %lx ovlan %04x\n",
1448                    info->pause_on_host, info->protocol,
1449                    info->bandwidth_min, info->bandwidth_max,
1450                    info->mac[0], info->mac[1], info->mac[2],
1451                    info->mac[3], info->mac[4], info->mac[5],
1452                    (unsigned long)info->wwn_port,
1453                    (unsigned long)info->wwn_node, info->ovlan);
1454
1455         return ECORE_SUCCESS;
1456 }
1457
1458 struct ecore_mcp_link_params
1459 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1460 {
1461         if (!p_hwfn || !p_hwfn->mcp_info)
1462                 return OSAL_NULL;
1463         return &p_hwfn->mcp_info->link_input;
1464 }
1465
1466 struct ecore_mcp_link_state
1467 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1468 {
1469         if (!p_hwfn || !p_hwfn->mcp_info)
1470                 return OSAL_NULL;
1471
1472 #ifndef ASIC_ONLY
1473         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1474                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1475                 p_hwfn->mcp_info->link_output.link_up = true;
1476         }
1477 #endif
1478
1479         return &p_hwfn->mcp_info->link_output;
1480 }
1481
1482 struct ecore_mcp_link_capabilities
1483 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1484 {
1485         if (!p_hwfn || !p_hwfn->mcp_info)
1486                 return OSAL_NULL;
1487         return &p_hwfn->mcp_info->link_capabilities;
1488 }
1489
1490 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1491                                      struct ecore_ptt *p_ptt)
1492 {
1493         u32 resp = 0, param = 0;
1494         enum _ecore_status_t rc;
1495
1496         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1497                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1498
1499         /* Wait for the drain to complete before returning */
1500         OSAL_MSLEEP(1020);
1501
1502         return rc;
1503 }
1504
1505 const struct ecore_mcp_function_info
1506 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1507 {
1508         if (!p_hwfn || !p_hwfn->mcp_info)
1509                 return OSAL_NULL;
1510         return &p_hwfn->mcp_info->func_info;
1511 }
1512
1513 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1514                                            struct ecore_ptt *p_ptt,
1515                                            struct ecore_mcp_nvm_params *params)
1516 {
1517         enum _ecore_status_t rc;
1518
1519         switch (params->type) {
1520         case ECORE_MCP_NVM_RD:
1521                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1522                                           params->nvm_common.offset,
1523                                           &params->nvm_common.resp,
1524                                           &params->nvm_common.param,
1525                                           params->nvm_rd.buf_size,
1526                                           params->nvm_rd.buf);
1527                 break;
1528         case ECORE_MCP_CMD:
1529                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1530                                    params->nvm_common.offset,
1531                                    &params->nvm_common.resp,
1532                                    &params->nvm_common.param);
1533                 break;
1534         case ECORE_MCP_NVM_WR:
1535                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1536                                           params->nvm_common.offset,
1537                                           &params->nvm_common.resp,
1538                                           &params->nvm_common.param,
1539                                           params->nvm_wr.buf_size,
1540                                           params->nvm_wr.buf);
1541                 break;
1542         default:
1543                 rc = ECORE_NOTIMPL;
1544                 break;
1545         }
1546         return rc;
1547 }
1548
1549 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1550                                   struct ecore_ptt *p_ptt, u32 personalities)
1551 {
1552         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1553         struct public_func shmem_info;
1554         int i, count = 0, num_pfs;
1555
1556         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1557
1558         for (i = 0; i < num_pfs; i++) {
1559                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1560                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1561                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1562                         continue;
1563
1564                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1565                                               &protocol) != ECORE_SUCCESS)
1566                         continue;
1567
1568                 if ((1 << ((u32)protocol)) & personalities)
1569                         count++;
1570         }
1571
1572         return count;
1573 }
1574
1575 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1576                                               struct ecore_ptt *p_ptt,
1577                                               u32 *p_flash_size)
1578 {
1579         u32 flash_size;
1580
1581 #ifndef ASIC_ONLY
1582         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1583                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1584                 return ECORE_INVAL;
1585         }
1586 #endif
1587
1588         if (IS_VF(p_hwfn->p_dev))
1589                 return ECORE_INVAL;
1590
1591         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1592         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1593             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1594         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1595
1596         *p_flash_size = flash_size;
1597
1598         return ECORE_SUCCESS;
1599 }
1600
1601 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1602                                                   struct ecore_ptt *p_ptt)
1603 {
1604         struct ecore_dev *p_dev = p_hwfn->p_dev;
1605
1606         if (p_dev->recov_in_prog) {
1607                 DP_NOTICE(p_hwfn, false,
1608                           "Avoid triggering a recovery since such a process"
1609                           " is already in progress\n");
1610                 return ECORE_AGAIN;
1611         }
1612
1613         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1614         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1615
1616         return ECORE_SUCCESS;
1617 }
1618
1619 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1620                                               struct ecore_ptt *p_ptt,
1621                                               u8 vf_id, u8 num)
1622 {
1623         u32 resp = 0, param = 0, rc_param = 0;
1624         enum _ecore_status_t rc;
1625
1626 /* Only Leader can configure MSIX, and need to take CMT into account */
1627
1628         if (!IS_LEAD_HWFN(p_hwfn))
1629                 return ECORE_SUCCESS;
1630         num *= p_hwfn->p_dev->num_hwfns;
1631
1632         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1633             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1634         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1635             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1636
1637         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1638                            &resp, &rc_param);
1639
1640         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1641                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1642                           vf_id);
1643                 rc = ECORE_INVAL;
1644         } else {
1645                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1646                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1647                             num, vf_id);
1648         }
1649
1650         return rc;
1651 }
1652
1653 enum _ecore_status_t
1654 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1655                            struct ecore_mcp_drv_version *p_ver)
1656 {
1657         struct drv_version_stc *p_drv_version;
1658         struct ecore_mcp_mb_params mb_params;
1659         union drv_union_data union_data;
1660         u32 num_words, i;
1661         void *p_name;
1662         OSAL_BE32 val;
1663         enum _ecore_status_t rc;
1664
1665 #ifndef ASIC_ONLY
1666         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1667                 return ECORE_SUCCESS;
1668 #endif
1669
1670         p_drv_version = &union_data.drv_version;
1671         p_drv_version->version = p_ver->version;
1672         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1673         for (i = 0; i < num_words; i++) {
1674                 p_name = &p_ver->name[i * sizeof(u32)];
1675                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1676                 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1677         }
1678
1679         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1680         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1681         mb_params.p_data_src = &union_data;
1682         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1683         if (rc != ECORE_SUCCESS)
1684                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1685
1686         return rc;
1687 }
1688
1689 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1690                                     struct ecore_ptt *p_ptt)
1691 {
1692         enum _ecore_status_t rc;
1693         u32 resp = 0, param = 0;
1694
1695         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1696                            &param);
1697         if (rc != ECORE_SUCCESS)
1698                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1699
1700         return rc;
1701 }
1702
1703 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1704                                       struct ecore_ptt *p_ptt)
1705 {
1706         u32 value, cpu_mode;
1707
1708         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1709
1710         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1711         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1712         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1713         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1714
1715         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1716 }
1717
1718 enum _ecore_status_t
1719 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1720                                    struct ecore_ptt *p_ptt,
1721                                    enum ecore_ov_config_method config,
1722                                    enum ecore_ov_client client)
1723 {
1724         enum _ecore_status_t rc;
1725         u32 resp = 0, param = 0;
1726         u32 drv_mb_param;
1727
1728         switch (config) {
1729         case ECORE_OV_CLIENT_DRV:
1730                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1731                 break;
1732         case ECORE_OV_CLIENT_USER:
1733                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1734                 break;
1735         default:
1736                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", config);
1737                 return ECORE_INVAL;
1738         }
1739
1740         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1741                            drv_mb_param, &resp, &param);
1742         if (rc != ECORE_SUCCESS)
1743                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1744
1745         return rc;
1746 }
1747
1748 enum _ecore_status_t
1749 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1750                                  struct ecore_ptt *p_ptt,
1751                                  enum ecore_ov_driver_state drv_state)
1752 {
1753         enum _ecore_status_t rc;
1754         u32 resp = 0, param = 0;
1755         u32 drv_mb_param;
1756
1757         switch (drv_state) {
1758         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1759                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1760                 break;
1761         case ECORE_OV_DRIVER_STATE_DISABLED:
1762                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1763                 break;
1764         case ECORE_OV_DRIVER_STATE_ACTIVE:
1765                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1766                 break;
1767         default:
1768                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1769                 return ECORE_INVAL;
1770         }
1771
1772         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1773                            drv_state, &resp, &param);
1774         if (rc != ECORE_SUCCESS)
1775                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1776
1777         return rc;
1778 }
1779
1780 enum _ecore_status_t
1781 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1782                          struct ecore_fc_npiv_tbl *p_table)
1783 {
1784         return 0;
1785 }
1786
1787 enum _ecore_status_t
1788 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1789                         struct ecore_ptt *p_ptt, u16 mtu)
1790 {
1791         return 0;
1792 }
1793
1794 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1795                                        struct ecore_ptt *p_ptt,
1796                                        enum ecore_led_mode mode)
1797 {
1798         u32 resp = 0, param = 0, drv_mb_param;
1799         enum _ecore_status_t rc;
1800
1801         switch (mode) {
1802         case ECORE_LED_MODE_ON:
1803                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1804                 break;
1805         case ECORE_LED_MODE_OFF:
1806                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1807                 break;
1808         case ECORE_LED_MODE_RESTORE:
1809                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1810                 break;
1811         default:
1812                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1813                 return ECORE_INVAL;
1814         }
1815
1816         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1817                            drv_mb_param, &resp, &param);
1818         if (rc != ECORE_SUCCESS)
1819                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1820
1821         return rc;
1822 }
1823
1824 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1825                                              struct ecore_ptt *p_ptt,
1826                                              u32 mask_parities)
1827 {
1828         enum _ecore_status_t rc;
1829         u32 resp = 0, param = 0;
1830
1831         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1832                            mask_parities, &resp, &param);
1833
1834         if (rc != ECORE_SUCCESS) {
1835                 DP_ERR(p_hwfn,
1836                        "MCP response failure for mask parities, aborting\n");
1837         } else if (resp != FW_MSG_CODE_OK) {
1838                 DP_ERR(p_hwfn,
1839                        "MCP did not ack mask parity request. Old MFW?\n");
1840                 rc = ECORE_INVAL;
1841         }
1842
1843         return rc;
1844 }
1845
1846 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1847                                         u8 *p_buf, u32 len)
1848 {
1849         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1850         u32 bytes_left, offset, bytes_to_copy, buf_size;
1851         struct ecore_mcp_nvm_params params;
1852         struct ecore_ptt *p_ptt;
1853         enum _ecore_status_t rc = ECORE_SUCCESS;
1854
1855         p_ptt = ecore_ptt_acquire(p_hwfn);
1856         if (!p_ptt)
1857                 return ECORE_BUSY;
1858
1859         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1860         bytes_left = len;
1861         offset = 0;
1862         params.type = ECORE_MCP_NVM_RD;
1863         params.nvm_rd.buf_size = &buf_size;
1864         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1865         while (bytes_left > 0) {
1866                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1867                                            MCP_DRV_NVM_BUF_LEN);
1868                 params.nvm_common.offset = (addr + offset) |
1869                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1870                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1871                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1872                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1873                                             FW_MSG_CODE_NVM_OK)) {
1874                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1875                         break;
1876                 }
1877
1878                 /* This can be a lengthy process, and it's possible scheduler
1879                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
1880                  */
1881                 if (bytes_left % 0x1000 <
1882                     (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
1883                         OSAL_MSLEEP(1);
1884
1885                 offset += *params.nvm_rd.buf_size;
1886                 bytes_left -= *params.nvm_rd.buf_size;
1887         }
1888
1889         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1890         ecore_ptt_release(p_hwfn, p_ptt);
1891
1892         return rc;
1893 }
1894
1895 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1896                                         u32 addr, u8 *p_buf, u32 len)
1897 {
1898         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1899         struct ecore_mcp_nvm_params params;
1900         struct ecore_ptt *p_ptt;
1901         enum _ecore_status_t rc;
1902
1903         p_ptt = ecore_ptt_acquire(p_hwfn);
1904         if (!p_ptt)
1905                 return ECORE_BUSY;
1906
1907         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1908         params.type = ECORE_MCP_NVM_RD;
1909         params.nvm_rd.buf_size = &len;
1910         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1911             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1912         params.nvm_common.offset = addr;
1913         params.nvm_rd.buf = (u32 *)p_buf;
1914         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1915         if (rc != ECORE_SUCCESS)
1916                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1917
1918         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1919         ecore_ptt_release(p_hwfn, p_ptt);
1920
1921         return rc;
1922 }
1923
1924 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1925 {
1926         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1927         struct ecore_mcp_nvm_params params;
1928         struct ecore_ptt *p_ptt;
1929
1930         p_ptt = ecore_ptt_acquire(p_hwfn);
1931         if (!p_ptt)
1932                 return ECORE_BUSY;
1933
1934         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1935         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1936         ecore_ptt_release(p_hwfn, p_ptt);
1937
1938         return ECORE_SUCCESS;
1939 }
1940
1941 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1942 {
1943         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1944         struct ecore_mcp_nvm_params params;
1945         struct ecore_ptt *p_ptt;
1946         enum _ecore_status_t rc;
1947
1948         p_ptt = ecore_ptt_acquire(p_hwfn);
1949         if (!p_ptt)
1950                 return ECORE_BUSY;
1951         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1952         params.type = ECORE_MCP_CMD;
1953         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1954         params.nvm_common.offset = addr;
1955         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1956         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1957         ecore_ptt_release(p_hwfn, p_ptt);
1958
1959         return rc;
1960 }
1961
1962 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1963                                                   u32 addr)
1964 {
1965         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1966         struct ecore_mcp_nvm_params params;
1967         struct ecore_ptt *p_ptt;
1968         enum _ecore_status_t rc;
1969
1970         p_ptt = ecore_ptt_acquire(p_hwfn);
1971         if (!p_ptt)
1972                 return ECORE_BUSY;
1973         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1974         params.type = ECORE_MCP_CMD;
1975         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1976         params.nvm_common.offset = addr;
1977         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1978         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1979         ecore_ptt_release(p_hwfn, p_ptt);
1980
1981         return rc;
1982 }
1983
1984 /* rc receives ECORE_INVAL as default parameter because
1985  * it might not enter the while loop if the len is 0
1986  */
1987 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1988                                          u32 addr, u8 *p_buf, u32 len)
1989 {
1990         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1991         enum _ecore_status_t rc = ECORE_INVAL;
1992         struct ecore_mcp_nvm_params params;
1993         struct ecore_ptt *p_ptt;
1994         u32 buf_idx, buf_size;
1995
1996         p_ptt = ecore_ptt_acquire(p_hwfn);
1997         if (!p_ptt)
1998                 return ECORE_BUSY;
1999
2000         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2001         params.type = ECORE_MCP_NVM_WR;
2002         if (cmd == ECORE_PUT_FILE_DATA)
2003                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2004         else
2005                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2006         buf_idx = 0;
2007         while (buf_idx < len) {
2008                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2009                                       MCP_DRV_NVM_BUF_LEN);
2010                 params.nvm_common.offset = ((buf_size <<
2011                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
2012                                             | addr) + buf_idx;
2013                 params.nvm_wr.buf_size = buf_size;
2014                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2015                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2016                 if (rc != ECORE_SUCCESS ||
2017                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2018                      (params.nvm_common.resp !=
2019                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2020                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2021
2022                 /* This can be a lengthy process, and it's possible scheduler
2023                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2024                  */
2025                 if (buf_idx % 0x1000 >
2026                     (buf_idx + buf_size) % 0x1000)
2027                         OSAL_MSLEEP(1);
2028
2029                 buf_idx += buf_size;
2030         }
2031
2032         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2033         ecore_ptt_release(p_hwfn, p_ptt);
2034
2035         return rc;
2036 }
2037
2038 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2039                                          u32 addr, u8 *p_buf, u32 len)
2040 {
2041         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2042         struct ecore_mcp_nvm_params params;
2043         struct ecore_ptt *p_ptt;
2044         enum _ecore_status_t rc;
2045
2046         p_ptt = ecore_ptt_acquire(p_hwfn);
2047         if (!p_ptt)
2048                 return ECORE_BUSY;
2049
2050         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2051         params.type = ECORE_MCP_NVM_WR;
2052         params.nvm_wr.buf_size = len;
2053         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2054             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2055         params.nvm_common.offset = addr;
2056         params.nvm_wr.buf = (u32 *)p_buf;
2057         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2058         if (rc != ECORE_SUCCESS)
2059                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2060         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2061         ecore_ptt_release(p_hwfn, p_ptt);
2062
2063         return rc;
2064 }
2065
2066 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2067                                                    u32 addr)
2068 {
2069         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2070         struct ecore_mcp_nvm_params params;
2071         struct ecore_ptt *p_ptt;
2072         enum _ecore_status_t rc;
2073
2074         p_ptt = ecore_ptt_acquire(p_hwfn);
2075         if (!p_ptt)
2076                 return ECORE_BUSY;
2077
2078         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2079         params.type = ECORE_MCP_CMD;
2080         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2081         params.nvm_common.offset = addr;
2082         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2083         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2084         ecore_ptt_release(p_hwfn, p_ptt);
2085
2086         return rc;
2087 }
2088
2089 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2090                                             struct ecore_ptt *p_ptt,
2091                                             u32 port, u32 addr, u32 offset,
2092                                             u32 len, u8 *p_buf)
2093 {
2094         struct ecore_mcp_nvm_params params;
2095         enum _ecore_status_t rc;
2096         u32 bytes_left, bytes_to_copy, buf_size;
2097
2098         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2099         params.nvm_common.offset =
2100                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2101                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2102         addr = offset;
2103         offset = 0;
2104         bytes_left = len;
2105         params.type = ECORE_MCP_NVM_RD;
2106         params.nvm_rd.buf_size = &buf_size;
2107         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2108         while (bytes_left > 0) {
2109                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2110                                            MAX_I2C_TRANSACTION_SIZE);
2111                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2112                 params.nvm_common.offset &=
2113                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2114                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2115                 params.nvm_common.offset |=
2116                         ((addr + offset) <<
2117                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2118                 params.nvm_common.offset |=
2119                         (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2120                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2121                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2122                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2123                         return ECORE_NODEV;
2124                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2125                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2126                         return ECORE_UNKNOWN_ERROR;
2127
2128                 offset += *params.nvm_rd.buf_size;
2129                 bytes_left -= *params.nvm_rd.buf_size;
2130         }
2131
2132         return ECORE_SUCCESS;
2133 }
2134
2135 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2136                                              struct ecore_ptt *p_ptt,
2137                                              u32 port, u32 addr, u32 offset,
2138                                              u32 len, u8 *p_buf)
2139 {
2140         struct ecore_mcp_nvm_params params;
2141         enum _ecore_status_t rc;
2142         u32 buf_idx, buf_size;
2143
2144         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2145         params.nvm_common.offset =
2146                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2147                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2148         params.type = ECORE_MCP_NVM_WR;
2149         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2150         buf_idx = 0;
2151         while (buf_idx < len) {
2152                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2153                                       MAX_I2C_TRANSACTION_SIZE);
2154                 params.nvm_common.offset &=
2155                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2156                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2157                 params.nvm_common.offset |=
2158                         ((offset + buf_idx) <<
2159                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2160                 params.nvm_common.offset |=
2161                         (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2162                 params.nvm_wr.buf_size = buf_size;
2163                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2164                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2165                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2166                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2167                         return ECORE_NODEV;
2168                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2169                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2170                         return ECORE_UNKNOWN_ERROR;
2171
2172                 buf_idx += buf_size;
2173         }
2174
2175         return ECORE_SUCCESS;
2176 }
2177
2178 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2179                                          struct ecore_ptt *p_ptt,
2180                                          u16 gpio, u32 *gpio_val)
2181 {
2182         enum _ecore_status_t rc = ECORE_SUCCESS;
2183         u32 drv_mb_param = 0, rsp;
2184
2185         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2186
2187         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2188                            drv_mb_param, &rsp, gpio_val);
2189
2190         if (rc != ECORE_SUCCESS)
2191                 return rc;
2192
2193         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2194                 return ECORE_UNKNOWN_ERROR;
2195
2196         return ECORE_SUCCESS;
2197 }
2198
2199 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2200                                           struct ecore_ptt *p_ptt,
2201                                           u16 gpio, u16 gpio_val)
2202 {
2203         enum _ecore_status_t rc = ECORE_SUCCESS;
2204         u32 drv_mb_param = 0, param, rsp;
2205
2206         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2207                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2208
2209         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2210                            drv_mb_param, &rsp, &param);
2211
2212         if (rc != ECORE_SUCCESS)
2213                 return rc;
2214
2215         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2216                 return ECORE_UNKNOWN_ERROR;
2217
2218         return ECORE_SUCCESS;
2219 }
2220
2221 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2222                                          struct ecore_ptt *p_ptt,
2223                                          u16 gpio, u32 *gpio_direction,
2224                                          u32 *gpio_ctrl)
2225 {
2226         u32 drv_mb_param = 0, rsp, val = 0;
2227         enum _ecore_status_t rc = ECORE_SUCCESS;
2228
2229         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2230
2231         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2232                            drv_mb_param, &rsp, &val);
2233         if (rc != ECORE_SUCCESS)
2234                 return rc;
2235
2236         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2237                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2238         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2239                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2240
2241         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2242                 return ECORE_UNKNOWN_ERROR;
2243
2244         return ECORE_SUCCESS;
2245 }
2246
2247 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2248                                                   struct ecore_ptt *p_ptt)
2249 {
2250         u32 drv_mb_param = 0, rsp, param;
2251         enum _ecore_status_t rc = ECORE_SUCCESS;
2252
2253         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2254                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2255
2256         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2257                            drv_mb_param, &rsp, &param);
2258
2259         if (rc != ECORE_SUCCESS)
2260                 return rc;
2261
2262         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2263             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2264                 rc = ECORE_UNKNOWN_ERROR;
2265
2266         return rc;
2267 }
2268
2269 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2270                                                struct ecore_ptt *p_ptt)
2271 {
2272         u32 drv_mb_param = 0, rsp, param;
2273         enum _ecore_status_t rc = ECORE_SUCCESS;
2274
2275         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2276                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2277
2278         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2279                            drv_mb_param, &rsp, &param);
2280
2281         if (rc != ECORE_SUCCESS)
2282                 return rc;
2283
2284         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2285             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2286                 rc = ECORE_UNKNOWN_ERROR;
2287
2288         return rc;
2289 }
2290
2291 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2292         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2293 {
2294         u32 drv_mb_param = 0, rsp;
2295         enum _ecore_status_t rc = ECORE_SUCCESS;
2296
2297         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2298                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2299
2300         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2301                            drv_mb_param, &rsp, num_images);
2302
2303         if (rc != ECORE_SUCCESS)
2304                 return rc;
2305
2306         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2307                 rc = ECORE_UNKNOWN_ERROR;
2308
2309         return rc;
2310 }
2311
2312 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2313         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2314         struct bist_nvm_image_att *p_image_att, u32 image_index)
2315 {
2316         struct ecore_mcp_nvm_params params;
2317         enum _ecore_status_t rc;
2318         u32 buf_size;
2319
2320         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2321         params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2322                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2323         params.nvm_common.offset |= (image_index <<
2324                                     DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2325
2326         params.type = ECORE_MCP_NVM_RD;
2327         params.nvm_rd.buf_size = &buf_size;
2328         params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2329         params.nvm_rd.buf = (u32 *)p_image_att;
2330
2331         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2332         if (rc != ECORE_SUCCESS)
2333                 return rc;
2334
2335         if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2336             (p_image_att->return_code != 1))
2337                 rc = ECORE_UNKNOWN_ERROR;
2338
2339         return rc;
2340 }
2341
2342 enum _ecore_status_t
2343 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2344                                struct ecore_ptt *p_ptt,
2345                                struct ecore_temperature_info *p_temp_info)
2346 {
2347         struct ecore_temperature_sensor *p_temp_sensor;
2348         struct temperature_status_stc *p_mfw_temp_info;
2349         struct ecore_mcp_mb_params mb_params;
2350         union drv_union_data union_data;
2351         u32 val;
2352         enum _ecore_status_t rc;
2353         u8 i;
2354
2355         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2356         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2357         mb_params.p_data_dst = &union_data;
2358         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2359         if (rc != ECORE_SUCCESS)
2360                 return rc;
2361
2362         p_mfw_temp_info = &union_data.temp_info;
2363
2364         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2365         p_temp_info->num_sensors = OSAL_MIN_T(u32,
2366                                               p_mfw_temp_info->num_of_sensors,
2367                                               ECORE_MAX_NUM_OF_SENSORS);
2368         for (i = 0; i < p_temp_info->num_sensors; i++) {
2369                 val = p_mfw_temp_info->sensor[i];
2370                 p_temp_sensor = &p_temp_info->sensors[i];
2371                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2372                                                  SENSOR_LOCATION_SHIFT;
2373                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2374                                                 THRESHOLD_HIGH_SHIFT;
2375                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2376                                           CRITICAL_TEMPERATURE_SHIFT;
2377                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2378                                               CURRENT_TEMP_SHIFT;
2379         }
2380
2381         return ECORE_SUCCESS;
2382 }
2383
2384 enum _ecore_status_t ecore_mcp_get_mba_versions(
2385         struct ecore_hwfn *p_hwfn,
2386         struct ecore_ptt *p_ptt,
2387         struct ecore_mba_vers *p_mba_vers)
2388 {
2389         struct ecore_mcp_nvm_params params;
2390         enum _ecore_status_t rc;
2391         u32 buf_size;
2392
2393         OSAL_MEM_ZERO(&params, sizeof(params));
2394         params.type = ECORE_MCP_NVM_RD;
2395         params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2396         params.nvm_common.offset = 0;
2397         params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2398         params.nvm_rd.buf_size = &buf_size;
2399         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2400
2401         if (rc != ECORE_SUCCESS)
2402                 return rc;
2403
2404         if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2405             FW_MSG_CODE_NVM_OK)
2406                 rc = ECORE_UNKNOWN_ERROR;
2407
2408         if (buf_size != MCP_DRV_NVM_BUF_LEN)
2409                 rc = ECORE_UNKNOWN_ERROR;
2410
2411         return rc;
2412 }
2413
2414 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2415                                               struct ecore_ptt *p_ptt,
2416                                               u64 *num_events)
2417 {
2418         u32 rsp;
2419
2420         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2421                              0, &rsp, (u32 *)num_events);
2422 }
2423
2424 #define ECORE_RESC_ALLOC_VERSION_MAJOR  1
2425 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
2426 #define ECORE_RESC_ALLOC_VERSION                                \
2427         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
2428           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
2429          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
2430           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2431
2432 enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
2433                                              struct ecore_ptt *p_ptt,
2434                                              struct resource_info *p_resc_info,
2435                                              u32 *p_mcp_resp, u32 *p_mcp_param)
2436 {
2437         struct ecore_mcp_mb_params mb_params;
2438         union drv_union_data *p_union_data;
2439         enum _ecore_status_t rc;
2440
2441         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2442         mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2443         mb_params.param = ECORE_RESC_ALLOC_VERSION;
2444         p_union_data = (union drv_union_data *)p_resc_info;
2445         mb_params.p_data_src = p_union_data;
2446         mb_params.p_data_dst = p_union_data;
2447         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2448         if (rc != ECORE_SUCCESS)
2449                 return rc;
2450
2451         *p_mcp_resp = mb_params.mcp_resp;
2452         *p_mcp_param = mb_params.mcp_param;
2453
2454         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2455                    "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
2456                    " offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
2457                    *p_mcp_param, p_resc_info->res_id, p_resc_info->size,
2458                    p_resc_info->offset, p_resc_info->vf_size,
2459                    p_resc_info->vf_offset, p_resc_info->flags);
2460
2461         return ECORE_SUCCESS;
2462 }
2463
2464 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
2465                                                struct ecore_ptt *p_ptt)
2466 {
2467         u32 mcp_resp, mcp_param;
2468
2469         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2470                              &mcp_resp, &mcp_param);
2471 }