1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 /* Runtime array offsets */
11 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
12 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
13 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
14 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
15 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
16 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
17 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
18 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
19 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
20 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
21 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
22 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
23 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
24 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
25 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
26 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
27 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16
28 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17
29 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18
30 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19
31 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20
32 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21
33 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22
34 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23
35 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24
36 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25
37 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26
38 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
39 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762
40 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
41 #define CAU_REG_PI_MEMORY_RT_OFFSET 1498
42 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
43 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914
44 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915
45 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916
46 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917
47 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918
48 #define PRS_REG_SEARCH_TCP_RT_OFFSET 5919
49 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920
50 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921
51 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922
52 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923
53 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924
54 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925
55 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926
56 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927
57 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928
58 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929
59 #define SRC_REG_FIRSTFREE_RT_OFFSET 5930
60 #define SRC_REG_FIRSTFREE_RT_SIZE 2
61 #define SRC_REG_LASTFREE_RT_OFFSET 5932
62 #define SRC_REG_LASTFREE_RT_SIZE 2
63 #define SRC_REG_COUNTFREE_RT_OFFSET 5934
64 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935
65 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936
66 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937
67 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938
68 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939
69 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940
70 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941
71 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942
72 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943
73 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944
74 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945
75 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946
76 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947
77 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948
78 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949
79 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950
80 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951
81 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952
82 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953
83 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954
84 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955
85 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956
86 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957
87 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958
88 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959
89 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960
90 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961
91 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962
92 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963
93 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964
94 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965
95 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966
96 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967
97 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
98 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967
99 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968
100 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969
101 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970
102 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971
103 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972
104 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973
105 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974
106 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975
107 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976
108 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977
109 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978
110 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979
111 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
112 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395
113 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
114 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907
115 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908
116 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909
117 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910
118 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911
119 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912
120 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913
121 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914
122 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915
123 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916
124 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917
125 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918
126 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919
127 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920
128 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921
129 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922
130 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923
131 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924
132 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925
133 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926
134 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927
135 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928
136 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929
137 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930
138 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931
139 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932
140 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933
141 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934
142 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935
143 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936
144 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937
145 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938
146 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939
147 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940
148 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941
149 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942
150 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943
151 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944
152 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945
153 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946
154 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947
155 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948
156 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949
157 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950
158 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951
159 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952
160 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953
161 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954
162 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955
163 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956
164 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957
165 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958
166 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959
167 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960
168 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961
169 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962
170 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963
171 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964
172 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965
173 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966
174 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967
175 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968
176 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969
177 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970
178 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971
179 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972
180 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973
181 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974
182 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
183 #define QM_REG_PTRTBLOTHER_RT_OFFSET 29102
184 #define QM_REG_PTRTBLOTHER_RT_SIZE 256
185 #define QM_REG_VOQCRDLINE_RT_OFFSET 29358
186 #define QM_REG_VOQCRDLINE_RT_SIZE 20
187 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378
188 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
189 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398
190 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399
191 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400
192 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401
193 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402
194 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403
195 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404
196 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405
197 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406
198 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407
199 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408
200 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409
201 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410
202 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411
203 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412
204 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413
205 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414
206 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415
207 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416
208 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417
209 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418
210 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419
211 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420
212 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421
213 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422
214 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423
215 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424
216 #define QM_REG_PQTX2PF_0_RT_OFFSET 29425
217 #define QM_REG_PQTX2PF_1_RT_OFFSET 29426
218 #define QM_REG_PQTX2PF_2_RT_OFFSET 29427
219 #define QM_REG_PQTX2PF_3_RT_OFFSET 29428
220 #define QM_REG_PQTX2PF_4_RT_OFFSET 29429
221 #define QM_REG_PQTX2PF_5_RT_OFFSET 29430
222 #define QM_REG_PQTX2PF_6_RT_OFFSET 29431
223 #define QM_REG_PQTX2PF_7_RT_OFFSET 29432
224 #define QM_REG_PQTX2PF_8_RT_OFFSET 29433
225 #define QM_REG_PQTX2PF_9_RT_OFFSET 29434
226 #define QM_REG_PQTX2PF_10_RT_OFFSET 29435
227 #define QM_REG_PQTX2PF_11_RT_OFFSET 29436
228 #define QM_REG_PQTX2PF_12_RT_OFFSET 29437
229 #define QM_REG_PQTX2PF_13_RT_OFFSET 29438
230 #define QM_REG_PQTX2PF_14_RT_OFFSET 29439
231 #define QM_REG_PQTX2PF_15_RT_OFFSET 29440
232 #define QM_REG_PQTX2PF_16_RT_OFFSET 29441
233 #define QM_REG_PQTX2PF_17_RT_OFFSET 29442
234 #define QM_REG_PQTX2PF_18_RT_OFFSET 29443
235 #define QM_REG_PQTX2PF_19_RT_OFFSET 29444
236 #define QM_REG_PQTX2PF_20_RT_OFFSET 29445
237 #define QM_REG_PQTX2PF_21_RT_OFFSET 29446
238 #define QM_REG_PQTX2PF_22_RT_OFFSET 29447
239 #define QM_REG_PQTX2PF_23_RT_OFFSET 29448
240 #define QM_REG_PQTX2PF_24_RT_OFFSET 29449
241 #define QM_REG_PQTX2PF_25_RT_OFFSET 29450
242 #define QM_REG_PQTX2PF_26_RT_OFFSET 29451
243 #define QM_REG_PQTX2PF_27_RT_OFFSET 29452
244 #define QM_REG_PQTX2PF_28_RT_OFFSET 29453
245 #define QM_REG_PQTX2PF_29_RT_OFFSET 29454
246 #define QM_REG_PQTX2PF_30_RT_OFFSET 29455
247 #define QM_REG_PQTX2PF_31_RT_OFFSET 29456
248 #define QM_REG_PQTX2PF_32_RT_OFFSET 29457
249 #define QM_REG_PQTX2PF_33_RT_OFFSET 29458
250 #define QM_REG_PQTX2PF_34_RT_OFFSET 29459
251 #define QM_REG_PQTX2PF_35_RT_OFFSET 29460
252 #define QM_REG_PQTX2PF_36_RT_OFFSET 29461
253 #define QM_REG_PQTX2PF_37_RT_OFFSET 29462
254 #define QM_REG_PQTX2PF_38_RT_OFFSET 29463
255 #define QM_REG_PQTX2PF_39_RT_OFFSET 29464
256 #define QM_REG_PQTX2PF_40_RT_OFFSET 29465
257 #define QM_REG_PQTX2PF_41_RT_OFFSET 29466
258 #define QM_REG_PQTX2PF_42_RT_OFFSET 29467
259 #define QM_REG_PQTX2PF_43_RT_OFFSET 29468
260 #define QM_REG_PQTX2PF_44_RT_OFFSET 29469
261 #define QM_REG_PQTX2PF_45_RT_OFFSET 29470
262 #define QM_REG_PQTX2PF_46_RT_OFFSET 29471
263 #define QM_REG_PQTX2PF_47_RT_OFFSET 29472
264 #define QM_REG_PQTX2PF_48_RT_OFFSET 29473
265 #define QM_REG_PQTX2PF_49_RT_OFFSET 29474
266 #define QM_REG_PQTX2PF_50_RT_OFFSET 29475
267 #define QM_REG_PQTX2PF_51_RT_OFFSET 29476
268 #define QM_REG_PQTX2PF_52_RT_OFFSET 29477
269 #define QM_REG_PQTX2PF_53_RT_OFFSET 29478
270 #define QM_REG_PQTX2PF_54_RT_OFFSET 29479
271 #define QM_REG_PQTX2PF_55_RT_OFFSET 29480
272 #define QM_REG_PQTX2PF_56_RT_OFFSET 29481
273 #define QM_REG_PQTX2PF_57_RT_OFFSET 29482
274 #define QM_REG_PQTX2PF_58_RT_OFFSET 29483
275 #define QM_REG_PQTX2PF_59_RT_OFFSET 29484
276 #define QM_REG_PQTX2PF_60_RT_OFFSET 29485
277 #define QM_REG_PQTX2PF_61_RT_OFFSET 29486
278 #define QM_REG_PQTX2PF_62_RT_OFFSET 29487
279 #define QM_REG_PQTX2PF_63_RT_OFFSET 29488
280 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489
281 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490
282 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491
283 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492
284 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493
285 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494
286 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495
287 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496
288 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497
289 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498
290 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499
291 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500
292 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501
293 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502
294 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503
295 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504
296 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505
297 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506
298 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507
299 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508
300 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509
301 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510
302 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511
303 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512
304 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513
305 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514
306 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515
307 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516
308 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517
309 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
310 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773
311 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
312 #define QM_REG_RLGLBLCRD_RT_OFFSET 30029
313 #define QM_REG_RLGLBLCRD_RT_SIZE 256
314 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30285
315 #define QM_REG_RLPFPERIOD_RT_OFFSET 30286
316 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287
317 #define QM_REG_RLPFINCVAL_RT_OFFSET 30288
318 #define QM_REG_RLPFINCVAL_RT_SIZE 16
319 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304
320 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
321 #define QM_REG_RLPFCRD_RT_OFFSET 30320
322 #define QM_REG_RLPFCRD_RT_SIZE 16
323 #define QM_REG_RLPFENABLE_RT_OFFSET 30336
324 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337
325 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338
326 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
327 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354
328 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
329 #define QM_REG_WFQPFCRD_RT_OFFSET 30370
330 #define QM_REG_WFQPFCRD_RT_SIZE 160
331 #define QM_REG_WFQPFENABLE_RT_OFFSET 30530
332 #define QM_REG_WFQVPENABLE_RT_OFFSET 30531
333 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532
334 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
335 #define QM_REG_TXPQMAP_RT_OFFSET 31044
336 #define QM_REG_TXPQMAP_RT_SIZE 512
337 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556
338 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
339 #define QM_REG_WFQVPCRD_RT_OFFSET 32068
340 #define QM_REG_WFQVPCRD_RT_SIZE 512
341 #define QM_REG_WFQVPMAP_RT_OFFSET 32580
342 #define QM_REG_WFQVPMAP_RT_SIZE 512
343 #define QM_REG_PTRTBLTX_RT_OFFSET 33092
344 #define QM_REG_PTRTBLTX_RT_SIZE 1024
345 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116
346 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
347 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276
348 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277
349 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278
350 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279
351 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280
352 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281
353 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282
354 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283
355 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
356 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287
357 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
358 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291
359 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
360 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323
361 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
362 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339
363 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
364 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355
365 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
366 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371
367 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
368 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387
369 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388
370 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
371 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396
372 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397
373 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398
374 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399
375 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400
376 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401
377 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402
378 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403
379 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404
380 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405
381 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406
382 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407
383 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408
384 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409
385 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410
386 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411
387 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412
388 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413
389 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414
390 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415
391 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416
392 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417
393 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418
394 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419
395 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420
396 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421
397 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422
398 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423
399 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424
400 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425
401 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426
402 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427
403 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428
404 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429
405 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430
406 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431
407 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432
408 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433
409 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434
410 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435
411 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436
412 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437
413 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438
414 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439
415 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440
416 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441
417 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442
418 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443
419 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444
420 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445
421 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446
422 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447
423 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448
424 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449
425 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450
426 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451
427 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452
428 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453
429 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454
430 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455
431 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456
432 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457
433 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458
434 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459
435 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460
436 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461
437 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462
438 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463
439 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464
440 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465
441 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466
442 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467
443 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468
444 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469
445 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470
446 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471
448 #define RUNTIME_ARRAY_SIZE 34472
451 #define DMAE_READY_CB 0
453 #endif /* __RT_DEFS_H__ */