2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 /* Runtime array offsets */
13 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
14 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
15 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
16 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
17 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
18 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
19 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
20 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
21 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
22 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
23 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
24 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
25 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
26 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
27 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
28 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
29 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
30 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
31 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
32 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
33 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
34 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
35 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
36 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
37 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
38 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
39 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
40 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
41 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
42 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
43 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
44 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
45 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
46 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
47 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
48 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
49 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
50 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
51 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
52 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
53 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
54 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
55 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
56 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
57 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
58 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
59 #define SRC_REG_FIRSTFREE_RT_SIZE 2
60 #define SRC_REG_LASTFREE_RT_OFFSET 6667
61 #define SRC_REG_LASTFREE_RT_SIZE 2
62 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
63 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
64 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
65 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
66 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
67 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
68 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
69 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
70 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
71 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
72 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
73 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
74 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
75 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
76 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
77 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
78 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
79 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
80 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
81 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
82 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
83 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
84 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
85 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
86 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
87 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
88 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
89 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
90 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
91 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
92 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
93 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
94 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
95 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
96 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
97 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
98 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
99 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
100 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
101 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
102 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
103 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
104 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
105 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
106 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
107 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
108 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
109 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
110 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
111 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
112 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
113 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29642
114 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29643
115 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29644
116 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29645
117 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29646
118 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29647
119 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29648
120 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29649
121 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29650
122 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29651
123 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29652
124 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29653
125 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29654
126 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29655
127 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29656
128 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29657
129 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29658
130 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29659
131 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29660
132 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29661
133 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29662
134 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29663
135 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29664
136 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29665
137 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29666
138 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29667
139 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29668
140 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29669
141 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29670
142 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29671
143 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29672
144 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29673
145 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29674
146 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29675
147 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29676
148 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29677
149 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29678
150 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29679
151 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29680
152 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29681
153 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29682
154 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29683
155 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29684
156 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29685
157 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29686
158 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29687
159 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29688
160 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29689
161 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29690
162 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29691
163 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29692
164 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29693
165 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29694
166 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29695
167 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29696
168 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29697
169 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29698
170 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29699
171 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29700
172 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29701
173 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29702
174 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29703
175 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29704
176 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29705
177 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29706
178 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29707
179 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29708
180 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29709
181 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
182 #define QM_REG_VOQCRDLINE_RT_OFFSET 29837
183 #define QM_REG_VOQCRDLINE_RT_SIZE 20
184 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29857
185 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
186 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29877
187 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29878
188 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29879
189 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29880
190 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29881
191 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29882
192 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29883
193 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29884
194 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29885
195 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29886
196 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29887
197 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29888
198 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29889
199 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29890
200 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29891
201 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29892
202 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29893
203 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29894
204 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29895
205 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29896
206 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29897
207 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29898
208 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29899
209 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29900
210 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29901
211 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29902
212 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29903
213 #define QM_REG_PQTX2PF_0_RT_OFFSET 29904
214 #define QM_REG_PQTX2PF_1_RT_OFFSET 29905
215 #define QM_REG_PQTX2PF_2_RT_OFFSET 29906
216 #define QM_REG_PQTX2PF_3_RT_OFFSET 29907
217 #define QM_REG_PQTX2PF_4_RT_OFFSET 29908
218 #define QM_REG_PQTX2PF_5_RT_OFFSET 29909
219 #define QM_REG_PQTX2PF_6_RT_OFFSET 29910
220 #define QM_REG_PQTX2PF_7_RT_OFFSET 29911
221 #define QM_REG_PQTX2PF_8_RT_OFFSET 29912
222 #define QM_REG_PQTX2PF_9_RT_OFFSET 29913
223 #define QM_REG_PQTX2PF_10_RT_OFFSET 29914
224 #define QM_REG_PQTX2PF_11_RT_OFFSET 29915
225 #define QM_REG_PQTX2PF_12_RT_OFFSET 29916
226 #define QM_REG_PQTX2PF_13_RT_OFFSET 29917
227 #define QM_REG_PQTX2PF_14_RT_OFFSET 29918
228 #define QM_REG_PQTX2PF_15_RT_OFFSET 29919
229 #define QM_REG_PQTX2PF_16_RT_OFFSET 29920
230 #define QM_REG_PQTX2PF_17_RT_OFFSET 29921
231 #define QM_REG_PQTX2PF_18_RT_OFFSET 29922
232 #define QM_REG_PQTX2PF_19_RT_OFFSET 29923
233 #define QM_REG_PQTX2PF_20_RT_OFFSET 29924
234 #define QM_REG_PQTX2PF_21_RT_OFFSET 29925
235 #define QM_REG_PQTX2PF_22_RT_OFFSET 29926
236 #define QM_REG_PQTX2PF_23_RT_OFFSET 29927
237 #define QM_REG_PQTX2PF_24_RT_OFFSET 29928
238 #define QM_REG_PQTX2PF_25_RT_OFFSET 29929
239 #define QM_REG_PQTX2PF_26_RT_OFFSET 29930
240 #define QM_REG_PQTX2PF_27_RT_OFFSET 29931
241 #define QM_REG_PQTX2PF_28_RT_OFFSET 29932
242 #define QM_REG_PQTX2PF_29_RT_OFFSET 29933
243 #define QM_REG_PQTX2PF_30_RT_OFFSET 29934
244 #define QM_REG_PQTX2PF_31_RT_OFFSET 29935
245 #define QM_REG_PQTX2PF_32_RT_OFFSET 29936
246 #define QM_REG_PQTX2PF_33_RT_OFFSET 29937
247 #define QM_REG_PQTX2PF_34_RT_OFFSET 29938
248 #define QM_REG_PQTX2PF_35_RT_OFFSET 29939
249 #define QM_REG_PQTX2PF_36_RT_OFFSET 29940
250 #define QM_REG_PQTX2PF_37_RT_OFFSET 29941
251 #define QM_REG_PQTX2PF_38_RT_OFFSET 29942
252 #define QM_REG_PQTX2PF_39_RT_OFFSET 29943
253 #define QM_REG_PQTX2PF_40_RT_OFFSET 29944
254 #define QM_REG_PQTX2PF_41_RT_OFFSET 29945
255 #define QM_REG_PQTX2PF_42_RT_OFFSET 29946
256 #define QM_REG_PQTX2PF_43_RT_OFFSET 29947
257 #define QM_REG_PQTX2PF_44_RT_OFFSET 29948
258 #define QM_REG_PQTX2PF_45_RT_OFFSET 29949
259 #define QM_REG_PQTX2PF_46_RT_OFFSET 29950
260 #define QM_REG_PQTX2PF_47_RT_OFFSET 29951
261 #define QM_REG_PQTX2PF_48_RT_OFFSET 29952
262 #define QM_REG_PQTX2PF_49_RT_OFFSET 29953
263 #define QM_REG_PQTX2PF_50_RT_OFFSET 29954
264 #define QM_REG_PQTX2PF_51_RT_OFFSET 29955
265 #define QM_REG_PQTX2PF_52_RT_OFFSET 29956
266 #define QM_REG_PQTX2PF_53_RT_OFFSET 29957
267 #define QM_REG_PQTX2PF_54_RT_OFFSET 29958
268 #define QM_REG_PQTX2PF_55_RT_OFFSET 29959
269 #define QM_REG_PQTX2PF_56_RT_OFFSET 29960
270 #define QM_REG_PQTX2PF_57_RT_OFFSET 29961
271 #define QM_REG_PQTX2PF_58_RT_OFFSET 29962
272 #define QM_REG_PQTX2PF_59_RT_OFFSET 29963
273 #define QM_REG_PQTX2PF_60_RT_OFFSET 29964
274 #define QM_REG_PQTX2PF_61_RT_OFFSET 29965
275 #define QM_REG_PQTX2PF_62_RT_OFFSET 29966
276 #define QM_REG_PQTX2PF_63_RT_OFFSET 29967
277 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29968
278 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29969
279 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29970
280 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29971
281 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29972
282 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29973
283 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29974
284 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29975
285 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29976
286 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29977
287 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29978
288 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29979
289 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29980
290 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29981
291 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29982
292 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29983
293 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29984
294 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29985
295 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29986
296 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29987
297 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29988
298 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29989
299 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29990
300 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29991
301 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29992
302 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29993
303 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29994
304 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29995
305 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29996
306 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
307 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30252
308 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
309 #define QM_REG_RLGLBLCRD_RT_OFFSET 30508
310 #define QM_REG_RLGLBLCRD_RT_SIZE 256
311 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30764
312 #define QM_REG_RLPFPERIOD_RT_OFFSET 30765
313 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30766
314 #define QM_REG_RLPFINCVAL_RT_OFFSET 30767
315 #define QM_REG_RLPFINCVAL_RT_SIZE 16
316 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30783
317 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
318 #define QM_REG_RLPFCRD_RT_OFFSET 30799
319 #define QM_REG_RLPFCRD_RT_SIZE 16
320 #define QM_REG_RLPFENABLE_RT_OFFSET 30815
321 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30816
322 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30817
323 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
324 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30833
325 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
326 #define QM_REG_WFQPFCRD_RT_OFFSET 30849
327 #define QM_REG_WFQPFCRD_RT_SIZE 160
328 #define QM_REG_WFQPFENABLE_RT_OFFSET 31009
329 #define QM_REG_WFQVPENABLE_RT_OFFSET 31010
330 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31011
331 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
332 #define QM_REG_TXPQMAP_RT_OFFSET 31523
333 #define QM_REG_TXPQMAP_RT_SIZE 512
334 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32035
335 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
336 #define QM_REG_WFQVPCRD_RT_OFFSET 32547
337 #define QM_REG_WFQVPCRD_RT_SIZE 512
338 #define QM_REG_WFQVPMAP_RT_OFFSET 33059
339 #define QM_REG_WFQVPMAP_RT_SIZE 512
340 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33571
341 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
342 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33731
343 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33732
344 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33733
345 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33734
346 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33735
347 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33736
348 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33737
349 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33738
350 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
351 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33742
352 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
353 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33746
354 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
355 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33750
356 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33751
357 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
358 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33783
359 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
360 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33799
361 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
362 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33815
363 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
364 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33831
365 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
366 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33847
367 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33848
368 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33849
369 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33850
370 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33851
371 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33852
372 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33853
373 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33854
374 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33855
375 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33856
376 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33857
377 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33858
378 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33859
379 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33860
380 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33861
381 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33862
382 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33863
383 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33864
384 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33865
385 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33866
386 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33867
387 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33868
388 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33869
389 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33870
390 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33871
391 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33872
392 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33873
393 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33874
394 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33875
395 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33876
396 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33877
397 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33878
398 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33879
399 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33880
400 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33881
401 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33882
402 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33883
403 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33884
404 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33885
405 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33886
406 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33887
407 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33888
408 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33889
409 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33890
410 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33891
411 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33892
412 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33893
413 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33894
414 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33895
415 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33896
416 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33897
417 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33898
418 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33899
419 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33900
420 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33901
421 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33902
422 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33903
423 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33904
424 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33905
425 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33906
426 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33907
427 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33908
428 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33909
429 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33910
430 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33911
431 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33912
432 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33913
433 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33914
434 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33915
435 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33916
436 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33917
437 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33918
438 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33919
439 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33920
440 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33921
441 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33922
442 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33923
444 #define RUNTIME_ARRAY_SIZE 33924
446 #endif /* __RT_DEFS_H__ */