2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 /* Runtime array offsets */
13 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
14 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
15 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
16 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
17 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
18 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
19 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
20 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
21 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
22 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
23 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
24 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
25 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
26 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
27 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
28 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
29 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
30 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
31 #define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18
32 #define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19
33 #define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20
34 #define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21
35 #define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22
36 #define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23
37 #define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24
38 #define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25
39 #define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26
40 #define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27
41 #define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28
42 #define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29
43 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30
44 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31
45 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32
46 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33
47 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34
48 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35
49 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36
50 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37
51 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38
52 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39
53 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40
54 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41
55 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42
56 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43
57 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44
58 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45
59 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024
60 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069
61 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024
62 #define CAU_REG_PI_MEMORY_RT_OFFSET 2093
63 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
64 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509
65 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510
66 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511
67 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512
68 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513
69 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6514
70 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515
71 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516
72 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517
73 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518
74 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519
75 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520
76 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521
77 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522
78 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523
79 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524
80 #define SRC_REG_FIRSTFREE_RT_OFFSET 6525
81 #define SRC_REG_FIRSTFREE_RT_SIZE 2
82 #define SRC_REG_LASTFREE_RT_OFFSET 6527
83 #define SRC_REG_LASTFREE_RT_SIZE 2
84 #define SRC_REG_COUNTFREE_RT_OFFSET 6529
85 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530
86 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531
87 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532
88 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533
89 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534
90 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535
91 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536
92 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537
93 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538
94 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539
95 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540
96 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541
97 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542
98 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543
99 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544
100 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545
101 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546
102 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547
103 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548
104 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549
105 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550
106 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551
107 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552
108 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553
109 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554
110 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555
111 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556
112 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557
113 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558
114 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559
115 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560
116 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561
117 #define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562
118 #define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563
119 #define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564
120 #define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565
121 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566
122 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414
123 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980
124 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981
125 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982
126 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983
127 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984
128 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985
129 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986
130 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987
131 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988
132 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989
133 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990
134 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991
135 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992
136 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
137 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408
138 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
139 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016
140 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017
141 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018
142 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019
143 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020
144 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021
145 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022
146 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023
147 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024
148 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025
149 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026
150 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027
151 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028
152 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029
153 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030
154 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031
155 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032
156 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033
157 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034
158 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035
159 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036
160 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037
161 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038
162 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039
163 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040
164 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041
165 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042
166 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043
167 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044
168 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045
169 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046
170 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047
171 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048
172 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049
173 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050
174 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051
175 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052
176 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053
177 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054
178 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055
179 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056
180 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057
181 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058
182 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059
183 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060
184 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061
185 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062
186 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063
187 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064
188 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065
189 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066
190 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067
191 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068
192 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069
193 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070
194 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071
195 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072
196 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073
197 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074
198 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075
199 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076
200 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077
201 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078
202 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079
203 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080
204 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081
205 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082
206 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083
207 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
208 #define QM_REG_PTRTBLOTHER_RT_OFFSET 34211
209 #define QM_REG_PTRTBLOTHER_RT_SIZE 256
210 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467
211 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468
212 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469
213 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470
214 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471
215 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472
216 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473
217 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474
218 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475
219 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476
220 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477
221 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478
222 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479
223 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480
224 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481
225 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482
226 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483
227 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484
228 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485
229 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486
230 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487
231 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488
232 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489
233 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490
234 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491
235 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492
236 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493
237 #define QM_REG_PQTX2PF_0_RT_OFFSET 34494
238 #define QM_REG_PQTX2PF_1_RT_OFFSET 34495
239 #define QM_REG_PQTX2PF_2_RT_OFFSET 34496
240 #define QM_REG_PQTX2PF_3_RT_OFFSET 34497
241 #define QM_REG_PQTX2PF_4_RT_OFFSET 34498
242 #define QM_REG_PQTX2PF_5_RT_OFFSET 34499
243 #define QM_REG_PQTX2PF_6_RT_OFFSET 34500
244 #define QM_REG_PQTX2PF_7_RT_OFFSET 34501
245 #define QM_REG_PQTX2PF_8_RT_OFFSET 34502
246 #define QM_REG_PQTX2PF_9_RT_OFFSET 34503
247 #define QM_REG_PQTX2PF_10_RT_OFFSET 34504
248 #define QM_REG_PQTX2PF_11_RT_OFFSET 34505
249 #define QM_REG_PQTX2PF_12_RT_OFFSET 34506
250 #define QM_REG_PQTX2PF_13_RT_OFFSET 34507
251 #define QM_REG_PQTX2PF_14_RT_OFFSET 34508
252 #define QM_REG_PQTX2PF_15_RT_OFFSET 34509
253 #define QM_REG_PQTX2PF_16_RT_OFFSET 34510
254 #define QM_REG_PQTX2PF_17_RT_OFFSET 34511
255 #define QM_REG_PQTX2PF_18_RT_OFFSET 34512
256 #define QM_REG_PQTX2PF_19_RT_OFFSET 34513
257 #define QM_REG_PQTX2PF_20_RT_OFFSET 34514
258 #define QM_REG_PQTX2PF_21_RT_OFFSET 34515
259 #define QM_REG_PQTX2PF_22_RT_OFFSET 34516
260 #define QM_REG_PQTX2PF_23_RT_OFFSET 34517
261 #define QM_REG_PQTX2PF_24_RT_OFFSET 34518
262 #define QM_REG_PQTX2PF_25_RT_OFFSET 34519
263 #define QM_REG_PQTX2PF_26_RT_OFFSET 34520
264 #define QM_REG_PQTX2PF_27_RT_OFFSET 34521
265 #define QM_REG_PQTX2PF_28_RT_OFFSET 34522
266 #define QM_REG_PQTX2PF_29_RT_OFFSET 34523
267 #define QM_REG_PQTX2PF_30_RT_OFFSET 34524
268 #define QM_REG_PQTX2PF_31_RT_OFFSET 34525
269 #define QM_REG_PQTX2PF_32_RT_OFFSET 34526
270 #define QM_REG_PQTX2PF_33_RT_OFFSET 34527
271 #define QM_REG_PQTX2PF_34_RT_OFFSET 34528
272 #define QM_REG_PQTX2PF_35_RT_OFFSET 34529
273 #define QM_REG_PQTX2PF_36_RT_OFFSET 34530
274 #define QM_REG_PQTX2PF_37_RT_OFFSET 34531
275 #define QM_REG_PQTX2PF_38_RT_OFFSET 34532
276 #define QM_REG_PQTX2PF_39_RT_OFFSET 34533
277 #define QM_REG_PQTX2PF_40_RT_OFFSET 34534
278 #define QM_REG_PQTX2PF_41_RT_OFFSET 34535
279 #define QM_REG_PQTX2PF_42_RT_OFFSET 34536
280 #define QM_REG_PQTX2PF_43_RT_OFFSET 34537
281 #define QM_REG_PQTX2PF_44_RT_OFFSET 34538
282 #define QM_REG_PQTX2PF_45_RT_OFFSET 34539
283 #define QM_REG_PQTX2PF_46_RT_OFFSET 34540
284 #define QM_REG_PQTX2PF_47_RT_OFFSET 34541
285 #define QM_REG_PQTX2PF_48_RT_OFFSET 34542
286 #define QM_REG_PQTX2PF_49_RT_OFFSET 34543
287 #define QM_REG_PQTX2PF_50_RT_OFFSET 34544
288 #define QM_REG_PQTX2PF_51_RT_OFFSET 34545
289 #define QM_REG_PQTX2PF_52_RT_OFFSET 34546
290 #define QM_REG_PQTX2PF_53_RT_OFFSET 34547
291 #define QM_REG_PQTX2PF_54_RT_OFFSET 34548
292 #define QM_REG_PQTX2PF_55_RT_OFFSET 34549
293 #define QM_REG_PQTX2PF_56_RT_OFFSET 34550
294 #define QM_REG_PQTX2PF_57_RT_OFFSET 34551
295 #define QM_REG_PQTX2PF_58_RT_OFFSET 34552
296 #define QM_REG_PQTX2PF_59_RT_OFFSET 34553
297 #define QM_REG_PQTX2PF_60_RT_OFFSET 34554
298 #define QM_REG_PQTX2PF_61_RT_OFFSET 34555
299 #define QM_REG_PQTX2PF_62_RT_OFFSET 34556
300 #define QM_REG_PQTX2PF_63_RT_OFFSET 34557
301 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558
302 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559
303 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560
304 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561
305 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562
306 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563
307 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564
308 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565
309 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566
310 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567
311 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568
312 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569
313 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570
314 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571
315 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572
316 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573
317 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574
318 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575
319 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576
320 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577
321 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578
322 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579
323 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580
324 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581
325 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582
326 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583
327 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584
328 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585
329 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586
330 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
331 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842
332 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
333 #define QM_REG_RLGLBLCRD_RT_OFFSET 35098
334 #define QM_REG_RLGLBLCRD_RT_SIZE 256
335 #define QM_REG_RLGLBLENABLE_RT_OFFSET 35354
336 #define QM_REG_RLPFPERIOD_RT_OFFSET 35355
337 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356
338 #define QM_REG_RLPFINCVAL_RT_OFFSET 35357
339 #define QM_REG_RLPFINCVAL_RT_SIZE 16
340 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373
341 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
342 #define QM_REG_RLPFCRD_RT_OFFSET 35389
343 #define QM_REG_RLPFCRD_RT_SIZE 16
344 #define QM_REG_RLPFENABLE_RT_OFFSET 35405
345 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406
346 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407
347 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
348 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423
349 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
350 #define QM_REG_WFQPFCRD_RT_OFFSET 35439
351 #define QM_REG_WFQPFCRD_RT_SIZE 256
352 #define QM_REG_WFQPFENABLE_RT_OFFSET 35695
353 #define QM_REG_WFQVPENABLE_RT_OFFSET 35696
354 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697
355 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
356 #define QM_REG_TXPQMAP_RT_OFFSET 36209
357 #define QM_REG_TXPQMAP_RT_SIZE 512
358 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721
359 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
360 #define QM_REG_WFQVPCRD_RT_OFFSET 37233
361 #define QM_REG_WFQVPCRD_RT_SIZE 512
362 #define QM_REG_WFQVPMAP_RT_OFFSET 37745
363 #define QM_REG_WFQVPMAP_RT_SIZE 512
364 #define QM_REG_PTRTBLTX_RT_OFFSET 38257
365 #define QM_REG_PTRTBLTX_RT_SIZE 1024
366 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281
367 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
368 #define QM_REG_VOQCRDLINE_RT_OFFSET 39601
369 #define QM_REG_VOQCRDLINE_RT_SIZE 36
370 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637
371 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36
372 #define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673
373 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674
374 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675
375 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676
376 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677
377 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678
378 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679
379 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680
380 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681
381 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
382 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685
383 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
384 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689
385 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
386 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721
387 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
388 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737
389 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
390 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753
391 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
392 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769
393 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
394 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785
395 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786
396 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787
397 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
398 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795
399 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024
400 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819
401 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512
402 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331
403 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512
404 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843
405 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512
406 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355
407 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512
408 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867
409 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32
410 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899
411 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900
412 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901
413 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902
414 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903
415 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904
416 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905
417 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906
418 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907
419 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908
420 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909
421 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910
422 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911
423 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912
424 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913
425 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914
426 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915
427 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916
428 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917
429 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918
430 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919
431 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920
432 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921
433 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922
434 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923
435 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924
436 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925
437 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926
438 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927
439 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928
440 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929
441 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930
442 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931
443 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932
444 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933
445 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934
446 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935
447 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936
448 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937
449 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938
450 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939
451 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940
452 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941
453 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942
454 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943
455 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944
456 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945
457 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946
458 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947
459 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948
460 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949
461 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950
462 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951
463 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952
464 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953
465 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954
466 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955
467 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956
468 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957
469 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958
470 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959
471 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960
472 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961
473 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962
474 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963
475 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964
476 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965
477 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966
478 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967
479 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968
480 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969
481 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970
482 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971
483 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972
484 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973
485 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974
486 #define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975
487 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976
488 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977
489 #define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978
490 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979
491 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980
492 #define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981
493 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982
494 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983
495 #define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984
496 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985
497 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986
498 #define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987
499 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988
500 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989
501 #define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990
502 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991
503 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992
504 #define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993
505 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994
506 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995
507 #define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996
508 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997
509 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998
510 #define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999
511 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000
512 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001
513 #define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002
514 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003
515 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004
516 #define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005
517 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006
518 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007
519 #define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008
520 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009
521 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010
522 #define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011
523 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012
524 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013
525 #define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014
526 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015
527 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016
528 #define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017
529 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018
530 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019
531 #define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020
532 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021
533 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022
535 #define RUNTIME_ARRAY_SIZE 43023
538 #define DMAE_READY_CB 0
540 #endif /* __RT_DEFS_H__ */