2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 /* Runtime array offsets */
13 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
14 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
15 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
16 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
17 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
18 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
19 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
20 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
21 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
22 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
23 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
24 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
25 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
26 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
27 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
28 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
29 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
30 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
31 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
32 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
33 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
34 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
35 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
36 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
37 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
38 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
39 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
40 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
41 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
42 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
43 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
44 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
45 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
46 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
47 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
48 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
49 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
50 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
51 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
52 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
53 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
54 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
55 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
56 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
57 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
58 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
59 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
60 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
61 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
62 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
63 #define SRC_REG_FIRSTFREE_RT_SIZE 2
64 #define SRC_REG_LASTFREE_RT_OFFSET 6667
65 #define SRC_REG_LASTFREE_RT_SIZE 2
66 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
67 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
68 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
69 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
70 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
71 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
72 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
73 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
74 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
75 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
76 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
77 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
78 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
79 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
80 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
81 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
82 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
83 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
84 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
85 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
86 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
87 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
88 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
89 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
90 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
91 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
92 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
93 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
94 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
95 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
96 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
97 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700
98 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701
99 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702
100 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
101 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702
102 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703
103 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704
104 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
105 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
106 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
107 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
108 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
109 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
110 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
111 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
112 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
113 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
114 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
115 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
116 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
117 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738
118 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739
119 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740
120 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741
121 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742
122 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743
123 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744
124 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745
125 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746
126 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747
127 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748
128 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749
129 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750
130 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751
131 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752
132 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753
133 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754
134 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755
135 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756
136 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757
137 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758
138 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759
139 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760
140 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761
141 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762
142 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763
143 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764
144 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765
145 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766
146 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767
147 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768
148 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769
149 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770
150 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771
151 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772
152 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773
153 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774
154 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775
155 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776
156 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777
157 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778
158 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779
159 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780
160 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781
161 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782
162 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783
163 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784
164 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785
165 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786
166 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787
167 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788
168 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789
169 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790
170 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791
171 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792
172 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793
173 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794
174 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795
175 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796
176 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797
177 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798
178 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799
179 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800
180 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801
181 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802
182 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803
183 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804
184 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805
185 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
186 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933
187 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934
188 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935
189 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936
190 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937
191 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938
192 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939
193 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940
194 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941
195 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942
196 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943
197 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944
198 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945
199 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946
200 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947
201 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948
202 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949
203 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950
204 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951
205 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952
206 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953
207 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954
208 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955
209 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956
210 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957
211 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958
212 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959
213 #define QM_REG_PQTX2PF_0_RT_OFFSET 29960
214 #define QM_REG_PQTX2PF_1_RT_OFFSET 29961
215 #define QM_REG_PQTX2PF_2_RT_OFFSET 29962
216 #define QM_REG_PQTX2PF_3_RT_OFFSET 29963
217 #define QM_REG_PQTX2PF_4_RT_OFFSET 29964
218 #define QM_REG_PQTX2PF_5_RT_OFFSET 29965
219 #define QM_REG_PQTX2PF_6_RT_OFFSET 29966
220 #define QM_REG_PQTX2PF_7_RT_OFFSET 29967
221 #define QM_REG_PQTX2PF_8_RT_OFFSET 29968
222 #define QM_REG_PQTX2PF_9_RT_OFFSET 29969
223 #define QM_REG_PQTX2PF_10_RT_OFFSET 29970
224 #define QM_REG_PQTX2PF_11_RT_OFFSET 29971
225 #define QM_REG_PQTX2PF_12_RT_OFFSET 29972
226 #define QM_REG_PQTX2PF_13_RT_OFFSET 29973
227 #define QM_REG_PQTX2PF_14_RT_OFFSET 29974
228 #define QM_REG_PQTX2PF_15_RT_OFFSET 29975
229 #define QM_REG_PQTX2PF_16_RT_OFFSET 29976
230 #define QM_REG_PQTX2PF_17_RT_OFFSET 29977
231 #define QM_REG_PQTX2PF_18_RT_OFFSET 29978
232 #define QM_REG_PQTX2PF_19_RT_OFFSET 29979
233 #define QM_REG_PQTX2PF_20_RT_OFFSET 29980
234 #define QM_REG_PQTX2PF_21_RT_OFFSET 29981
235 #define QM_REG_PQTX2PF_22_RT_OFFSET 29982
236 #define QM_REG_PQTX2PF_23_RT_OFFSET 29983
237 #define QM_REG_PQTX2PF_24_RT_OFFSET 29984
238 #define QM_REG_PQTX2PF_25_RT_OFFSET 29985
239 #define QM_REG_PQTX2PF_26_RT_OFFSET 29986
240 #define QM_REG_PQTX2PF_27_RT_OFFSET 29987
241 #define QM_REG_PQTX2PF_28_RT_OFFSET 29988
242 #define QM_REG_PQTX2PF_29_RT_OFFSET 29989
243 #define QM_REG_PQTX2PF_30_RT_OFFSET 29990
244 #define QM_REG_PQTX2PF_31_RT_OFFSET 29991
245 #define QM_REG_PQTX2PF_32_RT_OFFSET 29992
246 #define QM_REG_PQTX2PF_33_RT_OFFSET 29993
247 #define QM_REG_PQTX2PF_34_RT_OFFSET 29994
248 #define QM_REG_PQTX2PF_35_RT_OFFSET 29995
249 #define QM_REG_PQTX2PF_36_RT_OFFSET 29996
250 #define QM_REG_PQTX2PF_37_RT_OFFSET 29997
251 #define QM_REG_PQTX2PF_38_RT_OFFSET 29998
252 #define QM_REG_PQTX2PF_39_RT_OFFSET 29999
253 #define QM_REG_PQTX2PF_40_RT_OFFSET 30000
254 #define QM_REG_PQTX2PF_41_RT_OFFSET 30001
255 #define QM_REG_PQTX2PF_42_RT_OFFSET 30002
256 #define QM_REG_PQTX2PF_43_RT_OFFSET 30003
257 #define QM_REG_PQTX2PF_44_RT_OFFSET 30004
258 #define QM_REG_PQTX2PF_45_RT_OFFSET 30005
259 #define QM_REG_PQTX2PF_46_RT_OFFSET 30006
260 #define QM_REG_PQTX2PF_47_RT_OFFSET 30007
261 #define QM_REG_PQTX2PF_48_RT_OFFSET 30008
262 #define QM_REG_PQTX2PF_49_RT_OFFSET 30009
263 #define QM_REG_PQTX2PF_50_RT_OFFSET 30010
264 #define QM_REG_PQTX2PF_51_RT_OFFSET 30011
265 #define QM_REG_PQTX2PF_52_RT_OFFSET 30012
266 #define QM_REG_PQTX2PF_53_RT_OFFSET 30013
267 #define QM_REG_PQTX2PF_54_RT_OFFSET 30014
268 #define QM_REG_PQTX2PF_55_RT_OFFSET 30015
269 #define QM_REG_PQTX2PF_56_RT_OFFSET 30016
270 #define QM_REG_PQTX2PF_57_RT_OFFSET 30017
271 #define QM_REG_PQTX2PF_58_RT_OFFSET 30018
272 #define QM_REG_PQTX2PF_59_RT_OFFSET 30019
273 #define QM_REG_PQTX2PF_60_RT_OFFSET 30020
274 #define QM_REG_PQTX2PF_61_RT_OFFSET 30021
275 #define QM_REG_PQTX2PF_62_RT_OFFSET 30022
276 #define QM_REG_PQTX2PF_63_RT_OFFSET 30023
277 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024
278 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025
279 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026
280 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027
281 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028
282 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029
283 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030
284 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031
285 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032
286 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033
287 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034
288 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035
289 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036
290 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037
291 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038
292 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039
293 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040
294 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041
295 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042
296 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043
297 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044
298 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045
299 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046
300 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047
301 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048
302 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049
303 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050
304 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051
305 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052
306 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
307 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308
308 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
309 #define QM_REG_RLGLBLCRD_RT_OFFSET 30564
310 #define QM_REG_RLGLBLCRD_RT_SIZE 256
311 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30820
312 #define QM_REG_RLPFPERIOD_RT_OFFSET 30821
313 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822
314 #define QM_REG_RLPFINCVAL_RT_OFFSET 30823
315 #define QM_REG_RLPFINCVAL_RT_SIZE 16
316 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839
317 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
318 #define QM_REG_RLPFCRD_RT_OFFSET 30855
319 #define QM_REG_RLPFCRD_RT_SIZE 16
320 #define QM_REG_RLPFENABLE_RT_OFFSET 30871
321 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872
322 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873
323 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
324 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889
325 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
326 #define QM_REG_WFQPFCRD_RT_OFFSET 30905
327 #define QM_REG_WFQPFCRD_RT_SIZE 256
328 #define QM_REG_WFQPFENABLE_RT_OFFSET 31161
329 #define QM_REG_WFQVPENABLE_RT_OFFSET 31162
330 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163
331 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
332 #define QM_REG_TXPQMAP_RT_OFFSET 31675
333 #define QM_REG_TXPQMAP_RT_SIZE 512
334 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187
335 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
336 #define QM_REG_WFQVPCRD_RT_OFFSET 32699
337 #define QM_REG_WFQVPCRD_RT_SIZE 512
338 #define QM_REG_WFQVPMAP_RT_OFFSET 33211
339 #define QM_REG_WFQVPMAP_RT_SIZE 512
340 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723
341 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
342 #define QM_REG_VOQCRDLINE_RT_OFFSET 34043
343 #define QM_REG_VOQCRDLINE_RT_SIZE 36
344 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079
345 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36
346 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115
347 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116
348 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117
349 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118
350 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119
351 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120
352 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121
353 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122
354 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
355 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126
356 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
357 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130
358 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
359 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134
360 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135
361 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
362 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167
363 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
364 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183
365 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
366 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199
367 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
368 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215
369 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
370 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231
371 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232
372 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233
373 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234
374 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235
375 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236
376 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237
377 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238
378 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239
379 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240
380 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241
381 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242
382 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243
383 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244
384 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245
385 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246
386 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247
387 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248
388 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249
389 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250
390 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251
391 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252
392 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253
393 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254
394 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255
395 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256
396 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257
397 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258
398 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259
399 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260
400 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261
401 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262
402 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263
403 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264
404 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265
405 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266
406 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267
407 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268
408 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269
409 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270
410 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271
411 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272
412 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273
413 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274
414 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275
415 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276
416 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277
417 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278
418 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279
419 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280
420 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281
421 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282
422 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283
423 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284
424 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285
425 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286
426 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287
427 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288
428 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289
429 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290
430 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291
431 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292
432 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293
433 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294
434 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295
435 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296
436 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297
437 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298
438 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299
439 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300
440 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301
441 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302
442 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303
443 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304
444 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305
445 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306
446 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307
447 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308
449 #define RUNTIME_ARRAY_SIZE 34309
451 #endif /* __RT_DEFS_H__ */