2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_chain.h"
14 #include "ecore_spq.h"
15 #include "ecore_init_fw_funcs.h"
16 #include "ecore_cxt.h"
17 #include "ecore_sp_commands.h"
18 #include "ecore_gtt_reg_addr.h"
19 #include "ecore_iro.h"
21 #include "ecore_int.h"
23 #include "ecore_dcbx.h"
24 #include "ecore_sriov.h"
27 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
28 struct ecore_spq_entry **pp_ent,
31 struct ecore_sp_init_data *p_data)
33 u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
34 struct ecore_spq_entry *p_ent = OSAL_NULL;
35 enum _ecore_status_t rc;
40 /* Get an SPQ entry */
41 rc = ecore_spq_get_entry(p_hwfn, pp_ent);
42 if (rc != ECORE_SUCCESS)
45 /* Fill the SPQ entry */
47 p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid);
48 p_ent->elem.hdr.cmd_id = cmd;
49 p_ent->elem.hdr.protocol_id = protocol;
50 p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL;
51 p_ent->comp_mode = p_data->comp_mode;
52 p_ent->comp_done.done = 0;
54 switch (p_ent->comp_mode) {
55 case ECORE_SPQ_MODE_EBLOCK:
56 p_ent->comp_cb.cookie = &p_ent->comp_done;
59 case ECORE_SPQ_MODE_BLOCK:
60 if (!p_data->p_comp_data)
63 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
66 case ECORE_SPQ_MODE_CB:
67 if (!p_data->p_comp_data)
68 p_ent->comp_cb.function = OSAL_NULL;
70 p_ent->comp_cb = *p_data->p_comp_data;
74 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n",
79 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
80 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
81 opaque_cid, cmd, protocol,
82 (unsigned long)&p_ent->ramrod,
83 D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK,
84 ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
87 OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
92 static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type)
95 case ECORE_TUNN_CLSS_MAC_VLAN:
96 return TUNNEL_CLSS_MAC_VLAN;
97 case ECORE_TUNN_CLSS_MAC_VNI:
98 return TUNNEL_CLSS_MAC_VNI;
99 case ECORE_TUNN_CLSS_INNER_MAC_VLAN:
100 return TUNNEL_CLSS_INNER_MAC_VLAN;
101 case ECORE_TUNN_CLSS_INNER_MAC_VNI:
102 return TUNNEL_CLSS_INNER_MAC_VNI;
103 case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
104 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
106 return TUNNEL_CLSS_MAC_VLAN;
111 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun,
112 struct ecore_tunnel_info *p_src,
115 if (p_src->vxlan.b_update_mode || b_pf_start)
116 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
118 if (p_src->l2_gre.b_update_mode || b_pf_start)
119 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
121 if (p_src->ip_gre.b_update_mode || b_pf_start)
122 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
124 if (p_src->l2_geneve.b_update_mode || b_pf_start)
125 p_tun->l2_geneve.b_mode_enabled =
126 p_src->l2_geneve.b_mode_enabled;
128 if (p_src->ip_geneve.b_update_mode || b_pf_start)
129 p_tun->ip_geneve.b_mode_enabled =
130 p_src->ip_geneve.b_mode_enabled;
133 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun,
134 struct ecore_tunnel_info *p_src)
136 enum tunnel_clss type;
138 p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
139 p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
141 /* @DPDK - typecast tunnul class */
142 type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
143 p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type;
144 type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
145 p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type;
146 type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
147 p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type;
148 type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
149 p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type;
150 type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
151 p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type;
154 static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun,
155 struct ecore_tunnel_info *p_src)
157 p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
158 p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
160 if (p_src->geneve_port.b_update_port)
161 p_tun->geneve_port.port = p_src->geneve_port.port;
163 if (p_src->vxlan_port.b_update_port)
164 p_tun->vxlan_port.port = p_src->vxlan_port.port;
168 __ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
169 struct ecore_tunn_update_type *tun_type)
171 *p_tunn_cls = tun_type->tun_cls;
175 ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
176 struct ecore_tunn_update_type *tun_type,
177 u8 *p_update_port, __le16 *p_port,
178 struct ecore_tunn_update_udp_port *p_udp_port)
180 __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
181 if (p_udp_port->b_update_port) {
183 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port);
188 ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn,
189 struct ecore_tunnel_info *p_src,
190 struct pf_update_tunnel_config *p_tunn_cfg)
192 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
194 ecore_set_pf_update_tunn_mode(p_tun, p_src, false);
195 ecore_set_tunn_cls_info(p_tun, p_src);
196 ecore_set_tunn_ports(p_tun, p_src);
198 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
200 &p_tunn_cfg->set_vxlan_udp_port_flg,
201 &p_tunn_cfg->vxlan_udp_port,
204 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
206 &p_tunn_cfg->set_geneve_udp_port_flg,
207 &p_tunn_cfg->geneve_udp_port,
208 &p_tun->geneve_port);
210 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
213 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
216 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
219 p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
222 static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,
223 struct ecore_ptt *p_ptt,
224 struct ecore_tunnel_info *p_tun)
226 ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
227 p_tun->ip_gre.b_mode_enabled);
228 ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
230 ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
231 p_tun->ip_geneve.b_mode_enabled);
234 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn,
235 struct ecore_ptt *p_ptt,
236 struct ecore_tunnel_info *p_tunn)
238 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
239 DP_NOTICE(p_hwfn, true,
240 "A0 chip: tunnel hw config is not supported\n");
244 if (p_tunn->vxlan_port.b_update_port)
245 ecore_set_vxlan_dest_port(p_hwfn, p_ptt,
246 p_tunn->vxlan_port.port);
248 if (p_tunn->geneve_port.b_update_port)
249 ecore_set_geneve_dest_port(p_hwfn, p_ptt,
250 p_tunn->geneve_port.port);
252 ecore_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
256 ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,
257 struct ecore_tunnel_info *p_src,
258 struct pf_start_tunnel_config *p_tunn_cfg)
260 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
262 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
263 DP_NOTICE(p_hwfn, true,
264 "A0 chip: tunnel pf start config is not supported\n");
271 ecore_set_pf_update_tunn_mode(p_tun, p_src, true);
272 ecore_set_tunn_cls_info(p_tun, p_src);
273 ecore_set_tunn_ports(p_tun, p_src);
275 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
277 &p_tunn_cfg->set_vxlan_udp_port_flg,
278 &p_tunn_cfg->vxlan_udp_port,
281 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
283 &p_tunn_cfg->set_geneve_udp_port_flg,
284 &p_tunn_cfg->geneve_udp_port,
285 &p_tun->geneve_port);
287 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
290 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
293 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
297 #define ETH_P_8021Q 0x8100
298 #define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN */
300 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
301 struct ecore_ptt *p_ptt,
302 struct ecore_tunnel_info *p_tunn,
303 bool allow_npar_tx_switch)
305 struct pf_start_ramrod_data *p_ramrod = OSAL_NULL;
306 u16 sb = ecore_int_get_sp_sb_id(p_hwfn);
307 u8 sb_index = p_hwfn->p_eq->eq_sb_index;
308 struct ecore_spq_entry *p_ent = OSAL_NULL;
309 struct ecore_sp_init_data init_data;
310 enum _ecore_status_t rc = ECORE_NOTIMPL;
314 /* update initial eq producer */
315 ecore_eq_prod_update(p_hwfn,
316 ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain));
318 /* Initialize the SPQ entry for the ramrod */
319 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
320 init_data.cid = ecore_spq_get_cid(p_hwfn);
321 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
322 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
324 rc = ecore_sp_init_request(p_hwfn, &p_ent,
325 COMMON_RAMROD_PF_START,
326 PROTOCOLID_COMMON, &init_data);
327 if (rc != ECORE_SUCCESS)
330 /* Fill the ramrod data */
331 p_ramrod = &p_ent->ramrod.pf_start;
332 p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
333 p_ramrod->event_ring_sb_index = sb_index;
334 p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
336 /* For easier debugging */
337 p_ramrod->dont_log_ramrods = 0;
338 p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);
340 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
341 p_ramrod->mf_mode = MF_OVLAN;
343 p_ramrod->mf_mode = MF_NPAR;
345 p_ramrod->outer_tag_config.outer_tag.tci =
346 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
347 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {
348 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
349 } else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
350 &p_hwfn->p_dev->mf_bits)) {
351 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
352 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
355 p_ramrod->outer_tag_config.pri_map_valid = 1;
356 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
357 p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;
359 /* enable_stag_pri_change should be set if port is in BD mode or,
360 * UFP with Host Control mode or, UFP with DCB over base interface.
362 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
363 if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
364 (p_hwfn->p_dcbx_info->results.dcbx_enabled))
365 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
367 p_ramrod->outer_tag_config.enable_stag_pri_change = 0;
370 /* Place EQ address in RAMROD */
371 DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
372 p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
373 page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain);
374 p_ramrod->event_ring_num_pages = page_cnt;
375 DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
376 p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
378 ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
379 &p_ramrod->tunnel_config);
381 if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH,
382 &p_hwfn->p_dev->mf_bits))
383 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
385 switch (p_hwfn->hw_info.personality) {
387 p_ramrod->personality = PERSONALITY_ETH;
390 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n",
391 p_hwfn->hw_info.personality);
392 p_ramrod->personality = PERSONALITY_ETH;
395 if (p_hwfn->p_dev->p_iov_info) {
396 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
398 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
399 p_ramrod->num_vfs = (u8)p_iov->total_vfs;
401 /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
402 * version is available.
404 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
405 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
407 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
408 "Setting event_ring_sb [id %04x index %02x], outer_tag.tpid [%d], outer_tag.tci [%d]\n",
409 sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tpid,
410 p_ramrod->outer_tag_config.outer_tag.tci);
412 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
415 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt,
416 &p_hwfn->p_dev->tunnel);
421 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn)
423 struct ecore_spq_entry *p_ent = OSAL_NULL;
424 struct ecore_sp_init_data init_data;
425 enum _ecore_status_t rc = ECORE_NOTIMPL;
428 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
429 init_data.cid = ecore_spq_get_cid(p_hwfn);
430 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
431 init_data.comp_mode = ECORE_SPQ_MODE_CB;
433 rc = ecore_sp_init_request(p_hwfn, &p_ent,
434 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
436 if (rc != ECORE_SUCCESS)
439 ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
440 &p_ent->ramrod.pf_update);
442 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
445 enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn)
447 struct ecore_spq_entry *p_ent = OSAL_NULL;
448 struct ecore_sp_init_data init_data;
449 enum _ecore_status_t rc = ECORE_NOTIMPL;
452 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
453 init_data.cid = ecore_spq_get_cid(p_hwfn);
454 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
455 init_data.comp_mode = ECORE_SPQ_MODE_CB;
457 rc = ecore_sp_init_request(p_hwfn, &p_ent,
458 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
460 if (rc != ECORE_SUCCESS)
463 p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
464 if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
465 (p_hwfn->p_dcbx_info->results.dcbx_enabled))
466 p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
468 p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
470 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
474 /* QM rate limiter resolution is 1.6Mbps */
475 #define QM_RL_RESOLUTION(mb_val) ((mb_val) * 10 / 16)
477 /* FW uses 1/64k to express gd */
478 #define FW_GD_RESOLUTION(gd) (64 * 1024 / (gd))
480 u16 ecore_sp_rl_mb_to_qm(u32 mb_val)
482 return (u16)OSAL_MIN_T(u32, (u16)(~0U), QM_RL_RESOLUTION(mb_val));
485 u16 ecore_sp_rl_gd_denom(u32 gd)
487 return gd ? (u16)OSAL_MIN_T(u32, (u16)(~0U), FW_GD_RESOLUTION(gd)) : 0;
490 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
491 struct ecore_rl_update_params *params)
493 struct ecore_spq_entry *p_ent = OSAL_NULL;
494 enum _ecore_status_t rc = ECORE_NOTIMPL;
495 struct rl_update_ramrod_data *rl_update;
496 struct ecore_sp_init_data init_data;
499 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
500 init_data.cid = ecore_spq_get_cid(p_hwfn);
501 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
502 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
504 rc = ecore_sp_init_request(p_hwfn, &p_ent,
505 COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
507 if (rc != ECORE_SUCCESS)
510 rl_update = &p_ent->ramrod.rl_update;
512 rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
513 rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
514 rl_update->rl_init_flg = params->rl_init_flg;
515 rl_update->rl_start_flg = params->rl_start_flg;
516 rl_update->rl_stop_flg = params->rl_stop_flg;
517 rl_update->rl_id_first = params->rl_id_first;
518 rl_update->rl_id_last = params->rl_id_last;
519 rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
520 rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
521 rl_update->rl_max_rate =
522 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_max_rate));
524 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_ai));
525 rl_update->rl_r_hai =
526 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_hai));
528 OSAL_CPU_TO_LE16(ecore_sp_rl_gd_denom(params->dcqcn_gd));
529 rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
530 rl_update->dcqcn_timeuot_us =
531 OSAL_CPU_TO_LE32(params->dcqcn_timeuot_us);
532 rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
534 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
535 rl_update->qcn_update_param_flg,
536 rl_update->dcqcn_update_param_flg,
537 rl_update->rl_init_flg, rl_update->rl_start_flg,
538 rl_update->rl_stop_flg, rl_update->rl_id_first,
539 rl_update->rl_id_last, rl_update->rl_dc_qcn_flg,
540 rl_update->rl_bc_rate, rl_update->rl_max_rate,
541 rl_update->rl_r_ai, rl_update->rl_r_hai,
542 rl_update->dcqcn_g, rl_update->dcqcn_k_us,
543 rl_update->dcqcn_timeuot_us, rl_update->qcn_timeuot_us);
545 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
548 /* Set pf update ramrod command params */
550 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
551 struct ecore_ptt *p_ptt,
552 struct ecore_tunnel_info *p_tunn,
553 enum spq_mode comp_mode,
554 struct ecore_spq_comp_cb *p_comp_data)
556 struct ecore_spq_entry *p_ent = OSAL_NULL;
557 struct ecore_sp_init_data init_data;
558 enum _ecore_status_t rc = ECORE_NOTIMPL;
560 if (IS_VF(p_hwfn->p_dev))
561 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
563 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
564 DP_NOTICE(p_hwfn, true,
565 "A0 chip: tunnel pf update config is not supported\n");
573 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
574 init_data.cid = ecore_spq_get_cid(p_hwfn);
575 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
576 init_data.comp_mode = comp_mode;
577 init_data.p_comp_data = p_comp_data;
579 rc = ecore_sp_init_request(p_hwfn, &p_ent,
580 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
582 if (rc != ECORE_SUCCESS)
585 ecore_tunn_set_pf_update_params(p_hwfn, p_tunn,
586 &p_ent->ramrod.pf_update.tunnel_config);
588 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
589 if (rc != ECORE_SUCCESS)
592 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->p_dev->tunnel);
597 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn)
599 struct ecore_spq_entry *p_ent = OSAL_NULL;
600 struct ecore_sp_init_data init_data;
601 enum _ecore_status_t rc = ECORE_NOTIMPL;
604 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
605 init_data.cid = ecore_spq_get_cid(p_hwfn);
606 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
607 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
609 rc = ecore_sp_init_request(p_hwfn, &p_ent,
610 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
612 if (rc != ECORE_SUCCESS)
615 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
618 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
620 struct ecore_spq_entry *p_ent = OSAL_NULL;
621 struct ecore_sp_init_data init_data;
622 enum _ecore_status_t rc;
625 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
626 init_data.cid = ecore_spq_get_cid(p_hwfn);
627 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
628 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
630 rc = ecore_sp_init_request(p_hwfn, &p_ent,
631 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
633 if (rc != ECORE_SUCCESS)
636 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
639 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn)
641 struct ecore_spq_entry *p_ent = OSAL_NULL;
642 struct ecore_sp_init_data init_data;
643 enum _ecore_status_t rc = ECORE_NOTIMPL;
646 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
647 init_data.cid = ecore_spq_get_cid(p_hwfn);
648 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
649 init_data.comp_mode = ECORE_SPQ_MODE_CB;
651 rc = ecore_sp_init_request(p_hwfn, &p_ent,
652 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
654 if (rc != ECORE_SUCCESS)
657 p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
658 p_ent->ramrod.pf_update.mf_vlan =
659 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
661 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);