2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #define __ETH_COMMON__
11 /********************/
12 /* ETH FW CONSTANTS */
13 /********************/
14 #define ETH_CACHE_LINE_SIZE 64
15 #define ETH_RX_CQE_GAP 32
16 #define ETH_MAX_RAMROD_PER_CON 8
17 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096
18 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096
19 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
20 #define ETH_RX_NUM_NEXT_PAGE_BDS 2
22 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
23 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
24 #define ETH_TX_MAX_LSO_HDR_NBD 4
25 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3
26 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
27 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
28 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
29 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
30 #define ETH_TX_MAX_LSO_HDR_BYTES 510
31 #define ETH_TX_LSO_WINDOW_BDS_NUM 18
32 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700
33 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFFFF
35 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
37 #define ETH_RX_MAX_BUFF_PER_PKT 5
39 /* num of MAC/VLAN filters */
40 #define ETH_NUM_MAC_FILTERS 512
41 #define ETH_NUM_VLAN_FILTERS 512
43 /* approx. multicast constants */
44 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
45 #define ETH_MULTICAST_MAC_BINS 256
46 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
48 /* ethernet vport update constants */
49 #define ETH_FILTER_RULES_COUNT 10
50 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
51 #define ETH_RSS_KEY_SIZE_REGS 10
52 #define ETH_RSS_ENGINE_NUM_K2 207
53 #define ETH_RSS_ENGINE_NUM_BB 127
56 #define ETH_TPA_MAX_AGGS_NUM 64
57 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
58 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
59 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
62 * Interrupt coalescing TimeSet
64 struct coalescing_timeset {
66 u8 valid /* Only if this flag is set, timeset will take effect */;
70 * Destination port mode
73 DEST_PORT_PHY /* Send to physical port. */,
74 DEST_PORT_LOOPBACK /* Send to loopback port. */,
75 DEST_PORT_PHY_LOOPBACK /* Send to physical and loopback port. */,
76 DEST_PORT_DROP /* Drop the packet in PBF. */,
81 * Ethernet address type
91 struct eth_tx_1st_bd_flags {
93 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
94 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
95 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
96 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
97 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
98 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
99 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
100 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
101 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
102 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
103 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
104 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
105 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
106 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
107 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
108 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
112 * The parsing information data for the first tx bd of a given packet.
114 struct eth_tx_data_1st_bd {
115 __le16 vlan /* VLAN to insert to packet (if needed). */;
116 /* Number of BDs in packet. Should be at least 2 in non-LSO
117 * packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet.
120 struct eth_tx_1st_bd_flags bd_flags;
122 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1
123 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0
124 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
125 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
126 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF
127 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2
131 * The parsing information data for the second tx bd of a given packet.
133 struct eth_tx_data_2nd_bd {
136 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
137 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
138 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
139 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
140 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
141 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
142 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
143 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
144 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
145 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
146 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
147 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
148 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
149 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
150 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
151 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
152 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
153 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
154 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
155 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
157 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
158 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
159 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
160 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
164 * Firmware data for L2-EDPM packet.
166 struct eth_edpm_fw_data {
167 struct eth_tx_data_1st_bd data_1st_bd
168 /* Parsing information data from the 1st BD. */;
169 struct eth_tx_data_2nd_bd data_2nd_bd
170 /* Parsing information data from the 2nd BD. */;
177 struct eth_fast_path_cqe_fw_debug {
178 u8 reserved0 /* FW reserved. */;
179 u8 reserved1 /* FW reserved. */;
180 __le16 reserved2 /* FW reserved. */;
183 struct tunnel_parsing_flags {
185 #define TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
186 #define TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
187 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
188 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
189 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
190 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
191 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
192 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
193 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
194 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
195 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
196 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
200 * Regular ETH Rx FP CQE.
202 struct eth_fast_path_rx_reg_cqe {
203 u8 type /* CQE type */;
205 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
206 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
207 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
208 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
209 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
210 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
211 __le16 pkt_len /* Total packet length (from the parser) */;
212 struct parsing_and_err_flags pars_flags
213 /* Parsing and error flags from the parser */;
214 __le16 vlan_tag /* 802.1q VLAN tag */;
215 __le32 rss_hash /* RSS hash result */;
216 __le16 len_on_first_bd /* Number of bytes placed on first BD */;
217 u8 placement_offset /* Offset of placement from BD start */;
218 struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
220 u8 bd_num /* Number of BDs, used for packet */;
222 struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
225 #define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
226 #define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
227 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
228 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
229 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
230 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
234 * TPA-continue ETH Rx FP CQE.
236 struct eth_fast_path_rx_tpa_cont_cqe {
237 u8 type /* CQE type */;
238 u8 tpa_agg_index /* TPA aggregation index */;
239 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]
240 /* List of the segment sizes */;
242 u8 reserved1 /* FW reserved. */;
243 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* FW reserved. */;
247 * TPA-end ETH Rx FP CQE .
249 struct eth_fast_path_rx_tpa_end_cqe {
250 u8 type /* CQE type */;
251 u8 tpa_agg_index /* TPA aggregation index */;
252 __le16 total_packet_len /* Total aggregated packet length */;
253 u8 num_of_bds /* Total number of BDs comprising the packet */;
254 u8 end_reason /* Aggregation end reason. Use enum eth_tpa_end_reason */
256 __le16 num_of_coalesced_segs /* Number of coalesced TCP segments */;
257 __le32 ts_delta /* TCP timestamp delta */;
258 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]
259 /* List of the segment sizes */;
261 u8 reserved2 /* FW reserved. */;
262 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* FW reserved. */;
266 * TPA-start ETH Rx FP CQE.
268 struct eth_fast_path_rx_tpa_start_cqe {
269 u8 type /* CQE type */;
271 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
272 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
273 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
274 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
275 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
276 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
277 __le16 seg_len /* Segment length (packetLen from the parser) */;
278 struct parsing_and_err_flags pars_flags
279 /* Parsing and error flags from the parser */;
280 __le16 vlan_tag /* 802.1q VLAN tag */;
281 __le32 rss_hash /* RSS hash result */;
282 __le16 len_on_first_bd /* Number of bytes placed on first BD */;
283 u8 placement_offset /* Offset of placement from BD start */;
284 struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
286 u8 tpa_agg_index /* TPA aggregation index */;
287 u8 header_len /* Packet L2+L3+L4 header length */;
288 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]
289 /* Additional BDs length list. */;
290 struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
294 * The L4 pseudo checksum mode for Ethernet
296 enum eth_l4_pseudo_checksum_mode {
297 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH
298 /* Pseudo Header checksum on packet is calculated
299 * with the correct packet length field.
302 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH
303 /* Pseudo Hdr checksum on packet is calc with zero len field. */
305 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
309 struct regpair addr /* single continues buffer */;
313 * regular ETH Rx SP CQE
315 struct eth_slow_path_rx_cqe {
316 u8 type /* CQE type */;
323 #define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
324 #define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
325 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
326 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
327 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
328 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
332 * union for all ETH Rx CQE types
335 struct eth_fast_path_rx_reg_cqe fast_path_regular /* Regular FP CQE */;
336 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start
338 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont
339 /* TPA-continue CQE */;
340 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end /* TPA-end CQE */
342 struct eth_slow_path_rx_cqe slow_path /* SP CQE */;
348 enum eth_rx_cqe_type {
349 ETH_RX_CQE_TYPE_UNUSED,
350 ETH_RX_CQE_TYPE_REGULAR /* Regular FP ETH Rx CQE */,
351 ETH_RX_CQE_TYPE_SLOW_PATH /* Slow path ETH Rx CQE */,
352 ETH_RX_CQE_TYPE_TPA_START /* TPA start ETH Rx CQE */,
353 ETH_RX_CQE_TYPE_TPA_CONT /* TPA Continue ETH Rx CQE */,
354 ETH_RX_CQE_TYPE_TPA_END /* TPA end ETH Rx CQE */,
359 * Wrapp for PD RX CQE used in order to cover full cache line when writing CQE
361 struct eth_rx_pmd_cqe {
362 union eth_rx_cqe cqe /* CQE data itself */;
363 u8 reserved[ETH_RX_CQE_GAP];
367 * ETH Rx producers data
369 struct eth_rx_prod_data {
370 __le16 bd_prod /* BD producer */;
371 __le16 cqe_prod /* CQE producer */;
373 __le16 reserved1 /* FW reserved. */;
377 * Aggregation end reason.
379 enum eth_tpa_end_reason {
381 ETH_AGG_END_SP_UPDATE /* SP configuration update */,
383 /* Maximum aggregation length or maximum buffer number used. */,
385 /* TCP PSH flag or TCP payload length below continue threshold. */,
386 ETH_AGG_END_TIMEOUT /* Timeout expiration. */,
387 ETH_AGG_END_NOT_CONSISTENT,
388 ETH_AGG_END_OUT_OF_ORDER,
389 ETH_AGG_END_NON_TPA_SEG,
390 MAX_ETH_TPA_END_REASON
397 ETH_TUNN_GENEVE /* GENEVE Tunnel. */,
398 ETH_TUNN_TTAG /* T-Tag Tunnel. */,
399 ETH_TUNN_GRE /* GRE Tunnel. */,
400 ETH_TUNN_VXLAN /* VXLAN Tunnel. */,
405 * The first tx bd of a given packet
407 struct eth_tx_1st_bd {
408 struct regpair addr /* Single continuous buffer */;
409 __le16 nbytes /* Number of bytes in this BD. */;
410 struct eth_tx_data_1st_bd data /* Parsing information data. */;
414 * The second tx bd of a given packet
416 struct eth_tx_2nd_bd {
417 struct regpair addr /* Single continuous buffer */;
418 __le16 nbytes /* Number of bytes in this BD. */;
419 struct eth_tx_data_2nd_bd data /* Parsing information data. */;
423 * The parsing information data for the third tx bd of a given packet.
425 struct eth_tx_data_3rd_bd {
426 __le16 lso_mss /* For LSO packet - the MSS in bytes. */;
428 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
429 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
430 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
431 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
432 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
433 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
434 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
435 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
436 u8 tunn_l4_hdr_start_offset_w;
441 * The third tx bd of a given packet
443 struct eth_tx_3rd_bd {
444 struct regpair addr /* Single continuous buffer */;
445 __le16 nbytes /* Number of bytes in this BD. */;
446 struct eth_tx_data_3rd_bd data /* Parsing information data. */;
450 * Complementary information for the regular tx bd of a given packet.
452 struct eth_tx_data_bd {
455 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
456 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
457 #define ETH_TX_DATA_BD_START_BD_MASK 0x1
458 #define ETH_TX_DATA_BD_START_BD_SHIFT 8
459 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
460 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
465 * The common regular TX BD ring element
468 struct regpair addr /* Single continuous buffer */;
469 __le16 nbytes /* Number of bytes in this BD. */;
470 struct eth_tx_data_bd data /* Complementary information. */;
473 union eth_tx_bd_types {
474 struct eth_tx_1st_bd first_bd /* The first tx bd of a given packet */;
475 struct eth_tx_2nd_bd second_bd /* The second tx bd of a given packet */
477 struct eth_tx_3rd_bd third_bd /* The third tx bd of a given packet */;
478 struct eth_tx_bd reg_bd /* The common non-special bd */;
484 struct mstorm_eth_queue_zone {
485 struct eth_rx_prod_data rx_producers;
492 struct ustorm_eth_queue_zone {
493 struct coalescing_timeset int_coalescing_timeset
494 /* Rx interrupt coalescing TimeSet */;
501 struct ystorm_eth_queue_zone {
502 struct coalescing_timeset int_coalescing_timeset
503 /* Tx interrupt coalescing TimeSet */;
512 #define ETH_DB_DATA_DEST_MASK 0x3
513 #define ETH_DB_DATA_DEST_SHIFT 0
514 #define ETH_DB_DATA_AGG_CMD_MASK 0x3
515 #define ETH_DB_DATA_AGG_CMD_SHIFT 2
516 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1
517 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4
518 #define ETH_DB_DATA_RESERVED_MASK 0x1
519 #define ETH_DB_DATA_RESERVED_SHIFT 5
520 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
521 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
526 #endif /* __ETH_COMMON__ */