2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #define __ETH_COMMON__
11 /********************/
12 /* ETH FW CONSTANTS */
13 /********************/
14 #define ETH_CACHE_LINE_SIZE 64
15 #define ETH_RX_CQE_GAP 32
16 #define ETH_MAX_RAMROD_PER_CON 8
17 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096
18 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096
19 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
20 #define ETH_RX_NUM_NEXT_PAGE_BDS 2
22 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
23 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
24 #define ETH_TX_MAX_LSO_HDR_NBD 4
25 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3
26 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
27 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
28 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
29 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
30 #define ETH_TX_MAX_LSO_HDR_BYTES 510
31 #define ETH_TX_LSO_WINDOW_BDS_NUM 18
32 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700
33 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFFFF
35 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
37 #define ETH_RX_MAX_BUFF_PER_PKT 5
39 /* num of MAC/VLAN filters */
40 #define ETH_NUM_MAC_FILTERS 512
41 #define ETH_NUM_VLAN_FILTERS 512
43 /* approx. multicast constants */
44 /* CRC seed for multicast bin calculation */
45 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
46 #define ETH_MULTICAST_MAC_BINS 256
47 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
49 /* ethernet vport update constants */
50 #define ETH_FILTER_RULES_COUNT 10
51 /* number of RSS indirection table entries, per Vport) */
52 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
53 /* Length of RSS key (in regs) */
54 #define ETH_RSS_KEY_SIZE_REGS 10
55 /* number of available RSS engines in K2 */
56 #define ETH_RSS_ENGINE_NUM_K2 207
57 #define ETH_RSS_ENGINE_NUM_BB 127
60 #define ETH_TPA_MAX_AGGS_NUM 64
61 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
62 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
63 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
66 * Destination port mode
69 DEST_PORT_PHY /* Send to physical port. */,
70 DEST_PORT_LOOPBACK /* Send to loopback port. */,
71 DEST_PORT_PHY_LOOPBACK /* Send to physical and loopback port. */,
72 DEST_PORT_DROP /* Drop the packet in PBF. */,
77 * Ethernet address type
87 struct eth_tx_1st_bd_flags {
89 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
90 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
91 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
92 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
93 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
94 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
95 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
96 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
97 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
98 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
99 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
100 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
101 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
102 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
103 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
104 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
108 * The parsing information data for the first tx bd of a given packet.
110 struct eth_tx_data_1st_bd {
111 __le16 vlan /* VLAN to insert to packet (if needed). */;
112 /* Number of BDs in packet. Should be at least 2 in non-LSO
113 * packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet.
116 struct eth_tx_1st_bd_flags bd_flags;
118 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1
119 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0
120 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
121 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
122 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF
123 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2
127 * The parsing information data for the second tx bd of a given packet.
129 struct eth_tx_data_2nd_bd {
132 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
133 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
134 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
135 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
136 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
137 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
138 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
139 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
140 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
141 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
142 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
143 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
144 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
145 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
146 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
147 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
148 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
149 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
150 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
151 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
153 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
154 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
155 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
156 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
160 * Firmware data for L2-EDPM packet.
162 struct eth_edpm_fw_data {
163 /* Parsing information data from the 1st BD. */
164 struct eth_tx_data_1st_bd data_1st_bd;
165 /* Parsing information data from the 2nd BD. */
166 struct eth_tx_data_2nd_bd data_2nd_bd;
173 struct eth_fast_path_cqe_fw_debug {
174 u8 reserved0 /* FW reserved. */;
175 u8 reserved1 /* FW reserved. */;
176 __le16 reserved2 /* FW reserved. */;
179 struct tunnel_parsing_flags {
181 #define TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
182 #define TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
183 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
184 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
185 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
186 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
187 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
188 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
189 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
190 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
191 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
192 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
196 * Regular ETH Rx FP CQE.
198 struct eth_fast_path_rx_reg_cqe {
199 u8 type /* CQE type */;
201 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
202 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
203 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
204 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
205 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
206 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
207 __le16 pkt_len /* Total packet length (from the parser) */;
208 struct parsing_and_err_flags pars_flags
209 /* Parsing and error flags from the parser */;
210 __le16 vlan_tag /* 802.1q VLAN tag */;
211 __le32 rss_hash /* RSS hash result */;
212 __le16 len_on_first_bd /* Number of bytes placed on first BD */;
213 u8 placement_offset /* Offset of placement from BD start */;
214 struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
216 u8 bd_num /* Number of BDs, used for packet */;
218 struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
221 #define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
222 #define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
223 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
224 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
225 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
226 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
230 * TPA-continue ETH Rx FP CQE.
232 struct eth_fast_path_rx_tpa_cont_cqe {
233 u8 type /* CQE type */;
234 u8 tpa_agg_index /* TPA aggregation index */;
235 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]
236 /* List of the segment sizes */;
238 u8 reserved1 /* FW reserved. */;
239 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* FW reserved. */;
243 * TPA-end ETH Rx FP CQE .
245 struct eth_fast_path_rx_tpa_end_cqe {
246 u8 type /* CQE type */;
247 u8 tpa_agg_index /* TPA aggregation index */;
248 __le16 total_packet_len /* Total aggregated packet length */;
249 u8 num_of_bds /* Total number of BDs comprising the packet */;
250 u8 end_reason /* Aggregation end reason. Use enum eth_tpa_end_reason */
252 __le16 num_of_coalesced_segs /* Number of coalesced TCP segments */;
253 __le32 ts_delta /* TCP timestamp delta */;
254 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]
255 /* List of the segment sizes */;
257 u8 reserved2 /* FW reserved. */;
258 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* FW reserved. */;
262 * TPA-start ETH Rx FP CQE.
264 struct eth_fast_path_rx_tpa_start_cqe {
265 u8 type /* CQE type */;
267 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
268 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
269 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
270 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
271 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
272 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
273 __le16 seg_len /* Segment length (packetLen from the parser) */;
274 struct parsing_and_err_flags pars_flags
275 /* Parsing and error flags from the parser */;
276 __le16 vlan_tag /* 802.1q VLAN tag */;
277 __le32 rss_hash /* RSS hash result */;
278 __le16 len_on_first_bd /* Number of bytes placed on first BD */;
279 u8 placement_offset /* Offset of placement from BD start */;
280 struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
282 u8 tpa_agg_index /* TPA aggregation index */;
283 u8 header_len /* Packet L2+L3+L4 header length */;
284 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]
285 /* Additional BDs length list. */;
286 struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
290 * The L4 pseudo checksum mode for Ethernet
292 enum eth_l4_pseudo_checksum_mode {
293 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH
294 /* Pseudo Header checksum on packet is calculated
295 * with the correct packet length field.
298 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH
299 /* Pseudo Hdr checksum on packet is calc with zero len field. */
301 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
305 struct regpair addr /* single continues buffer */;
309 * regular ETH Rx SP CQE
311 struct eth_slow_path_rx_cqe {
312 u8 type /* CQE type */;
319 #define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
320 #define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
321 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
322 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
323 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
324 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
328 * union for all ETH Rx CQE types
331 struct eth_fast_path_rx_reg_cqe fast_path_regular /* Regular FP CQE */;
332 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start
334 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont
335 /* TPA-continue CQE */;
336 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end /* TPA-end CQE */
338 struct eth_slow_path_rx_cqe slow_path /* SP CQE */;
344 enum eth_rx_cqe_type {
345 ETH_RX_CQE_TYPE_UNUSED,
346 ETH_RX_CQE_TYPE_REGULAR /* Regular FP ETH Rx CQE */,
347 ETH_RX_CQE_TYPE_SLOW_PATH /* Slow path ETH Rx CQE */,
348 ETH_RX_CQE_TYPE_TPA_START /* TPA start ETH Rx CQE */,
349 ETH_RX_CQE_TYPE_TPA_CONT /* TPA Continue ETH Rx CQE */,
350 ETH_RX_CQE_TYPE_TPA_END /* TPA end ETH Rx CQE */,
355 * Wrapper for PD RX CQE - used in order to cover full cache line when writing
358 struct eth_rx_pmd_cqe {
359 union eth_rx_cqe cqe /* CQE data itself */;
360 u8 reserved[ETH_RX_CQE_GAP];
364 * Aggregation end reason.
366 enum eth_tpa_end_reason {
368 ETH_AGG_END_SP_UPDATE /* SP configuration update */,
370 /* Maximum aggregation length or maximum buffer number used. */,
372 /* TCP PSH flag or TCP payload length below continue threshold. */,
373 ETH_AGG_END_TIMEOUT /* Timeout expiration. */,
374 ETH_AGG_END_NOT_CONSISTENT,
375 ETH_AGG_END_OUT_OF_ORDER,
376 ETH_AGG_END_NON_TPA_SEG,
377 MAX_ETH_TPA_END_REASON
384 ETH_TUNN_GENEVE /* GENEVE Tunnel. */,
385 ETH_TUNN_TTAG /* T-Tag Tunnel. */,
386 ETH_TUNN_GRE /* GRE Tunnel. */,
387 ETH_TUNN_VXLAN /* VXLAN Tunnel. */,
392 * The first tx bd of a given packet
394 struct eth_tx_1st_bd {
395 struct regpair addr /* Single continuous buffer */;
396 __le16 nbytes /* Number of bytes in this BD. */;
397 struct eth_tx_data_1st_bd data /* Parsing information data. */;
401 * The second tx bd of a given packet
403 struct eth_tx_2nd_bd {
404 struct regpair addr /* Single continuous buffer */;
405 __le16 nbytes /* Number of bytes in this BD. */;
406 struct eth_tx_data_2nd_bd data /* Parsing information data. */;
410 * The parsing information data for the third tx bd of a given packet.
412 struct eth_tx_data_3rd_bd {
413 __le16 lso_mss /* For LSO packet - the MSS in bytes. */;
415 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
416 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
417 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
418 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
419 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
420 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
421 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
422 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
423 u8 tunn_l4_hdr_start_offset_w;
428 * The third tx bd of a given packet
430 struct eth_tx_3rd_bd {
431 struct regpair addr /* Single continuous buffer */;
432 __le16 nbytes /* Number of bytes in this BD. */;
433 struct eth_tx_data_3rd_bd data /* Parsing information data. */;
437 * Complementary information for the regular tx bd of a given packet.
439 struct eth_tx_data_bd {
442 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
443 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
444 #define ETH_TX_DATA_BD_START_BD_MASK 0x1
445 #define ETH_TX_DATA_BD_START_BD_SHIFT 8
446 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
447 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
452 * The common regular TX BD ring element
455 struct regpair addr /* Single continuous buffer */;
456 __le16 nbytes /* Number of bytes in this BD. */;
457 struct eth_tx_data_bd data /* Complementary information. */;
460 union eth_tx_bd_types {
461 struct eth_tx_1st_bd first_bd /* The first tx bd of a given packet */;
462 struct eth_tx_2nd_bd second_bd /* The second tx bd of a given packet */
464 struct eth_tx_3rd_bd third_bd /* The third tx bd of a given packet */;
465 struct eth_tx_bd reg_bd /* The common non-special bd */;
471 struct mstorm_eth_queue_zone {
472 struct eth_rx_prod_data rx_producers;
479 struct ystorm_eth_queue_zone {
480 struct coalescing_timeset int_coalescing_timeset
481 /* Tx interrupt coalescing TimeSet */;
490 #define ETH_DB_DATA_DEST_MASK 0x3
491 #define ETH_DB_DATA_DEST_SHIFT 0
492 #define ETH_DB_DATA_AGG_CMD_MASK 0x3
493 #define ETH_DB_DATA_AGG_CMD_SHIFT 2
494 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1
495 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4
496 #define ETH_DB_DATA_RESERVED_MASK 0x1
497 #define ETH_DB_DATA_RESERVED_SHIFT 5
498 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
499 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
504 #endif /* __ETH_COMMON__ */