2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: MCP public data
15 * Created: 13/01/2013 yanivr
17 ****************************************************************************/
22 #define VF_MAX_STATIC 192 /* In case of AH */
24 #define MCP_GLOB_PATH_MAX 2
25 #define MCP_PORT_MAX 2 /* Global */
26 #define MCP_GLOB_PORT_MAX 4 /* Global */
27 #define MCP_GLOB_FUNC_MAX 16 /* Global */
29 typedef u32 offsize_t; /* In DWORDS !!! */
30 /* Offset from the beginning of the MCP scratchpad */
31 #define OFFSIZE_OFFSET_OFFSET 0
32 #define OFFSIZE_OFFSET_MASK 0x0000ffff
33 /* Size of specific element (not the whole array if any) */
34 #define OFFSIZE_SIZE_OFFSET 16
35 #define OFFSIZE_SIZE_MASK 0xffff0000
37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
38 #define SECTION_OFFSET(_offsize) \
39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2))
41 /* SECTION_SIZE is calculating the size in bytes out of offsize */
42 #define SECTION_SIZE(_offsize) \
43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2)
45 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
48 #define SECTION_ADDR(_offsize, idx) \
50 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
52 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use
53 * offsetof, since the OFFSETUP collide with the firmware definition
55 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
56 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
57 /* PHY configuration */
59 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
61 #define ETH_SPEED_AUTONEG 0
62 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
64 u32 pause; /* bitmask */
65 #define ETH_PAUSE_NONE 0x0
66 #define ETH_PAUSE_AUTONEG 0x1
67 #define ETH_PAUSE_RX 0x2
68 #define ETH_PAUSE_TX 0x4
70 u32 adv_speed; /* Default should be the speed_cap_mask */
72 #define ETH_LOOPBACK_NONE (0)
73 /* Serdes loopback. In AH, it refers to Near End */
74 #define ETH_LOOPBACK_INT_PHY (1)
75 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */
76 /* External Loopback (Require loopback plug) */
77 #define ETH_LOOPBACK_EXT (3)
78 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */
79 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */
80 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */
81 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */
82 /* Loop RX packet from PCS to TX */
83 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8)
84 /* Remote Serdes Loopback (RX to TX) */
85 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9)
88 /* EEE is enabled (configuration). Refer to eee_status->active for negotiated
91 #define EEE_CFG_EEE_ENABLED (1 << 0)
92 #define EEE_CFG_TX_LPI (1 << 1)
93 #define EEE_CFG_ADV_SPEED_1G (1 << 2)
94 #define EEE_CFG_ADV_SPEED_10G (1 << 3)
95 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
96 #define EEE_TX_TIMER_USEC_OFFSET 4
97 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
98 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
99 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
101 u32 link_modes; /* Additional link modes */
102 #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */
106 u32 dynamic_cfg; /* device control channel */
107 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
108 #define PORT_MF_CFG_OV_TAG_OFFSET 0
109 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
114 /* DO NOT add new fields in the middle
115 * MUST be synced with struct pmm_stats_map
118 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
119 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
120 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
121 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
122 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
123 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
127 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
129 /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
131 /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
133 /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
135 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
140 /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/
147 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
148 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
149 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
150 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
151 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
152 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
153 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
154 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
155 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
156 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
157 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
158 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
159 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
160 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
161 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
162 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
166 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
168 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
170 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
172 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
176 /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */
183 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
184 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
185 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
188 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
190 /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
198 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
199 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
200 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
201 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
202 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
204 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
205 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
206 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
207 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
208 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
209 /* HSI - Cannot add more stats to this struct. If needed, then need to open new
221 struct brb_stats brb;
222 struct eth_stats eth;
225 /*----+------------------------------------------------------------------------
226 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
227 * h | rate of | team #1 | team #2 |are used|per path | (paths)
228 * i | physical | | | | | enabled
229 * p | ports | | | | |
230 *====+============+=========+=========+========+==========+===================
231 * BB | 1x100G | This is special mode, where there are actually 2 HW func
232 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1
233 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
234 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
235 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional)
236 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional)
237 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional)
238 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
239 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA
240 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
241 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
242 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
243 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
244 *====+============+=========+=========+========+==========+===================
249 #define CMT_TEAM_MAX 2
251 struct couple_mode_teaming {
252 u8 port_cmt[MCP_GLOB_PORT_MAX];
253 #define PORT_CMT_IN_TEAM (1 << 0)
255 #define PORT_CMT_PORT_ROLE (1 << 1)
256 #define PORT_CMT_PORT_INACTIVE (0 << 1)
257 #define PORT_CMT_PORT_ACTIVE (1 << 1)
259 #define PORT_CMT_TEAM_MASK (1 << 2)
260 #define PORT_CMT_TEAM0 (0 << 2)
261 #define PORT_CMT_TEAM1 (1 << 2)
264 /**************************************
265 * LLDP and DCBX HSI structures
266 **************************************/
267 #define LLDP_CHASSIS_ID_STAT_LEN 4
268 #define LLDP_PORT_ID_STAT_LEN 4
269 #define DCBX_MAX_APP_PROTOCOL 32
270 #define MAX_SYSTEM_LLDP_TLV_DATA 32
272 typedef enum _lldp_agent_e {
273 LLDP_NEAREST_BRIDGE = 0,
274 LLDP_NEAREST_NON_TPMR_BRIDGE,
275 LLDP_NEAREST_CUSTOMER_BRIDGE,
279 struct lldp_config_params_s {
281 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
282 #define LLDP_CONFIG_TX_INTERVAL_OFFSET 0
283 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
284 #define LLDP_CONFIG_HOLD_OFFSET 8
285 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
286 #define LLDP_CONFIG_MAX_CREDIT_OFFSET 12
287 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
288 #define LLDP_CONFIG_ENABLE_RX_OFFSET 30
289 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
290 #define LLDP_CONFIG_ENABLE_TX_OFFSET 31
291 /* Holds local Chassis ID TLV header, subtype and 9B of payload.
292 * If firtst byte is 0, then we will use default chassis ID
294 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
295 /* Holds local Port ID TLV header, subtype and 9B of payload.
296 * If firtst byte is 0, then we will use default port ID
298 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
301 struct lldp_status_params_s {
303 u32 status; /* TBD */
304 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
305 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
306 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
307 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
311 struct dcbx_ets_feature {
313 #define DCBX_ETS_ENABLED_MASK 0x00000001
314 #define DCBX_ETS_ENABLED_OFFSET 0
315 #define DCBX_ETS_WILLING_MASK 0x00000002
316 #define DCBX_ETS_WILLING_OFFSET 1
317 #define DCBX_ETS_ERROR_MASK 0x00000004
318 #define DCBX_ETS_ERROR_OFFSET 2
319 #define DCBX_ETS_CBS_MASK 0x00000008
320 #define DCBX_ETS_CBS_OFFSET 3
321 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
322 #define DCBX_ETS_MAX_TCS_OFFSET 4
323 #define DCBX_OOO_TC_MASK 0x00000f00
324 #define DCBX_OOO_TC_OFFSET 8
325 /* Entries in tc table are orginized that the left most is pri 0, right most is
330 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward
333 #define DCBX_TCP_OOO_TC (4)
334 #define DCBX_TCP_OOO_K2_4PORT_TC (3)
336 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
337 #define DCBX_CEE_STRICT_PRIORITY 0xf
338 /* Entries in tc table are orginized that the left most is pri 0, right most is
343 /* Entries in tc table are orginized that the left most is pri 0, right most is
348 #define DCBX_ETS_TSA_STRICT 0
349 #define DCBX_ETS_TSA_CBS 1
350 #define DCBX_ETS_TSA_ETS 2
353 struct dcbx_app_priority_entry {
355 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
356 #define DCBX_APP_PRI_MAP_OFFSET 0
357 #define DCBX_APP_PRI_0 0x01
358 #define DCBX_APP_PRI_1 0x02
359 #define DCBX_APP_PRI_2 0x04
360 #define DCBX_APP_PRI_3 0x08
361 #define DCBX_APP_PRI_4 0x10
362 #define DCBX_APP_PRI_5 0x20
363 #define DCBX_APP_PRI_6 0x40
364 #define DCBX_APP_PRI_7 0x80
365 #define DCBX_APP_SF_MASK 0x00000300
366 #define DCBX_APP_SF_OFFSET 8
367 #define DCBX_APP_SF_ETHTYPE 0
368 #define DCBX_APP_SF_PORT 1
369 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
370 #define DCBX_APP_SF_IEEE_OFFSET 12
371 #define DCBX_APP_SF_IEEE_RESERVED 0
372 #define DCBX_APP_SF_IEEE_ETHTYPE 1
373 #define DCBX_APP_SF_IEEE_TCP_PORT 2
374 #define DCBX_APP_SF_IEEE_UDP_PORT 3
375 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
377 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
378 #define DCBX_APP_PROTOCOL_ID_OFFSET 16
382 /* FW structure in BE */
383 struct dcbx_app_priority_feature {
385 #define DCBX_APP_ENABLED_MASK 0x00000001
386 #define DCBX_APP_ENABLED_OFFSET 0
387 #define DCBX_APP_WILLING_MASK 0x00000002
388 #define DCBX_APP_WILLING_OFFSET 1
389 #define DCBX_APP_ERROR_MASK 0x00000004
390 #define DCBX_APP_ERROR_OFFSET 2
392 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
393 #define DCBX_APP_DEFAULT_PRI_OFFSET 8
395 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
396 #define DCBX_APP_MAX_TCS_OFFSET 12
397 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
398 #define DCBX_APP_NUM_ENTRIES_OFFSET 16
399 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
402 /* FW structure in BE */
403 struct dcbx_features {
405 struct dcbx_ets_feature ets;
408 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
409 #define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0
410 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
411 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
412 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
413 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
414 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
415 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
416 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
417 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
419 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
420 #define DCBX_PFC_FLAGS_OFFSET 8
421 #define DCBX_PFC_CAPS_MASK 0x00000f00
422 #define DCBX_PFC_CAPS_OFFSET 8
423 #define DCBX_PFC_MBC_MASK 0x00004000
424 #define DCBX_PFC_MBC_OFFSET 14
425 #define DCBX_PFC_WILLING_MASK 0x00008000
426 #define DCBX_PFC_WILLING_OFFSET 15
427 #define DCBX_PFC_ENABLED_MASK 0x00010000
428 #define DCBX_PFC_ENABLED_OFFSET 16
429 #define DCBX_PFC_ERROR_MASK 0x00020000
430 #define DCBX_PFC_ERROR_OFFSET 17
433 struct dcbx_app_priority_feature app;
436 struct dcbx_local_params {
438 #define DCBX_CONFIG_VERSION_MASK 0x00000007
439 #define DCBX_CONFIG_VERSION_OFFSET 0
440 #define DCBX_CONFIG_VERSION_DISABLED 0
441 #define DCBX_CONFIG_VERSION_IEEE 1
442 #define DCBX_CONFIG_VERSION_CEE 2
443 #define DCBX_CONFIG_VERSION_STATIC 4
446 struct dcbx_features features;
453 #define DCBX_CONFIG_VERSION_MASK 0x00000007
454 #define DCBX_CONFIG_VERSION_OFFSET 0
455 #define DCBX_CONFIG_VERSION_DISABLED 0
456 #define DCBX_CONFIG_VERSION_IEEE 1
457 #define DCBX_CONFIG_VERSION_CEE 2
458 #define DCBX_CONFIG_VERSION_STATIC 4
460 struct dcbx_features features;
464 struct lldp_system_tlvs_buffer_s {
467 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
470 struct dcb_dscp_map {
472 #define DCB_DSCP_ENABLE_MASK 0x1
473 #define DCB_DSCP_ENABLE_OFFSET 0
474 #define DCB_DSCP_ENABLE 1
478 /**************************************/
480 /* P U B L I C G L O B A L */
482 /**************************************/
483 struct public_global {
484 u32 max_path; /* 32bit is wasty, but this will be used often */
485 /* (Global) 32bit is wasty, but this will be used often */
487 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */
492 u32 phymod_dbg_mb_offset;
493 struct couple_mode_teaming cmt;
494 /* Temperature in Celcius (-255C / +255C), measured every second. */
495 s32 internal_temperature;
497 u32 running_bundle_id;
498 s32 external_temperature;
500 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0)
501 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1)
502 #define MDUMP_REASON_DUMP_AGED (1 << 2)
503 u32 ext_phy_upgrade_fw;
504 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff)
505 #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0)
506 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1)
507 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2)
508 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3)
509 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000)
510 #define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16)
513 /**************************************/
515 /* P U B L I C P A T H */
517 /**************************************/
519 /****************************************************************************
520 * Shared Memory 2 Region *
521 ****************************************************************************/
522 /* The fw_flr_ack is actually built in the following way: */
524 /* 128 bit: VF ack */
525 /* 8 bit: ios_dis_ack */
526 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
527 /* u32. The fw must have the VF right after the PF since this is how it */
528 /* access arrays(it expects always the VF to reside after the PF, and that */
529 /* makes the calculation much easier for it. ) */
530 /* In order to answer both limitations, and keep the struct small, the code */
531 /* will abuse the structure defined here to achieve the actual partition */
533 /****************************************************************************/
537 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
538 #define ACCUM_ACK_PF_BASE 0
539 #define ACCUM_ACK_PF_SHIFT 0
541 #define ACCUM_ACK_VF_BASE 8
542 #define ACCUM_ACK_VF_SHIFT 3
544 #define ACCUM_ACK_IOV_DIS_BASE 256
545 #define ACCUM_ACK_IOV_DIS_SHIFT 8
550 struct fw_flr_mb flr_mb;
552 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
553 * which were disabled/flred
555 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
557 /* Reset on mcp reset, and incremented for eveny process kill event. */
559 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
560 #define PROCESS_KILL_COUNTER_OFFSET 0
561 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
562 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16
563 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
566 /**************************************/
568 /* P U B L I C P O R T */
570 /**************************************/
571 #define FC_NPIV_WWPN_SIZE 8
572 #define FC_NPIV_WWNN_SIZE 8
573 struct dci_npiv_settings {
574 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
575 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
578 struct dci_fc_npiv_cfg {
579 /* hdr used internally by the MFW */
584 #define MAX_NUMBER_NPIV 64
585 struct dci_fc_npiv_tbl {
586 struct dci_fc_npiv_cfg fc_npiv_cfg;
587 struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
590 /****************************************************************************
591 * Driver <-> FW Mailbox *
592 ****************************************************************************/
595 u32 validity_map; /* 0x0 (4*2 = 0x8) */
598 #define MCP_VALIDITY_PCI_CFG 0x00100000
599 #define MCP_VALIDITY_MB 0x00200000
600 #define MCP_VALIDITY_DEV_INFO 0x00400000
601 #define MCP_VALIDITY_RESERVED 0x00000007
603 /* One licensing bit should be set */
604 /* yaniv - tbd ? license */
605 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
606 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
607 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
608 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
611 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
612 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
613 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
614 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
617 #define LINK_STATUS_LINK_UP 0x00000001
618 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
619 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
620 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
621 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
622 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
623 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
624 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
625 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
626 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
627 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
628 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
629 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
630 #define LINK_STATUS_PFC_ENABLED 0x00000100
631 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
632 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
633 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
634 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
635 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
636 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
637 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
638 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
639 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
640 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
641 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
642 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
643 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
644 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
645 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
646 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
647 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
648 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
649 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
650 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
651 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
652 #define LINK_STATUS_FEC_MODE_NONE (0 << 27)
653 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27)
654 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27)
655 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000
658 u32 ext_phy_fw_version;
659 /* Points to struct eth_phy_cfg (For READ-ONLY) */
660 u32 drv_phy_cfg_addr;
666 struct port_mf_cfg port_mf_config;
667 struct port_stats stats;
670 #define MEDIA_UNSPECIFIED 0x0
671 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */
672 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */
673 #define MEDIA_DA_TWINAX 0x3
674 #define MEDIA_BASE_T 0x4
675 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */
676 #define MEDIA_MODULE_FIBER 0x6
677 #define MEDIA_KR 0xf0
678 #define MEDIA_NOT_PRESENT 0xff
681 #define LFA_LINK_FLAP_REASON_OFFSET 0
682 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
683 #define LFA_NO_REASON (0 << 0)
684 #define LFA_LINK_DOWN (1 << 0)
685 #define LFA_FORCE_INIT (1 << 1)
686 #define LFA_LOOPBACK_MISMATCH (1 << 2)
687 #define LFA_SPEED_MISMATCH (1 << 3)
688 #define LFA_FLOW_CTRL_MISMATCH (1 << 4)
689 #define LFA_ADV_SPEED_MISMATCH (1 << 5)
690 #define LFA_EEE_MISMATCH (1 << 6)
691 #define LFA_LINK_MODES_MISMATCH (1 << 7)
692 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
693 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
694 #define LINK_FLAP_COUNT_OFFSET 16
695 #define LINK_FLAP_COUNT_MASK 0x00ff0000
697 u32 link_change_count;
700 /* offset: 536 bytes? */
701 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
702 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
703 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
705 /* DCBX related MIB */
706 struct dcbx_local_params local_admin_dcbx_mib;
707 struct dcbx_mib remote_dcbx_mib;
708 struct dcbx_mib operational_dcbx_mib;
710 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
712 u32 fc_npiv_nvram_tbl_addr;
713 u32 fc_npiv_nvram_tbl_size;
714 u32 transceiver_data;
715 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
716 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
717 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
718 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
719 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
720 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
721 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
722 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x00000008
723 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000
724 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF
725 /* 1G Passive copper cable */
726 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
727 /* 1G Active copper cable */
728 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
729 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
730 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
731 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
732 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
733 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
734 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
735 /* 10G Passive copper cable */
736 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
737 /* 10G Active copper cable */
738 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
739 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
740 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
741 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
742 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
743 /* Active optical cable */
744 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
745 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
746 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
747 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
748 /* Active copper cable */
749 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
750 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
751 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
752 /* 25G Passive copper cable - short */
753 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
754 /* 25G Active copper cable - short */
755 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
756 /* 25G Passive copper cable - medium */
757 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
758 /* 25G Active copper cable - medium */
759 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
760 /* 25G Passive copper cable - long */
761 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
762 /* 25G Active copper cable - long */
763 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
764 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
765 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
766 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
768 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
769 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
770 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
771 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
772 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
773 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
774 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
775 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
776 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
780 struct dcb_dscp_map dcb_dscp_map;
783 /* Set when EEE negotiation is complete. */
784 #define EEE_ACTIVE_BIT (1 << 0)
786 /* Shows the Local Device EEE capabilities */
787 #define EEE_LD_ADV_STATUS_MASK 0x000000f0
788 #define EEE_LD_ADV_STATUS_OFFSET 4
789 #define EEE_1G_ADV (1 << 1)
790 #define EEE_10G_ADV (1 << 2)
791 /* Same values as in EEE_LD_ADV, but for Link Parter */
792 #define EEE_LP_ADV_STATUS_MASK 0x00000f00
793 #define EEE_LP_ADV_STATUS_OFFSET 8
795 /* Supported speeds for EEE */
796 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000
797 #define EEE_SUPPORTED_SPEED_OFFSET 12
798 #define EEE_1G_SUPPORTED (1 << 1)
799 #define EEE_10G_SUPPORTED (1 << 2)
801 u32 eee_remote; /* Used for EEE in LLDP */
802 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
803 #define EEE_REMOTE_TW_TX_OFFSET 0
804 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
805 #define EEE_REMOTE_TW_RX_OFFSET 16
808 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF
809 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0
810 #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2)
811 #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3)
812 #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4)
813 #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5)
814 #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6)
815 #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00
816 #define ETH_TRANSCEIVER_IDENT_OFFSET 8
819 /**************************************/
821 /* P U B L I C F U N C */
823 /**************************************/
826 u32 iscsi_boot_signature;
827 u32 iscsi_boot_block_offset;
829 /* MTU size per funciton is needed for the OV feature */
831 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
833 /* For PCP values 0-3 use the map lower */
834 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
835 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
837 u32 c2s_pcp_map_lower;
838 /* For PCP values 4-7 use the map upper */
839 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
840 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
842 u32 c2s_pcp_map_upper;
844 /* For PCP default value get the MSB byte of the map default */
845 u32 c2s_pcp_map_default;
849 /* replace old mf_cfg */
852 /* function 0 of each port cannot be hidden */
853 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
854 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
855 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001
858 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
859 #define FUNC_MF_CFG_PROTOCOL_OFFSET 4
860 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
861 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
862 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
863 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
864 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
867 /* value range - 0..100, increments in 1 % */
868 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
869 #define FUNC_MF_CFG_MIN_BW_OFFSET 8
870 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
871 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
872 #define FUNC_MF_CFG_MAX_BW_OFFSET 16
873 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
876 #define FUNC_STATUS_VLINK_DOWN 0x00000001
878 u32 mac_upper; /* MAC */
879 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
880 #define FUNC_MF_CFG_UPPERMAC_OFFSET 0
881 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
883 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
885 u32 fcoe_wwn_port_name_upper;
886 u32 fcoe_wwn_port_name_lower;
888 u32 fcoe_wwn_node_name_upper;
889 u32 fcoe_wwn_node_name_lower;
891 u32 ovlan_stag; /* tags */
892 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
893 #define FUNC_MF_CFG_OV_STAG_OFFSET 0
894 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
896 u32 pf_allocation; /* vf per pf */
898 u32 preserve_data; /* Will be used bt CCM */
900 u32 driver_last_activity_ts;
903 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
906 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
909 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
910 #define DRV_ID_PDA_COMP_VER_OFFSET 0
912 #define LOAD_REQ_HSI_VERSION 2
913 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
914 #define DRV_ID_MCP_HSI_VER_OFFSET 16
915 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
916 DRV_ID_MCP_HSI_VER_OFFSET)
918 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
919 #define DRV_ID_DRV_TYPE_OFFSET 24
920 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET)
921 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET)
922 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET)
923 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET)
924 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET)
925 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET)
926 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET)
927 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET)
928 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET)
930 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
931 #define DRV_ID_DRV_INIT_HW_OFFSET 31
932 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET)
935 /**************************************/
937 /* P U B L I C M B */
939 /**************************************/
940 /* This is the only section that the driver can write to, and each */
941 /* Basically each driver request to set feature parameters,
942 * will be done using a different command, which will be linked
943 * to a specific data structure from the union below.
944 * For huge strucuture, the common blank structure should be used.
948 u32 mac_upper; /* Upper 16 bits are always zeroes */
957 struct mcp_file_att {
962 struct bist_nvm_image_att {
964 u32 image_type; /* Image type */
965 u32 nvm_start_addr; /* NVM address of the image */
966 u32 len; /* Include CRC */
969 #define MCP_DRV_VER_STR_SIZE 16
970 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
971 #define MCP_DRV_NVM_BUF_LEN 32
972 struct drv_version_stc {
974 u8 name[MCP_DRV_VER_STR_SIZE - 4];
977 /* statistics for ncsi */
978 struct lan_stats_stc {
985 struct fcoe_stats_stc {
992 struct iscsi_stats_stc {
999 struct rdma_stats_stc {
1006 struct ocbb_data_stc {
1009 u32 ocsd_req_update_interval;
1012 #define MAX_NUM_OF_SENSORS 7
1013 #define MFW_SENSOR_LOCATION_INTERNAL 1
1014 #define MFW_SENSOR_LOCATION_EXTERNAL 2
1015 #define MFW_SENSOR_LOCATION_SFP 3
1017 #define SENSOR_LOCATION_OFFSET 0
1018 #define SENSOR_LOCATION_MASK 0x000000ff
1019 #define THRESHOLD_HIGH_OFFSET 8
1020 #define THRESHOLD_HIGH_MASK 0x0000ff00
1021 #define CRITICAL_TEMPERATURE_OFFSET 16
1022 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000
1023 #define CURRENT_TEMP_OFFSET 24
1024 #define CURRENT_TEMP_MASK 0xff000000
1025 struct temperature_status_stc {
1027 u32 sensor[MAX_NUM_OF_SENSORS];
1030 /* crash dump configuration header */
1031 struct mdump_config_stc {
1039 enum resource_id_enum {
1040 RESOURCE_NUM_SB_E = 0,
1041 RESOURCE_NUM_L2_QUEUE_E = 1,
1042 RESOURCE_NUM_VPORT_E = 2,
1043 RESOURCE_NUM_VMQ_E = 3,
1044 /* Not a real resource!! it's a factor used to calculate others */
1045 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
1046 /* Not a real resource!! it's a factor used to calculate others */
1047 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
1048 RESOURCE_NUM_RL_E = 6,
1049 RESOURCE_NUM_PQ_E = 7,
1050 RESOURCE_NUM_VF_E = 8,
1051 RESOURCE_VFC_FILTER_E = 9,
1052 RESOURCE_ILT_E = 10,
1053 RESOURCE_CQS_E = 11,
1054 RESOURCE_GFT_PROFILES_E = 12,
1055 RESOURCE_NUM_TC_E = 13,
1056 RESOURCE_NUM_RSS_ENGINES_E = 14,
1057 RESOURCE_LL2_QUEUE_E = 15,
1058 RESOURCE_RDMA_STATS_QUEUE_E = 16,
1059 RESOURCE_BDQ_E = 17,
1061 RESOURCE_NUM_INVALID = 0xFFFFFFFF
1064 /* Resource ID is to be filled by the driver in the MB request
1065 * Size, offset & flags to be filled by the MFW in the MB response
1067 struct resource_info {
1068 enum resource_id_enum res_id;
1069 u32 size; /* number of allocated resources */
1070 u32 offset; /* Offset of the 1st resource */
1074 #define RESOURCE_ELEMENT_STRICT (1 << 0)
1077 #define DRV_ROLE_NONE 0
1078 #define DRV_ROLE_PREBOOT 1
1079 #define DRV_ROLE_OS 2
1080 #define DRV_ROLE_KDUMP 3
1082 struct load_req_stc {
1087 #define LOAD_REQ_ROLE_MASK 0x000000FF
1088 #define LOAD_REQ_ROLE_OFFSET 0
1089 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
1090 #define LOAD_REQ_LOCK_TO_OFFSET 8
1091 #define LOAD_REQ_LOCK_TO_DEFAULT 0
1092 #define LOAD_REQ_LOCK_TO_NONE 255
1093 #define LOAD_REQ_FORCE_MASK 0x000F0000
1094 #define LOAD_REQ_FORCE_OFFSET 16
1095 #define LOAD_REQ_FORCE_NONE 0
1096 #define LOAD_REQ_FORCE_PF 1
1097 #define LOAD_REQ_FORCE_ALL 2
1098 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
1099 #define LOAD_REQ_FLAGS0_OFFSET 20
1100 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
1103 struct load_rsp_stc {
1108 #define LOAD_RSP_ROLE_MASK 0x000000FF
1109 #define LOAD_RSP_ROLE_OFFSET 0
1110 #define LOAD_RSP_HSI_MASK 0x0000FF00
1111 #define LOAD_RSP_HSI_OFFSET 8
1112 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
1113 #define LOAD_RSP_FLAGS0_OFFSET 16
1114 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
1117 struct mdump_retain_data_stc {
1124 union drv_union_data {
1125 struct mcp_mac wol_mac; /* UNLOAD_DONE */
1127 /* This configuration should be set by the driver for the LINK_SET command. */
1129 struct eth_phy_cfg drv_phy_cfg;
1131 struct mcp_val64 val64; /* For PHY / AVS commands */
1133 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
1135 struct mcp_file_att file_att;
1137 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
1139 struct drv_version_stc drv_version;
1141 struct lan_stats_stc lan_stats;
1142 struct fcoe_stats_stc fcoe_stats;
1143 struct iscsi_stats_stc iscsi_stats;
1144 struct rdma_stats_stc rdma_stats;
1145 struct ocbb_data_stc ocbb_info;
1146 struct temperature_status_stc temp_info;
1147 struct resource_info resource;
1148 struct bist_nvm_image_att nvm_image_att;
1149 struct mdump_config_stc mdump_config;
1152 struct load_req_stc load_req;
1153 struct load_rsp_stc load_rsp;
1154 struct mdump_retain_data_stc mdump_retain;
1158 struct public_drv_mb {
1160 #define DRV_MSG_CODE_MASK 0xffff0000
1161 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1162 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1163 #define DRV_MSG_CODE_INIT_HW 0x12000000
1164 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
1165 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
1166 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1167 #define DRV_MSG_CODE_INIT_PHY 0x22000000
1168 /* Params - FORCE - Reinitialize the link regardless of LFA */
1169 /* - DONT_CARE - Don't flap the link if up */
1170 #define DRV_MSG_CODE_LINK_RESET 0x23000000
1172 /* Vitaly: LLDP commands */
1173 #define DRV_MSG_CODE_SET_LLDP 0x24000000
1174 #define DRV_MSG_CODE_SET_DCBX 0x25000000
1175 /* OneView feature driver HSI*/
1176 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
1177 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
1178 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
1179 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
1180 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
1181 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
1182 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
1183 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
1184 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp,
1185 * data: struct resource_info
1187 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
1188 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
1190 /*deprecated don't use*/
1191 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000
1192 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
1193 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1194 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
1195 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
1196 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */
1197 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
1198 /* Param should be set to the transaction size (up to 64 bytes) */
1199 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
1200 /* MFW will place the file offset and len in file_att struct */
1201 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
1202 /* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] –
1205 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
1206 /* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] –
1207 * Len in Bytes. In case this address is in the range of secured file in
1208 * secured mode, the operation will fail
1210 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
1211 /* Delete a file from nvram. Param is image_type. */
1212 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
1213 /* Reset MCP when no NVM operation is going on, and no drivers are loaded.
1214 * In case operation succeed, MCP will not ack back.
1216 #define DRV_MSG_CODE_MCP_RESET 0x00090000
1217 /* Temporary command to set secure mode, where the param is 0 (None secure) /
1218 * 1 (Secure) / 2 (Full-Secure)
1220 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
1221 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane,
1222 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port,
1225 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
1226 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane,
1227 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port,
1230 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
1231 /* Param: [0:15] - Address, [30:31] - port */
1232 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
1233 /* Param: [0:15] - Address, [30:31] - port */
1234 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
1235 /* Param: [0:3] - version, [4:15] - name (null terminated) */
1236 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
1237 /* Halts the MCP. To resume MCP, user will need to use
1238 * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers.
1240 #define DRV_MSG_CODE_MCP_HALT 0x00100000
1241 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type,
1242 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN
1244 #define DRV_MSG_CODE_SET_VMAC 0x00110000
1245 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type,
1246 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN
1248 #define DRV_MSG_CODE_GET_VMAC 0x00120000
1249 #define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4
1250 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
1251 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
1252 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
1253 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
1254 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */
1255 #define DRV_MSG_CODE_GET_STATS 0x00130000
1256 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
1257 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
1258 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
1259 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
1260 /* Host shall provide buffer and size for MFW */
1261 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000
1262 /* Host shall provide buffer and size for MFW */
1263 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000
1264 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address,
1267 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
1268 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address,
1271 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000
1272 /* indicate OCBB related information */
1273 #define DRV_MSG_CODE_OCBB_DATA 0x00180000
1274 /* Set function BW, params[15:8] - min, params[7:0] - max */
1275 #define DRV_MSG_CODE_SET_BW 0x00190000
1276 #define BW_MAX_MASK 0x000000ff
1277 #define BW_MAX_OFFSET 0
1278 #define BW_MIN_MASK 0x0000ff00
1279 #define BW_MIN_OFFSET 8
1281 /* When param is set to 1, all parities will be masked(disabled). When params
1282 * are set to 0, parities will be unmasked again.
1284 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
1285 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */
1286 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000
1287 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
1288 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1)
1289 /* Param: [0:15] - gpio number */
1290 #define DRV_MSG_CODE_GPIO_READ 0x001c0000
1291 /* Param: [0:15] - gpio number, [16:31] - gpio value */
1292 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000
1293 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */
1294 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
1295 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
1297 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */
1298 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
1299 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] -
1300 * driver version (MAJ MIN BUILD SUB)
1302 #define DRV_MSG_CODE_TIMESTAMP 0x00210000
1303 /* This is an empty mailbox just return OK*/
1304 #define DRV_MSG_CODE_EMPTY_MB 0x00220000
1306 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode,
1309 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
1311 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
1312 #define RESOURCE_CMD_REQ_RESC_OFFSET 0
1313 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
1314 #define RESOURCE_CMD_REQ_OPCODE_OFFSET 5
1315 /* request resource ownership with default aging */
1316 #define RESOURCE_OPCODE_REQ 1
1317 /* request resource ownership without aging */
1318 #define RESOURCE_OPCODE_REQ_WO_AGING 2
1319 /* request resource ownership with specific aging timer (in seconds) */
1320 #define RESOURCE_OPCODE_REQ_W_AGING 3
1321 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */
1322 /* force resource release */
1323 #define RESOURCE_OPCODE_FORCE_RELEASE 5
1324 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
1325 #define RESOURCE_CMD_REQ_AGE_OFFSET 8
1327 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
1328 #define RESOURCE_CMD_RSP_OWNER_OFFSET 0
1329 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
1330 #define RESOURCE_CMD_RSP_OPCODE_OFFSET 8
1331 /* resource is free and granted to requester */
1332 #define RESOURCE_OPCODE_GNT 1
1333 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15,
1334 * 16 = MFW, 17 = diag over serial
1336 #define RESOURCE_OPCODE_BUSY 2
1337 /* indicate release request was acknowledged */
1338 #define RESOURCE_OPCODE_RELEASED 3
1339 /* indicate release request was previously received by other owner */
1340 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
1341 /* indicate wrong owner during release */
1342 #define RESOURCE_OPCODE_WRONG_OWNER 5
1343 #define RESOURCE_OPCODE_UNKNOWN_CMD 255
1345 /* dedicate resource 0 for dump */
1346 #define RESOURCE_DUMP 0
1348 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */
1349 /* Send crash dump commands with param[3:0] - opcode */
1350 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000
1351 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
1352 /* acknowledge reception of error indication */
1353 #define DRV_MSG_CODE_MDUMP_ACK 0x01
1354 /* set epoc and personality as follow: drv_data[3:0] - epoch,
1355 * drv_data[7:4] - personality
1357 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
1358 /* trigger crash dump procedure */
1359 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
1360 /* Request valid logs and config words */
1361 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
1362 /* Set triggers mask. drv_mb_param should indicate (bitwise) which
1365 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
1366 /* Clear all logs */
1367 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06
1368 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */
1369 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */
1370 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */
1371 /* Param: [0:15] - gpio number */
1372 #define DRV_MSG_CODE_GPIO_INFO 0x00270000
1373 /* Value will be placed in union */
1374 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000
1375 /* Value should be placed in union */
1376 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000
1377 #define DRV_MB_PARAM_ADDR_OFFSET 0
1378 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF
1379 #define DRV_MB_PARAM_DEVAD_OFFSET 16
1380 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000
1381 #define DRV_MB_PARAM_PORT_OFFSET 21
1382 #define DRV_MB_PARAM_PORT_MASK 0x00600000
1383 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000
1385 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
1386 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
1387 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */
1388 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
1390 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1393 /* UNLOAD_REQ params */
1394 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
1395 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
1396 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
1397 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
1399 /* UNLOAD_DONE_params */
1400 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
1402 /* INIT_PHY params */
1403 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
1404 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
1406 /* LLDP / DCBX params*/
1407 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
1408 #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0
1409 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
1410 #define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1
1411 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
1412 #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3
1414 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
1415 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0
1417 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
1418 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
1420 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
1421 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
1422 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24
1423 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
1425 #define DRV_MB_PARAM_PHY_ADDR_OFFSET 0
1426 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
1427 #define DRV_MB_PARAM_PHY_LANE_OFFSET 16
1428 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
1429 #define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29
1430 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
1431 #define DRV_MB_PARAM_PHY_PORT_OFFSET 30
1432 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
1434 #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0
1435 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
1436 #define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8
1437 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
1438 /* configure vf MSIX params BB */
1439 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0
1440 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
1441 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8
1442 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
1443 /* configure vf MSIX for PF params AH*/
1444 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0
1445 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF
1447 /* OneView configuration parametres */
1448 #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0
1449 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
1450 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
1451 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
1452 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
1453 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
1454 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4
1455 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5
1456 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6
1457 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7
1459 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0
1460 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
1461 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
1462 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1)
1463 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1)
1464 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2)
1465 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3)
1466 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3)
1467 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4)
1468 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5)
1469 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
1470 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
1472 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0
1473 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
1475 #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0
1476 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
1477 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
1478 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
1479 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
1480 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
1482 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0
1483 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
1484 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
1486 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
1487 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
1488 /* installed but disabled by user/admin/OS */
1489 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
1490 /* installed and active */
1491 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
1493 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0
1494 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
1496 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
1497 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
1498 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
1500 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
1501 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
1502 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
1503 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
1504 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
1505 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
1506 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
1507 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
1509 #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0
1510 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
1511 #define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16
1512 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
1513 #define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16
1514 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
1515 #define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24
1516 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
1518 /* Resource Allocation params - Driver version support*/
1519 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1520 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16
1521 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1522 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
1524 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
1525 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
1526 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
1527 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
1528 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
1530 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
1531 #define DRV_MB_PARAM_BIST_RC_PASSED 1
1532 #define DRV_MB_PARAM_BIST_RC_FAILED 2
1533 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
1535 #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0
1536 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
1537 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8
1538 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
1540 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
1541 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
1542 /* driver supports SmartLinQ parameter */
1543 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001
1544 /* driver supports EEE parameter */
1545 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
1546 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000
1547 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16
1550 #define FW_MSG_CODE_MASK 0xffff0000
1551 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
1552 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
1553 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1554 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1555 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
1556 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
1557 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
1558 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
1559 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
1560 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
1561 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1562 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
1563 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
1564 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
1565 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1566 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
1567 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
1568 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
1569 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
1570 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
1571 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
1572 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000
1573 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000
1574 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000
1575 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000
1576 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
1577 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1578 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
1579 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
1580 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
1581 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
1582 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000
1583 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
1584 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1585 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
1586 #define FW_MSG_CODE_FLR_ACK 0x02000000
1587 #define FW_MSG_CODE_FLR_NACK 0x02100000
1588 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000
1589 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000
1590 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000
1592 #define FW_MSG_CODE_NVM_OK 0x00010000
1593 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
1594 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
1595 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
1596 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
1597 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
1598 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1599 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1600 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
1601 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
1602 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
1603 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
1604 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
1605 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
1606 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
1607 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
1608 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
1609 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
1610 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
1611 /* MFW reject "mcp reset" command if one of the drivers is up */
1612 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
1613 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000
1614 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000
1615 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000
1617 #define FW_MSG_CODE_PHY_OK 0x00110000
1618 #define FW_MSG_CODE_PHY_ERROR 0x00120000
1619 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
1620 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
1621 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
1622 #define FW_MSG_CODE_OK 0x00160000
1623 #define FW_MSG_CODE_ERROR 0x00170000
1624 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000
1625 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000
1626 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000
1627 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000
1628 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000
1629 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1630 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000
1631 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000
1632 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
1633 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
1634 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
1635 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
1636 #define FW_MSG_CODE_GPIO_OK 0x00160000
1637 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000
1638 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
1639 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000
1640 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
1641 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000
1642 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000
1643 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000
1644 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000
1645 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000
1646 #define FW_MSG_CODE_RECOVERY_MODE 0x00740000
1648 /* mdump related response codes */
1649 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000
1650 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000
1651 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
1652 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000
1653 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000
1656 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
1657 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000
1659 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1663 /* Resource Allocation params - MFW version support */
1664 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1665 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16
1666 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1667 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
1669 /* get MFW feature support response */
1670 /* MFW supports SmartLinQ */
1671 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001
1672 /* MFW supports EEE */
1673 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
1676 #define DRV_PULSE_SEQ_MASK 0x00007fff
1677 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1679 * The system time is in the format of
1680 * (year-2001)*12*32 + month*32 + day.
1682 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1684 * Indicate to the firmware not to go into the
1685 * OS-absent when it is not getting driver pulse.
1686 * This is used for debugging as well for PXE(MBA).
1690 #define MCP_PULSE_SEQ_MASK 0x00007fff
1691 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1692 /* Indicates to the driver not to assert due to lack
1695 #define MCP_EVENT_MASK 0xffff0000
1696 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1698 /* The union data is used by the driver to pass parameters to the scratchpad. */
1700 union drv_union_data union_data;
1705 /**********************************************************************
1707 * Incremental Aggregative
1708 * 8-bit MFW counter per message
1709 * 8-bit ack-counter per message
1711 * Provides up to 256 aggregative message per type
1712 * Provides 4 message types in dword
1713 * Message type pointers to byte offset
1714 * Backward Compatibility by using sizeof for the counters.
1715 * No lock requires for 32bit messages
1717 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
1718 * is required to prevent data corruption.
1719 **********************************************************************/
1720 enum MFW_DRV_MSG_TYPE {
1721 MFW_DRV_MSG_LINK_CHANGE,
1722 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1723 MFW_DRV_MSG_VF_DISABLED,
1724 MFW_DRV_MSG_LLDP_DATA_UPDATED,
1725 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1726 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1727 MFW_DRV_MSG_ERROR_RECOVERY,
1728 MFW_DRV_MSG_BW_UPDATE,
1729 MFW_DRV_MSG_S_TAG_UPDATE,
1730 MFW_DRV_MSG_GET_LAN_STATS,
1731 MFW_DRV_MSG_GET_FCOE_STATS,
1732 MFW_DRV_MSG_GET_ISCSI_STATS,
1733 MFW_DRV_MSG_GET_RDMA_STATS,
1734 MFW_DRV_MSG_FAILURE_DETECTED,
1735 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1736 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
1737 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE,
1741 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
1742 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
1743 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
1744 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1746 #ifdef BIG_ENDIAN /* Like MFW */
1747 #define DRV_ACK_MSG(msg_p, msg_id) \
1748 ((u8)((u8 *)msg_p)[msg_id]++;)
1750 #define DRV_ACK_MSG(msg_p, msg_id) \
1751 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;)
1754 #define MFW_DRV_UPDATE(shmem_func, msg_id) \
1755 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;)
1757 struct public_mfw_mb {
1758 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */
1759 /* Incremented by the MFW */
1760 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1761 /* Incremented by the driver */
1762 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1765 /**************************************/
1767 /* P U B L I C D A T A */
1769 /**************************************/
1770 enum public_sections {
1771 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
1772 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
1780 struct drv_ver_info_stc {
1785 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1786 * Please make sure data does not exceed this size.
1788 #define NUM_RUNTIME_DWORDS 16
1789 struct drv_init_hw_stc {
1790 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1791 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1794 struct mcp_public_data {
1795 /* The sections fields is an array */
1797 offsize_t sections[PUBLIC_MAX_SECTIONS];
1798 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1799 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1800 struct public_global global;
1801 struct public_path path[MCP_GLOB_PATH_MAX];
1802 struct public_port port[MCP_GLOB_PORT_MAX];
1803 struct public_func func[MCP_GLOB_FUNC_MAX];
1806 #define I2C_TRANSCEIVER_ADDR 0xa0
1807 #define MAX_I2C_TRANSACTION_SIZE 16
1808 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256
1810 #endif /* MCP_PUBLIC_H */