2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: MCP public data
15 * Created: 13/01/2013 yanivr
17 ****************************************************************************/
22 #define VF_MAX_STATIC 192 /* In case of AH */
24 #define MCP_GLOB_PATH_MAX 2
25 #define MCP_PORT_MAX 2 /* Global */
26 #define MCP_GLOB_PORT_MAX 4 /* Global */
27 #define MCP_GLOB_FUNC_MAX 16 /* Global */
29 typedef u32 offsize_t; /* In DWORDS !!! */
30 /* Offset from the beginning of the MCP scratchpad */
31 #define OFFSIZE_OFFSET_SHIFT 0
32 #define OFFSIZE_OFFSET_MASK 0x0000ffff
33 /* Size of specific element (not the whole array if any) */
34 #define OFFSIZE_SIZE_SHIFT 16
35 #define OFFSIZE_SIZE_MASK 0xffff0000
37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
38 #define SECTION_OFFSET(_offsize) \
39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))
41 /* SECTION_SIZE is calculating the size in bytes out of offsize */
42 #define SECTION_SIZE(_offsize) \
43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)
45 #define SECTION_ADDR(_offsize, idx) \
46 (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
48 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
49 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
51 /* PHY configuration */
53 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
54 #define PMM_SPEED_AUTONEG 0
55 #define PMM_SPEED_SMARTLINQ 0x8
57 u32 pause; /* bitmask */
58 #define PMM_PAUSE_NONE 0x0
59 #define PMM_PAUSE_AUTONEG 0x1
60 #define PMM_PAUSE_RX 0x2
61 #define PMM_PAUSE_TX 0x4
63 u32 adv_speed; /* Default should be the speed_cap_mask */
65 #define PMM_LOOPBACK_NONE 0
66 #define PMM_LOOPBACK_INT_PHY 1
67 #define PMM_LOOPBACK_EXT_PHY 2
68 #define PMM_LOOPBACK_EXT 3
69 #define PMM_LOOPBACK_MAC 4
70 #define PMM_LOOPBACK_CNIG_AH_ONLY_0123 5 /* Port to itself */
71 #define PMM_LOOPBACK_CNIG_AH_ONLY_2301 6 /* Port to Port */
74 u32 feature_config_flags;
79 u32 dynamic_cfg; /* device control channel */
80 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
81 #define PORT_MF_CFG_OV_TAG_SHIFT 0
82 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
87 /* DO NOT add new fields in the middle
88 * MUST be synced with struct pmm_stats_map
91 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
92 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
93 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
94 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
95 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
96 u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
97 u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged */
98 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
99 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
100 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
101 u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame ctr */
102 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
103 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
104 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
105 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
106 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
107 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
108 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
109 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
110 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
111 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
112 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
113 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
114 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
115 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
116 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
117 u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
118 u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
119 u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
120 u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
121 u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame ctr */
122 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
123 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
124 u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC */
125 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
126 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
127 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
128 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
129 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
130 u64 rxpok; /* 0x22 (Offset 0x138) RX good frame */
131 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
132 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
133 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
134 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
135 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
144 struct brb_stats brb;
145 struct pmm_stats pmm;
148 /*-----+-----------------------------------------------------------------------
149 * Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
150 * | rate of physical | team #1 | team #2 |are used|per path | (paths)
152 *======+==================+=========+=========+========+======================
153 * BB | 1x100G | This is special mode, where there are 2 HW func
154 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1
155 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
156 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
157 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2
158 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2
159 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2
160 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
161 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA
162 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
163 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
164 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
165 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
166 *======+==================+=========+=========+========+=======================
171 #define CMT_TEAM_MAX 2
173 struct couple_mode_teaming {
174 u8 port_cmt[MCP_GLOB_PORT_MAX];
175 #define PORT_CMT_IN_TEAM (1 << 0)
177 #define PORT_CMT_PORT_ROLE (1 << 1)
178 #define PORT_CMT_PORT_INACTIVE (0 << 1)
179 #define PORT_CMT_PORT_ACTIVE (1 << 1)
181 #define PORT_CMT_TEAM_MASK (1 << 2)
182 #define PORT_CMT_TEAM0 (0 << 2)
183 #define PORT_CMT_TEAM1 (1 << 2)
186 /**************************************
187 * LLDP and DCBX HSI structures
188 **************************************/
189 #define LLDP_CHASSIS_ID_STAT_LEN 4
190 #define LLDP_PORT_ID_STAT_LEN 4
191 #define DCBX_MAX_APP_PROTOCOL 32
192 #define MAX_SYSTEM_LLDP_TLV_DATA 32
194 typedef enum _lldp_agent_e {
195 LLDP_NEAREST_BRIDGE = 0,
196 LLDP_NEAREST_NON_TPMR_BRIDGE,
197 LLDP_NEAREST_CUSTOMER_BRIDGE,
201 struct lldp_config_params_s {
203 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
204 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
205 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
206 #define LLDP_CONFIG_HOLD_SHIFT 8
207 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
208 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
209 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
210 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
211 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
212 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
213 /* Holds local Chassis ID TLV header, subtype and 9B of payload.
214 * If firtst byte is 0, then we will use default chassis ID
216 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
217 /* Holds local Port ID TLV header, subtype and 9B of payload.
218 * If firtst byte is 0, then we will use default port ID
220 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
223 struct lldp_status_params_s {
225 u32 status; /* TBD */
226 /* Holds remote Chassis ID TLV header, subtype and 9B of payload.
228 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
229 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
230 /* Holds remote Port ID TLV header, subtype and 9B of payload.
232 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
236 struct dcbx_ets_feature {
238 #define DCBX_ETS_ENABLED_MASK 0x00000001
239 #define DCBX_ETS_ENABLED_SHIFT 0
240 #define DCBX_ETS_WILLING_MASK 0x00000002
241 #define DCBX_ETS_WILLING_SHIFT 1
242 #define DCBX_ETS_ERROR_MASK 0x00000004
243 #define DCBX_ETS_ERROR_SHIFT 2
244 #define DCBX_ETS_CBS_MASK 0x00000008
245 #define DCBX_ETS_CBS_SHIFT 3
246 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
247 #define DCBX_ETS_MAX_TCS_SHIFT 4
249 #define DCBX_CEE_STRICT_PRIORITY 0xf
250 #define DCBX_CEE_STRICT_PRIORITY_TC 0x7
253 #define DCBX_ETS_TSA_STRICT 0
254 #define DCBX_ETS_TSA_CBS 1
255 #define DCBX_ETS_TSA_ETS 2
258 struct dcbx_app_priority_entry {
260 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
261 #define DCBX_APP_PRI_MAP_SHIFT 0
262 #define DCBX_APP_PRI_0 0x01
263 #define DCBX_APP_PRI_1 0x02
264 #define DCBX_APP_PRI_2 0x04
265 #define DCBX_APP_PRI_3 0x08
266 #define DCBX_APP_PRI_4 0x10
267 #define DCBX_APP_PRI_5 0x20
268 #define DCBX_APP_PRI_6 0x40
269 #define DCBX_APP_PRI_7 0x80
270 #define DCBX_APP_SF_MASK 0x00000300
271 #define DCBX_APP_SF_SHIFT 8
272 #define DCBX_APP_SF_ETHTYPE 0
273 #define DCBX_APP_SF_PORT 1
274 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
275 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
278 /* FW structure in BE */
279 struct dcbx_app_priority_feature {
281 #define DCBX_APP_ENABLED_MASK 0x00000001
282 #define DCBX_APP_ENABLED_SHIFT 0
283 #define DCBX_APP_WILLING_MASK 0x00000002
284 #define DCBX_APP_WILLING_SHIFT 1
285 #define DCBX_APP_ERROR_MASK 0x00000004
286 #define DCBX_APP_ERROR_SHIFT 2
288 * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
289 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8
291 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
292 #define DCBX_APP_MAX_TCS_SHIFT 12
293 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
294 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
295 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
298 /* FW structure in BE */
299 struct dcbx_features {
301 struct dcbx_ets_feature ets;
304 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
305 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
306 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
307 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
308 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
309 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
310 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
311 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
312 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
313 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
315 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
316 #define DCBX_PFC_FLAGS_SHIFT 8
317 #define DCBX_PFC_CAPS_MASK 0x00000f00
318 #define DCBX_PFC_CAPS_SHIFT 8
319 #define DCBX_PFC_MBC_MASK 0x00004000
320 #define DCBX_PFC_MBC_SHIFT 14
321 #define DCBX_PFC_WILLING_MASK 0x00008000
322 #define DCBX_PFC_WILLING_SHIFT 15
323 #define DCBX_PFC_ENABLED_MASK 0x00010000
324 #define DCBX_PFC_ENABLED_SHIFT 16
325 #define DCBX_PFC_ERROR_MASK 0x00020000
326 #define DCBX_PFC_ERROR_SHIFT 17
329 struct dcbx_app_priority_feature app;
332 struct dcbx_local_params {
334 #define DCBX_CONFIG_VERSION_MASK 0x00000003
335 #define DCBX_CONFIG_VERSION_SHIFT 0
336 #define DCBX_CONFIG_VERSION_DISABLED 0
337 #define DCBX_CONFIG_VERSION_IEEE 1
338 #define DCBX_CONFIG_VERSION_CEE 2
341 struct dcbx_features features;
348 * #define DCBX_CONFIG_VERSION_MASK 0x00000003
349 * #define DCBX_CONFIG_VERSION_SHIFT 0
350 * #define DCBX_CONFIG_VERSION_DISABLED 0
351 * #define DCBX_CONFIG_VERSION_IEEE 1
352 * #define DCBX_CONFIG_VERSION_CEE 2
354 struct dcbx_features features;
358 struct lldp_system_tlvs_buffer_s {
361 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
364 /**************************************/
366 /* P U B L I C G L O B A L */
368 /**************************************/
369 struct public_global {
370 u32 max_path; /* 32bit is wasty, but this will be used often */
371 u32 max_ports; /* (Global) 32bit is wasty, this will be used often */
372 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */
377 u32 phymod_dbg_mb_offset;
378 struct couple_mode_teaming cmt;
379 s32 internal_temperature;
381 u32 running_bundle_id;
382 s32 external_temperature;
385 /**************************************/
387 /* P U B L I C P A T H */
389 /**************************************/
391 /****************************************************************************
392 * Shared Memory 2 Region *
393 ****************************************************************************/
394 /* The fw_flr_ack is actually built in the following way: */
396 /* 128 bit: VF ack */
397 /* 8 bit: ios_dis_ack */
398 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
399 /* u32. The fw must have the VF right after the PF since this is how it */
400 /* access arrays(it expects always the VF to reside after the PF, and that */
401 /* makes the calculation much easier for it. ) */
402 /* In order to answer both limitations, and keep the struct small, the code */
403 /* will abuse the structure defined here to achieve the actual partition */
405 /****************************************************************************/
409 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
410 #define ACCUM_ACK_PF_BASE 0
411 #define ACCUM_ACK_PF_SHIFT 0
413 #define ACCUM_ACK_VF_BASE 8
414 #define ACCUM_ACK_VF_SHIFT 3
416 #define ACCUM_ACK_IOV_DIS_BASE 256
417 #define ACCUM_ACK_IOV_DIS_SHIFT 8
422 struct fw_flr_mb flr_mb;
424 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
425 * which were disabled/flred
427 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
430 /* Reset on mcp reset, and incremented for eveny process kill event. */
431 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
432 #define PROCESS_KILL_COUNTER_SHIFT 0
433 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
434 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
435 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
438 /**************************************/
440 /* P U B L I C P O R T */
442 /**************************************/
443 #define FC_NPIV_WWPN_SIZE 8
444 #define FC_NPIV_WWNN_SIZE 8
445 struct dci_npiv_settings {
446 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
447 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
450 struct dci_fc_npiv_cfg {
451 /* hdr used internally by the MFW */
456 #define MAX_NUMBER_NPIV 64
457 struct dci_fc_npiv_tbl {
458 struct dci_fc_npiv_cfg fc_npiv_cfg;
459 struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
462 /****************************************************************************
463 * Driver <-> FW Mailbox *
464 ****************************************************************************/
467 u32 validity_map; /* 0x0 (4*2 = 0x8) */
470 #define MCP_VALIDITY_PCI_CFG 0x00100000
471 #define MCP_VALIDITY_MB 0x00200000
472 #define MCP_VALIDITY_DEV_INFO 0x00400000
473 #define MCP_VALIDITY_RESERVED 0x00000007
475 /* One licensing bit should be set */
476 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd */
477 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
478 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
479 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
482 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
483 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
484 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
485 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
488 #define LINK_STATUS_LINK_UP 0x00000001
489 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
490 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
491 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
492 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
493 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
494 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
495 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
496 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
497 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
499 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
501 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
502 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
504 #define LINK_STATUS_PFC_ENABLED 0x00000100
505 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
506 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
507 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
508 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
509 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
510 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
511 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
512 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
514 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
515 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
516 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
517 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
518 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
520 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
521 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
522 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
523 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
524 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
525 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
526 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
529 u32 ext_phy_fw_version;
530 u32 drv_phy_cfg_addr; /* Points to pmm_phy_cfg (For READ-ONLY) */
536 struct port_mf_cfg port_mf_config;
537 struct port_stats stats;
540 #define MEDIA_UNSPECIFIED 0x0
541 #define MEDIA_SFPP_10G_FIBER 0x1
542 #define MEDIA_XFP_FIBER 0x2
543 #define MEDIA_DA_TWINAX 0x3
544 #define MEDIA_BASE_T 0x4
545 #define MEDIA_SFP_1G_FIBER 0x5
546 #define MEDIA_MODULE_FIBER 0x6
547 #define MEDIA_KR 0xf0
548 #define MEDIA_NOT_PRESENT 0xff
551 #define LFA_LINK_FLAP_REASON_OFFSET 0
552 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
553 #define LFA_NO_REASON (0 << 0)
554 #define LFA_LINK_DOWN (1 << 0)
555 #define LFA_FORCE_INIT (1 << 1)
556 #define LFA_LOOPBACK_MISMATCH (1 << 2)
557 #define LFA_SPEED_MISMATCH (1 << 3)
558 #define LFA_FLOW_CTRL_MISMATCH (1 << 4)
559 #define LFA_ADV_SPEED_MISMATCH (1 << 5)
560 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
561 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
562 #define LINK_FLAP_COUNT_OFFSET 16
563 #define LINK_FLAP_COUNT_MASK 0x00ff0000
565 u32 link_change_count;
568 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
569 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
570 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
572 /* DCBX related MIB */
573 struct dcbx_local_params local_admin_dcbx_mib;
574 struct dcbx_mib remote_dcbx_mib;
575 struct dcbx_mib operational_dcbx_mib;
577 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
578 u32 fc_npiv_nvram_tbl_addr;
579 u32 fc_npiv_nvram_tbl_size;
580 u32 transceiver_data;
581 #define PMM_TRANSCEIVER_STATE_MASK 0x000000FF
582 #define PMM_TRANSCEIVER_STATE_SHIFT 0x00000000
583 #define PMM_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
584 #define PMM_TRANSCEIVER_STATE_PRESENT 0x00000001
585 #define PMM_TRANSCEIVER_STATE_VALID 0x00000003
586 #define PMM_TRANSCEIVER_STATE_UPDATING 0x00000008
587 #define PMM_TRANSCEIVER_TYPE_MASK 0x0000FF00
588 #define PMM_TRANSCEIVER_TYPE_SHIFT 0x00000008
589 #define PMM_TRANSCEIVER_TYPE_NONE 0x00000000
590 #define PMM_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF
591 #define PMM_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */
592 #define PMM_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */
593 #define PMM_TRANSCEIVER_TYPE_1G_LX 0x03
594 #define PMM_TRANSCEIVER_TYPE_1G_SX 0x04
595 #define PMM_TRANSCEIVER_TYPE_10G_SR 0x05
596 #define PMM_TRANSCEIVER_TYPE_10G_LR 0x06
597 #define PMM_TRANSCEIVER_TYPE_10G_LRM 0x07
598 #define PMM_TRANSCEIVER_TYPE_10G_ER 0x08
599 #define PMM_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */
600 #define PMM_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */
601 #define PMM_TRANSCEIVER_TYPE_XLPPI 0x0b
602 #define PMM_TRANSCEIVER_TYPE_40G_LR4 0x0c
603 #define PMM_TRANSCEIVER_TYPE_40G_SR4 0x0d
604 #define PMM_TRANSCEIVER_TYPE_40G_CR4 0x0e
605 #define PMM_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */
606 #define PMM_TRANSCEIVER_TYPE_100G_SR4 0x10
607 #define PMM_TRANSCEIVER_TYPE_100G_LR4 0x11
608 #define PMM_TRANSCEIVER_TYPE_100G_ER4 0x12
609 #define PMM_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */
610 #define PMM_TRANSCEIVER_TYPE_100G_CR4 0x14
611 #define PMM_TRANSCEIVER_TYPE_4x10G_SR 0x15
612 #define PMM_TRANSCEIVER_TYPE_25G_PCC_S 0x16
613 #define PMM_TRANSCEIVER_TYPE_25G_ACC_S 0x17
614 #define PMM_TRANSCEIVER_TYPE_25G_PCC_M 0x18
615 #define PMM_TRANSCEIVER_TYPE_25G_ACC_M 0x19
616 #define PMM_TRANSCEIVER_TYPE_25G_PCC_L 0x1a
617 #define PMM_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
618 #define PMM_TRANSCEIVER_TYPE_25G_SR 0x1c
619 #define PMM_TRANSCEIVER_TYPE_25G_LR 0x1d
620 #define PMM_TRANSCEIVER_TYPE_25G_AOC 0x1e
622 #define PMM_TRANSCEIVER_TYPE_4x10G 0x1d
623 #define PMM_TRANSCEIVER_TYPE_4x25G_CR 0x1e
624 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40GR 0x30
625 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
626 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
627 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
628 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
629 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
630 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
633 /**************************************/
635 /* P U B L I C F U N C */
637 /**************************************/
642 /* MTU size per funciton is needed for the OV feature */
644 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
645 /* For PCP values 0-3 use the map lower */
646 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
647 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
649 u32 c2s_pcp_map_lower;
650 /* For PCP values 4-7 use the map upper */
651 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
652 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
654 u32 c2s_pcp_map_upper;
656 /* For PCP default value get the MSB byte of the map default */
657 u32 c2s_pcp_map_default;
661 /* replace old mf_cfg */
664 /* function 0 of each port cannot be hidden */
665 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
666 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
667 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
669 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
670 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
671 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
672 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000000
675 /* value range - 0..100, increments in 1 % */
676 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
677 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
678 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
679 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
680 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
681 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
684 #define FUNC_STATUS_VLINK_DOWN 0x00000001
686 u32 mac_upper; /* MAC */
687 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
688 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
689 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
691 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
695 u32 ovlan_stag; /* tags */
696 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
697 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
698 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
700 u32 pf_allocation; /* vf per pf */
702 u32 preserve_data; /* Will be used bt CCM */
704 u32 driver_last_activity_ts;
707 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
710 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
713 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
714 #define DRV_ID_PDA_COMP_VER_SHIFT 0
716 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
717 #define DRV_ID_MCP_HSI_VER_SHIFT 16
718 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT)
720 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
721 #define DRV_ID_DRV_TYPE_SHIFT 24
722 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
723 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
724 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
725 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
726 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
727 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
728 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
729 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
730 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
732 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
733 #define DRV_ID_DRV_INIT_HW_SHIFT 31
734 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
737 /**************************************/
739 /* P U B L I C M B */
741 /**************************************/
742 /* This is the only section that the driver can write to, and each */
743 /* Basically each driver request to set feature parameters,
744 * will be done using a different command, which will be linked
745 * to a specific data structure from the union below.
746 * For huge strucuture, the common blank structure should be used.
750 u32 mac_upper; /* Upper 16 bits are always zeroes */
759 struct mcp_file_att {
764 struct bist_nvm_image_att {
766 u32 image_type; /* Image type */
767 u32 nvm_start_addr; /* NVM address of the image */
768 u32 len; /* Include CRC */
771 #define MCP_DRV_VER_STR_SIZE 16
772 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
773 #define MCP_DRV_NVM_BUF_LEN 32
774 struct drv_version_stc {
776 u8 name[MCP_DRV_VER_STR_SIZE - 4];
779 /* statistics for ncsi */
780 struct lan_stats_stc {
787 struct ocbb_data_stc {
790 u32 ocsd_req_update_interval;
793 #define MAX_NUM_OF_SENSORS 7
794 #define MFW_SENSOR_LOCATION_INTERNAL 1
795 #define MFW_SENSOR_LOCATION_EXTERNAL 2
796 #define MFW_SENSOR_LOCATION_SFP 3
798 #define SENSOR_LOCATION_SHIFT 0
799 #define SENSOR_LOCATION_MASK 0x000000ff
800 #define THRESHOLD_HIGH_SHIFT 8
801 #define THRESHOLD_HIGH_MASK 0x0000ff00
802 #define CRITICAL_TEMPERATURE_SHIFT 16
803 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000
804 #define CURRENT_TEMP_SHIFT 24
805 #define CURRENT_TEMP_MASK 0xff000000
806 struct temperature_status_stc {
808 u32 sensor[MAX_NUM_OF_SENSORS];
811 enum resource_id_enum {
812 RESOURCE_NUM_SB_E = 0,
813 RESOURCE_NUM_L2_QUEUE_E = 1,
814 RESOURCE_NUM_VPORT_E = 2,
815 RESOURCE_NUM_VMQ_E = 3,
816 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
817 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
818 RESOURCE_NUM_RL_E = 6,
819 RESOURCE_NUM_PQ_E = 7,
820 RESOURCE_NUM_VF_E = 8,
821 RESOURCE_VFC_FILTER_E = 9,
824 RESOURCE_GFT_PROFILES_E = 12,
825 RESOURCE_NUM_TC_E = 13,
826 RESOURCE_NUM_RSS_ENGINES_E = 14,
827 RESOURCE_LL2_QUEUE_E = 15,
828 RESOURCE_RDMA_STATS_QUEUE_E = 16,
830 RESOURCE_NUM_INVALID = 0xFFFFFFFF
833 /* Resource ID is to be filled by the driver in the MB request
834 * Size, offset & flags to be filled by the MFW in the MB response
836 struct resource_info {
837 enum resource_id_enum res_id;
838 u32 size; /* number of allocated resources */
839 u32 offset; /* Offset of the 1st resource */
843 #define RESOURCE_ELEMENT_STRICT (1 << 0)
846 union drv_union_data {
847 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */
848 struct mcp_mac wol_mac; /* UNLOAD_DONE */
850 struct pmm_phy_cfg drv_phy_cfg;
852 struct mcp_val64 val64; /* For PHY / AVS commands */
854 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
856 struct mcp_file_att file_att;
858 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
860 struct drv_version_stc drv_version;
862 struct lan_stats_stc lan_stats;
864 struct ocbb_data_stc ocbb_info;
865 struct temperature_status_stc temp_info;
866 struct resource_info resource;
867 struct bist_nvm_image_att nvm_image_att;
872 struct public_drv_mb {
874 #define DRV_MSG_CODE_MASK 0xffff0000
875 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
876 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
877 #define DRV_MSG_CODE_INIT_HW 0x12000000
878 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
879 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
880 #define DRV_MSG_CODE_INIT_PHY 0x22000000
881 /* Params - FORCE - Reinitialize the link regardless of LFA */
882 /* - DONT_CARE - Don't flap the link if up */
883 #define DRV_MSG_CODE_LINK_RESET 0x23000000
885 /* Vitaly: LLDP commands */
886 #define DRV_MSG_CODE_SET_LLDP 0x24000000
887 #define DRV_MSG_CODE_SET_DCBX 0x25000000
888 /* OneView feature driver HSI*/
889 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
890 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
891 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
892 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
893 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
894 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
895 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
897 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
899 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
901 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
902 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
903 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
904 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
905 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
906 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
907 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
908 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
909 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
910 #define DRV_MSG_CODE_MCP_RESET 0x00090000
911 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
912 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
913 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
914 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
915 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
916 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
917 #define DRV_MSG_CODE_MCP_HALT 0x00100000
918 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000
919 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000
920 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
921 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000
923 #define DRV_MSG_CODE_SET_VMAC 0x00110000
924 #define DRV_MSG_CODE_GET_VMAC 0x00120000
925 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
926 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
927 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
929 #define DRV_MSG_CODE_GET_STATS 0x00130000
930 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
932 #define DRV_MSG_CODE_OCBB_DATA 0x00180000
933 #define DRV_MSG_CODE_SET_BW 0x00190000
934 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
935 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000
936 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
937 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1)
939 #define DRV_MSG_CODE_GPIO_READ 0x001c0000
940 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000
941 #define DRV_MSG_CODE_GPIO_INFO 0x00270000
943 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
944 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
946 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
947 #define DRV_MSG_CODE_TIMESTAMP 0x00210000
948 #define DRV_MSG_CODE_EMPTY_MB 0x00220000
950 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000
951 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000
953 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
956 /* UNLOAD_REQ params */
957 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
958 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
959 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
960 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
962 /* UNLOAD_DONE_params */
963 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
965 /* INIT_PHY params */
966 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
967 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
969 /* LLDP / DCBX params*/
970 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
971 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
972 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
973 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
974 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
975 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
977 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
978 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
980 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
981 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
983 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
984 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
985 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
986 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
988 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
989 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
990 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16
991 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
992 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
993 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
994 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30
995 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
997 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0
998 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
999 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8
1000 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
1001 /* configure vf MSIX params*/
1002 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
1003 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
1004 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
1005 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
1007 /* OneView configuration parametres */
1008 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
1009 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
1010 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
1011 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
1012 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
1013 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
1014 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4
1015 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5
1016 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6
1017 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7
1019 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0
1020 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
1021 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
1022 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2)
1023 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4)
1024 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5)
1025 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
1026 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
1028 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0
1029 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
1031 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
1032 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
1033 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
1034 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
1035 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
1036 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
1038 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
1039 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
1040 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
1041 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
1042 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
1043 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
1044 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
1046 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
1047 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
1049 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
1050 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
1051 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
1053 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0
1054 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
1055 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2
1056 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
1057 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8
1058 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
1059 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16
1060 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
1062 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0
1063 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
1064 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16
1065 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
1067 #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16
1068 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
1069 #define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24
1070 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
1072 /* Resource Allocation params - Driver version support*/
1073 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1074 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
1075 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1076 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
1078 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
1079 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
1080 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
1081 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
1082 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
1084 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
1085 #define DRV_MB_PARAM_BIST_RC_PASSED 1
1086 #define DRV_MB_PARAM_BIST_RC_FAILED 2
1087 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
1089 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
1090 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
1091 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
1092 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
1095 #define FW_MSG_CODE_MASK 0xffff0000
1096 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
1097 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1098 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1099 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
1100 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
1101 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
1102 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1103 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
1104 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
1105 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
1106 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1107 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
1108 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
1109 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
1110 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
1111 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
1112 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
1113 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000
1114 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000
1115 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000
1116 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000
1117 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
1118 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1119 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
1120 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
1121 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1122 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
1123 #define FW_MSG_CODE_FLR_ACK 0x02000000
1124 #define FW_MSG_CODE_FLR_NACK 0x02100000
1125 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000
1126 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000
1127 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000
1129 #define FW_MSG_CODE_NVM_OK 0x00010000
1130 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
1131 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
1132 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
1133 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
1134 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
1135 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1136 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1137 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
1138 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
1139 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
1140 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
1141 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
1142 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
1143 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
1144 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
1145 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
1146 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
1147 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
1148 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
1149 #define FW_MSG_CODE_PHY_OK 0x00110000
1150 #define FW_MSG_CODE_PHY_ERROR 0x00120000
1151 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
1152 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
1153 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
1154 #define FW_MSG_CODE_OK 0x00160000
1155 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000
1156 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000
1157 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000
1158 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000
1159 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000
1160 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1161 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000
1162 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000
1163 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
1164 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
1165 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
1166 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
1167 #define FW_MSG_CODE_GPIO_OK 0x00160000
1168 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000
1169 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
1170 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000
1171 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
1173 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1178 #define DRV_PULSE_SEQ_MASK 0x00007fff
1179 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1181 * The system time is in the format of
1182 * (year-2001)*12*32 + month*32 + day.
1184 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1186 * Indicate to the firmware not to go into the
1187 * OS-absent when it is not getting driver pulse.
1188 * This is used for debugging as well for PXE(MBA).
1192 #define MCP_PULSE_SEQ_MASK 0x00007fff
1193 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1194 /* Indicates to the driver not to assert due to lack
1197 #define MCP_EVENT_MASK 0xffff0000
1198 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1200 union drv_union_data union_data;
1204 /**********************************************************************
1206 * Incremental Aggregative
1207 * 8-bit MFW counter per message
1208 * 8-bit ack-counter per message
1210 * Provides up to 256 aggregative message per type
1211 * Provides 4 message types in dword
1212 * Message type pointers to byte offset
1213 * Backward Compatibility by using sizeof for the counters.
1214 * No lock requires for 32bit messages
1216 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
1217 * is required to prevent data corruption.
1218 **********************************************************************/
1219 enum MFW_DRV_MSG_TYPE {
1220 MFW_DRV_MSG_LINK_CHANGE,
1221 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1222 MFW_DRV_MSG_VF_DISABLED,
1223 MFW_DRV_MSG_LLDP_DATA_UPDATED,
1224 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1225 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1226 MFW_DRV_MSG_ERROR_RECOVERY,
1227 MFW_DRV_MSG_BW_UPDATE,
1228 MFW_DRV_MSG_S_TAG_UPDATE,
1229 MFW_DRV_MSG_GET_LAN_STATS,
1230 MFW_DRV_MSG_GET_FCOE_STATS,
1231 MFW_DRV_MSG_GET_ISCSI_STATS,
1232 MFW_DRV_MSG_GET_RDMA_STATS,
1233 MFW_DRV_MSG_FAILURE_DETECTED,
1234 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1238 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
1239 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
1240 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
1241 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1243 #ifdef BIG_ENDIAN /* Like MFW */
1244 #define DRV_ACK_MSG(msg_p, msg_id) \
1245 ((u8)((u8 *)msg_p)[msg_id]++;)
1247 #define DRV_ACK_MSG(msg_p, msg_id) \
1248 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;)
1251 #define MFW_DRV_UPDATE(shmem_func, msg_id) \
1252 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;)
1254 struct public_mfw_mb {
1255 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */
1256 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1257 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1260 /**************************************/
1262 /* P U B L I C D A T A */
1264 /**************************************/
1265 enum public_sections {
1266 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
1267 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
1275 struct drv_ver_info_stc {
1280 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1281 * Please make sure data does not exceed this size.
1283 #define NUM_RUNTIME_DWORDS 16
1284 struct drv_init_hw_stc {
1285 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1286 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1289 struct mcp_public_data {
1290 /* The sections fields is an array */
1292 offsize_t sections[PUBLIC_MAX_SECTIONS];
1293 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1294 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1295 struct public_global global;
1296 struct public_path path[MCP_GLOB_PATH_MAX];
1297 struct public_port port[MCP_GLOB_PORT_MAX];
1298 struct public_func func[MCP_GLOB_FUNC_MAX];
1301 #define I2C_TRANSCEIVER_ADDR 0xa0
1302 #define MAX_I2C_TRANSACTION_SIZE 16
1303 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256
1305 #endif /* MCP_PUBLIC_H */