2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: MCP public data
15 * Created: 13/01/2013 yanivr
17 ****************************************************************************/
22 #define VF_MAX_STATIC 192 /* In case of AH */
24 #define MCP_GLOB_PATH_MAX 2
25 #define MCP_PORT_MAX 2 /* Global */
26 #define MCP_GLOB_PORT_MAX 4 /* Global */
27 #define MCP_GLOB_FUNC_MAX 16 /* Global */
29 typedef u32 offsize_t; /* In DWORDS !!! */
30 /* Offset from the beginning of the MCP scratchpad */
31 #define OFFSIZE_OFFSET_SHIFT 0
32 #define OFFSIZE_OFFSET_MASK 0x0000ffff
33 /* Size of specific element (not the whole array if any) */
34 #define OFFSIZE_SIZE_SHIFT 16
35 #define OFFSIZE_SIZE_MASK 0xffff0000
37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
38 #define SECTION_OFFSET(_offsize) \
39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))
41 /* SECTION_SIZE is calculating the size in bytes out of offsize */
42 #define SECTION_SIZE(_offsize) \
43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)
45 #define SECTION_ADDR(_offsize, idx) \
46 (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
48 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
49 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
51 /* PHY configuration */
53 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
54 #define PMM_SPEED_AUTONEG 0
55 #define PMM_SPEED_SMARTLINQ 0x8
57 u32 pause; /* bitmask */
58 #define PMM_PAUSE_NONE 0x0
59 #define PMM_PAUSE_AUTONEG 0x1
60 #define PMM_PAUSE_RX 0x2
61 #define PMM_PAUSE_TX 0x4
63 u32 adv_speed; /* Default should be the speed_cap_mask */
65 #define PMM_LOOPBACK_NONE 0
66 #define PMM_LOOPBACK_INT_PHY 1
67 #define PMM_LOOPBACK_EXT_PHY 2
68 #define PMM_LOOPBACK_EXT 3
69 #define PMM_LOOPBACK_MAC 4
70 #define PMM_LOOPBACK_CNIG_AH_ONLY_0123 5 /* Port to itself */
71 #define PMM_LOOPBACK_CNIG_AH_ONLY_2301 6 /* Port to Port */
74 u32 feature_config_flags;
79 u32 dynamic_cfg; /* device control channel */
80 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
81 #define PORT_MF_CFG_OV_TAG_SHIFT 0
82 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
87 /* DO NOT add new fields in the middle
88 * MUST be synced with struct pmm_stats_map
91 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter */
92 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter */
93 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter */
94 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter */
95 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter */
96 u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
97 u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged */
98 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter */
99 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter */
100 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter */
101 u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame ctr */
102 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter */
103 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter */
104 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter */
105 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter */
106 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter */
107 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
108 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter */
109 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
110 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
111 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
112 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
113 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
114 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter */
115 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter */
116 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter */
117 u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
118 u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
119 u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
120 u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
121 u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame ctr */
122 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
123 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
124 u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC */
125 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
126 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
127 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
128 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
129 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
130 u64 rxpok; /* 0x22 (Offset 0x138) RX good frame */
131 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
132 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
133 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
134 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
135 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
144 struct brb_stats brb;
145 struct pmm_stats pmm;
148 /*-----+-----------------------------------------------------------------------
149 * Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
150 * | rate of physical | team #1 | team #2 |are used|per path | (paths)
152 *======+==================+=========+=========+========+======================
153 * BB | 1x100G | This is special mode, where there are 2 HW func
154 * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1
155 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
156 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
157 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2
158 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2
159 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2
160 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
161 * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA
162 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
163 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
164 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
165 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
166 *======+==================+=========+=========+========+=======================
171 #define CMT_TEAM_MAX 2
173 struct couple_mode_teaming {
174 u8 port_cmt[MCP_GLOB_PORT_MAX];
175 #define PORT_CMT_IN_TEAM (1 << 0)
177 #define PORT_CMT_PORT_ROLE (1 << 1)
178 #define PORT_CMT_PORT_INACTIVE (0 << 1)
179 #define PORT_CMT_PORT_ACTIVE (1 << 1)
181 #define PORT_CMT_TEAM_MASK (1 << 2)
182 #define PORT_CMT_TEAM0 (0 << 2)
183 #define PORT_CMT_TEAM1 (1 << 2)
186 /**************************************/
188 /* P U B L I C G L O B A L */
190 /**************************************/
191 struct public_global {
192 u32 max_path; /* 32bit is wasty, but this will be used often */
193 u32 max_ports; /* (Global) 32bit is wasty, this will be used often */
194 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */
199 u32 phymod_dbg_mb_offset;
200 struct couple_mode_teaming cmt;
201 s32 internal_temperature;
203 u32 running_bundle_id;
204 s32 external_temperature;
207 /**************************************/
209 /* P U B L I C P A T H */
211 /**************************************/
213 /****************************************************************************
214 * Shared Memory 2 Region *
215 ****************************************************************************/
216 /* The fw_flr_ack is actually built in the following way: */
218 /* 128 bit: VF ack */
219 /* 8 bit: ios_dis_ack */
220 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
221 /* u32. The fw must have the VF right after the PF since this is how it */
222 /* access arrays(it expects always the VF to reside after the PF, and that */
223 /* makes the calculation much easier for it. ) */
224 /* In order to answer both limitations, and keep the struct small, the code */
225 /* will abuse the structure defined here to achieve the actual partition */
227 /****************************************************************************/
231 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
232 #define ACCUM_ACK_PF_BASE 0
233 #define ACCUM_ACK_PF_SHIFT 0
235 #define ACCUM_ACK_VF_BASE 8
236 #define ACCUM_ACK_VF_SHIFT 3
238 #define ACCUM_ACK_IOV_DIS_BASE 256
239 #define ACCUM_ACK_IOV_DIS_SHIFT 8
244 struct fw_flr_mb flr_mb;
246 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
247 * which were disabled/flred
249 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
252 /* Reset on mcp reset, and incremented for eveny process kill event. */
253 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
254 #define PROCESS_KILL_COUNTER_SHIFT 0
255 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
256 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
257 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
260 /**************************************/
262 /* P U B L I C P O R T */
264 /**************************************/
265 #define FC_NPIV_WWPN_SIZE 8
266 #define FC_NPIV_WWNN_SIZE 8
267 struct dci_npiv_settings {
268 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
269 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
272 struct dci_fc_npiv_cfg {
273 /* hdr used internally by the MFW */
278 #define MAX_NUMBER_NPIV 64
279 struct dci_fc_npiv_tbl {
280 struct dci_fc_npiv_cfg fc_npiv_cfg;
281 struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
284 /****************************************************************************
285 * Driver <-> FW Mailbox *
286 ****************************************************************************/
289 u32 validity_map; /* 0x0 (4*2 = 0x8) */
292 #define MCP_VALIDITY_PCI_CFG 0x00100000
293 #define MCP_VALIDITY_MB 0x00200000
294 #define MCP_VALIDITY_DEV_INFO 0x00400000
295 #define MCP_VALIDITY_RESERVED 0x00000007
297 /* One licensing bit should be set */
298 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd */
299 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
300 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
301 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
304 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
305 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
306 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
307 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
310 #define LINK_STATUS_LINK_UP 0x00000001
311 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
312 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
313 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
314 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
315 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
316 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
317 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
318 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
319 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
321 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
323 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
324 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
326 #define LINK_STATUS_PFC_ENABLED 0x00000100
327 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
328 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
329 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
330 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
331 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
332 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
333 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
334 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
336 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
337 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
338 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
339 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
340 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
342 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
343 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
344 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
345 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
346 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
347 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
348 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
351 u32 ext_phy_fw_version;
352 u32 drv_phy_cfg_addr; /* Points to pmm_phy_cfg (For READ-ONLY) */
358 struct port_mf_cfg port_mf_config;
359 struct port_stats stats;
362 #define MEDIA_UNSPECIFIED 0x0
363 #define MEDIA_SFPP_10G_FIBER 0x1
364 #define MEDIA_XFP_FIBER 0x2
365 #define MEDIA_DA_TWINAX 0x3
366 #define MEDIA_BASE_T 0x4
367 #define MEDIA_SFP_1G_FIBER 0x5
368 #define MEDIA_MODULE_FIBER 0x6
369 #define MEDIA_KR 0xf0
370 #define MEDIA_NOT_PRESENT 0xff
373 #define LFA_LINK_FLAP_REASON_OFFSET 0
374 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
375 #define LFA_NO_REASON (0 << 0)
376 #define LFA_LINK_DOWN (1 << 0)
377 #define LFA_FORCE_INIT (1 << 1)
378 #define LFA_LOOPBACK_MISMATCH (1 << 2)
379 #define LFA_SPEED_MISMATCH (1 << 3)
380 #define LFA_FLOW_CTRL_MISMATCH (1 << 4)
381 #define LFA_ADV_SPEED_MISMATCH (1 << 5)
382 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
383 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
384 #define LINK_FLAP_COUNT_OFFSET 16
385 #define LINK_FLAP_COUNT_MASK 0x00ff0000
387 u32 link_change_count;
389 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
390 u32 fc_npiv_nvram_tbl_addr;
391 u32 fc_npiv_nvram_tbl_size;
392 u32 transceiver_data;
393 #define PMM_TRANSCEIVER_STATE_MASK 0x000000FF
394 #define PMM_TRANSCEIVER_STATE_SHIFT 0x00000000
395 #define PMM_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
396 #define PMM_TRANSCEIVER_STATE_PRESENT 0x00000001
397 #define PMM_TRANSCEIVER_STATE_VALID 0x00000003
398 #define PMM_TRANSCEIVER_STATE_UPDATING 0x00000008
399 #define PMM_TRANSCEIVER_TYPE_MASK 0x0000FF00
400 #define PMM_TRANSCEIVER_TYPE_SHIFT 0x00000008
401 #define PMM_TRANSCEIVER_TYPE_NONE 0x00000000
402 #define PMM_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF
403 #define PMM_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */
404 #define PMM_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */
405 #define PMM_TRANSCEIVER_TYPE_1G_LX 0x03
406 #define PMM_TRANSCEIVER_TYPE_1G_SX 0x04
407 #define PMM_TRANSCEIVER_TYPE_10G_SR 0x05
408 #define PMM_TRANSCEIVER_TYPE_10G_LR 0x06
409 #define PMM_TRANSCEIVER_TYPE_10G_LRM 0x07
410 #define PMM_TRANSCEIVER_TYPE_10G_ER 0x08
411 #define PMM_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */
412 #define PMM_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */
413 #define PMM_TRANSCEIVER_TYPE_XLPPI 0x0b
414 #define PMM_TRANSCEIVER_TYPE_40G_LR4 0x0c
415 #define PMM_TRANSCEIVER_TYPE_40G_SR4 0x0d
416 #define PMM_TRANSCEIVER_TYPE_40G_CR4 0x0e
417 #define PMM_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */
418 #define PMM_TRANSCEIVER_TYPE_100G_SR4 0x10
419 #define PMM_TRANSCEIVER_TYPE_100G_LR4 0x11
420 #define PMM_TRANSCEIVER_TYPE_100G_ER4 0x12
421 #define PMM_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */
422 #define PMM_TRANSCEIVER_TYPE_100G_CR4 0x14
423 #define PMM_TRANSCEIVER_TYPE_4x10G_SR 0x15
424 #define PMM_TRANSCEIVER_TYPE_25G_PCC_S 0x16
425 #define PMM_TRANSCEIVER_TYPE_25G_ACC_S 0x17
426 #define PMM_TRANSCEIVER_TYPE_25G_PCC_M 0x18
427 #define PMM_TRANSCEIVER_TYPE_25G_ACC_M 0x19
428 #define PMM_TRANSCEIVER_TYPE_25G_PCC_L 0x1a
429 #define PMM_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
430 #define PMM_TRANSCEIVER_TYPE_25G_SR 0x1c
431 #define PMM_TRANSCEIVER_TYPE_25G_LR 0x1d
432 #define PMM_TRANSCEIVER_TYPE_25G_AOC 0x1e
434 #define PMM_TRANSCEIVER_TYPE_4x10G 0x1d
435 #define PMM_TRANSCEIVER_TYPE_4x25G_CR 0x1e
436 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40GR 0x30
437 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
438 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
439 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
440 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
441 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
442 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
445 /**************************************/
447 /* P U B L I C F U N C */
449 /**************************************/
454 /* MTU size per funciton is needed for the OV feature */
456 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
457 /* For PCP values 0-3 use the map lower */
458 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
459 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
461 u32 c2s_pcp_map_lower;
462 /* For PCP values 4-7 use the map upper */
463 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
464 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
466 u32 c2s_pcp_map_upper;
468 /* For PCP default value get the MSB byte of the map default */
469 u32 c2s_pcp_map_default;
473 /* replace old mf_cfg */
476 /* function 0 of each port cannot be hidden */
477 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
478 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
479 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
481 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
482 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
483 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
484 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000000
487 /* value range - 0..100, increments in 1 % */
488 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
489 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
490 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
491 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
492 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
493 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
496 #define FUNC_STATUS_VLINK_DOWN 0x00000001
498 u32 mac_upper; /* MAC */
499 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
500 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
501 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
503 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
507 u32 ovlan_stag; /* tags */
508 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
509 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
510 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
512 u32 pf_allocation; /* vf per pf */
514 u32 preserve_data; /* Will be used bt CCM */
516 u32 driver_last_activity_ts;
519 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
522 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
525 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
526 #define DRV_ID_PDA_COMP_VER_SHIFT 0
528 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
529 #define DRV_ID_MCP_HSI_VER_SHIFT 16
530 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT)
532 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
533 #define DRV_ID_DRV_TYPE_SHIFT 24
534 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
535 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
536 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
537 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
538 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
539 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
540 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
541 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
542 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
544 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
545 #define DRV_ID_DRV_INIT_HW_SHIFT 31
546 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
549 /**************************************/
551 /* P U B L I C M B */
553 /**************************************/
554 /* This is the only section that the driver can write to, and each */
555 /* Basically each driver request to set feature parameters,
556 * will be done using a different command, which will be linked
557 * to a specific data structure from the union below.
558 * For huge strucuture, the common blank structure should be used.
562 u32 mac_upper; /* Upper 16 bits are always zeroes */
571 struct mcp_file_att {
576 #define MCP_DRV_VER_STR_SIZE 16
577 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
578 #define MCP_DRV_NVM_BUF_LEN 32
579 struct drv_version_stc {
581 u8 name[MCP_DRV_VER_STR_SIZE - 4];
584 /* statistics for ncsi */
585 struct lan_stats_stc {
592 struct ocbb_data_stc {
595 u32 ocsd_req_update_interval;
598 union drv_union_data {
599 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */
600 struct mcp_mac wol_mac; /* UNLOAD_DONE */
602 struct pmm_phy_cfg drv_phy_cfg;
604 struct mcp_val64 val64; /* For PHY / AVS commands */
606 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
608 struct mcp_file_att file_att;
610 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
612 struct drv_version_stc drv_version;
614 struct lan_stats_stc lan_stats;
616 struct ocbb_data_stc ocbb_info;
621 struct public_drv_mb {
623 #define DRV_MSG_CODE_MASK 0xffff0000
624 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
625 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
626 #define DRV_MSG_CODE_INIT_HW 0x12000000
627 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
628 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
629 #define DRV_MSG_CODE_INIT_PHY 0x22000000
630 /* Params - FORCE - Reinitialize the link regardless of LFA */
631 /* - DONT_CARE - Don't flap the link if up */
632 #define DRV_MSG_CODE_LINK_RESET 0x23000000
634 /* OneView feature driver HSI */
635 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
636 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
637 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
638 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
639 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
640 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
641 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
643 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
645 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
646 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
647 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
648 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
649 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
650 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
651 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
652 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
653 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
654 #define DRV_MSG_CODE_MCP_RESET 0x00090000
655 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
656 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
657 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
658 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
659 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
660 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
661 #define DRV_MSG_CODE_MCP_HALT 0x00100000
662 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000
663 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000
664 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
665 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000
667 #define DRV_MSG_CODE_SET_VMAC 0x00110000
668 #define DRV_MSG_CODE_GET_VMAC 0x00120000
669 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
670 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
671 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
673 #define DRV_MSG_CODE_GET_STATS 0x00130000
674 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
676 #define DRV_MSG_CODE_OCBB_DATA 0x00180000
677 #define DRV_MSG_CODE_SET_BW 0x00190000
678 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
679 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000
680 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
681 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1)
683 #define DRV_MSG_CODE_GPIO_READ 0x001c0000
684 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000
686 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
687 #define DRV_MSG_CODE_EMPTY_MB 0x00220000
689 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
692 /* UNLOAD_REQ params */
693 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
694 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
695 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
696 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
698 /* UNLOAD_DONE_params */
699 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
701 /* INIT_PHY params */
702 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
703 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
705 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
706 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
708 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
709 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
711 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
712 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
713 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
714 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
716 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
717 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
718 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16
719 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
720 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
721 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
722 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30
723 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
725 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0
726 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
727 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8
728 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
729 /* configure vf MSIX params */
730 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
731 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
732 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
733 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
735 /* OneView configuration parametres */
736 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
737 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
738 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
739 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
740 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
741 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
742 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4
743 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5
744 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6
745 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7
747 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0
748 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
749 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
750 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2)
751 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4)
752 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5)
753 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
754 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
756 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0
757 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
759 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
760 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
761 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
762 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
763 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
764 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
766 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
767 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
768 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
769 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
770 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
771 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
772 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
774 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
775 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
777 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
778 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
779 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
781 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0
782 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
783 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2
784 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
785 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8
786 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
787 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16
788 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
790 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0
791 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
792 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16
793 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
796 #define FW_MSG_CODE_MASK 0xffff0000
797 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
798 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
799 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
800 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
801 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
802 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
803 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
804 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
805 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
806 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
807 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
808 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
809 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
810 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
811 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000
812 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000
813 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000
814 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000
815 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
816 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
817 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
818 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
819 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
820 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
821 #define FW_MSG_CODE_FLR_ACK 0x02000000
822 #define FW_MSG_CODE_FLR_NACK 0x02100000
823 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000
824 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000
825 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000
827 #define FW_MSG_CODE_NVM_OK 0x00010000
828 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
829 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
830 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
831 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
832 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
833 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
834 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
835 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
836 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
837 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
838 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
839 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
840 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
841 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
842 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
843 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
844 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
845 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
846 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
847 #define FW_MSG_CODE_PHY_OK 0x00110000
848 #define FW_MSG_CODE_PHY_ERROR 0x00120000
849 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
850 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
851 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
852 #define FW_MSG_CODE_OK 0x00160000
853 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000
854 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000
855 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000
856 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000
857 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000
858 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
859 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000
860 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000
861 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
862 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
863 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
864 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
865 #define FW_MSG_CODE_GPIO_OK 0x00160000
866 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000
867 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
868 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000
869 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
871 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
876 #define DRV_PULSE_SEQ_MASK 0x00007fff
877 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
879 * The system time is in the format of
880 * (year-2001)*12*32 + month*32 + day.
882 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
884 * Indicate to the firmware not to go into the
885 * OS-absent when it is not getting driver pulse.
886 * This is used for debugging as well for PXE(MBA).
890 #define MCP_PULSE_SEQ_MASK 0x00007fff
891 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
892 /* Indicates to the driver not to assert due to lack
895 #define MCP_EVENT_MASK 0xffff0000
896 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
898 union drv_union_data union_data;
902 /**********************************************************************
904 * Incremental Aggregative
905 * 8-bit MFW counter per message
906 * 8-bit ack-counter per message
908 * Provides up to 256 aggregative message per type
909 * Provides 4 message types in dword
910 * Message type pointers to byte offset
911 * Backward Compatibility by using sizeof for the counters.
912 * No lock requires for 32bit messages
914 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
915 * is required to prevent data corruption.
916 **********************************************************************/
917 enum MFW_DRV_MSG_TYPE {
918 MFW_DRV_MSG_LINK_CHANGE,
919 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
920 MFW_DRV_MSG_VF_DISABLED,
921 MFW_DRV_MSG_ERROR_RECOVERY,
922 MFW_DRV_MSG_BW_UPDATE,
923 MFW_DRV_MSG_S_TAG_UPDATE,
924 MFW_DRV_MSG_GET_LAN_STATS,
925 MFW_DRV_MSG_GET_FCOE_STATS,
926 MFW_DRV_MSG_GET_ISCSI_STATS,
927 MFW_DRV_MSG_GET_RDMA_STATS,
928 MFW_DRV_MSG_FAILURE_DETECTED,
929 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
933 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
934 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
935 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
936 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
938 #ifdef BIG_ENDIAN /* Like MFW */
939 #define DRV_ACK_MSG(msg_p, msg_id) \
940 ((u8)((u8 *)msg_p)[msg_id]++;)
942 #define DRV_ACK_MSG(msg_p, msg_id) \
943 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;)
946 #define MFW_DRV_UPDATE(shmem_func, msg_id) \
947 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;)
949 struct public_mfw_mb {
950 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */
951 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
952 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
955 /**************************************/
957 /* P U B L I C D A T A */
959 /**************************************/
960 enum public_sections {
961 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
962 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
970 struct drv_ver_info_stc {
975 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
976 * Please make sure data does not exceed this size.
978 #define NUM_RUNTIME_DWORDS 16
979 struct drv_init_hw_stc {
980 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
981 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
984 struct mcp_public_data {
985 /* The sections fields is an array */
987 offsize_t sections[PUBLIC_MAX_SECTIONS];
988 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
989 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
990 struct public_global global;
991 struct public_path path[MCP_GLOB_PATH_MAX];
992 struct public_port port[MCP_GLOB_PORT_MAX];
993 struct public_func func[MCP_GLOB_FUNC_MAX];
996 #define I2C_TRANSCEIVER_ADDR 0xa0
997 #define MAX_I2C_TRANSACTION_SIZE 16
998 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256
1000 #endif /* MCP_PUBLIC_H */