2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: MCP public data
15 * Created: 13/01/2013 yanivr
17 ****************************************************************************/
22 #define VF_MAX_STATIC 192 /* In case of AH */
24 #define MCP_GLOB_PATH_MAX 2
25 #define MCP_PORT_MAX 2 /* Global */
26 #define MCP_GLOB_PORT_MAX 4 /* Global */
27 #define MCP_GLOB_FUNC_MAX 16 /* Global */
29 typedef u32 offsize_t; /* In DWORDS !!! */
30 /* Offset from the beginning of the MCP scratchpad */
31 #define OFFSIZE_OFFSET_SHIFT 0
32 #define OFFSIZE_OFFSET_MASK 0x0000ffff
33 /* Size of specific element (not the whole array if any) */
34 #define OFFSIZE_SIZE_SHIFT 16
35 #define OFFSIZE_SIZE_MASK 0xffff0000
37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
38 #define SECTION_OFFSET(_offsize) \
39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))
41 /* SECTION_SIZE is calculating the size in bytes out of offsize */
42 #define SECTION_SIZE(_offsize) \
43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)
45 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
48 #define SECTION_ADDR(_offsize, idx) \
50 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
52 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use
53 * offsetof, since the OFFSETUP collide with the firmware definition
55 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
56 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
57 /* PHY configuration */
59 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
61 #define PMM_SPEED_AUTONEG 0
62 #define PMM_SPEED_SMARTLINQ 0x8
64 u32 pause; /* bitmask */
65 #define PMM_PAUSE_NONE 0x0
66 #define PMM_PAUSE_AUTONEG 0x1
67 #define PMM_PAUSE_RX 0x2
68 #define PMM_PAUSE_TX 0x4
70 u32 adv_speed; /* Default should be the speed_cap_mask */
72 #define PMM_LOOPBACK_NONE 0
73 #define PMM_LOOPBACK_INT_PHY 1
74 #define PMM_LOOPBACK_EXT_PHY 2
75 #define PMM_LOOPBACK_EXT 3
76 #define PMM_LOOPBACK_MAC 4
77 #define PMM_LOOPBACK_CNIG_AH_ONLY_0123 5 /* Port to itself */
78 #define PMM_LOOPBACK_CNIG_AH_ONLY_2301 6 /* Port to Port */
81 u32 feature_config_flags;
86 u32 dynamic_cfg; /* device control channel */
87 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
88 #define PORT_MF_CFG_OV_TAG_SHIFT 0
89 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
94 /* DO NOT add new fields in the middle
95 * MUST be synced with struct pmm_stats_map
98 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
99 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
100 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
101 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
102 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
103 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
105 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
107 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
108 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
109 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
110 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
112 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
113 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
114 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
115 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
116 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
117 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
118 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
119 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
120 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
121 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
122 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
123 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
124 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
125 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
126 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
127 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
129 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
131 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
133 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
135 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
137 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
138 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
139 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
141 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
142 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
143 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
144 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
145 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
146 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
148 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
149 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
150 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
151 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
152 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
153 /* HSI - Cannot add more stats to this struct. If needed, then need to open new
165 struct brb_stats brb;
166 struct pmm_stats pmm;
169 /*----+------------------------------------------------------------------------
170 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
171 * h | rate of | team #1 | team #2 |are used|per path | (paths)
172 * i | physical | | | | | enabled
173 * p | ports | | | | |
174 *====+============+=========+=========+========+==========+===================
175 * BB | 1x100G | This is special mode, where there are actually 2 HW func
176 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1
177 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
178 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
179 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional)
180 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional)
181 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional)
182 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
183 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA
184 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
185 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
186 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
187 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
188 *====+============+=========+=========+========+==========+===================
193 #define CMT_TEAM_MAX 2
195 struct couple_mode_teaming {
196 u8 port_cmt[MCP_GLOB_PORT_MAX];
197 #define PORT_CMT_IN_TEAM (1 << 0)
199 #define PORT_CMT_PORT_ROLE (1 << 1)
200 #define PORT_CMT_PORT_INACTIVE (0 << 1)
201 #define PORT_CMT_PORT_ACTIVE (1 << 1)
203 #define PORT_CMT_TEAM_MASK (1 << 2)
204 #define PORT_CMT_TEAM0 (0 << 2)
205 #define PORT_CMT_TEAM1 (1 << 2)
208 /**************************************
209 * LLDP and DCBX HSI structures
210 **************************************/
211 #define LLDP_CHASSIS_ID_STAT_LEN 4
212 #define LLDP_PORT_ID_STAT_LEN 4
213 #define DCBX_MAX_APP_PROTOCOL 32
214 #define MAX_SYSTEM_LLDP_TLV_DATA 32
216 typedef enum _lldp_agent_e {
217 LLDP_NEAREST_BRIDGE = 0,
218 LLDP_NEAREST_NON_TPMR_BRIDGE,
219 LLDP_NEAREST_CUSTOMER_BRIDGE,
223 struct lldp_config_params_s {
225 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
226 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
227 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
228 #define LLDP_CONFIG_HOLD_SHIFT 8
229 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
230 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
231 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
232 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
233 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
234 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
235 /* Holds local Chassis ID TLV header, subtype and 9B of payload.
236 * If firtst byte is 0, then we will use default chassis ID
238 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
239 /* Holds local Port ID TLV header, subtype and 9B of payload.
240 * If firtst byte is 0, then we will use default port ID
242 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
245 struct lldp_status_params_s {
247 u32 status; /* TBD */
248 /* Holds remote Chassis ID TLV header, subtype and 9B of payload.
250 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
251 /* Holds remote Port ID TLV header, subtype and 9B of payload.
253 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
257 struct dcbx_ets_feature {
259 #define DCBX_ETS_ENABLED_MASK 0x00000001
260 #define DCBX_ETS_ENABLED_SHIFT 0
261 #define DCBX_ETS_WILLING_MASK 0x00000002
262 #define DCBX_ETS_WILLING_SHIFT 1
263 #define DCBX_ETS_ERROR_MASK 0x00000004
264 #define DCBX_ETS_ERROR_SHIFT 2
265 #define DCBX_ETS_CBS_MASK 0x00000008
266 #define DCBX_ETS_CBS_SHIFT 3
267 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
268 #define DCBX_ETS_MAX_TCS_SHIFT 4
269 #define DCBX_ISCSI_OOO_TC_MASK 0x00000f00
270 #define DCBX_ISCSI_OOO_TC_SHIFT 8
271 /* Entries in tc table are orginized that the left most is pri 0, right most is
276 #define DCBX_ISCSI_OOO_TC (4)
278 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
279 #define DCBX_CEE_STRICT_PRIORITY 0xf
280 /* Entries in tc table are orginized that the left most is pri 0, right most is
285 /* Entries in tc table are orginized that the left most is pri 0, right most is
290 #define DCBX_ETS_TSA_STRICT 0
291 #define DCBX_ETS_TSA_CBS 1
292 #define DCBX_ETS_TSA_ETS 2
295 struct dcbx_app_priority_entry {
297 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
298 #define DCBX_APP_PRI_MAP_SHIFT 0
299 #define DCBX_APP_PRI_0 0x01
300 #define DCBX_APP_PRI_1 0x02
301 #define DCBX_APP_PRI_2 0x04
302 #define DCBX_APP_PRI_3 0x08
303 #define DCBX_APP_PRI_4 0x10
304 #define DCBX_APP_PRI_5 0x20
305 #define DCBX_APP_PRI_6 0x40
306 #define DCBX_APP_PRI_7 0x80
307 #define DCBX_APP_SF_MASK 0x00000300
308 #define DCBX_APP_SF_SHIFT 8
309 #define DCBX_APP_SF_ETHTYPE 0
310 #define DCBX_APP_SF_PORT 1
311 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
312 #define DCBX_APP_SF_IEEE_SHIFT 12
313 #define DCBX_APP_SF_IEEE_RESERVED 0
314 #define DCBX_APP_SF_IEEE_ETHTYPE 1
315 #define DCBX_APP_SF_IEEE_TCP_PORT 2
316 #define DCBX_APP_SF_IEEE_UDP_PORT 3
317 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
319 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
320 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
323 /* FW structure in BE */
324 struct dcbx_app_priority_feature {
326 #define DCBX_APP_ENABLED_MASK 0x00000001
327 #define DCBX_APP_ENABLED_SHIFT 0
328 #define DCBX_APP_WILLING_MASK 0x00000002
329 #define DCBX_APP_WILLING_SHIFT 1
330 #define DCBX_APP_ERROR_MASK 0x00000004
331 #define DCBX_APP_ERROR_SHIFT 2
333 * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
334 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8
336 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
337 #define DCBX_APP_MAX_TCS_SHIFT 12
338 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
339 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
340 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
343 /* FW structure in BE */
344 struct dcbx_features {
346 struct dcbx_ets_feature ets;
349 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
350 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
351 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
352 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
353 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
354 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
355 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
356 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
357 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
358 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
360 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
361 #define DCBX_PFC_FLAGS_SHIFT 8
362 #define DCBX_PFC_CAPS_MASK 0x00000f00
363 #define DCBX_PFC_CAPS_SHIFT 8
364 #define DCBX_PFC_MBC_MASK 0x00004000
365 #define DCBX_PFC_MBC_SHIFT 14
366 #define DCBX_PFC_WILLING_MASK 0x00008000
367 #define DCBX_PFC_WILLING_SHIFT 15
368 #define DCBX_PFC_ENABLED_MASK 0x00010000
369 #define DCBX_PFC_ENABLED_SHIFT 16
370 #define DCBX_PFC_ERROR_MASK 0x00020000
371 #define DCBX_PFC_ERROR_SHIFT 17
374 struct dcbx_app_priority_feature app;
377 struct dcbx_local_params {
379 #define DCBX_CONFIG_VERSION_MASK 0x00000007
380 #define DCBX_CONFIG_VERSION_SHIFT 0
381 #define DCBX_CONFIG_VERSION_DISABLED 0
382 #define DCBX_CONFIG_VERSION_IEEE 1
383 #define DCBX_CONFIG_VERSION_CEE 2
384 #define DCBX_CONFIG_VERSION_STATIC 4
387 struct dcbx_features features;
394 * #define DCBX_CONFIG_VERSION_MASK 0x00000007
395 * #define DCBX_CONFIG_VERSION_SHIFT 0
396 * #define DCBX_CONFIG_VERSION_DISABLED 0
397 * #define DCBX_CONFIG_VERSION_IEEE 1
398 * #define DCBX_CONFIG_VERSION_CEE 2
399 * #define DCBX_CONFIG_VERSION_STATIC 4
401 struct dcbx_features features;
405 struct lldp_system_tlvs_buffer_s {
408 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
411 struct dcb_dscp_map {
413 #define DCB_DSCP_ENABLE_MASK 0x1
414 #define DCB_DSCP_ENABLE_SHIFT 0
415 #define DCB_DSCP_ENABLE 1
419 /**************************************/
421 /* P U B L I C G L O B A L */
423 /**************************************/
424 struct public_global {
425 u32 max_path; /* 32bit is wasty, but this will be used often */
426 /* (Global) 32bit is wasty, but this will be used often */
428 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */
433 u32 phymod_dbg_mb_offset;
434 struct couple_mode_teaming cmt;
435 s32 internal_temperature;
437 u32 running_bundle_id;
438 s32 external_temperature;
440 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0)
441 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1)
442 #define MDUMP_REASON_DUMP_AGED (1 << 2)
445 /**************************************/
447 /* P U B L I C P A T H */
449 /**************************************/
451 /****************************************************************************
452 * Shared Memory 2 Region *
453 ****************************************************************************/
454 /* The fw_flr_ack is actually built in the following way: */
456 /* 128 bit: VF ack */
457 /* 8 bit: ios_dis_ack */
458 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
459 /* u32. The fw must have the VF right after the PF since this is how it */
460 /* access arrays(it expects always the VF to reside after the PF, and that */
461 /* makes the calculation much easier for it. ) */
462 /* In order to answer both limitations, and keep the struct small, the code */
463 /* will abuse the structure defined here to achieve the actual partition */
465 /****************************************************************************/
469 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
470 #define ACCUM_ACK_PF_BASE 0
471 #define ACCUM_ACK_PF_SHIFT 0
473 #define ACCUM_ACK_VF_BASE 8
474 #define ACCUM_ACK_VF_SHIFT 3
476 #define ACCUM_ACK_IOV_DIS_BASE 256
477 #define ACCUM_ACK_IOV_DIS_SHIFT 8
482 struct fw_flr_mb flr_mb;
484 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
485 * which were disabled/flred
487 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
489 /* Reset on mcp reset, and incremented for eveny process kill event. */
491 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
492 #define PROCESS_KILL_COUNTER_SHIFT 0
493 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
494 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
495 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
498 /**************************************/
500 /* P U B L I C P O R T */
502 /**************************************/
503 #define FC_NPIV_WWPN_SIZE 8
504 #define FC_NPIV_WWNN_SIZE 8
505 struct dci_npiv_settings {
506 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
507 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
510 struct dci_fc_npiv_cfg {
511 /* hdr used internally by the MFW */
516 #define MAX_NUMBER_NPIV 64
517 struct dci_fc_npiv_tbl {
518 struct dci_fc_npiv_cfg fc_npiv_cfg;
519 struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
522 /****************************************************************************
523 * Driver <-> FW Mailbox *
524 ****************************************************************************/
527 u32 validity_map; /* 0x0 (4*2 = 0x8) */
530 #define MCP_VALIDITY_PCI_CFG 0x00100000
531 #define MCP_VALIDITY_MB 0x00200000
532 #define MCP_VALIDITY_DEV_INFO 0x00400000
533 #define MCP_VALIDITY_RESERVED 0x00000007
535 /* One licensing bit should be set */
536 /* yaniv - tbd ? license */
537 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
538 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
539 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
540 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
543 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
544 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
545 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
546 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
549 #define LINK_STATUS_LINK_UP 0x00000001
550 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
551 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
552 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
553 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
554 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
555 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
556 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
557 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
558 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
560 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
562 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
563 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
565 #define LINK_STATUS_PFC_ENABLED 0x00000100
566 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
567 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
568 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
569 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
570 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
571 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
572 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
573 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
575 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
576 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
577 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
578 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
579 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
581 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
582 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
583 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
584 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
585 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
586 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
587 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
589 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
590 #define LINK_STATUS_FEC_MODE_NONE (0 << 27)
591 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27)
592 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27)
595 u32 ext_phy_fw_version;
596 /* Points to struct pmm_phy_cfg (For READ-ONLY) */
597 u32 drv_phy_cfg_addr;
603 struct port_mf_cfg port_mf_config;
604 struct port_stats stats;
607 #define MEDIA_UNSPECIFIED 0x0
608 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */
609 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */
610 #define MEDIA_DA_TWINAX 0x3
611 #define MEDIA_BASE_T 0x4
612 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */
613 #define MEDIA_MODULE_FIBER 0x6
614 #define MEDIA_KR 0xf0
615 #define MEDIA_NOT_PRESENT 0xff
618 #define LFA_LINK_FLAP_REASON_OFFSET 0
619 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
620 #define LFA_NO_REASON (0 << 0)
621 #define LFA_LINK_DOWN (1 << 0)
622 #define LFA_FORCE_INIT (1 << 1)
623 #define LFA_LOOPBACK_MISMATCH (1 << 2)
624 #define LFA_SPEED_MISMATCH (1 << 3)
625 #define LFA_FLOW_CTRL_MISMATCH (1 << 4)
626 #define LFA_ADV_SPEED_MISMATCH (1 << 5)
627 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
628 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
629 #define LINK_FLAP_COUNT_OFFSET 16
630 #define LINK_FLAP_COUNT_MASK 0x00ff0000
632 u32 link_change_count;
635 /* offset: 536 bytes? */
636 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
637 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
638 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
640 /* DCBX related MIB */
641 struct dcbx_local_params local_admin_dcbx_mib;
642 struct dcbx_mib remote_dcbx_mib;
643 struct dcbx_mib operational_dcbx_mib;
645 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
647 u32 fc_npiv_nvram_tbl_addr;
648 u32 fc_npiv_nvram_tbl_size;
649 u32 transceiver_data;
650 #define PMM_TRANSCEIVER_STATE_MASK 0x000000FF
651 #define PMM_TRANSCEIVER_STATE_SHIFT 0x00000000
652 #define PMM_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
653 #define PMM_TRANSCEIVER_STATE_PRESENT 0x00000001
654 #define PMM_TRANSCEIVER_STATE_VALID 0x00000003
655 #define PMM_TRANSCEIVER_STATE_UPDATING 0x00000008
656 #define PMM_TRANSCEIVER_TYPE_MASK 0x0000FF00
657 #define PMM_TRANSCEIVER_TYPE_SHIFT 0x00000008
658 #define PMM_TRANSCEIVER_TYPE_NONE 0x00000000
659 #define PMM_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF
660 #define PMM_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */
661 #define PMM_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */
662 #define PMM_TRANSCEIVER_TYPE_1G_LX 0x03
663 #define PMM_TRANSCEIVER_TYPE_1G_SX 0x04
664 #define PMM_TRANSCEIVER_TYPE_10G_SR 0x05
665 #define PMM_TRANSCEIVER_TYPE_10G_LR 0x06
666 #define PMM_TRANSCEIVER_TYPE_10G_LRM 0x07
667 #define PMM_TRANSCEIVER_TYPE_10G_ER 0x08
668 #define PMM_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */
669 #define PMM_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */
670 #define PMM_TRANSCEIVER_TYPE_XLPPI 0x0b
671 #define PMM_TRANSCEIVER_TYPE_40G_LR4 0x0c
672 #define PMM_TRANSCEIVER_TYPE_40G_SR4 0x0d
673 #define PMM_TRANSCEIVER_TYPE_40G_CR4 0x0e
674 #define PMM_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */
675 #define PMM_TRANSCEIVER_TYPE_100G_SR4 0x10
676 #define PMM_TRANSCEIVER_TYPE_100G_LR4 0x11
677 #define PMM_TRANSCEIVER_TYPE_100G_ER4 0x12
678 #define PMM_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */
679 #define PMM_TRANSCEIVER_TYPE_100G_CR4 0x14
680 #define PMM_TRANSCEIVER_TYPE_4x10G_SR 0x15
681 #define PMM_TRANSCEIVER_TYPE_25G_PCC_S 0x16
682 #define PMM_TRANSCEIVER_TYPE_25G_ACC_S 0x17
683 #define PMM_TRANSCEIVER_TYPE_25G_PCC_M 0x18
684 #define PMM_TRANSCEIVER_TYPE_25G_ACC_M 0x19
685 #define PMM_TRANSCEIVER_TYPE_25G_PCC_L 0x1a
686 #define PMM_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
687 #define PMM_TRANSCEIVER_TYPE_25G_SR 0x1c
688 #define PMM_TRANSCEIVER_TYPE_25G_LR 0x1d
689 #define PMM_TRANSCEIVER_TYPE_25G_AOC 0x1e
691 #define PMM_TRANSCEIVER_TYPE_4x10G 0x1d
692 #define PMM_TRANSCEIVER_TYPE_4x25G_CR 0x1e
693 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40GR 0x30
694 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
695 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
696 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
697 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
698 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
699 #define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
700 struct dcb_dscp_map dcb_dscp_map;
703 /**************************************/
705 /* P U B L I C F U N C */
707 /**************************************/
710 u32 iscsi_boot_signature;
711 u32 iscsi_boot_block_offset;
713 /* MTU size per funciton is needed for the OV feature */
715 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
716 /* For PCP values 0-3 use the map lower */
717 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
718 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
720 u32 c2s_pcp_map_lower;
721 /* For PCP values 4-7 use the map upper */
722 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
723 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
725 u32 c2s_pcp_map_upper;
727 /* For PCP default value get the MSB byte of the map default */
728 u32 c2s_pcp_map_default;
732 /* replace old mf_cfg */
735 /* function 0 of each port cannot be hidden */
736 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
737 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
738 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
740 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
741 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
742 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
743 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
744 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
745 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
746 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
749 /* value range - 0..100, increments in 1 % */
750 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
751 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
752 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
753 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
754 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
755 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
758 #define FUNC_STATUS_VLINK_DOWN 0x00000001
760 u32 mac_upper; /* MAC */
761 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
762 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
763 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
765 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
767 u32 fcoe_wwn_port_name_upper;
768 u32 fcoe_wwn_port_name_lower;
770 u32 fcoe_wwn_node_name_upper;
771 u32 fcoe_wwn_node_name_lower;
773 u32 ovlan_stag; /* tags */
774 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
775 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
776 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
778 u32 pf_allocation; /* vf per pf */
780 u32 preserve_data; /* Will be used bt CCM */
782 u32 driver_last_activity_ts;
785 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
788 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
791 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
792 #define DRV_ID_PDA_COMP_VER_SHIFT 0
794 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
795 #define DRV_ID_MCP_HSI_VER_SHIFT 16
796 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT)
798 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
799 #define DRV_ID_DRV_TYPE_SHIFT 24
800 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
801 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
802 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
803 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
804 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
805 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
806 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
807 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
808 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
810 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
811 #define DRV_ID_DRV_INIT_HW_SHIFT 31
812 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
815 /**************************************/
817 /* P U B L I C M B */
819 /**************************************/
820 /* This is the only section that the driver can write to, and each */
821 /* Basically each driver request to set feature parameters,
822 * will be done using a different command, which will be linked
823 * to a specific data structure from the union below.
824 * For huge strucuture, the common blank structure should be used.
828 u32 mac_upper; /* Upper 16 bits are always zeroes */
837 struct mcp_file_att {
842 struct bist_nvm_image_att {
844 u32 image_type; /* Image type */
845 u32 nvm_start_addr; /* NVM address of the image */
846 u32 len; /* Include CRC */
849 #define MCP_DRV_VER_STR_SIZE 16
850 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
851 #define MCP_DRV_NVM_BUF_LEN 32
852 struct drv_version_stc {
854 u8 name[MCP_DRV_VER_STR_SIZE - 4];
857 /* statistics for ncsi */
858 struct lan_stats_stc {
865 struct fcoe_stats_stc {
872 struct iscsi_stats_stc {
879 struct rdma_stats_stc {
886 struct ocbb_data_stc {
889 u32 ocsd_req_update_interval;
892 #define MAX_NUM_OF_SENSORS 7
893 #define MFW_SENSOR_LOCATION_INTERNAL 1
894 #define MFW_SENSOR_LOCATION_EXTERNAL 2
895 #define MFW_SENSOR_LOCATION_SFP 3
897 #define SENSOR_LOCATION_SHIFT 0
898 #define SENSOR_LOCATION_MASK 0x000000ff
899 #define THRESHOLD_HIGH_SHIFT 8
900 #define THRESHOLD_HIGH_MASK 0x0000ff00
901 #define CRITICAL_TEMPERATURE_SHIFT 16
902 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000
903 #define CURRENT_TEMP_SHIFT 24
904 #define CURRENT_TEMP_MASK 0xff000000
905 struct temperature_status_stc {
907 u32 sensor[MAX_NUM_OF_SENSORS];
910 /* crash dump configuration header */
911 struct mdump_config_stc {
919 enum resource_id_enum {
920 RESOURCE_NUM_SB_E = 0,
921 RESOURCE_NUM_L2_QUEUE_E = 1,
922 RESOURCE_NUM_VPORT_E = 2,
923 RESOURCE_NUM_VMQ_E = 3,
924 /* Not a real resource!! it's a factor used to calculate others */
925 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
926 /* Not a real resource!! it's a factor used to calculate others */
927 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
928 RESOURCE_NUM_RL_E = 6,
929 RESOURCE_NUM_PQ_E = 7,
930 RESOURCE_NUM_VF_E = 8,
931 RESOURCE_VFC_FILTER_E = 9,
934 RESOURCE_GFT_PROFILES_E = 12,
935 RESOURCE_NUM_TC_E = 13,
936 RESOURCE_NUM_RSS_ENGINES_E = 14,
937 RESOURCE_LL2_QUEUE_E = 15,
938 RESOURCE_RDMA_STATS_QUEUE_E = 16,
940 RESOURCE_NUM_INVALID = 0xFFFFFFFF
943 /* Resource ID is to be filled by the driver in the MB request
944 * Size, offset & flags to be filled by the MFW in the MB response
946 struct resource_info {
947 enum resource_id_enum res_id;
948 u32 size; /* number of allocated resources */
949 u32 offset; /* Offset of the 1st resource */
953 #define RESOURCE_ELEMENT_STRICT (1 << 0)
956 union drv_union_data {
957 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */
958 struct mcp_mac wol_mac; /* UNLOAD_DONE */
960 /* This configuration should be set by the driver for the LINK_SET command. */
962 struct pmm_phy_cfg drv_phy_cfg;
964 struct mcp_val64 val64; /* For PHY / AVS commands */
966 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
968 struct mcp_file_att file_att;
970 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
972 struct drv_version_stc drv_version;
974 struct lan_stats_stc lan_stats;
975 struct fcoe_stats_stc fcoe_stats;
976 struct iscsi_stats_stc icsci_stats;
977 struct rdma_stats_stc rdma_stats;
978 struct ocbb_data_stc ocbb_info;
979 struct temperature_status_stc temp_info;
980 struct resource_info resource;
981 struct bist_nvm_image_att nvm_image_att;
982 struct mdump_config_stc mdump_config;
986 struct public_drv_mb {
988 #define DRV_MSG_CODE_MASK 0xffff0000
989 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
990 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
991 #define DRV_MSG_CODE_INIT_HW 0x12000000
992 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
993 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
994 #define DRV_MSG_CODE_INIT_PHY 0x22000000
995 /* Params - FORCE - Reinitialize the link regardless of LFA */
996 /* - DONT_CARE - Don't flap the link if up */
997 #define DRV_MSG_CODE_LINK_RESET 0x23000000
999 /* Vitaly: LLDP commands */
1000 #define DRV_MSG_CODE_SET_LLDP 0x24000000
1001 #define DRV_MSG_CODE_SET_DCBX 0x25000000
1002 /* OneView feature driver HSI*/
1003 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
1004 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
1005 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
1006 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
1007 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
1008 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
1009 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
1011 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
1013 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp,
1014 * data: struct resource_info
1016 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
1018 /*deprecated don't use*/
1019 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000
1020 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
1021 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1022 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
1023 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
1024 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
1025 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
1026 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
1027 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
1028 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
1029 #define DRV_MSG_CODE_MCP_RESET 0x00090000
1030 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
1031 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
1032 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
1033 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
1034 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
1035 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
1036 #define DRV_MSG_CODE_MCP_HALT 0x00100000
1037 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000
1038 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000
1039 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
1040 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000
1042 #define DRV_MSG_CODE_SET_VMAC 0x00110000
1043 #define DRV_MSG_CODE_GET_VMAC 0x00120000
1044 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
1045 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
1046 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
1048 #define DRV_MSG_CODE_GET_STATS 0x00130000
1049 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
1050 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
1051 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
1052 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
1054 #define DRV_MSG_CODE_OCBB_DATA 0x00180000
1055 #define DRV_MSG_CODE_SET_BW 0x00190000
1056 #define BW_MAX_MASK 0x000000ff
1057 #define BW_MAX_SHIFT 0
1058 #define BW_MIN_MASK 0x0000ff00
1059 #define BW_MIN_SHIFT 8
1060 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
1061 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000
1062 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
1063 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1)
1065 #define DRV_MSG_CODE_GPIO_READ 0x001c0000
1066 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000
1067 /* Param: [0:15] - gpio number */
1068 #define DRV_MSG_CODE_GPIO_INFO 0x00270000
1070 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */
1071 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
1072 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
1074 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
1075 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] -
1076 * driver version (MAJ MIN BUILD SUB)
1078 #define DRV_MSG_CODE_TIMESTAMP 0x00210000
1079 /* This is an empty mailbox just return OK*/
1080 #define DRV_MSG_CODE_EMPTY_MB 0x00220000
1081 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode,
1084 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
1086 /* request resource ownership with default aging */
1087 #define RESOURCE_OPCODE_REQ 1
1088 /* request resource ownership without aging */
1089 #define RESOURCE_OPCODE_REQ_WO_AGING 2
1090 /* request resource ownership with specific aging timer (in seconds) */
1091 #define RESOURCE_OPCODE_REQ_W_AGING 3
1092 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */
1093 #define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */
1095 /* resource is free and granted to requester */
1096 #define RESOURCE_OPCODE_GNT 1
1097 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15,
1098 * 16 = MFW, 17 = diag over serial
1100 #define RESOURCE_OPCODE_BUSY 2
1101 /* indicate release request was acknowledged */
1102 #define RESOURCE_OPCODE_RELEASED 3
1103 /* indicate release request was previously received by other owner */
1104 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
1105 /* indicate wrong owner during release */
1106 #define RESOURCE_OPCODE_WRONG_OWNER 5
1107 #define RESOURCE_OPCODE_UNKNOWN_CMD 255
1108 /* dedicate resource 0 for dump */
1109 #define RESOURCE_DUMP (1 << 0)
1111 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */
1113 /* Send crash dump commands with param[3:0] - opcode */
1114 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000
1115 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
1116 /* acknowledge reception of error indication */
1117 #define DRV_MSG_CODE_MDUMP_ACK 0x01
1118 /* set epoc and personality as follow: drv_data[3:0] - epoch,
1119 * drv_data[7:4] - personality
1121 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
1122 /* trigger crash dump procedure */
1123 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
1124 /* Request valid logs and config words */
1125 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
1126 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger
1129 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
1130 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */
1133 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */
1135 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1138 /* UNLOAD_REQ params */
1139 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
1140 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
1141 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
1142 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
1144 /* UNLOAD_DONE_params */
1145 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
1147 /* INIT_PHY params */
1148 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
1149 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
1151 /* LLDP / DCBX params*/
1152 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
1153 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
1154 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
1155 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
1156 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
1157 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
1159 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
1160 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
1162 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
1163 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
1165 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
1166 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
1167 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
1168 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
1170 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
1171 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
1172 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16
1173 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
1174 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
1175 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
1176 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30
1177 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
1179 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0
1180 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
1181 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8
1182 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
1183 /* configure vf MSIX params*/
1184 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
1185 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
1186 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
1187 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
1189 /* OneView configuration parametres */
1190 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
1191 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
1192 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
1193 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
1194 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
1195 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
1196 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4
1197 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5
1198 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6
1199 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7
1201 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0
1202 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
1203 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
1204 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1)
1205 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1)
1206 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2)
1207 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3)
1208 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3)
1209 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4)
1210 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5)
1211 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
1212 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
1214 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0
1215 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
1217 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
1218 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
1219 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
1220 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
1221 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
1222 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
1224 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
1225 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
1226 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
1227 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
1228 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
1229 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
1230 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
1232 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
1233 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
1235 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
1236 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
1237 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
1239 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0
1240 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
1241 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2
1242 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
1243 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8
1244 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
1245 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16
1246 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
1248 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0
1249 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
1250 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16
1251 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
1252 #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16
1253 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
1254 #define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24
1255 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
1257 /* Resource Allocation params - Driver version support*/
1258 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1259 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
1260 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1261 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
1263 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
1264 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
1265 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
1266 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
1267 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
1269 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
1270 #define DRV_MB_PARAM_BIST_RC_PASSED 1
1271 #define DRV_MB_PARAM_BIST_RC_FAILED 2
1272 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
1274 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
1275 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
1276 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
1277 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
1280 #define FW_MSG_CODE_MASK 0xffff0000
1281 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
1282 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1283 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1284 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
1285 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
1286 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
1287 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1288 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
1289 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
1290 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
1291 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1292 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
1293 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
1294 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
1295 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
1296 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
1297 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
1298 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000
1299 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000
1300 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000
1301 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000
1302 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
1303 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1304 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
1305 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
1306 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
1307 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
1308 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000
1309 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
1310 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1311 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
1312 #define FW_MSG_CODE_FLR_ACK 0x02000000
1313 #define FW_MSG_CODE_FLR_NACK 0x02100000
1314 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000
1315 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000
1316 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000
1318 #define FW_MSG_CODE_NVM_OK 0x00010000
1319 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
1320 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
1321 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
1322 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
1323 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
1324 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1325 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1326 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
1327 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
1328 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
1329 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
1330 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
1331 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
1332 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
1333 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
1334 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
1335 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
1336 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
1337 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
1338 #define FW_MSG_CODE_PHY_OK 0x00110000
1339 #define FW_MSG_CODE_PHY_ERROR 0x00120000
1340 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
1341 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
1342 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
1343 #define FW_MSG_CODE_OK 0x00160000
1344 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000
1345 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000
1346 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000
1347 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000
1348 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000
1349 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1350 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000
1351 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000
1352 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
1353 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
1354 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
1355 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
1356 #define FW_MSG_CODE_GPIO_OK 0x00160000
1357 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000
1358 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
1359 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000
1360 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
1361 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000
1363 /* mdump related response codes */
1364 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000
1365 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000
1366 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
1367 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000
1368 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000
1370 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1373 /* Resource Allocation params - MFW version support*/
1374 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1375 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
1376 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1377 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
1381 #define DRV_PULSE_SEQ_MASK 0x00007fff
1382 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1384 * The system time is in the format of
1385 * (year-2001)*12*32 + month*32 + day.
1387 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1389 * Indicate to the firmware not to go into the
1390 * OS-absent when it is not getting driver pulse.
1391 * This is used for debugging as well for PXE(MBA).
1395 #define MCP_PULSE_SEQ_MASK 0x00007fff
1396 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1397 /* Indicates to the driver not to assert due to lack
1400 #define MCP_EVENT_MASK 0xffff0000
1401 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1403 union drv_union_data union_data;
1407 /**********************************************************************
1409 * Incremental Aggregative
1410 * 8-bit MFW counter per message
1411 * 8-bit ack-counter per message
1413 * Provides up to 256 aggregative message per type
1414 * Provides 4 message types in dword
1415 * Message type pointers to byte offset
1416 * Backward Compatibility by using sizeof for the counters.
1417 * No lock requires for 32bit messages
1419 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
1420 * is required to prevent data corruption.
1421 **********************************************************************/
1422 enum MFW_DRV_MSG_TYPE {
1423 MFW_DRV_MSG_LINK_CHANGE,
1424 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1425 MFW_DRV_MSG_VF_DISABLED,
1426 MFW_DRV_MSG_LLDP_DATA_UPDATED,
1427 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1428 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1429 MFW_DRV_MSG_ERROR_RECOVERY,
1430 MFW_DRV_MSG_BW_UPDATE,
1431 MFW_DRV_MSG_S_TAG_UPDATE,
1432 MFW_DRV_MSG_GET_LAN_STATS,
1433 MFW_DRV_MSG_GET_FCOE_STATS,
1434 MFW_DRV_MSG_GET_ISCSI_STATS,
1435 MFW_DRV_MSG_GET_RDMA_STATS,
1436 MFW_DRV_MSG_FAILURE_DETECTED,
1437 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1438 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
1442 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
1443 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
1444 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
1445 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1447 #ifdef BIG_ENDIAN /* Like MFW */
1448 #define DRV_ACK_MSG(msg_p, msg_id) \
1449 ((u8)((u8 *)msg_p)[msg_id]++;)
1451 #define DRV_ACK_MSG(msg_p, msg_id) \
1452 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;)
1455 #define MFW_DRV_UPDATE(shmem_func, msg_id) \
1456 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;)
1458 struct public_mfw_mb {
1459 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */
1460 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1461 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1464 /**************************************/
1466 /* P U B L I C D A T A */
1468 /**************************************/
1469 enum public_sections {
1470 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
1471 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
1479 struct drv_ver_info_stc {
1484 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1485 * Please make sure data does not exceed this size.
1487 #define NUM_RUNTIME_DWORDS 16
1488 struct drv_init_hw_stc {
1489 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1490 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1493 struct mcp_public_data {
1494 /* The sections fields is an array */
1496 offsize_t sections[PUBLIC_MAX_SECTIONS];
1497 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1498 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1499 struct public_global global;
1500 struct public_path path[MCP_GLOB_PATH_MAX];
1501 struct public_port port[MCP_GLOB_PORT_MAX];
1502 struct public_func func[MCP_GLOB_FUNC_MAX];
1505 #define I2C_TRANSCEIVER_ADDR 0xa0
1506 #define MAX_I2C_TRANSACTION_SIZE 16
1507 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256
1509 #endif /* MCP_PUBLIC_H */