2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: NVM config file - Generated file from nvm cfg excel.
18 ****************************************************************************/
23 #define NVM_CFG_version 0x81805
25 #define NVM_CFG_new_option_seq 15
27 #define NVM_CFG_removed_option_seq 0
29 #define NVM_CFG_updated_value_seq 1
31 struct nvm_cfg_mac_address {
33 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
34 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
38 /******************************************
40 ******************************************/
41 struct nvm_cfg1_glob {
42 u32 generic_cont0; /* 0x0 */
43 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
44 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
45 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
46 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
47 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
48 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
49 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
50 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
51 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
52 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
53 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
54 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
55 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
56 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
57 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
58 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
59 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
60 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
61 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
62 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
63 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
64 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
65 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
66 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
67 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
68 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
69 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
70 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
71 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
72 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
73 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
74 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
75 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
76 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
77 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
78 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
79 u32 engineering_change[3]; /* 0x4 */
80 u32 manufacturing_id; /* 0x10 */
81 u32 serial_number[4]; /* 0x14 */
82 u32 pcie_cfg; /* 0x24 */
83 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
84 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
85 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
86 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
87 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
88 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
89 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
90 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
91 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
92 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
93 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
94 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
95 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
96 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
97 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
98 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \
100 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
101 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
102 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
103 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
104 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
105 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
106 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
107 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
108 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
109 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
110 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
111 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
112 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
113 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
114 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
115 /* Set the duration, in sec, fan failure signal should be sampled */
116 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \
118 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
119 u32 mgmt_traffic; /* 0x28 */
120 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
121 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
122 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
123 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
124 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
125 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
126 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
127 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
128 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
129 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
130 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
131 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
132 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
133 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
134 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
135 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
136 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
137 /* Indicates whether external thermal sonsor is available */
138 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
139 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
140 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
141 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
142 u32 core_cfg; /* 0x2C */
143 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
144 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
145 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
146 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
147 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
148 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
149 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
150 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
151 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
152 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
153 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
154 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
155 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
156 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
157 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
158 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
159 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
160 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
161 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
162 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
163 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
164 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
165 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
166 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
167 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
168 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
169 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
170 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
171 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
172 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
173 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
174 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
175 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
176 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
177 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
178 u32 e_lane_cfg1; /* 0x30 */
179 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
180 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
181 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
182 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
183 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
184 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
185 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
186 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
187 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
188 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
189 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
190 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
191 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
192 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
193 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
194 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
195 u32 e_lane_cfg2; /* 0x34 */
196 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
197 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
198 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
199 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
200 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
201 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
202 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
203 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
204 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
205 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
206 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
207 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
208 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
209 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
210 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
211 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
212 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
213 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
214 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
215 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
216 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
217 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
218 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
219 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
220 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
221 /* Maximum advertised pcie link width */
222 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
223 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
224 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
225 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
226 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
227 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
228 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
230 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
231 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
232 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
233 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
234 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
235 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
236 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
237 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
238 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
239 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
240 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \
242 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
243 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
244 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
245 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
246 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
247 /* Set the PLDM sensor modes */
248 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
249 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
250 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
251 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
252 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
254 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000
255 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31
256 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0
257 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1
258 u32 f_lane_cfg1; /* 0x38 */
259 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
260 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
261 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
262 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
263 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
264 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
265 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
266 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
267 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
268 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
269 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
270 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
271 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
272 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
273 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
274 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
275 u32 f_lane_cfg2; /* 0x3C */
276 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
277 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
278 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
279 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
280 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
281 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
282 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
283 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
284 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
285 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
286 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
287 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
288 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
289 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
290 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
291 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
292 /* Control the period between two successive checks */
293 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \
295 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
296 /* Set shutdown temperature */
297 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \
299 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
300 /* Set max. count for over operational temperature */
301 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
302 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
303 u32 mps10_preemphasis; /* 0x40 */
304 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
305 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
306 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
307 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
308 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
309 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
310 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
311 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
312 u32 mps10_driver_current; /* 0x44 */
313 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
314 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
315 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
316 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
317 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
318 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
319 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
320 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
321 u32 mps25_preemphasis; /* 0x48 */
322 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
323 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
324 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
325 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
326 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
327 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
328 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
329 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
330 u32 mps25_driver_current; /* 0x4C */
331 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
332 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
333 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
334 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
335 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
336 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
337 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
338 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
339 u32 pci_id; /* 0x50 */
340 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
341 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
342 /* Set caution temperature */
343 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK \
345 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16
346 /* Set external thermal sensor I2C address */
347 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \
349 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
350 u32 pci_subsys_id; /* 0x54 */
351 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
352 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
353 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
354 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
356 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
357 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
358 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
359 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
360 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
361 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
362 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
363 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
364 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
365 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
366 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
367 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
368 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
369 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
370 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
371 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
372 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
373 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
374 /* BB VF BAR2 size */
375 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
376 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
377 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
378 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
379 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
380 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
381 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
382 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
383 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
384 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
385 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
386 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
387 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
388 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
389 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
390 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
391 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
392 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
393 /* BB BAR2 size (global) */
394 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
395 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
396 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
397 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
398 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
399 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
400 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
401 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
402 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
403 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
404 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
405 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
406 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
407 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
408 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
409 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
410 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
411 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
412 /* Set the duration, in secs, fan failure signal should be sampled */
413 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
414 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
415 /* This field defines the board total budget for bar2 when disabled
416 * the regular bar size is used.
418 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
419 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
420 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
421 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
422 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
423 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
424 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
425 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
426 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
427 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
428 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
429 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
430 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
431 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
432 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
433 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
434 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
435 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
436 /* Enable/Disable Crash dump triggers */
437 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
438 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
439 u32 mps10_txfir_main; /* 0x5C */
440 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
441 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
442 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
443 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
444 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
445 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
446 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
447 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
448 u32 mps10_txfir_post; /* 0x60 */
449 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
450 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
451 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
452 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
453 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
454 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
455 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
456 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
457 u32 mps25_txfir_main; /* 0x64 */
458 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
459 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
460 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
461 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
462 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
463 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
464 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
465 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
466 u32 mps25_txfir_post; /* 0x68 */
467 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
468 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
469 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
470 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
471 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
472 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
473 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
474 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
475 u32 manufacture_ver; /* 0x6C */
476 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
477 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
478 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
479 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
480 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
481 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
482 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
483 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
484 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
485 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
486 /* Select package id method */
487 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000
488 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30
489 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0
490 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1
491 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000
492 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31
493 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0
494 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1
495 u32 manufacture_time; /* 0x70 */
496 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
497 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
498 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
499 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
500 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
501 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
502 /* Max MSIX for Ethernet in default mode */
503 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000
504 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18
506 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000
507 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26
508 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0
509 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1
510 u32 led_global_settings; /* 0x74 */
511 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
512 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
513 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
514 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
515 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
516 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
517 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
518 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
519 /* Max. continues operating temperature */
520 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000
521 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16
522 /* GPIO which triggers run-time port swap according to the map
523 * specified in option 205
525 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000
526 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24
527 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0
528 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1
529 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2
530 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3
531 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4
532 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5
533 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6
534 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7
535 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8
536 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9
537 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA
538 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB
539 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC
540 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD
541 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE
542 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF
543 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10
544 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11
545 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12
546 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13
547 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14
548 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15
549 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16
550 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17
551 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18
552 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19
553 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A
554 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B
555 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C
556 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D
557 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E
558 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F
559 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20
560 u32 generic_cont1; /* 0x78 */
561 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
562 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
563 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
564 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
565 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
566 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
567 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
568 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
569 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
570 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
571 /* Enable option 195 - Overriding the PCIe Preset value */
572 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000
573 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18
574 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0
575 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1
576 /* PCIe Preset value - applies only if option 194 is enabled */
577 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000
578 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19
579 /* Port mapping to be used when the run-time GPIO for port-swap is
582 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000
583 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23
584 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000
585 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25
586 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000
587 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27
588 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000
589 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29
590 u32 mbi_version; /* 0x7C */
591 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
592 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
593 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
594 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
595 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
596 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
597 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event
600 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000
601 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24
602 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0
603 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1
604 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2
605 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3
606 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4
607 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5
608 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6
609 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7
610 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8
611 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9
612 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA
613 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB
614 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC
615 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD
616 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE
617 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF
618 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10
619 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11
620 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12
621 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13
622 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14
623 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15
624 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16
625 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17
626 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18
627 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19
628 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A
629 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B
630 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C
631 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D
632 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E
633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F
634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20
635 u32 mbi_date; /* 0x80 */
636 u32 misc_sig; /* 0x84 */
637 /* Define the GPIO mapping to switch i2c mux */
638 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
639 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
640 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
641 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
642 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
643 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
644 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
645 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
646 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
647 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
648 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
649 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
650 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
651 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
652 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
653 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
654 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
655 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
656 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
657 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
658 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
659 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
660 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
661 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
662 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
663 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
664 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
665 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
666 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
667 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
668 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
669 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
670 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
675 /* Interrupt signal used for SMBus/I2C management interface
676 * 0 = Interrupt event occurred
679 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000
680 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16
681 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0
682 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1
683 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2
684 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3
685 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4
686 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5
687 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6
688 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7
689 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8
690 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9
691 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA
692 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB
693 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC
694 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD
695 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE
696 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF
697 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10
698 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11
699 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12
700 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13
701 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14
702 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15
703 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16
704 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17
705 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18
706 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19
707 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A
708 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B
709 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C
710 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D
711 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E
712 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F
713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20
714 /* Set aLOM FAN on GPIO */
715 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000
716 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24
717 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0
718 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1
719 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2
720 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3
721 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4
722 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5
723 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6
724 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7
725 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8
726 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9
727 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA
728 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB
729 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC
730 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD
731 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE
732 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF
733 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10
734 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11
735 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12
736 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13
737 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14
738 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15
739 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16
740 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17
741 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18
742 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19
743 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A
744 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B
745 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C
746 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D
747 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E
748 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F
749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20
750 u32 device_capabilities; /* 0x88 */
751 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
752 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
753 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
754 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
755 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
756 u32 power_dissipated; /* 0x8C */
757 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
758 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
759 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
760 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
761 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
762 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
763 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
764 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
765 u32 power_consumed; /* 0x90 */
766 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
767 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
768 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
769 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
770 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
771 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
772 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
773 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
774 u32 efi_version; /* 0x94 */
775 u32 multi_network_modes_capability; /* 0x98 */
776 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
777 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
778 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
779 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
780 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
781 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
782 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
783 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
785 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100
787 u32 reserved1[12]; /* 0x9C */
788 u32 oem1_number[8]; /* 0xCC */
789 u32 oem2_number[8]; /* 0xEC */
790 u32 mps25_active_txfir_pre; /* 0x10C */
791 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF
792 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0
793 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00
794 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8
795 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000
796 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16
797 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000
798 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24
799 u32 mps25_active_txfir_main; /* 0x110 */
800 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF
801 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0
802 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00
803 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8
804 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000
805 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16
806 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000
807 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24
808 u32 mps25_active_txfir_post; /* 0x114 */
809 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF
810 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0
811 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00
812 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8
813 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000
814 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16
815 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000
816 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24
817 u32 features; /* 0x118 */
818 /* Set the Aux Fan on temperature */
819 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF
820 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0
821 /* Set NC-SI package ID */
822 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00
823 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8
824 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0
825 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1
826 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2
827 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3
828 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4
829 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5
830 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6
831 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7
832 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8
833 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9
834 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA
835 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB
836 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC
837 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD
838 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE
839 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF
840 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10
841 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11
842 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12
843 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13
844 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14
845 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15
846 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16
847 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17
848 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18
849 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19
850 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A
851 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B
852 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C
853 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D
854 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E
855 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F
856 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20
857 /* PMBUS Clock GPIO */
858 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000
859 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16
860 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0
861 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1
862 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2
863 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3
864 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4
865 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5
866 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6
867 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7
868 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8
869 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9
870 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA
871 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB
872 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC
873 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD
874 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE
875 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF
876 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10
877 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11
878 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12
879 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13
880 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14
881 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15
882 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16
883 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17
884 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18
885 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19
886 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A
887 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B
888 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C
889 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D
890 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E
891 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F
892 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20
893 /* PMBUS Data GPIO */
894 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000
895 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24
896 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0
897 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1
898 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2
899 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3
900 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4
901 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5
902 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6
903 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7
904 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8
905 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9
906 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA
907 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB
908 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC
909 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD
910 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE
911 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF
912 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10
913 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11
914 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12
915 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13
916 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14
917 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15
918 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16
919 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17
920 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18
921 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19
922 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A
923 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B
924 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C
925 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D
926 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E
927 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F
928 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20
929 u32 tx_rx_eq_25g_hlpc; /* 0x11C */
930 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF
931 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0
932 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00
933 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8
934 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000
935 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16
936 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000
937 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24
938 u32 tx_rx_eq_25g_llpc; /* 0x120 */
939 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF
940 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0
941 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00
942 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8
943 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000
944 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16
945 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000
946 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24
947 u32 tx_rx_eq_25g_ac; /* 0x124 */
948 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF
949 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0
950 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00
951 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8
952 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000
953 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16
954 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000
955 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24
956 u32 tx_rx_eq_10g_pc; /* 0x128 */
957 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF
958 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0
959 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00
960 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8
961 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000
962 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16
963 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000
964 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24
965 u32 tx_rx_eq_10g_ac; /* 0x12C */
966 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF
967 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0
968 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00
969 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8
970 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000
971 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16
972 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000
973 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24
974 u32 tx_rx_eq_1g; /* 0x130 */
975 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF
976 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0
977 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00
978 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8
979 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000
980 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16
981 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000
982 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24
983 u32 tx_rx_eq_25g_bt; /* 0x134 */
984 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF
985 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0
986 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00
987 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8
988 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000
989 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16
990 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000
991 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24
992 u32 tx_rx_eq_10g_bt; /* 0x138 */
993 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF
994 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0
995 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00
996 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8
997 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000
998 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16
999 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000
1000 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24
1001 u32 generic_cont4; /* 0x13C */
1002 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF
1003 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0
1004 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0
1005 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1
1006 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2
1007 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3
1008 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4
1009 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5
1010 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6
1011 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7
1012 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8
1013 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9
1014 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA
1015 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB
1016 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC
1017 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD
1018 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE
1019 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF
1020 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10
1021 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11
1022 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12
1023 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13
1024 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14
1025 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15
1026 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16
1027 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17
1028 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18
1029 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19
1030 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A
1031 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B
1032 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C
1033 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D
1034 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E
1035 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F
1036 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20
1037 u32 reserved[58]; /* 0x140 */
1040 struct nvm_cfg1_path {
1041 u32 reserved[1]; /* 0x0 */
1044 struct nvm_cfg1_port {
1045 u32 reserved__m_relocated_to_option_123; /* 0x0 */
1046 u32 reserved__m_relocated_to_option_124; /* 0x4 */
1047 u32 generic_cont0; /* 0x8 */
1048 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
1049 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
1050 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
1051 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
1052 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
1053 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
1054 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
1055 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
1056 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
1057 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
1058 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
1059 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
1060 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
1061 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
1062 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
1063 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
1064 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
1065 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
1066 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
1067 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
1068 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
1069 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
1070 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
1071 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
1072 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
1073 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
1074 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
1075 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
1076 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
1077 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
1078 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
1079 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
1080 /* GPIO for HW reset the PHY. In case it is the same for all ports,
1081 * need to set same value for all ports
1083 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000
1084 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24
1085 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0
1086 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1
1087 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2
1088 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3
1089 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4
1090 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5
1091 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6
1092 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7
1093 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8
1094 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9
1095 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA
1096 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB
1097 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC
1098 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD
1099 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE
1100 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF
1101 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10
1102 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11
1103 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12
1104 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13
1105 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14
1106 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15
1107 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16
1108 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17
1109 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18
1110 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19
1111 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A
1112 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B
1113 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C
1114 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D
1115 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E
1116 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F
1117 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20
1118 u32 pcie_cfg; /* 0xC */
1119 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
1120 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
1121 u32 features; /* 0x10 */
1122 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
1123 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
1124 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
1125 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
1126 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
1127 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
1128 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
1129 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
1130 u32 speed_cap_mask; /* 0x14 */
1131 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1132 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1133 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1134 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1135 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1136 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1137 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1138 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1139 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1140 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1141 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1142 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1143 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1144 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1145 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1146 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1147 u32 link_settings; /* 0x18 */
1148 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
1149 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
1150 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
1151 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
1152 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
1153 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
1154 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
1155 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
1156 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
1157 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
1158 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
1159 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
1160 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
1161 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
1162 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
1163 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
1164 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
1165 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
1166 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
1167 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
1168 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
1169 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
1170 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
1171 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
1172 #define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
1173 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
1174 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
1175 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
1176 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
1177 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
1178 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \
1180 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
1181 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \
1183 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \
1185 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
1186 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
1187 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
1188 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
1189 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
1190 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
1191 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
1192 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
1193 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
1194 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
1195 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000
1196 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20
1197 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0
1198 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1
1199 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2
1200 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3
1201 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4
1202 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5
1203 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6
1204 u32 phy_cfg; /* 0x1C */
1205 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
1206 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
1207 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
1208 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
1209 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
1210 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
1211 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
1212 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
1213 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
1214 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
1215 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
1216 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
1217 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
1218 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
1219 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
1220 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
1221 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
1222 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
1223 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
1224 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
1225 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
1226 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
1227 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
1228 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
1229 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
1230 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
1231 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
1232 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
1233 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
1234 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
1235 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
1236 u32 mgmt_traffic; /* 0x20 */
1237 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
1238 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
1239 u32 ext_phy; /* 0x24 */
1240 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
1241 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
1242 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
1243 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1
1244 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
1245 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
1246 /* EEE power saving mode */
1247 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
1248 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
1249 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
1250 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
1251 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
1252 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
1253 u32 mba_cfg1; /* 0x28 */
1254 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
1255 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
1256 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
1257 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
1258 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
1259 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
1260 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
1261 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
1262 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
1263 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
1264 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
1265 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
1266 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
1267 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
1268 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
1269 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
1270 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
1271 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
1272 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
1273 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
1274 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
1275 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
1276 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
1277 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
1278 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
1279 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
1280 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
1281 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
1282 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
1284 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
1285 u32 mba_cfg2; /* 0x2C */
1286 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
1287 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
1288 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
1289 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
1290 u32 vf_cfg; /* 0x30 */
1291 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
1292 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
1293 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
1294 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
1295 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
1296 u32 led_port_settings; /* 0x3C */
1297 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
1298 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
1299 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
1300 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
1301 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
1302 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
1303 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
1304 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
1305 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
1306 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
1307 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
1308 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
1309 u32 transceiver_00; /* 0x40 */
1310 /* Define for mapping of transceiver signal module absent */
1311 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
1312 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
1313 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
1314 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
1315 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
1316 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
1317 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
1318 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
1319 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
1320 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
1321 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
1322 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
1323 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
1324 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
1325 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
1326 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
1327 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
1328 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
1329 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
1330 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
1331 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
1332 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
1333 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
1334 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
1335 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
1336 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
1337 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
1338 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
1339 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
1340 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
1341 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
1342 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
1343 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
1344 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
1345 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
1346 /* Define the GPIO mux settings to switch i2c mux to this port */
1347 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
1348 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
1349 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
1350 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
1351 u32 device_ids; /* 0x44 */
1352 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
1353 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
1354 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
1355 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
1356 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
1357 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
1358 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
1359 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
1360 u32 board_cfg; /* 0x48 */
1361 /* This field defines the board technology
1362 * (backpane,transceiver,external PHY)
1364 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
1365 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
1366 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
1367 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
1368 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
1369 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
1370 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
1371 /* This field defines the GPIO mapped to tx_disable signal in SFP */
1372 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
1373 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
1374 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
1375 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
1376 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
1377 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
1378 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
1379 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
1380 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
1381 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
1382 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
1383 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
1384 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
1385 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
1386 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
1387 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
1388 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
1389 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
1390 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
1391 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
1392 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
1393 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
1394 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
1395 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
1396 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
1397 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
1398 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
1399 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
1400 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
1401 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
1402 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
1403 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
1404 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
1405 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
1406 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
1407 u32 mnm_10g_cap; /* 0x4C */
1408 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
1410 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1411 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1412 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1413 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1414 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1415 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1417 NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1418 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
1420 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1422 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1423 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1424 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1425 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1426 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1428 NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1429 u32 mnm_10g_ctrl; /* 0x50 */
1430 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
1431 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
1432 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
1433 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
1434 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
1435 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
1436 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
1437 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
1438 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
1439 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_SMARTLINQ 0x8
1440 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
1441 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
1442 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
1443 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
1444 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
1445 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
1446 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
1447 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
1448 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
1449 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_SMARTLINQ 0x8
1450 /* This field defines the board technology
1451 * (backpane,transceiver,external PHY)
1453 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
1454 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
1455 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
1456 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
1457 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
1458 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
1459 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
1460 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
1462 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
1463 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
1464 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
1465 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
1466 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
1467 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
1468 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
1469 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
1470 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
1471 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
1472 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
1473 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
1474 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
1475 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
1476 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
1477 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
1478 u32 mnm_10g_misc; /* 0x54 */
1479 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
1480 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
1481 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
1482 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
1483 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
1484 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7
1485 u32 mnm_25g_cap; /* 0x58 */
1486 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
1488 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1489 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1490 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1491 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1492 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1493 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1495 NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1496 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
1498 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1500 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1501 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1502 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1503 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1504 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1506 NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1507 u32 mnm_25g_ctrl; /* 0x5C */
1508 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
1509 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
1510 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
1511 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
1512 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
1513 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
1514 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
1515 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
1516 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
1517 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_SMARTLINQ 0x8
1518 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
1519 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
1520 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
1521 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
1522 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
1523 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
1524 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
1525 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
1526 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
1527 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_SMARTLINQ 0x8
1528 /* This field defines the board technology
1529 * (backpane,transceiver,external PHY)
1531 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
1532 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
1533 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
1534 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
1535 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
1536 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
1537 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
1538 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
1540 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
1541 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
1542 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
1543 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
1544 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
1545 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
1546 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
1547 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
1548 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
1549 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
1550 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
1551 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
1552 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
1553 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
1554 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
1555 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
1556 u32 mnm_25g_misc; /* 0x60 */
1557 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
1558 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
1559 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
1560 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
1561 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
1562 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7
1563 u32 mnm_40g_cap; /* 0x64 */
1564 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
1566 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1567 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1568 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1569 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1570 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1571 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1573 NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1574 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
1576 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1578 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1579 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1580 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1581 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1582 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1584 NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1585 u32 mnm_40g_ctrl; /* 0x68 */
1586 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
1587 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
1588 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
1589 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
1590 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
1591 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
1592 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
1593 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
1594 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
1595 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_SMARTLINQ 0x8
1596 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
1597 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
1598 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
1599 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
1600 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
1601 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
1602 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
1603 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
1604 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
1605 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_SMARTLINQ 0x8
1606 /* This field defines the board technology
1607 * (backpane,transceiver,external PHY)
1609 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
1610 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
1611 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
1612 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
1613 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
1614 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
1615 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
1616 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
1618 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
1619 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
1620 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
1621 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
1622 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
1623 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
1624 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
1625 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
1626 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
1627 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
1628 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
1629 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
1630 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
1631 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
1632 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
1633 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
1634 u32 mnm_40g_misc; /* 0x6C */
1635 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
1636 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
1637 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
1638 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
1639 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
1640 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7
1641 u32 mnm_50g_cap; /* 0x70 */
1642 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
1644 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1645 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1646 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1647 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1648 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1649 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1651 NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
1653 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
1655 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1657 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1658 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1659 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1660 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1661 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1663 NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
1665 u32 mnm_50g_ctrl; /* 0x74 */
1666 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
1667 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
1668 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
1669 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
1670 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
1671 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
1672 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
1673 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
1674 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
1675 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_SMARTLINQ 0x8
1676 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
1677 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
1678 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
1679 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
1680 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
1681 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
1682 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
1683 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
1684 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
1685 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_SMARTLINQ 0x8
1686 /* This field defines the board technology
1687 * (backpane,transceiver,external PHY)
1689 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
1690 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
1691 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
1692 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
1693 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
1694 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
1695 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
1696 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
1698 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
1699 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
1700 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
1701 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
1702 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
1703 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
1704 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
1705 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
1706 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
1707 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
1708 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
1709 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
1710 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
1711 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
1712 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
1713 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
1714 u32 mnm_50g_misc; /* 0x78 */
1715 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
1716 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
1717 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
1718 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
1719 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
1720 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7
1721 u32 mnm_100g_cap; /* 0x7C */
1722 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
1724 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
1725 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
1726 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
1727 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
1728 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
1729 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
1730 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
1731 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
1733 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
1734 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
1735 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
1736 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
1737 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
1738 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
1739 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
1740 u32 mnm_100g_ctrl; /* 0x80 */
1741 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
1742 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
1743 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
1744 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
1745 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
1746 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
1747 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
1748 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
1749 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
1750 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_SMARTLINQ 0x8
1751 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
1752 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
1753 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
1754 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
1755 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
1756 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
1757 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
1758 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
1759 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
1760 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_SMARTLINQ 0x8
1761 /* This field defines the board technology
1762 * (backpane,transceiver,external PHY)
1764 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
1765 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
1766 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
1767 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
1768 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
1769 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
1770 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
1771 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
1773 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
1774 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
1775 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
1776 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
1777 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
1778 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
1779 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
1780 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
1781 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
1782 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
1783 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
1784 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
1785 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
1786 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
1787 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
1788 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
1789 u32 mnm_100g_misc; /* 0x84 */
1790 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
1791 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
1792 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
1793 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
1794 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
1795 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7
1796 u32 reserved[116]; /* 0x88 */
1799 struct nvm_cfg1_func {
1800 struct nvm_cfg_mac_address mac_address; /* 0x0 */
1801 u32 rsrv1; /* 0x8 */
1802 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
1803 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
1804 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
1805 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
1806 u32 rsrv2; /* 0xC */
1807 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
1808 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
1809 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
1810 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
1811 u32 device_id; /* 0x10 */
1812 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
1813 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
1814 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
1815 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
1816 u32 cmn_cfg; /* 0x14 */
1817 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
1818 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
1819 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
1820 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
1821 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
1822 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
1823 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
1824 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
1825 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
1826 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
1827 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
1828 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
1829 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
1830 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
1831 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
1832 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
1833 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
1834 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
1835 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
1836 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
1837 u32 pci_cfg; /* 0x18 */
1838 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
1839 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
1840 /* AH VF BAR2 size */
1841 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
1842 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
1843 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
1844 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
1845 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
1846 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
1847 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
1848 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
1849 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
1850 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
1851 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
1852 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
1853 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
1854 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
1855 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
1856 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
1857 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
1858 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
1859 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
1860 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
1861 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
1862 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
1863 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
1864 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
1865 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
1866 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
1867 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
1868 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
1869 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
1870 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
1871 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
1872 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
1873 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
1874 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
1875 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
1876 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
1877 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
1878 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
1879 /* Hide function in npar mode */
1880 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
1881 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
1882 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
1883 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
1884 /* AH BAR2 size (per function) */
1885 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
1886 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
1887 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
1888 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
1889 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
1890 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
1891 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
1892 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
1893 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
1894 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
1895 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
1896 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
1897 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
1898 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
1899 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
1900 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
1901 u32 preboot_generic_cfg; /* 0x2C */
1902 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
1903 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
1904 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
1905 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
1906 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000
1907 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17
1908 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1
1909 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2
1910 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4
1911 u32 reserved[8]; /* 0x30 */
1915 struct nvm_cfg1_glob glob; /* 0x0 */
1916 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */
1917 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
1918 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
1921 /******************************************
1923 ******************************************/
1924 enum nvm_cfg_sections {
1925 NVM_CFG_SECTION_NVM_CFG1,
1931 u32 sections_offset[NVM_CFG_SECTION_MAX];
1932 struct nvm_cfg1 cfg1;
1935 #endif /* NVM_CFG_H */