2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: NVM config file - Generated file from nvm cfg excel.
18 ****************************************************************************/
23 struct nvm_cfg_mac_address {
25 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
26 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
30 /******************************************
32 ******************************************/
33 struct nvm_cfg1_glob {
34 u32 generic_cont0; /* 0x0 */
35 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
36 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
37 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
38 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
39 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
40 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
41 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
42 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
43 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
44 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
45 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
46 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
47 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
48 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
49 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
50 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
51 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
52 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
53 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
54 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
55 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
56 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
57 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
58 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
59 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
60 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
61 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
62 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
63 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
64 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
65 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
66 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
67 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
68 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
69 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
70 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
71 u32 engineering_change[3]; /* 0x4 */
72 u32 manufacturing_id; /* 0x10 */
73 u32 serial_number[4]; /* 0x14 */
74 u32 pcie_cfg; /* 0x24 */
75 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
76 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
77 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
78 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
79 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
80 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
81 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
82 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
83 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
84 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
85 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
86 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
87 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
88 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
89 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
90 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \
92 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
93 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
94 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
95 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
96 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
97 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
98 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
99 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
100 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
101 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
102 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
103 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
104 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
105 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
106 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
107 /* Set the duration, in sec, fan failure signal should be sampled */
108 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \
110 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
111 u32 mgmt_traffic; /* 0x28 */
112 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
113 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
114 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
115 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
116 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
117 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
118 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
119 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
120 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
121 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
122 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
123 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
124 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
125 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
126 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
127 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
128 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
129 /* Indicates whether external thermal sonsor is available */
130 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
131 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
132 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
133 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
134 u32 core_cfg; /* 0x2C */
135 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
136 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
137 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
138 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
139 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
140 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
141 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
142 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
143 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
144 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
145 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
146 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
147 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
148 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
149 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
150 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
151 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
152 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
153 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
154 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
155 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
156 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
157 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
158 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
159 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
160 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
161 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
162 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
163 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
164 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
165 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
166 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
167 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
168 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
169 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
170 u32 e_lane_cfg1; /* 0x30 */
171 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
172 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
173 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
174 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
175 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
176 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
177 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
178 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
179 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
180 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
181 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
182 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
183 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
184 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
185 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
186 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
187 u32 e_lane_cfg2; /* 0x34 */
188 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
189 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
190 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
191 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
192 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
193 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
194 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
195 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
196 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
197 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
198 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
199 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
200 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
201 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
202 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
203 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
204 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
205 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
206 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
207 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
208 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
209 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
210 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
211 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
212 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
213 /* Maximum advertised pcie link width */
214 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
215 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
216 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
217 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
218 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
219 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
220 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
222 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
223 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
224 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
225 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
226 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
227 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
228 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
229 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
230 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
231 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
232 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \
234 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
235 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
236 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
237 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
238 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
239 /* Set the PLDM sensor modes */
240 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
241 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
242 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
243 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
244 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
245 u32 f_lane_cfg1; /* 0x38 */
246 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
247 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
248 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
249 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
250 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
251 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
252 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
253 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
254 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
255 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
256 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
257 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
258 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
259 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
260 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
261 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
262 u32 f_lane_cfg2; /* 0x3C */
263 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
264 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
265 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
266 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
267 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
268 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
269 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
270 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
271 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
272 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
273 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
274 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
275 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
276 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
277 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
278 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
279 /* Control the period between two successive checks */
280 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \
282 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
283 /* Set shutdown temperature */
284 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \
286 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
287 /* Set max. count for over operational temperature */
288 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
289 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
290 u32 mps10_preemphasis; /* 0x40 */
291 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
292 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
293 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
294 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
295 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
296 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
297 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
298 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
299 u32 mps10_driver_current; /* 0x44 */
300 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
301 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
302 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
303 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
304 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
305 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
306 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
307 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
308 u32 mps25_preemphasis; /* 0x48 */
309 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
310 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
311 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
312 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
313 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
314 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
315 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
316 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
317 u32 mps25_driver_current; /* 0x4C */
318 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
319 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
320 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
321 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
322 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
323 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
324 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
325 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
326 u32 pci_id; /* 0x50 */
327 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
328 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
329 /* Set caution temperature */
330 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK \
332 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16
333 /* Set external thermal sensor I2C address */
334 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \
336 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
337 u32 pci_subsys_id; /* 0x54 */
338 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
339 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
340 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
341 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
343 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
344 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
345 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
346 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
347 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
348 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
349 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
350 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
351 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
352 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
353 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
354 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
355 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
356 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
357 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
358 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
359 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
360 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
361 /* BB VF BAR2 size */
362 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
363 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
364 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
365 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
366 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
367 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
368 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
369 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
370 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
371 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
372 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
373 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
374 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
375 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
376 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
377 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
378 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
379 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
380 /* BB BAR2 size (global) */
381 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
382 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
383 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
384 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
385 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
386 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
387 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
388 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
389 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
390 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
391 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
392 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
393 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
394 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
395 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
396 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
397 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
398 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
399 /* Set the duration, in secs, fan failure signal should be sampled */
400 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
401 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
402 /* This field defines the board total budget for bar2 when disabled
403 * the regular bar size is used.
405 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
406 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
407 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
408 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
409 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
410 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
411 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
412 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
413 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
414 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
415 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
416 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
417 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
418 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
419 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
420 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
421 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
422 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
423 /* Enable/Disable Crash dump triggers */
424 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
425 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
426 u32 mps10_txfir_main; /* 0x5C */
427 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
428 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
429 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
430 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
431 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
432 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
433 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
434 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
435 u32 mps10_txfir_post; /* 0x60 */
436 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
437 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
438 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
439 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
440 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
441 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
442 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
443 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
444 u32 mps25_txfir_main; /* 0x64 */
445 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
446 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
447 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
448 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
449 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
450 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
451 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
452 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
453 u32 mps25_txfir_post; /* 0x68 */
454 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
455 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
456 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
457 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
458 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
459 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
460 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
461 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
462 u32 manufacture_ver; /* 0x6C */
463 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
464 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
465 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
466 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
467 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
468 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
469 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
470 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
471 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
472 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
473 u32 manufacture_time; /* 0x70 */
474 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
475 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
476 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
477 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
478 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
479 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
480 /* Max MSIX for Ethernet in default mode */
481 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000
482 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18
483 u32 led_global_settings; /* 0x74 */
484 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
485 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
486 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
487 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
488 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
489 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
490 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
491 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
492 u32 generic_cont1; /* 0x78 */
493 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
494 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
495 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
496 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
497 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
498 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
499 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
500 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
501 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
502 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
503 /* Enable option 195 - Overriding the PCIe Preset value */
504 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000
505 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18
506 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0
507 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1
508 /* PCIe Preset value - applies only if option 194 is enabled */
509 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000
510 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19
511 u32 mbi_version; /* 0x7C */
512 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
513 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
514 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
515 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
516 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
517 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
518 u32 mbi_date; /* 0x80 */
519 u32 misc_sig; /* 0x84 */
520 /* Define the GPIO mapping to switch i2c mux */
521 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
522 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
523 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
524 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
525 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
526 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
527 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
528 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
529 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
530 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
531 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
532 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
533 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
534 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
535 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
536 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
537 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
538 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
539 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
540 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
541 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
542 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
543 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
544 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
545 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
546 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
547 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
548 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
549 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
550 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
551 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
552 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
553 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
554 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
555 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
556 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
557 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
558 u32 device_capabilities; /* 0x88 */
559 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
560 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
561 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
562 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
563 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
564 u32 power_dissipated; /* 0x8C */
565 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
566 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
567 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
568 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
569 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
570 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
571 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
572 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
573 u32 power_consumed; /* 0x90 */
574 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
575 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
576 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
577 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
578 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
579 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
580 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
581 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
582 u32 efi_version; /* 0x94 */
583 u32 multi_network_modes_capability; /* 0x98 */
584 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
585 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
586 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
587 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
588 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
589 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
590 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
591 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
593 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100
594 u32 reserved[41]; /* 0x9C */
597 struct nvm_cfg1_path {
598 u32 reserved[30]; /* 0x0 */
601 struct nvm_cfg1_port {
602 u32 reserved__m_relocated_to_option_123; /* 0x0 */
603 u32 reserved__m_relocated_to_option_124; /* 0x4 */
604 u32 generic_cont0; /* 0x8 */
605 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
606 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
607 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
608 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
609 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
610 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
611 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
612 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
613 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
614 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
615 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
616 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
617 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
618 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
619 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
620 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
621 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
622 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
623 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
624 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
625 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
626 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
627 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
628 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
629 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
630 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
631 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
632 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
633 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
634 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
635 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
636 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
637 /* GPIO for HW reset the PHY. In case it is the same for all ports,
638 * need to set same value for all ports
640 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000
641 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24
642 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0
643 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1
644 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2
645 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3
646 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4
647 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5
648 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6
649 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7
650 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8
651 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9
652 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA
653 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB
654 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC
655 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD
656 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE
657 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF
658 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10
659 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11
660 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12
661 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13
662 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14
663 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15
664 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16
665 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17
666 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18
667 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19
668 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A
669 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B
670 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C
671 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D
672 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E
673 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F
674 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20
675 u32 pcie_cfg; /* 0xC */
676 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
677 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
678 u32 features; /* 0x10 */
679 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
680 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
681 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
682 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
683 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
684 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
685 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
686 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
687 u32 speed_cap_mask; /* 0x14 */
688 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
689 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
690 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
691 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
692 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
693 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
694 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
695 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
696 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
697 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
698 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
699 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
700 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
701 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
702 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
703 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
704 u32 link_settings; /* 0x18 */
705 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
706 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
707 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
708 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
709 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
710 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
711 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
712 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
713 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
714 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
715 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
716 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
717 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
718 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
719 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
720 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
721 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
722 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
723 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
724 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
725 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
726 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
727 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
728 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
729 #define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
730 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
731 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
732 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
733 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
734 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
735 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \
737 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
738 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \
740 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \
742 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
743 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
744 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
745 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
746 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
747 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
748 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
749 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
750 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
751 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
752 u32 phy_cfg; /* 0x1C */
753 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
754 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
755 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
756 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
757 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
758 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
759 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
760 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
761 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
762 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
763 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
764 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
765 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
766 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
767 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
768 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
769 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
770 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
771 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
772 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
773 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
774 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
775 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
776 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
777 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
778 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
779 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
780 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
781 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
782 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
783 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
784 u32 mgmt_traffic; /* 0x20 */
785 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
786 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
787 u32 ext_phy; /* 0x24 */
788 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
789 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
790 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
791 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1
792 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
793 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
794 /* EEE power saving mode */
795 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
796 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
797 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
798 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
799 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
800 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
801 u32 mba_cfg1; /* 0x28 */
802 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
803 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
804 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
805 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
806 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
807 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
808 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
809 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
810 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
811 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
812 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
813 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
814 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
815 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
816 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
817 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
818 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
819 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
820 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
821 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
822 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
823 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
824 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
825 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
826 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
827 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
828 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
829 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
830 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
832 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
833 u32 mba_cfg2; /* 0x2C */
834 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
835 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
836 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
837 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
838 u32 vf_cfg; /* 0x30 */
839 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
840 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
841 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
842 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
843 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
844 u32 led_port_settings; /* 0x3C */
845 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
846 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
847 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
848 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
849 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
850 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
851 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
852 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
853 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
854 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
855 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
856 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
857 u32 transceiver_00; /* 0x40 */
858 /* Define for mapping of transceiver signal module absent */
859 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
860 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
861 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
862 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
863 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
864 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
865 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
866 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
867 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
868 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
869 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
870 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
871 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
872 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
873 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
874 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
875 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
876 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
877 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
878 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
879 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
880 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
881 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
882 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
883 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
884 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
885 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
886 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
887 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
888 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
889 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
890 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
891 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
892 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
893 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
894 /* Define the GPIO mux settings to switch i2c mux to this port */
895 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
896 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
897 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
898 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
899 u32 device_ids; /* 0x44 */
900 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
901 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
902 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
903 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
904 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
905 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
906 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
907 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
908 u32 board_cfg; /* 0x48 */
909 /* This field defines the board technology
910 * (backpane,transceiver,external PHY)
912 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
913 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
914 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
915 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
916 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
917 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
918 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
919 /* This field defines the GPIO mapped to tx_disable signal in SFP */
920 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
921 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
922 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
923 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
924 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
925 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
926 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
927 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
928 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
929 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
930 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
931 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
932 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
933 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
934 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
935 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
936 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
937 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
938 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
939 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
940 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
941 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
942 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
943 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
944 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
945 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
946 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
947 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
948 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
949 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
950 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
951 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
952 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
953 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
954 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
955 u32 mnm_10g_cap; /* 0x4C */
956 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
958 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
959 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
960 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
961 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
962 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
963 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
965 NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
966 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
968 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
970 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
971 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
972 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
973 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
974 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
976 NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
977 u32 mnm_10g_ctrl; /* 0x50 */
978 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
979 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
980 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
981 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
982 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
983 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
984 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
985 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
986 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
987 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_SMARTLINQ 0x8
988 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
989 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
990 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
991 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
992 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
993 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
994 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
995 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
996 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
997 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_SMARTLINQ 0x8
998 /* This field defines the board technology
999 * (backpane,transceiver,external PHY)
1001 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
1002 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
1003 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
1004 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
1005 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
1006 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
1007 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
1008 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
1010 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
1011 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
1012 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
1013 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
1014 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
1015 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
1016 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
1017 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
1018 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
1019 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
1020 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
1021 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
1022 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
1023 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
1024 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
1025 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
1026 u32 mnm_10g_misc; /* 0x54 */
1027 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
1028 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
1029 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
1030 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
1031 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
1032 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7
1033 u32 mnm_25g_cap; /* 0x58 */
1034 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
1036 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1037 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1038 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1039 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1040 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1041 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1043 NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1044 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
1046 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1048 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1049 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1050 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1051 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1052 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1054 NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1055 u32 mnm_25g_ctrl; /* 0x5C */
1056 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
1057 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
1058 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
1059 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
1060 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
1061 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
1062 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
1063 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
1064 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
1065 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_SMARTLINQ 0x8
1066 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
1067 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
1068 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
1069 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
1070 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
1071 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
1072 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
1073 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
1074 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
1075 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_SMARTLINQ 0x8
1076 /* This field defines the board technology
1077 * (backpane,transceiver,external PHY)
1079 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
1080 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
1081 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
1082 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
1083 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
1084 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
1085 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
1086 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
1088 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
1089 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
1090 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
1091 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
1092 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
1093 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
1094 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
1095 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
1096 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
1097 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
1098 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
1099 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
1100 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
1101 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
1102 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
1103 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
1104 u32 mnm_25g_misc; /* 0x60 */
1105 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
1106 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
1107 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
1108 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
1109 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
1110 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7
1111 u32 mnm_40g_cap; /* 0x64 */
1112 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
1114 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1115 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1116 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1117 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1118 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1119 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1121 NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1122 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
1124 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1126 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1127 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1128 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1129 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1130 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1132 NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1133 u32 mnm_40g_ctrl; /* 0x68 */
1134 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
1135 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
1136 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
1137 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
1138 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
1139 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
1140 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
1141 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
1142 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
1143 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_SMARTLINQ 0x8
1144 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
1145 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
1146 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
1147 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
1148 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
1149 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
1150 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
1151 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
1152 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
1153 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_SMARTLINQ 0x8
1154 /* This field defines the board technology
1155 * (backpane,transceiver,external PHY)
1157 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
1158 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
1159 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
1160 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
1161 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
1162 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
1163 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
1164 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
1166 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
1167 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
1168 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
1169 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
1170 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
1171 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
1172 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
1173 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
1174 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
1175 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
1176 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
1177 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
1178 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
1179 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
1180 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
1181 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
1182 u32 mnm_40g_misc; /* 0x6C */
1183 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
1184 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
1185 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
1186 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
1187 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
1188 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7
1189 u32 mnm_50g_cap; /* 0x70 */
1190 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
1192 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1193 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1194 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1195 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1196 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1197 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1199 NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
1201 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
1203 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1205 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1206 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1207 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1208 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1209 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1211 NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
1213 u32 mnm_50g_ctrl; /* 0x74 */
1214 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
1215 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
1216 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
1217 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
1218 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
1219 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
1220 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
1221 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
1222 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
1223 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_SMARTLINQ 0x8
1224 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
1225 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
1226 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
1227 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
1228 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
1229 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
1230 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
1231 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
1232 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
1233 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_SMARTLINQ 0x8
1234 /* This field defines the board technology
1235 * (backpane,transceiver,external PHY)
1237 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
1238 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
1239 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
1240 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
1241 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
1242 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
1243 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
1244 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
1246 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
1247 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
1248 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
1249 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
1250 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
1251 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
1252 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
1253 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
1254 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
1255 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
1256 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
1257 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
1258 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
1259 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
1260 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
1261 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
1262 u32 mnm_50g_misc; /* 0x78 */
1263 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
1264 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
1265 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
1266 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
1267 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
1268 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7
1269 u32 mnm_100g_cap; /* 0x7C */
1270 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
1272 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
1273 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
1274 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
1275 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
1276 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
1277 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
1278 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
1279 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
1281 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
1282 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
1283 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
1284 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
1285 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
1286 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
1287 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
1288 u32 mnm_100g_ctrl; /* 0x80 */
1289 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
1290 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
1291 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
1292 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
1293 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
1294 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
1295 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
1296 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
1297 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
1298 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_SMARTLINQ 0x8
1299 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
1300 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
1301 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
1302 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
1303 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
1304 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
1305 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
1306 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
1307 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
1308 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_SMARTLINQ 0x8
1309 /* This field defines the board technology
1310 * (backpane,transceiver,external PHY)
1312 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
1313 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
1314 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
1315 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
1316 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
1317 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
1318 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
1319 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
1321 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
1322 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
1323 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
1324 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
1325 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
1326 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
1327 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
1328 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
1329 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
1330 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
1331 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
1332 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
1333 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
1334 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
1335 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
1336 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
1337 u32 mnm_100g_misc; /* 0x84 */
1338 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
1339 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
1340 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
1341 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
1342 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
1343 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7
1344 u32 reserved[116]; /* 0x88 */
1347 struct nvm_cfg1_func {
1348 struct nvm_cfg_mac_address mac_address; /* 0x0 */
1349 u32 rsrv1; /* 0x8 */
1350 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
1351 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
1352 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
1353 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
1354 u32 rsrv2; /* 0xC */
1355 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
1356 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
1357 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
1358 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
1359 u32 device_id; /* 0x10 */
1360 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
1361 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
1362 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
1363 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
1364 u32 cmn_cfg; /* 0x14 */
1365 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
1366 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
1367 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
1368 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
1369 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
1370 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
1371 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
1372 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
1373 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
1374 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
1375 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
1376 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
1377 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
1378 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
1379 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
1380 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
1381 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
1382 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
1383 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
1384 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
1385 u32 pci_cfg; /* 0x18 */
1386 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
1387 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
1388 /* AH VF BAR2 size */
1389 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
1390 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
1391 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
1392 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
1393 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
1394 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
1395 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
1396 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
1397 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
1398 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
1399 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
1400 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
1401 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
1402 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
1403 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
1404 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
1405 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
1406 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
1407 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
1408 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
1409 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
1410 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
1411 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
1412 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
1413 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
1414 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
1415 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
1416 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
1417 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
1418 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
1419 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
1420 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
1421 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
1422 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
1423 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
1424 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
1425 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
1426 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
1427 /* Hide function in npar mode */
1428 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
1429 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
1430 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
1431 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
1432 /* AH BAR2 size (per function) */
1433 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
1434 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
1435 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
1436 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
1437 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
1438 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
1439 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
1440 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
1441 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
1442 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
1443 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
1444 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
1445 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
1446 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
1447 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
1448 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
1449 u32 preboot_generic_cfg; /* 0x2C */
1450 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
1451 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
1452 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
1453 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
1454 u32 reserved[8]; /* 0x30 */
1458 struct nvm_cfg1_glob glob; /* 0x0 */
1459 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
1460 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
1461 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
1464 /******************************************
1466 ******************************************/
1467 enum nvm_cfg_sections {
1468 NVM_CFG_SECTION_NVM_CFG1,
1474 u32 sections_offset[NVM_CFG_SECTION_MAX];
1475 struct nvm_cfg1 cfg1;
1478 #endif /* NVM_CFG_H */