2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: NVM config file - Generated file from nvm cfg excel.
18 ****************************************************************************/
23 struct nvm_cfg_mac_address {
25 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
26 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
30 /******************************************
32 ******************************************/
33 struct nvm_cfg1_glob {
34 u32 generic_cont0; /* 0x0 */
35 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
36 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
37 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
38 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
39 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
40 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
41 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
42 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
43 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
44 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
45 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
46 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
47 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
48 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
49 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
50 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
51 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
52 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
53 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
54 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
55 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
56 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
57 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
58 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
59 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
60 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
61 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
62 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
63 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
64 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
65 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
66 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
67 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
68 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
69 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
70 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
71 u32 engineering_change[3]; /* 0x4 */
72 u32 manufacturing_id; /* 0x10 */
73 u32 serial_number[4]; /* 0x14 */
74 u32 pcie_cfg; /* 0x24 */
75 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
76 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
77 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
78 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
79 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
80 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
81 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
82 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
83 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
84 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
85 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
86 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
87 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
88 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020
89 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
90 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
91 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
92 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
93 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
94 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
95 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
96 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
97 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
98 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
99 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
100 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
101 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
102 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
103 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
104 /* Set the duration, in seconds, fan failure signal should be
107 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000
108 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
109 u32 mgmt_traffic; /* 0x28 */
110 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
111 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
112 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
113 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
114 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
115 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
116 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
117 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
118 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
119 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
120 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
121 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
122 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
123 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
124 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
125 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
126 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
127 /* Indicates whether external thermal sonsor is available */
128 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
129 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
130 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
131 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
132 u32 core_cfg; /* 0x2C */
133 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
134 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
135 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
136 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
137 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
138 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
139 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
140 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
141 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
142 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
143 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
144 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
145 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
146 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
147 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
148 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
149 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
150 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
151 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
152 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
153 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
154 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
155 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
156 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
157 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
158 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
159 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
160 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
161 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
162 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
163 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
164 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
165 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
166 u32 e_lane_cfg1; /* 0x30 */
167 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
168 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
169 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
170 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
171 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
172 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
173 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
174 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
175 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
176 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
177 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
178 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
179 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
180 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
181 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
182 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
183 u32 e_lane_cfg2; /* 0x34 */
184 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
185 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
186 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
187 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
188 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
189 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
190 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
191 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
192 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
193 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
194 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
195 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
196 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
197 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
198 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
199 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
200 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
201 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
202 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
203 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
204 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
205 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
206 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
207 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
208 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
209 /* Maximum advertised pcie link width */
210 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
211 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
212 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_16_LANES 0x0
213 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
214 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
215 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
216 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
218 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
219 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
220 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
221 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
222 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
223 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
224 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
225 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
226 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
227 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
228 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000
229 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
230 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
231 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
232 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
233 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
234 /* Set the PLDM sensor modes */
235 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
236 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
237 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
238 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
239 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
240 u32 f_lane_cfg1; /* 0x38 */
241 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
242 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
243 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
244 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
245 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
246 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
247 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
248 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
249 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
250 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
251 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
252 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
253 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
254 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
255 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
256 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
257 u32 f_lane_cfg2; /* 0x3C */
258 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
259 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
260 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
261 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
262 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
263 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
264 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
265 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
266 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
267 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
268 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
269 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
270 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
271 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
272 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
273 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
274 /* Control the period between two successive checks */
275 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00
276 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
277 /* Set shutdown temperature */
278 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000
279 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
280 /* Set max. count for over operational temperature */
281 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
282 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
283 u32 eagle_preemphasis; /* 0x40 */
284 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
285 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
286 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
287 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
288 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
289 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
290 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
291 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
292 u32 eagle_driver_current; /* 0x44 */
293 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
294 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
295 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
296 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
297 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
298 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
299 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
300 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
301 u32 falcon_preemphasis; /* 0x48 */
302 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
303 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
304 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
305 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
306 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
307 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
308 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
309 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
310 u32 falcon_driver_current; /* 0x4C */
311 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
312 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
313 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
314 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
315 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
316 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
317 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
318 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
319 u32 pci_id; /* 0x50 */
320 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
321 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
322 /* Set caution temperature */
323 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK 0x00FF0000
324 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16
325 /* Set external thermal sensor I2C address */
326 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000
327 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
328 u32 pci_subsys_id; /* 0x54 */
329 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
330 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
331 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
332 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
334 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
335 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
336 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
337 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
338 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
339 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
340 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
341 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
342 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
343 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
344 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
345 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
346 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
347 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
348 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
349 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
350 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
351 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
352 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
353 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
354 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
355 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
356 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
357 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
358 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
359 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
360 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
361 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
362 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
363 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
364 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
365 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
366 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
367 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
368 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
369 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
370 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
371 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
372 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
373 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
374 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
375 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
376 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
377 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
378 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
379 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
380 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
381 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
382 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
383 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
384 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
385 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
386 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
387 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
388 /* Set the duration, in seconds, fan failure signal should be
391 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
392 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
393 u32 eagle_txfir_main; /* 0x5C */
394 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
395 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
396 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
397 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
398 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
399 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
400 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
401 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
402 u32 eagle_txfir_post; /* 0x60 */
403 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
404 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
405 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
406 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
407 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
408 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
409 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
410 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
411 u32 falcon_txfir_main; /* 0x64 */
412 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
413 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
414 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
415 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
416 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
417 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
418 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
419 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
420 u32 falcon_txfir_post; /* 0x68 */
421 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
422 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
423 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
424 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
425 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
426 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
427 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
428 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
429 u32 manufacture_ver; /* 0x6C */
430 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
431 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
432 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
433 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
434 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
435 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
436 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
437 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
438 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
439 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
440 u32 manufacture_time; /* 0x70 */
441 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
442 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
443 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
444 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
445 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
446 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
447 u32 led_global_settings; /* 0x74 */
448 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
449 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
450 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
451 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
452 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
453 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
454 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
455 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
456 u32 generic_cont1; /* 0x78 */
457 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
458 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
459 u32 mbi_version; /* 0x7C */
460 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
461 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
462 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
463 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
464 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
465 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
466 u32 mbi_date; /* 0x80 */
467 u32 misc_sig; /* 0x84 */
468 /* Define the GPIO mapping to switch i2c mux */
469 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
470 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
471 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
472 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
473 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
474 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
475 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
476 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
477 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
478 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
479 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
480 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
481 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
482 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
483 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
484 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
485 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
486 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
487 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
488 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
489 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
490 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
491 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
492 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
493 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
494 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
495 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
496 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
497 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
498 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
499 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
500 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
501 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
502 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
503 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
504 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
505 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
506 u32 device_capabilities; /* 0x88 */
507 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
508 u32 power_dissipated; /* 0x8C */
509 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
510 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
511 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
512 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
513 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
514 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
515 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
516 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
517 u32 power_consumed; /* 0x90 */
518 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
519 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
520 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
521 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
522 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
523 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
524 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
525 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
526 u32 efi_version; /* 0x94 */
527 u32 reserved[42]; /* 0x98 */
530 struct nvm_cfg1_path {
531 u32 reserved[30]; /* 0x0 */
534 struct nvm_cfg1_port {
535 u32 reserved__m_relocated_to_option_123; /* 0x0 */
536 u32 reserved__m_relocated_to_option_124; /* 0x4 */
537 u32 generic_cont0; /* 0x8 */
538 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
539 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
540 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
541 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
542 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
543 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
544 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
545 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
546 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
547 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
548 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
549 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
550 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
551 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
552 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
553 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
554 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
555 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
556 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
557 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
558 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
559 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
560 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
561 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
562 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
563 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
564 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
565 u32 pcie_cfg; /* 0xC */
566 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
567 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
568 u32 features; /* 0x10 */
569 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
570 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
571 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
572 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
573 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
574 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
575 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
576 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
577 u32 speed_cap_mask; /* 0x14 */
578 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
579 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
580 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
581 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
582 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
583 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
584 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
585 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
586 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
587 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
588 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
589 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
590 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
591 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
592 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
593 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
594 u32 link_settings; /* 0x18 */
595 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
596 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
597 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
598 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
599 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
600 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
601 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
602 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
603 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
604 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
605 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
606 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
607 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
608 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
609 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
610 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
611 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
612 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
613 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
614 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
615 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
616 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
617 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
618 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
619 #define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
620 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
621 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
622 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
623 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
624 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
625 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
626 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
627 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
628 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
629 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
630 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
631 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
632 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
633 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
634 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
635 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_NONE 0x0
636 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_FIRECODE 0x1
637 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_RS 0x2
638 u32 phy_cfg; /* 0x1C */
639 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
640 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
641 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
642 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
643 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
644 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
645 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
646 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
647 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
648 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
649 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
650 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
651 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
652 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
653 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
654 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
655 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
656 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
657 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
658 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
659 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
660 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
661 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
662 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
663 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
664 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
665 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
666 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
667 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
668 #define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
669 #define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
670 u32 mgmt_traffic; /* 0x20 */
671 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
672 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
673 u32 ext_phy; /* 0x24 */
674 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
675 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
676 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
677 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
678 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
679 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
680 u32 mba_cfg1; /* 0x28 */
681 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
682 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
683 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
684 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
685 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
686 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
687 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
688 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
689 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
690 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
691 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
692 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
693 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
694 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
695 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
696 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
697 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
698 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
699 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
700 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
701 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
702 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
703 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
704 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
705 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
706 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
707 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
708 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
709 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
710 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
711 u32 mba_cfg2; /* 0x2C */
712 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
713 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
714 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
715 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
716 u32 vf_cfg; /* 0x30 */
717 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
718 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
719 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
720 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
721 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
722 u32 led_port_settings; /* 0x3C */
723 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
724 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
725 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
726 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
727 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
728 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
729 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
730 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
731 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
732 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
733 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
734 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
735 u32 transceiver_00; /* 0x40 */
736 /* Define for mapping of transceiver signal module absent */
737 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
738 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
739 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
740 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
741 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
742 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
743 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
744 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
745 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
746 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
747 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
748 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
749 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
750 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
751 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
752 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
753 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
754 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
755 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
756 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
757 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
758 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
759 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
760 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
761 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
762 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
763 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
764 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
765 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
766 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
767 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
768 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
769 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
770 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
771 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
772 /* Define the GPIO mux settings to switch i2c mux to this port */
773 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
774 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
775 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
776 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
777 u32 device_ids; /* 0x44 */
778 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
779 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
780 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
781 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
782 u32 board_cfg; /* 0x48 */
783 /* This field defines the board technology
784 * (backpane,transceiver,external PHY)
786 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
787 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
788 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
789 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
790 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
791 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
792 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
793 /* This field defines the GPIO mapped to tx_disable signal in SFP */
794 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
795 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
796 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
797 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
798 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
799 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
800 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
801 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
802 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
803 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
804 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
805 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
806 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
807 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
808 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
809 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
810 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
811 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
812 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
813 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
814 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
815 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
816 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
817 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
818 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
819 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
820 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
821 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
822 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
823 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
824 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
825 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
826 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
827 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
828 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
829 u32 reserved[131]; /* 0x4C */
832 struct nvm_cfg1_func {
833 struct nvm_cfg_mac_address mac_address; /* 0x0 */
835 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
836 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
837 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
838 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
840 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
841 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
842 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
843 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
844 u32 device_id; /* 0x10 */
845 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
846 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
847 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
848 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
849 u32 cmn_cfg; /* 0x14 */
850 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
851 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
852 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
853 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
854 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
855 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
856 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
857 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
858 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
859 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
860 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
861 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
862 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
863 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
864 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
865 u32 pci_cfg; /* 0x18 */
866 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
867 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
868 #define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
869 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
870 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
871 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
872 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
873 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
874 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
875 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
876 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
877 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
878 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
879 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
880 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
881 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
882 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
883 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
884 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
885 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
886 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
887 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
888 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
889 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
890 u32 preboot_generic_cfg; /* 0x2C */
891 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
892 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
893 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
894 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
895 u32 reserved[8]; /* 0x30 */
899 struct nvm_cfg1_glob glob; /* 0x0 */
900 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
901 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
902 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
905 /******************************************
907 ******************************************/
908 enum nvm_cfg_sections {
909 NVM_CFG_SECTION_NVM_CFG1,
915 u32 sections_offset[NVM_CFG_SECTION_MAX];
916 struct nvm_cfg1 cfg1;
919 #endif /* NVM_CFG_H */