2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: NVM config file - Generated file from nvm cfg excel.
18 ****************************************************************************/
23 struct nvm_cfg_mac_address {
25 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
26 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
30 /******************************************
32 ******************************************/
33 struct nvm_cfg1_glob {
34 u32 generic_cont0; /* 0x0 */
35 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
36 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
37 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
38 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
39 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
40 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
41 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
42 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
43 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
44 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
45 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
46 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
47 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
48 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
49 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
50 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
51 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
52 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
53 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
54 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
55 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
56 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
57 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
58 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
59 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
60 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
61 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
62 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
63 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
64 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
65 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
66 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
67 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
68 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
69 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
70 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
71 u32 engineering_change[3]; /* 0x4 */
72 u32 manufacturing_id; /* 0x10 */
73 u32 serial_number[4]; /* 0x14 */
74 u32 pcie_cfg; /* 0x24 */
75 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
76 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
77 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
78 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
79 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
80 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
81 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
82 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
83 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
84 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
85 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
86 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
87 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
88 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
89 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
90 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \
92 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
93 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
94 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
95 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
96 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
97 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
98 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
99 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
100 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
101 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
102 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
103 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
104 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
105 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
106 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
107 /* Set the duration, in sec, fan failure signal should be sampled */
108 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \
110 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
111 u32 mgmt_traffic; /* 0x28 */
112 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
113 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
114 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
115 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
116 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
117 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
118 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
119 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
120 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
121 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
122 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
123 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
124 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
125 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
126 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
127 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
128 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
129 /* Indicates whether external thermal sonsor is available */
130 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
131 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
132 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
133 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
134 u32 core_cfg; /* 0x2C */
135 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
136 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
137 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
138 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
139 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
140 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
141 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
142 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
143 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
144 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
145 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
146 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
147 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
148 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
149 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
150 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
151 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
152 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
153 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
154 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
155 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
156 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
157 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
158 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
159 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
160 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
161 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
162 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
163 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
164 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
165 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
166 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
167 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
168 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
169 u32 e_lane_cfg1; /* 0x30 */
170 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
171 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
172 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
173 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
174 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
175 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
176 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
177 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
178 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
179 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
180 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
181 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
182 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
183 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
184 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
185 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
186 u32 e_lane_cfg2; /* 0x34 */
187 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
188 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
189 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
190 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
191 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
192 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
193 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
194 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
195 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
196 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
197 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
198 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
199 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
200 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
201 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
202 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
203 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
204 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
205 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
206 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
207 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
208 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
209 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
210 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
211 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
212 /* Maximum advertised pcie link width */
213 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
214 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
215 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
216 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
217 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
218 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
219 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
221 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
222 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
223 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
224 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
225 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
226 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
227 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
228 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
229 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
230 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
231 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \
233 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
234 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
235 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
236 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
237 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
238 /* Set the PLDM sensor modes */
239 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
240 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
241 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
242 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
243 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
244 u32 f_lane_cfg1; /* 0x38 */
245 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
246 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
247 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
248 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
249 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
250 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
251 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
252 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
253 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
254 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
255 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
256 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
257 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
258 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
259 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
260 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
261 u32 f_lane_cfg2; /* 0x3C */
262 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
263 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
264 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
265 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
266 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
267 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
268 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
269 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
270 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
271 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
272 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
273 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
274 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
275 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
276 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
277 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
278 /* Control the period between two successive checks */
279 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \
281 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
282 /* Set shutdown temperature */
283 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \
285 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
286 /* Set max. count for over operational temperature */
287 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
288 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
289 u32 mps10_preemphasis; /* 0x40 */
290 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
291 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
292 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
293 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
294 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
295 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
296 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
297 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
298 u32 mps10_driver_current; /* 0x44 */
299 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
300 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
301 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
302 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
303 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
304 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
305 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
306 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
307 u32 mps25_preemphasis; /* 0x48 */
308 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
309 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
310 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
311 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
312 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
313 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
314 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
315 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
316 u32 mps25_driver_current; /* 0x4C */
317 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
318 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
319 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
320 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
321 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
322 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
323 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
324 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
325 u32 pci_id; /* 0x50 */
326 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
327 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
328 /* Set caution temperature */
329 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK \
331 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16
332 /* Set external thermal sensor I2C address */
333 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \
335 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
336 u32 pci_subsys_id; /* 0x54 */
337 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
338 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
339 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
340 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
342 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
343 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
344 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
345 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
346 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
347 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
348 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
349 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
350 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
351 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
352 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
353 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
354 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
355 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
356 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
357 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
358 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
359 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
360 /* BB VF BAR2 size */
361 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
362 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
363 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
364 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
365 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
366 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
367 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
368 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
369 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
370 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
371 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
372 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
373 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
374 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
375 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
376 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
377 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
378 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
379 /* BB BAR2 size (global) */
380 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
381 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
382 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
383 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
384 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
385 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
386 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
387 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
388 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
389 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
390 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
391 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
392 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
393 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
394 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
395 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
396 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
397 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
398 /* Set the duration, in secs, fan failure signal should be sampled */
399 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
400 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
401 /* This field defines the board total budget for bar2 when disabled
402 * the regular bar size is used.
404 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
405 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
406 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
407 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
408 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
409 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
410 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
411 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
412 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
413 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
414 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
415 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
416 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
417 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
418 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
419 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
420 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
421 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
422 /* Enable/Disable Crash dump triggers */
423 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
424 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
425 u32 mps10_txfir_main; /* 0x5C */
426 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
427 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
428 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
429 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
430 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
431 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
432 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
433 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
434 u32 mps10_txfir_post; /* 0x60 */
435 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
436 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
437 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
438 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
439 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
440 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
441 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
442 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
443 u32 mps25_txfir_main; /* 0x64 */
444 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
445 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
446 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
447 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
448 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
449 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
450 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
451 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
452 u32 mps25_txfir_post; /* 0x68 */
453 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
454 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
455 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
456 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
457 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
458 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
459 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
460 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
461 u32 manufacture_ver; /* 0x6C */
462 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
463 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
464 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
465 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
466 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
467 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
468 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
469 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
470 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
471 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
472 u32 manufacture_time; /* 0x70 */
473 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
474 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
475 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
476 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
477 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
478 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
479 u32 led_global_settings; /* 0x74 */
480 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
481 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
482 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
483 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
484 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
485 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
486 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
487 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
488 u32 generic_cont1; /* 0x78 */
489 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
490 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
491 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
492 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
493 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
494 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
495 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
496 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
497 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
498 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
499 u32 mbi_version; /* 0x7C */
500 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
501 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
502 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
503 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
504 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
505 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
506 u32 mbi_date; /* 0x80 */
507 u32 misc_sig; /* 0x84 */
508 /* Define the GPIO mapping to switch i2c mux */
509 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
510 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
511 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
512 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
513 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
514 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
515 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
516 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
517 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
518 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
519 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
520 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
521 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
522 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
523 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
524 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
525 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
526 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
527 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
528 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
529 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
530 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
531 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
532 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
533 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
534 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
535 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
536 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
537 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
538 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
539 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
540 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
541 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
542 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
543 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
544 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
545 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
546 u32 device_capabilities; /* 0x88 */
547 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
548 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
549 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
550 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
551 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
552 u32 power_dissipated; /* 0x8C */
553 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
554 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
555 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
556 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
557 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
558 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
559 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
560 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
561 u32 power_consumed; /* 0x90 */
562 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
563 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
564 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
565 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
566 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
567 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
568 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
569 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
570 u32 efi_version; /* 0x94 */
571 u32 multi_network_modes_capability; /* 0x98 */
572 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
573 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
574 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
575 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
576 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
577 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
578 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
579 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
581 u32 reserved[41]; /* 0x9C */
584 struct nvm_cfg1_path {
585 u32 reserved[30]; /* 0x0 */
588 struct nvm_cfg1_port {
589 u32 reserved__m_relocated_to_option_123; /* 0x0 */
590 u32 reserved__m_relocated_to_option_124; /* 0x4 */
591 u32 generic_cont0; /* 0x8 */
592 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
593 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
594 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
595 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
596 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
597 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
598 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
599 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
600 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
601 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
602 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
603 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
604 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
605 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
606 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
607 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
608 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
609 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
610 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
611 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
612 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
613 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
614 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
615 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
616 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
617 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
618 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
619 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
620 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
621 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
622 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
623 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
624 u32 pcie_cfg; /* 0xC */
625 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
626 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
627 u32 features; /* 0x10 */
628 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
629 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
630 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
631 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
632 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
633 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
634 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
635 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
636 u32 speed_cap_mask; /* 0x14 */
637 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
638 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
639 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
640 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
641 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
642 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
643 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
644 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
645 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
646 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
647 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
648 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
649 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
650 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
651 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
652 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
653 u32 link_settings; /* 0x18 */
654 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
655 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
656 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
657 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
658 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
659 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
660 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
661 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
662 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
663 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
664 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
665 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
666 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
667 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
668 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
669 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
670 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
671 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
672 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
673 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
674 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
675 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
676 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
677 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
678 #define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
679 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
680 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
681 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
682 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
683 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
684 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \
686 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
687 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \
689 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \
691 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
692 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
693 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
694 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
695 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
696 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
697 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
698 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
699 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
700 u32 phy_cfg; /* 0x1C */
701 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
702 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
703 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
704 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
705 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
706 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
707 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
708 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
709 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
710 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
711 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
712 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
713 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
714 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
715 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
716 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
717 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
718 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
719 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
720 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
721 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
722 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
723 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
724 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
725 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
726 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
727 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
728 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
729 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
730 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
731 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
732 u32 mgmt_traffic; /* 0x20 */
733 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
734 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
735 u32 ext_phy; /* 0x24 */
736 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
737 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
738 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
739 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
740 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
741 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
742 u32 mba_cfg1; /* 0x28 */
743 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
744 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
745 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
746 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
747 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
748 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
749 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
750 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
751 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
752 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
753 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
754 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
755 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
756 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
757 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
758 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
759 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
760 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
761 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
762 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
763 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
764 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
765 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
766 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
767 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
768 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
769 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
770 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
771 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
773 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
774 u32 mba_cfg2; /* 0x2C */
775 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
776 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
777 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
778 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
779 u32 vf_cfg; /* 0x30 */
780 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
781 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
782 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
783 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
784 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
785 u32 led_port_settings; /* 0x3C */
786 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
787 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
788 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
789 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
790 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
791 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
792 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
793 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
794 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
795 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
796 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
797 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
798 u32 transceiver_00; /* 0x40 */
799 /* Define for mapping of transceiver signal module absent */
800 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
801 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
802 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
803 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
804 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
805 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
806 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
807 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
808 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
809 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
810 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
811 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
812 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
813 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
814 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
815 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
816 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
817 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
818 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
819 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
820 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
821 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
822 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
823 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
824 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
825 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
826 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
827 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
828 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
829 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
830 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
831 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
832 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
833 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
834 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
835 /* Define the GPIO mux settings to switch i2c mux to this port */
836 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
837 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
838 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
839 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
840 u32 device_ids; /* 0x44 */
841 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
842 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
843 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
844 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
845 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
846 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
847 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
848 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
849 u32 board_cfg; /* 0x48 */
850 /* This field defines the board technology
851 * (backpane,transceiver,external PHY)
853 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
854 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
855 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
856 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
857 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
858 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
859 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
860 /* This field defines the GPIO mapped to tx_disable signal in SFP */
861 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
862 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
863 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
864 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
865 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
866 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
867 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
868 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
869 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
870 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
871 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
872 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
873 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
874 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
875 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
876 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
877 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
878 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
879 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
880 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
881 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
882 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
883 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
884 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
885 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
886 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
887 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
888 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
889 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
890 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
891 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
892 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
893 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
894 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
895 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
896 u32 mnm_10g_cap; /* 0x4C */
897 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
899 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
900 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
901 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
902 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
903 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
904 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
906 NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
907 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
909 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
911 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
912 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
913 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
914 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
915 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
917 NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
918 u32 mnm_10g_ctrl; /* 0x50 */
919 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
920 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
921 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
922 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
923 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
924 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
925 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
926 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
927 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
928 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_SMARTLINQ 0x8
929 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
930 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
931 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
932 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
933 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
934 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
935 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
936 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
937 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
938 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_SMARTLINQ 0x8
939 /* This field defines the board technology
940 * (backpane,transceiver,external PHY)
942 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
943 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
944 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
945 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
946 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
947 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
948 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
949 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
951 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
952 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
953 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
954 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
955 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
956 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
957 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
958 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
959 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
960 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
961 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
962 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
963 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
964 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
965 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
966 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
967 u32 mnm_10g_misc; /* 0x54 */
968 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
969 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
970 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
971 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
972 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
973 u32 mnm_25g_cap; /* 0x58 */
974 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
976 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
977 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
978 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
979 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
980 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
981 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
983 NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
984 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
986 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
988 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
989 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
990 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
991 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
992 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
994 NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
995 u32 mnm_25g_ctrl; /* 0x5C */
996 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
997 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
998 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
999 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
1000 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
1001 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
1002 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
1003 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
1004 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
1005 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_SMARTLINQ 0x8
1006 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
1007 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
1008 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
1009 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
1010 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
1011 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
1012 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
1013 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
1014 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
1015 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_SMARTLINQ 0x8
1016 /* This field defines the board technology
1017 * (backpane,transceiver,external PHY)
1019 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
1020 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
1021 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
1022 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
1023 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
1024 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
1025 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
1026 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
1028 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
1029 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
1030 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
1031 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
1032 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
1033 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
1034 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
1035 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
1036 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
1037 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
1038 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
1039 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
1040 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
1041 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
1042 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
1043 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
1044 u32 mnm_25g_misc; /* 0x60 */
1045 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
1046 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
1047 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
1048 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
1049 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
1050 u32 mnm_40g_cap; /* 0x64 */
1051 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
1053 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1054 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1055 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1056 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1057 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1058 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1060 NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1061 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
1063 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1065 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1066 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1067 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1068 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1069 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1071 NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1072 u32 mnm_40g_ctrl; /* 0x68 */
1073 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
1074 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
1075 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
1076 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
1077 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
1078 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
1079 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
1080 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
1081 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
1082 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_SMARTLINQ 0x8
1083 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
1084 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
1085 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
1086 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
1087 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
1088 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
1089 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
1090 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
1091 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
1092 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_SMARTLINQ 0x8
1093 /* This field defines the board technology
1094 * (backpane,transceiver,external PHY)
1096 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
1097 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
1098 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
1099 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
1100 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
1101 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
1102 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
1103 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
1105 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
1106 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
1107 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
1108 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
1109 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
1110 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
1111 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
1112 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
1113 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
1114 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
1115 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
1116 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
1117 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
1118 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
1119 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
1120 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
1121 u32 mnm_40g_misc; /* 0x6C */
1122 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
1123 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
1124 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
1125 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
1126 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
1127 u32 mnm_50g_cap; /* 0x70 */
1128 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
1130 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1131 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1132 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1133 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1134 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1135 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1137 NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
1139 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
1141 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1143 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1144 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1145 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1146 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1147 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1149 NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
1151 u32 mnm_50g_ctrl; /* 0x74 */
1152 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
1153 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
1154 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
1155 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
1156 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
1157 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
1158 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
1159 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
1160 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
1161 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_SMARTLINQ 0x8
1162 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
1163 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
1164 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
1165 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
1166 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
1167 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
1168 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
1169 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
1170 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
1171 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_SMARTLINQ 0x8
1172 /* This field defines the board technology
1173 * (backpane,transceiver,external PHY)
1175 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
1176 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
1177 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
1178 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
1179 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
1180 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
1181 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
1182 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
1184 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
1185 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
1186 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
1187 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
1188 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
1189 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
1190 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
1191 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
1192 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
1193 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
1194 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
1195 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
1196 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
1197 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
1198 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
1199 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
1200 u32 mnm_50g_misc; /* 0x78 */
1201 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
1202 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
1203 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
1204 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
1205 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
1206 u32 mnm_100g_cap; /* 0x7C */
1207 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
1209 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
1210 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
1211 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
1212 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
1213 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
1214 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
1215 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
1216 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
1218 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
1219 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
1220 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
1221 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
1222 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
1223 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
1224 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
1225 u32 mnm_100g_ctrl; /* 0x80 */
1226 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
1227 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
1228 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
1229 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
1230 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
1231 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
1232 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
1233 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
1234 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
1235 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_SMARTLINQ 0x8
1236 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
1237 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
1238 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
1239 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
1240 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
1241 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
1242 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
1243 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
1244 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
1245 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_SMARTLINQ 0x8
1246 /* This field defines the board technology
1247 * (backpane,transceiver,external PHY)
1249 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
1250 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
1251 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
1252 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
1253 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
1254 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
1255 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
1256 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
1258 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
1259 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
1260 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
1261 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
1262 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
1263 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
1264 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
1265 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
1266 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
1267 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
1268 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
1269 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
1270 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
1271 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
1272 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
1273 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
1274 u32 mnm_100g_misc; /* 0x84 */
1275 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
1276 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
1277 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
1278 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
1279 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
1280 u32 reserved[116]; /* 0x88 */
1283 struct nvm_cfg1_func {
1284 struct nvm_cfg_mac_address mac_address; /* 0x0 */
1285 u32 rsrv1; /* 0x8 */
1286 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
1287 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
1288 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
1289 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
1290 u32 rsrv2; /* 0xC */
1291 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
1292 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
1293 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
1294 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
1295 u32 device_id; /* 0x10 */
1296 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
1297 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
1298 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
1299 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
1300 u32 cmn_cfg; /* 0x14 */
1301 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
1302 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
1303 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
1304 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
1305 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
1306 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
1307 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
1308 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
1309 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
1310 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
1311 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
1312 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
1313 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
1314 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
1315 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
1316 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
1317 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
1318 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
1319 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
1320 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
1321 u32 pci_cfg; /* 0x18 */
1322 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
1323 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
1324 /* AH VF BAR2 size */
1325 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
1326 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
1327 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
1328 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
1329 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
1330 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
1331 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
1332 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
1333 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
1334 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
1335 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
1336 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
1337 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
1338 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
1339 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
1340 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
1341 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
1342 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
1343 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
1344 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
1345 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
1346 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
1347 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
1348 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
1349 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
1350 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
1351 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
1352 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
1353 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
1354 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
1355 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
1356 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
1357 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
1358 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
1359 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
1360 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
1361 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
1362 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
1363 /* Hide function in npar mode */
1364 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
1365 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
1366 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
1367 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
1368 /* AH BAR2 size (per function) */
1369 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
1370 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
1371 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
1372 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
1373 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
1374 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
1375 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
1376 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
1377 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
1378 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
1379 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
1380 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
1381 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
1382 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
1383 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
1384 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
1385 u32 preboot_generic_cfg; /* 0x2C */
1386 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
1387 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
1388 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
1389 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
1390 u32 reserved[8]; /* 0x30 */
1394 struct nvm_cfg1_glob glob; /* 0x0 */
1395 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
1396 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
1397 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
1400 /******************************************
1402 ******************************************/
1403 enum nvm_cfg_sections {
1404 NVM_CFG_SECTION_NVM_CFG1,
1410 u32 sections_offset[NVM_CFG_SECTION_MAX];
1411 struct nvm_cfg1 cfg1;
1414 #endif /* NVM_CFG_H */