2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: NVM config file - Generated file from nvm cfg excel.
18 ****************************************************************************/
23 #define NVM_CFG_version 0x83000
25 #define NVM_CFG_new_option_seq 23
27 #define NVM_CFG_removed_option_seq 1
29 #define NVM_CFG_updated_value_seq 4
31 struct nvm_cfg_mac_address {
33 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
34 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
38 /******************************************
40 ******************************************/
41 struct nvm_cfg1_glob {
42 u32 generic_cont0; /* 0x0 */
43 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
44 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
45 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
46 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
47 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
48 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
49 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
50 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
51 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
52 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
53 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
54 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
55 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
56 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
57 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
58 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
59 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
60 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
61 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
62 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
63 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
64 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
65 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
66 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
67 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
68 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
69 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
70 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
71 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
72 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
73 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
74 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
75 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK \
77 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31
78 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED \
80 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1
81 u32 engineering_change[3]; /* 0x4 */
82 u32 manufacturing_id; /* 0x10 */
83 u32 serial_number[4]; /* 0x14 */
84 u32 pcie_cfg; /* 0x24 */
85 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
86 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
87 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
88 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
89 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
90 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
91 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
92 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
93 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
94 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
95 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
96 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
97 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
98 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
99 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
100 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \
102 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
103 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
104 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
105 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
106 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
107 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
108 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
109 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
110 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
111 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
112 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
113 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
114 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
115 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
116 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
117 /* Set the duration, in sec, fan failure signal should be sampled */
118 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \
120 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
121 u32 mgmt_traffic; /* 0x28 */
122 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
123 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
124 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
125 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
126 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
127 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
128 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
129 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
130 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
131 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
132 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
133 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
134 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
135 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
136 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
137 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
138 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
139 /* Indicates whether external thermal sonsor is available */
140 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
141 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
142 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
143 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
144 u32 core_cfg; /* 0x2C */
145 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
146 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
147 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
148 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
149 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
150 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
151 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
152 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
153 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
154 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
155 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
156 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
157 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
158 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
159 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
160 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
161 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
162 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
163 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
164 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
165 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
166 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
167 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
168 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
169 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
170 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
171 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
172 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
173 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
174 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
175 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
176 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
177 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
178 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
179 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
180 u32 e_lane_cfg1; /* 0x30 */
181 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
182 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
183 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
184 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
185 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
186 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
187 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
188 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
189 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
190 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
191 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
192 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
193 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
194 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
195 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
196 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
197 u32 e_lane_cfg2; /* 0x34 */
198 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
199 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
200 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
201 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
202 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
203 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
204 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
205 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
206 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
207 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
208 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
209 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
210 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
211 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
212 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
213 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
214 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
215 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
216 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
217 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
218 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
219 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
220 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
221 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
222 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
223 /* Maximum advertised pcie link width */
224 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
225 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
226 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
227 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
228 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
229 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
230 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
232 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
233 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
234 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
235 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
236 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
237 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
238 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
239 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
240 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
241 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
242 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \
244 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
245 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
246 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
247 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
248 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
249 /* Set the PLDM sensor modes */
250 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
251 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
252 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
253 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
254 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
256 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000
257 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31
258 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0
259 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1
260 u32 f_lane_cfg1; /* 0x38 */
261 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
262 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
263 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
264 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
265 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
266 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
267 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
268 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
269 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
270 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
271 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
272 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
273 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
274 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
275 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
276 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
277 u32 f_lane_cfg2; /* 0x3C */
278 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
279 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
280 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
281 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
282 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
283 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
284 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
285 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
286 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
287 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
288 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
289 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
290 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
291 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
292 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
293 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
294 /* Control the period between two successive checks */
295 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \
297 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
298 /* Set shutdown temperature */
299 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \
301 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
302 /* Set max. count for over operational temperature */
303 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
304 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
305 u32 mps10_preemphasis; /* 0x40 */
306 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
307 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
308 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
309 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
310 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
311 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
312 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
313 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
314 u32 mps10_driver_current; /* 0x44 */
315 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
316 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
317 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
318 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
319 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
320 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
321 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
322 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
323 u32 mps25_preemphasis; /* 0x48 */
324 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
325 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
326 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
327 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
328 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
329 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
330 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
331 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
332 u32 mps25_driver_current; /* 0x4C */
333 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
334 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
335 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
336 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
337 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
338 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
339 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
340 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
341 u32 pci_id; /* 0x50 */
342 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
343 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
344 /* Set caution temperature */
345 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK 0x00FF0000
346 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_OFFSET 16
347 /* Set external thermal sensor I2C address */
348 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \
350 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
351 u32 pci_subsys_id; /* 0x54 */
352 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
353 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
354 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
355 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
357 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
358 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
359 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
360 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
361 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
362 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
363 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
364 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
365 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
366 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
367 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
368 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
369 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
370 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
371 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
372 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
373 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
374 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
375 /* BB VF BAR2 size */
376 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
377 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
378 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
379 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
380 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
381 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
382 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
383 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
384 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
385 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
386 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
387 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
388 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
389 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
390 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
391 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
392 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
393 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
394 /* BB BAR2 size (global) */
395 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
396 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
397 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
398 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
399 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
400 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
401 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
402 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
403 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
404 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
405 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
406 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
407 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
408 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
409 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
410 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
411 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
412 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
413 /* Set the duration, in secs, fan failure signal should be sampled */
414 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
415 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
416 /* This field defines the board total budget for bar2 when disabled
417 * the regular bar size is used.
419 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
420 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
421 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
422 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
423 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
424 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
425 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
426 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
427 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
428 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
429 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
430 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
431 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
432 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
433 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
434 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
435 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
436 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
437 /* Enable/Disable Crash dump triggers */
438 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
439 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
440 u32 mps10_txfir_main; /* 0x5C */
441 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
442 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
443 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
444 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
445 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
446 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
447 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
448 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
449 u32 mps10_txfir_post; /* 0x60 */
450 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
451 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
452 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
453 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
454 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
455 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
456 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
457 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
458 u32 mps25_txfir_main; /* 0x64 */
459 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
460 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
461 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
462 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
463 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
464 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
465 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
466 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
467 u32 mps25_txfir_post; /* 0x68 */
468 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
469 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
470 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
471 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
472 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
473 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
474 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
475 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
476 u32 manufacture_ver; /* 0x6C */
477 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
478 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
479 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
480 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
481 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
482 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
483 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
484 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
485 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
486 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
487 /* Select package id method */
488 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000
489 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30
490 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0
491 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1
492 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000
493 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31
494 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0
495 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1
496 u32 manufacture_time; /* 0x70 */
497 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
498 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
499 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
500 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
501 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
502 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
503 /* Max MSIX for Ethernet in default mode */
504 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000
505 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18
507 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000
508 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26
509 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0
510 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1
511 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000
512 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28
513 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0
514 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1
515 u32 led_global_settings; /* 0x74 */
516 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
517 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
518 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
519 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
520 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
521 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
522 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
523 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
524 /* Max. continues operating temperature */
525 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000
526 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16
527 /* GPIO which triggers run-time port swap according to the map
528 * specified in option 205
530 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000
531 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24
532 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0
533 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1
534 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2
535 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3
536 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4
537 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5
538 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6
539 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7
540 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8
541 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9
542 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA
543 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB
544 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC
545 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD
546 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE
547 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF
548 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10
549 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11
550 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12
551 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13
552 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14
553 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15
554 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16
555 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17
556 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18
557 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19
558 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A
559 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B
560 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C
561 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D
562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E
563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F
564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20
565 u32 generic_cont1; /* 0x78 */
566 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
567 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
568 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
569 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
570 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
571 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
572 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
573 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
574 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
575 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
576 /* Enable option 195 - Overriding the PCIe Preset value */
577 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000
578 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18
579 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0
580 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1
581 /* PCIe Preset value - applies only if option 194 is enabled */
582 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000
583 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19
584 /* Port mapping to be used when the run-time GPIO for port-swap is
587 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000
588 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23
589 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000
590 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25
591 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000
592 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27
593 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000
594 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29
595 u32 mbi_version; /* 0x7C */
596 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
597 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
598 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
599 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
600 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
601 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
602 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event
605 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000
606 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24
607 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0
608 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1
609 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2
610 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3
611 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4
612 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5
613 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6
614 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7
615 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8
616 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9
617 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA
618 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB
619 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC
620 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD
621 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE
622 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF
623 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10
624 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11
625 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12
626 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13
627 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14
628 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15
629 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16
630 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17
631 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18
632 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19
633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A
634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B
635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C
636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D
637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E
638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F
639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20
640 u32 mbi_date; /* 0x80 */
641 u32 misc_sig; /* 0x84 */
642 /* Define the GPIO mapping to switch i2c mux */
643 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
644 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
645 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
646 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
647 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
648 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
649 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
650 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
651 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
652 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
653 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
654 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
655 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
656 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
657 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
658 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
659 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
660 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
661 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
662 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
663 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
664 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
665 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
666 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
667 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
668 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
669 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
670 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
680 /* Interrupt signal used for SMBus/I2C management interface
681 * 0 = Interrupt event occurred
684 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000
685 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16
686 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0
687 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1
688 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2
689 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3
690 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4
691 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5
692 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6
693 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7
694 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8
695 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9
696 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA
697 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB
698 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC
699 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD
700 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE
701 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF
702 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10
703 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11
704 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12
705 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13
706 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14
707 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15
708 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16
709 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17
710 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18
711 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19
712 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A
713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B
714 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C
715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D
716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E
717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F
718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20
719 /* Set aLOM FAN on GPIO */
720 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000
721 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24
722 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0
723 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1
724 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2
725 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3
726 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4
727 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5
728 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6
729 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7
730 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8
731 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9
732 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA
733 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB
734 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC
735 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD
736 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE
737 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF
738 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10
739 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11
740 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12
741 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13
742 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14
743 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15
744 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16
745 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17
746 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18
747 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19
748 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A
749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B
750 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C
751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D
752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E
753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F
754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20
755 u32 device_capabilities; /* 0x88 */
756 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
757 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
758 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
759 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
760 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
761 u32 power_dissipated; /* 0x8C */
762 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
763 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
764 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
765 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
766 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
767 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
768 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
769 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
770 u32 power_consumed; /* 0x90 */
771 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
772 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
773 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
774 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
775 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
776 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
777 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
778 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
779 u32 efi_version; /* 0x94 */
780 u32 multi_network_modes_capability; /* 0x98 */
781 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
782 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
783 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
784 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
785 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
786 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
787 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
788 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
790 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100
792 u32 reserved1[12]; /* 0x9C */
793 u32 oem1_number[8]; /* 0xCC */
794 u32 oem2_number[8]; /* 0xEC */
795 u32 mps25_active_txfir_pre; /* 0x10C */
796 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF
797 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0
798 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00
799 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8
800 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000
801 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16
802 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000
803 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24
804 u32 mps25_active_txfir_main; /* 0x110 */
805 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF
806 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0
807 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00
808 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8
809 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000
810 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16
811 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000
812 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24
813 u32 mps25_active_txfir_post; /* 0x114 */
814 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF
815 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0
816 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00
817 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8
818 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000
819 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16
820 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000
821 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24
822 u32 features; /* 0x118 */
823 /* Set the Aux Fan on temperature */
824 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF
825 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0
826 /* Set NC-SI package ID */
827 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00
828 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8
829 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0
830 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1
831 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2
832 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3
833 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4
834 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5
835 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6
836 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7
837 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8
838 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9
839 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA
840 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB
841 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC
842 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD
843 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE
844 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF
845 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10
846 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11
847 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12
848 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13
849 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14
850 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15
851 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16
852 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17
853 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18
854 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19
855 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A
856 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B
857 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C
858 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D
859 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E
860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F
861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20
862 /* PMBUS Clock GPIO */
863 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000
864 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16
865 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0
866 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1
867 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2
868 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3
869 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4
870 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5
871 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6
872 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7
873 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8
874 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9
875 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA
876 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB
877 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC
878 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD
879 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE
880 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF
881 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10
882 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11
883 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12
884 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13
885 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14
886 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15
887 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16
888 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17
889 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18
890 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19
891 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A
892 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B
893 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C
894 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D
895 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E
896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F
897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20
898 /* PMBUS Data GPIO */
899 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000
900 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24
901 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0
902 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1
903 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2
904 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3
905 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4
906 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5
907 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6
908 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7
909 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8
910 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9
911 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA
912 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB
913 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC
914 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD
915 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE
916 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF
917 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10
918 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11
919 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12
920 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13
921 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14
922 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15
923 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16
924 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17
925 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18
926 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19
927 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A
928 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B
929 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C
930 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D
931 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E
932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F
933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20
934 u32 tx_rx_eq_25g_hlpc; /* 0x11C */
935 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF
936 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0
937 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00
938 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8
939 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000
940 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16
941 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000
942 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24
943 u32 tx_rx_eq_25g_llpc; /* 0x120 */
944 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF
945 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0
946 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00
947 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8
948 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000
949 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16
950 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000
951 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24
952 u32 tx_rx_eq_25g_ac; /* 0x124 */
953 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF
954 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0
955 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00
956 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8
957 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000
958 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16
959 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000
960 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24
961 u32 tx_rx_eq_10g_pc; /* 0x128 */
962 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF
963 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0
964 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00
965 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8
966 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000
967 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16
968 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000
969 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24
970 u32 tx_rx_eq_10g_ac; /* 0x12C */
971 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF
972 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0
973 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00
974 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8
975 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000
976 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16
977 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000
978 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24
979 u32 tx_rx_eq_1g; /* 0x130 */
980 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF
981 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0
982 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00
983 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8
984 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000
985 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16
986 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000
987 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24
988 u32 tx_rx_eq_25g_bt; /* 0x134 */
989 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF
990 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0
991 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00
992 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8
993 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000
994 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16
995 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000
996 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24
997 u32 tx_rx_eq_10g_bt; /* 0x138 */
998 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF
999 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0
1000 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00
1001 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8
1002 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000
1003 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16
1004 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000
1005 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24
1006 u32 generic_cont4; /* 0x13C */
1007 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF
1008 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0
1009 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0
1010 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1
1011 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2
1012 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3
1013 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4
1014 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5
1015 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6
1016 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7
1017 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8
1018 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9
1019 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA
1020 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB
1021 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC
1022 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD
1023 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE
1024 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF
1025 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10
1026 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11
1027 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12
1028 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13
1029 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14
1030 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15
1031 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16
1032 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17
1033 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18
1034 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19
1035 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A
1036 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B
1037 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C
1038 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D
1039 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E
1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F
1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20
1042 u32 preboot_debug_mode_std; /* 0x140 */
1043 u32 preboot_debug_mode_ext; /* 0x144 */
1044 u32 ext_phy_cfg1; /* 0x148 */
1045 /* Ext PHY MDI pair swap value */
1046 #define NVM_CFG1_GLOB_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF
1047 #define NVM_CFG1_GLOB_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0
1048 u32 reserved[55]; /* 0x14C */
1051 struct nvm_cfg1_path {
1052 u32 reserved[1]; /* 0x0 */
1055 struct nvm_cfg1_port {
1056 u32 reserved__m_relocated_to_option_123; /* 0x0 */
1057 u32 reserved__m_relocated_to_option_124; /* 0x4 */
1058 u32 generic_cont0; /* 0x8 */
1059 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
1060 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
1061 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
1062 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
1063 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
1064 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
1065 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
1066 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
1067 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
1068 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
1069 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
1070 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
1071 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
1072 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
1073 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
1074 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
1075 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
1076 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
1077 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
1078 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
1079 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
1080 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
1081 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
1082 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
1083 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
1084 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
1085 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
1086 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
1087 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
1088 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
1089 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
1090 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
1091 /* GPIO for HW reset the PHY. In case it is the same for all ports,
1092 * need to set same value for all ports
1094 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000
1095 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24
1096 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0
1097 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1
1098 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2
1099 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3
1100 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4
1101 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5
1102 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6
1103 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7
1104 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8
1105 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9
1106 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA
1107 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB
1108 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC
1109 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD
1110 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE
1111 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF
1112 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10
1113 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11
1114 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12
1115 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13
1116 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14
1117 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15
1118 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16
1119 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17
1120 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18
1121 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19
1122 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A
1123 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B
1124 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C
1125 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D
1126 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E
1127 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F
1128 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20
1129 u32 pcie_cfg; /* 0xC */
1130 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
1131 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
1132 u32 features; /* 0x10 */
1133 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
1134 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
1135 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
1136 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
1137 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
1138 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
1139 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
1140 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
1141 u32 speed_cap_mask; /* 0x14 */
1142 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1143 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1144 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1145 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1146 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1147 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1148 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1149 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1150 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1151 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1152 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1153 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1154 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1155 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1156 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1157 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1158 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1159 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1160 u32 link_settings; /* 0x18 */
1161 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
1162 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
1163 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
1164 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
1165 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
1166 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
1167 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
1168 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
1169 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
1170 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
1171 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
1172 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
1173 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
1174 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
1175 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
1176 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
1177 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
1178 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
1179 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
1180 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
1181 #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3
1182 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
1183 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
1184 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
1185 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
1186 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
1187 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
1188 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
1189 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
1190 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
1191 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \
1193 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
1194 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \
1196 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \
1198 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
1199 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
1200 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
1201 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
1202 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
1203 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
1204 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
1205 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
1206 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
1207 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
1208 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000
1209 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20
1210 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0
1211 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1
1212 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2
1213 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3
1214 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4
1215 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5
1216 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6
1217 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000
1218 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23
1219 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0
1220 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1
1221 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000
1222 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24
1223 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0
1224 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1
1225 u32 phy_cfg; /* 0x1C */
1226 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
1227 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
1228 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
1229 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
1230 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
1231 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
1232 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
1233 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
1234 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
1235 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
1236 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
1237 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
1238 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
1239 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
1240 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
1241 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
1242 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
1243 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
1244 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
1245 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
1246 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
1247 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
1248 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
1249 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
1250 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
1251 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
1252 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
1253 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
1254 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
1255 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
1256 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
1257 u32 mgmt_traffic; /* 0x20 */
1258 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
1259 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
1260 u32 ext_phy; /* 0x24 */
1261 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
1262 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
1263 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
1264 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1
1265 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2
1266 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
1267 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
1268 /* EEE power saving mode */
1269 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
1270 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
1271 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
1272 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
1273 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
1274 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
1275 u32 mba_cfg1; /* 0x28 */
1276 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
1277 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
1278 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
1279 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
1280 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
1281 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
1282 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
1283 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
1284 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
1285 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
1286 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
1287 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
1288 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
1289 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
1290 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
1291 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
1292 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
1293 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
1294 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
1295 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
1296 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
1297 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
1298 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
1299 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3
1300 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
1301 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
1302 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
1303 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
1304 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
1306 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
1307 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK \
1309 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24
1310 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED \
1312 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1
1313 u32 mba_cfg2; /* 0x2C */
1314 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
1315 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
1316 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
1317 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
1318 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000
1319 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17
1320 u32 vf_cfg; /* 0x30 */
1321 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
1322 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
1323 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
1324 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
1325 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
1326 u32 led_port_settings; /* 0x3C */
1327 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
1328 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
1329 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
1330 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
1331 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
1332 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
1333 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
1334 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
1335 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4
1336 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8
1337 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8
1338 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10
1339 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10
1340 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20
1341 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
1342 u32 transceiver_00; /* 0x40 */
1343 /* Define for mapping of transceiver signal module absent */
1344 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
1345 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
1346 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
1347 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
1348 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
1349 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
1350 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
1351 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
1352 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
1353 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
1354 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
1355 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
1356 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
1357 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
1358 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
1359 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
1360 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
1361 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
1362 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
1363 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
1364 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
1365 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
1366 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
1367 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
1368 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
1369 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
1370 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
1371 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
1372 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
1373 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
1374 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
1375 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
1376 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
1377 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
1378 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
1379 /* Define the GPIO mux settings to switch i2c mux to this port */
1380 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
1381 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
1382 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
1383 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
1384 u32 device_ids; /* 0x44 */
1385 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
1386 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
1387 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
1388 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
1389 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
1390 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
1391 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
1392 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
1393 u32 board_cfg; /* 0x48 */
1394 /* This field defines the board technology
1395 * (backpane,transceiver,external PHY)
1397 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
1398 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
1399 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
1400 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
1401 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
1402 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
1403 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
1404 /* This field defines the GPIO mapped to tx_disable signal in SFP */
1405 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
1406 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
1407 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
1408 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
1409 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
1410 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
1411 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
1412 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
1413 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
1414 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
1415 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
1416 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
1417 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
1418 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
1419 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
1420 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
1421 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
1422 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
1423 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
1424 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
1425 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
1426 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
1427 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
1428 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
1429 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
1430 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
1431 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
1432 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
1433 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
1434 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
1435 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
1436 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
1437 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
1438 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
1439 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
1440 u32 mnm_10g_cap; /* 0x4C */
1441 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
1443 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1444 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1445 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1446 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1447 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1448 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1449 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1451 NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1452 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
1454 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1456 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1457 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1458 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1459 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1460 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1461 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1463 NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1464 u32 mnm_10g_ctrl; /* 0x50 */
1465 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
1466 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
1467 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
1468 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
1469 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
1470 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3
1471 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
1472 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
1473 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
1474 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
1475 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
1476 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
1477 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
1478 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
1479 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
1480 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3
1481 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
1482 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
1483 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
1484 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
1485 /* This field defines the board technology
1486 * (backpane,transceiver,external PHY)
1488 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
1489 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
1490 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
1491 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
1492 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
1493 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
1494 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
1495 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
1497 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
1498 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
1499 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
1500 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
1501 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
1502 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
1503 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
1504 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
1505 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
1506 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
1507 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
1508 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
1509 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
1510 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
1511 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
1512 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
1513 u32 mnm_10g_misc; /* 0x54 */
1514 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
1515 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
1516 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
1517 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
1518 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
1519 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7
1520 u32 mnm_25g_cap; /* 0x58 */
1521 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
1523 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1524 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1525 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1526 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1527 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1528 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1529 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1531 NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1532 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
1534 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1536 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1537 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1538 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1539 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1540 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1541 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1543 NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1544 u32 mnm_25g_ctrl; /* 0x5C */
1545 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
1546 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
1547 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
1548 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
1549 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
1550 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3
1551 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
1552 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
1553 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
1554 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
1555 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
1556 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
1557 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
1558 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
1559 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
1560 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3
1561 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
1562 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
1563 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
1564 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
1565 /* This field defines the board technology
1566 * (backpane,transceiver,external PHY)
1568 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
1569 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
1570 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
1571 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
1572 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
1573 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
1574 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
1575 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
1577 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
1578 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
1579 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
1580 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
1581 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
1582 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
1583 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
1584 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
1585 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
1586 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
1587 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
1588 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
1589 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
1590 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
1591 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
1592 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
1593 u32 mnm_25g_misc; /* 0x60 */
1594 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
1595 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
1596 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
1597 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
1598 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
1599 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7
1600 u32 mnm_40g_cap; /* 0x64 */
1601 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
1603 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1604 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1605 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1606 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1607 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1608 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1609 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1611 NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1612 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
1614 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1616 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1617 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1618 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1619 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1620 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1621 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1623 NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1624 u32 mnm_40g_ctrl; /* 0x68 */
1625 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
1626 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
1627 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
1628 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
1629 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
1630 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3
1631 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
1632 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
1633 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
1634 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
1635 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
1636 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
1637 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
1638 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
1639 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
1640 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3
1641 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
1642 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
1643 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
1644 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
1645 /* This field defines the board technology
1646 * (backpane,transceiver,external PHY)
1648 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
1649 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
1650 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
1651 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
1652 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
1653 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
1654 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
1655 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
1657 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
1658 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
1659 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
1660 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
1661 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
1662 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
1663 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
1664 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
1665 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
1666 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
1667 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
1668 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
1669 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
1670 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
1671 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
1672 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
1673 u32 mnm_40g_misc; /* 0x6C */
1674 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
1675 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
1676 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
1677 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
1678 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
1679 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7
1680 u32 mnm_50g_cap; /* 0x70 */
1681 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
1683 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1684 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1685 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1686 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1687 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1688 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1689 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1691 NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
1693 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
1695 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1697 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1698 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1699 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1700 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1701 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1702 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1704 NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
1706 u32 mnm_50g_ctrl; /* 0x74 */
1707 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
1708 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
1709 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
1710 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
1711 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
1712 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3
1713 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
1714 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
1715 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
1716 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
1717 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
1718 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
1719 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
1720 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
1721 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
1722 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3
1723 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
1724 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
1725 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
1726 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
1727 /* This field defines the board technology
1728 * (backpane,transceiver,external PHY)
1730 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
1731 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
1732 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
1733 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
1734 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
1735 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
1736 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
1737 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
1739 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
1740 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
1741 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
1742 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
1743 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
1744 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
1745 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
1746 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
1747 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
1748 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
1749 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
1750 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
1751 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
1752 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
1753 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
1754 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
1755 u32 mnm_50g_misc; /* 0x78 */
1756 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
1757 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
1758 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
1759 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
1760 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
1761 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7
1762 u32 mnm_100g_cap; /* 0x7C */
1763 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
1765 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
1766 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
1767 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
1768 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4
1769 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
1770 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
1771 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
1772 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
1773 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
1775 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
1776 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
1777 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
1778 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4
1779 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
1780 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
1781 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
1782 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
1783 u32 mnm_100g_ctrl; /* 0x80 */
1784 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
1785 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
1786 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
1787 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
1788 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
1789 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3
1790 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
1791 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
1792 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
1793 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
1794 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
1795 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
1796 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
1797 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
1798 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
1799 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3
1800 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
1801 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
1802 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
1803 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
1804 /* This field defines the board technology
1805 * (backpane,transceiver,external PHY)
1807 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
1808 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
1809 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
1810 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
1811 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
1812 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
1813 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
1814 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
1816 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
1817 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
1818 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
1819 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
1820 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
1821 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
1822 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
1823 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
1824 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
1825 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
1826 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
1827 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
1828 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
1829 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
1830 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
1831 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
1832 u32 mnm_100g_misc; /* 0x84 */
1833 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
1834 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
1835 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
1836 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
1837 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
1838 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7
1839 u32 temperature; /* 0x88 */
1840 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF
1841 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0
1842 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK \
1844 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8
1845 u32 reserved[115]; /* 0x8C */
1848 struct nvm_cfg1_func {
1849 struct nvm_cfg_mac_address mac_address; /* 0x0 */
1850 u32 rsrv1; /* 0x8 */
1851 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
1852 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
1853 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
1854 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
1855 u32 rsrv2; /* 0xC */
1856 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
1857 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
1858 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
1859 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
1860 u32 device_id; /* 0x10 */
1861 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
1862 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
1863 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
1864 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
1865 u32 cmn_cfg; /* 0x14 */
1866 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
1867 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
1868 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
1869 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
1870 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
1871 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
1872 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
1873 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
1874 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
1875 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
1876 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
1877 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
1878 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
1879 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
1880 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
1881 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
1882 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
1883 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
1884 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
1885 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
1886 u32 pci_cfg; /* 0x18 */
1887 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
1888 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
1889 /* AH VF BAR2 size */
1890 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
1891 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
1892 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
1893 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
1894 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
1895 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
1896 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
1897 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
1898 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
1899 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
1900 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
1901 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
1902 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
1903 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
1904 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
1905 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
1906 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
1907 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
1908 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
1909 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
1910 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
1911 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
1912 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
1913 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
1914 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
1915 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
1916 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
1917 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
1918 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
1919 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
1920 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
1921 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
1922 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
1923 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
1924 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
1925 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
1926 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
1927 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
1928 /* Hide function in npar mode */
1929 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
1930 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
1931 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
1932 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
1933 /* AH BAR2 size (per function) */
1934 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
1935 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
1936 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
1937 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
1938 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
1939 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
1940 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
1941 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
1942 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
1943 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
1944 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
1945 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
1946 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
1947 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
1948 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
1949 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
1950 u32 preboot_generic_cfg; /* 0x2C */
1951 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
1952 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
1953 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
1954 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
1955 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000
1956 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17
1957 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1
1958 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2
1959 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4
1960 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8
1961 u32 reserved[8]; /* 0x30 */
1965 struct nvm_cfg1_glob glob; /* 0x0 */
1966 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */
1967 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
1968 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
1971 /******************************************
1973 ******************************************/
1974 enum nvm_cfg_sections {
1975 NVM_CFG_SECTION_NVM_CFG1,
1981 u32 sections_offset[NVM_CFG_SECTION_MAX];
1982 struct nvm_cfg1 cfg1;
1985 #endif /* NVM_CFG_H */