1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 /****************************************************************************
11 * Description: NVM config file - Generated file from nvm cfg excel.
16 ****************************************************************************/
22 #define NVM_CFG_version 0x84500
24 #define NVM_CFG_new_option_seq 45
26 #define NVM_CFG_removed_option_seq 4
28 #define NVM_CFG_updated_value_seq 13
30 struct nvm_cfg_mac_address {
32 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
33 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
37 /******************************************
39 ******************************************/
40 struct nvm_cfg1_glob {
41 u32 generic_cont0; /* 0x0 */
42 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
43 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
44 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
45 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
46 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
47 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
48 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
49 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
50 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
51 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
52 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
53 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
54 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
55 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
56 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
57 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
58 #define NVM_CFG1_GLOB_MF_MODE_DCI_NPAR 0x8
59 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
60 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
61 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
62 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
63 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
64 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
65 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
66 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
67 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
68 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
69 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
70 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
71 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
72 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
73 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
74 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
75 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK \
77 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31
78 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED \
80 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1
81 u32 engineering_change[3]; /* 0x4 */
82 u32 manufacturing_id; /* 0x10 */
83 u32 serial_number[4]; /* 0x14 */
84 u32 pcie_cfg; /* 0x24 */
85 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
86 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
87 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
88 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
89 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
90 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
91 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
92 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
93 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
94 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
95 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
96 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
97 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
98 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
99 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
100 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \
102 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
103 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
104 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
105 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
106 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
107 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
108 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
109 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
110 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
111 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
112 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
113 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
114 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
115 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
116 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
117 /* Set the duration, in sec, fan failure signal should be sampled */
118 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \
120 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
121 u32 mgmt_traffic; /* 0x28 */
122 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
123 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
124 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
125 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
126 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
127 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
128 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
129 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
130 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
131 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
132 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
133 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
134 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
135 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
136 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
137 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
138 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
139 /* Indicates whether external thermal sonsor is available */
140 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
141 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
142 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
143 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
144 u32 core_cfg; /* 0x2C */
145 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
146 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
147 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
148 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
149 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
150 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
151 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
152 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
153 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
154 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
155 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
156 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
157 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
158 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G_LIO2 0x10
159 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
160 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
161 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
162 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
163 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
164 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
165 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
166 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
167 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
168 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
169 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
170 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
171 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
172 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
173 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
174 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
175 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
176 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
177 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
178 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
179 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
180 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
181 u32 e_lane_cfg1; /* 0x30 */
182 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
183 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
184 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
185 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
186 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
187 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
188 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
189 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
190 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
191 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
192 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
193 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
194 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
195 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
196 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
197 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
198 u32 e_lane_cfg2; /* 0x34 */
199 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
200 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
201 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
202 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
203 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
204 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
205 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
206 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
207 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
208 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
209 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
210 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
211 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
212 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
213 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
214 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
215 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
216 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
217 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
218 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
219 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
220 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
221 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
222 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
223 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
224 /* Maximum advertised pcie link width */
225 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
226 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
227 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
228 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
229 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
230 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
231 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
233 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
234 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
235 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
236 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
237 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
238 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
239 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
240 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
241 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
242 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
243 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \
245 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
246 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
247 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
248 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
249 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
250 /* Set the PLDM sensor modes */
251 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
252 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
253 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
254 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
255 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
257 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000
258 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31
259 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0
260 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1
261 u32 f_lane_cfg1; /* 0x38 */
262 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
263 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
264 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
265 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
266 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
267 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
268 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
269 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
270 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
271 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
272 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
273 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
274 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
275 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
276 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
277 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
278 u32 f_lane_cfg2; /* 0x3C */
279 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
280 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
281 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
282 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
283 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
284 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
285 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
286 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
287 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
288 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
289 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
290 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
291 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
292 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
293 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
294 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
295 /* Control the period between two successive checks */
296 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \
298 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
299 /* Set shutdown temperature */
300 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \
302 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
303 /* Set max. count for over operational temperature */
304 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
305 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
306 u32 mps10_preemphasis; /* 0x40 */
307 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
308 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
309 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
310 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
311 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
312 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
313 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
314 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
315 u32 mps10_driver_current; /* 0x44 */
316 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
317 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
318 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
319 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
320 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
321 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
322 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
323 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
324 u32 mps25_preemphasis; /* 0x48 */
325 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
326 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
327 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
328 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
329 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
330 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
331 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
332 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
333 u32 mps25_driver_current; /* 0x4C */
334 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
335 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
336 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
337 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
338 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
339 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
340 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
341 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
342 u32 pci_id; /* 0x50 */
343 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
344 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
345 /* Set caution temperature */
346 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK 0x00FF0000
347 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_OFFSET 16
348 /* Set external thermal sensor I2C address */
349 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \
351 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
352 u32 pci_subsys_id; /* 0x54 */
353 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
354 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
355 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
356 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
358 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
359 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
360 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
361 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
362 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
363 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
364 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
365 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
366 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
367 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
368 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
369 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
370 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
371 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
372 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
373 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
374 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
375 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
376 /* BB VF BAR2 size */
377 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
378 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
379 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
380 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
381 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
382 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
383 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
384 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
385 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
386 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
387 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
388 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
389 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
390 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
391 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
392 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
393 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
394 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
395 /* BB BAR2 size (global) */
396 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
397 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
398 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
399 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
400 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
401 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
402 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
403 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
404 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
405 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
406 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
407 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
408 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
409 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
410 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
411 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
412 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
413 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
414 /* Set the duration, in secs, fan failure signal should be sampled */
415 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
416 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
417 /* This field defines the board total budget for bar2 when disabled
418 * the regular bar size is used.
420 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
421 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
422 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
423 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
424 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
425 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
426 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
427 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
428 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
429 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
430 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
431 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
432 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
433 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
434 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
435 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
436 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
437 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
438 /* Enable/Disable Crash dump triggers */
439 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
440 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
441 u32 mps10_txfir_main; /* 0x5C */
442 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
443 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
444 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
445 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
446 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
447 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
448 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
449 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
450 u32 mps10_txfir_post; /* 0x60 */
451 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
452 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
453 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
454 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
455 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
456 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
457 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
458 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
459 u32 mps25_txfir_main; /* 0x64 */
460 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
461 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
462 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
463 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
464 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
465 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
466 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
467 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
468 u32 mps25_txfir_post; /* 0x68 */
469 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
470 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
471 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
472 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
473 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
474 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
475 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
476 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
477 u32 manufacture_ver; /* 0x6C */
478 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
479 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
480 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
481 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
482 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
483 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
484 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
485 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
486 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
487 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
488 /* Select package id method */
489 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000
490 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30
491 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0
492 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1
493 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000
494 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31
495 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0
496 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1
497 u32 manufacture_time; /* 0x70 */
498 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
499 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
500 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
501 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
502 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
503 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
504 /* Max MSIX for Ethernet in default mode */
505 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000
506 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18
508 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000
509 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26
510 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0
511 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1
512 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000
513 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28
514 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0
515 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1
516 /* Enable/Disable PCIE Relaxed Ordering */
517 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_MASK 0x40000000
518 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_OFFSET 30
519 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_DISABLED 0x0
520 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_ENABLED 0x1
521 /* Reset the chip using iPOR to release PCIe due to short PERST
524 #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_MASK 0x80000000
525 #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_OFFSET 31
526 #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_DISABLED 0x0
527 #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_ENABLED 0x1
528 u32 led_global_settings; /* 0x74 */
529 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
530 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
531 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
532 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
533 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
534 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
535 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
536 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
537 /* Max. continues operating temperature */
538 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000
539 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16
540 /* GPIO which triggers run-time port swap according to the map
541 * specified in option 205
543 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000
544 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24
545 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0
546 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1
547 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2
548 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3
549 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4
550 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5
551 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6
552 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7
553 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8
554 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9
555 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA
556 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB
557 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC
558 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD
559 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE
560 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF
561 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10
562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11
563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12
564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13
565 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14
566 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15
567 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16
568 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17
569 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18
570 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19
571 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A
572 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B
573 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C
574 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D
575 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E
576 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F
577 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20
578 u32 generic_cont1; /* 0x78 */
579 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
580 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
581 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
582 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
583 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
584 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
585 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
586 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
587 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
588 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
589 /* Enable option 195 - Overriding the PCIe Preset value */
590 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000
591 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18
592 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0
593 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1
594 /* PCIe Preset value - applies only if option 194 is enabled */
595 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000
596 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19
597 /* Port mapping to be used when the run-time GPIO for port-swap is
600 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000
601 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23
602 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000
603 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25
604 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000
605 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27
606 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000
607 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29
608 /* Option to Disable embedded LLDP, 0 - Off, 1 - On */
609 #define NVM_CFG1_GLOB_LLDP_DISABLE_MASK 0x80000000
610 #define NVM_CFG1_GLOB_LLDP_DISABLE_OFFSET 31
611 #define NVM_CFG1_GLOB_LLDP_DISABLE_OFF 0x0
612 #define NVM_CFG1_GLOB_LLDP_DISABLE_ON 0x1
613 u32 mbi_version; /* 0x7C */
614 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
615 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
616 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
617 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
618 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
619 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
620 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event
623 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000
624 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24
625 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0
626 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1
627 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2
628 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3
629 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4
630 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5
631 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6
632 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7
633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8
634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9
635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA
636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB
637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC
638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD
639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE
640 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF
641 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10
642 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11
643 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12
644 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13
645 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14
646 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15
647 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16
648 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17
649 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18
650 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19
651 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A
652 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B
653 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C
654 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D
655 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E
656 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F
657 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20
658 u32 mbi_date; /* 0x80 */
659 u32 misc_sig; /* 0x84 */
660 /* Define the GPIO mapping to switch i2c mux */
661 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
662 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
663 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
664 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
665 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
666 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
667 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
668 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
669 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
670 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
680 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
681 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
682 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
683 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
684 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
685 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
686 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
687 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
688 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
689 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
690 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
691 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
692 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
693 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
694 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
695 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
696 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
697 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
698 /* Interrupt signal used for SMBus/I2C management interface
699 * 0 = Interrupt event occurred
702 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000
703 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16
704 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0
705 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1
706 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2
707 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3
708 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4
709 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5
710 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6
711 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7
712 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8
713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9
714 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA
715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB
716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC
717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD
718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE
719 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF
720 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10
721 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11
722 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12
723 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13
724 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14
725 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15
726 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16
727 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17
728 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18
729 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19
730 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A
731 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B
732 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C
733 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D
734 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E
735 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F
736 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20
737 /* Set aLOM FAN on GPIO */
738 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000
739 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24
740 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0
741 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1
742 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2
743 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3
744 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4
745 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5
746 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6
747 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7
748 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8
749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9
750 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA
751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB
752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC
753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD
754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE
755 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF
756 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10
757 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11
758 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12
759 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13
760 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14
761 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15
762 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16
763 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17
764 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18
765 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19
766 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A
767 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B
768 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C
769 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D
770 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E
771 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F
772 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20
773 u32 device_capabilities; /* 0x88 */
774 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
775 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
776 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
777 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
778 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
779 u32 power_dissipated; /* 0x8C */
780 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
781 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
782 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
783 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
784 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
785 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
786 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
787 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
788 u32 power_consumed; /* 0x90 */
789 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
790 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
791 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
792 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
793 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
794 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
795 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
796 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
797 u32 efi_version; /* 0x94 */
798 u32 multi_network_modes_capability; /* 0x98 */
799 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
800 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
801 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
802 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
803 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
804 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
805 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
806 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
808 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100
810 u32 reserved1[12]; /* 0x9C */
811 u32 oem1_number[8]; /* 0xCC */
812 u32 oem2_number[8]; /* 0xEC */
813 u32 mps25_active_txfir_pre; /* 0x10C */
814 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF
815 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0
816 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00
817 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8
818 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000
819 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16
820 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000
821 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24
822 u32 mps25_active_txfir_main; /* 0x110 */
823 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF
824 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0
825 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00
826 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8
827 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000
828 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16
829 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000
830 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24
831 u32 mps25_active_txfir_post; /* 0x114 */
832 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF
833 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0
834 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00
835 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8
836 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000
837 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16
838 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000
839 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24
840 u32 features; /* 0x118 */
841 /* Set the Aux Fan on temperature */
842 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF
843 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0
844 /* Set NC-SI package ID */
845 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00
846 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8
847 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0
848 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1
849 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2
850 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3
851 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4
852 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5
853 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6
854 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7
855 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8
856 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9
857 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA
858 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB
859 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC
860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD
861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE
862 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF
863 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10
864 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11
865 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12
866 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13
867 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14
868 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15
869 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16
870 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17
871 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18
872 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19
873 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A
874 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B
875 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C
876 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D
877 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E
878 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F
879 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20
880 /* PMBUS Clock GPIO */
881 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000
882 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16
883 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0
884 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1
885 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2
886 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3
887 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4
888 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5
889 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6
890 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7
891 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8
892 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9
893 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA
894 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB
895 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC
896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD
897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE
898 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF
899 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10
900 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11
901 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12
902 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13
903 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14
904 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15
905 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16
906 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17
907 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18
908 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19
909 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A
910 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B
911 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C
912 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D
913 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E
914 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F
915 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20
916 /* PMBUS Data GPIO */
917 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000
918 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24
919 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0
920 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1
921 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2
922 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3
923 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4
924 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5
925 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6
926 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7
927 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8
928 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9
929 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA
930 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB
931 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC
932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD
933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE
934 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF
935 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10
936 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11
937 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12
938 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13
939 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14
940 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15
941 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16
942 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17
943 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18
944 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19
945 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A
946 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B
947 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C
948 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D
949 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E
950 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F
951 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20
952 u32 tx_rx_eq_25g_hlpc; /* 0x11C */
953 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF
954 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0
955 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00
956 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8
957 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000
958 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16
959 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000
960 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24
961 u32 tx_rx_eq_25g_llpc; /* 0x120 */
962 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF
963 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0
964 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00
965 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8
966 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000
967 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16
968 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000
969 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24
970 u32 tx_rx_eq_25g_ac; /* 0x124 */
971 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF
972 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0
973 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00
974 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8
975 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000
976 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16
977 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000
978 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24
979 u32 tx_rx_eq_10g_pc; /* 0x128 */
980 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF
981 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0
982 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00
983 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8
984 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000
985 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16
986 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000
987 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24
988 u32 tx_rx_eq_10g_ac; /* 0x12C */
989 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF
990 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0
991 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00
992 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8
993 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000
994 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16
995 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000
996 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24
997 u32 tx_rx_eq_1g; /* 0x130 */
998 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF
999 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0
1000 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00
1001 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8
1002 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000
1003 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16
1004 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000
1005 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24
1006 u32 tx_rx_eq_25g_bt; /* 0x134 */
1007 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF
1008 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0
1009 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00
1010 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8
1011 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000
1012 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16
1013 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000
1014 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24
1015 u32 tx_rx_eq_10g_bt; /* 0x138 */
1016 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF
1017 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0
1018 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00
1019 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8
1020 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000
1021 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16
1022 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000
1023 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24
1024 u32 generic_cont4; /* 0x13C */
1025 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF
1026 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0
1027 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0
1028 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1
1029 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2
1030 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3
1031 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4
1032 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5
1033 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6
1034 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7
1035 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8
1036 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9
1037 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA
1038 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB
1039 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC
1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD
1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE
1042 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF
1043 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10
1044 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11
1045 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12
1046 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13
1047 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14
1048 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15
1049 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16
1050 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17
1051 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18
1052 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19
1053 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A
1054 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B
1055 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C
1056 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D
1057 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E
1058 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F
1059 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20
1060 /* Select the number of allowed port link in aux power */
1061 #define NVM_CFG1_GLOB_NCSI_AUX_LINK_MASK 0x00000300
1062 #define NVM_CFG1_GLOB_NCSI_AUX_LINK_OFFSET 8
1063 #define NVM_CFG1_GLOB_NCSI_AUX_LINK_DEFAULT 0x0
1064 #define NVM_CFG1_GLOB_NCSI_AUX_LINK_1_PORT 0x1
1065 #define NVM_CFG1_GLOB_NCSI_AUX_LINK_2_PORTS 0x2
1066 #define NVM_CFG1_GLOB_NCSI_AUX_LINK_3_PORTS 0x3
1067 /* Set Trace Filter Log Level */
1068 #define NVM_CFG1_GLOB_TRACE_LEVEL_MASK 0x00000C00
1069 #define NVM_CFG1_GLOB_TRACE_LEVEL_OFFSET 10
1070 #define NVM_CFG1_GLOB_TRACE_LEVEL_ALL 0x0
1071 #define NVM_CFG1_GLOB_TRACE_LEVEL_DEBUG 0x1
1072 #define NVM_CFG1_GLOB_TRACE_LEVEL_TRACE 0x2
1073 #define NVM_CFG1_GLOB_TRACE_LEVEL_ERROR 0x3
1074 /* For OCP2.0, MFW listens on SMBUS slave address 0x3e, and return
1075 * temperature reading
1077 #define NVM_CFG1_GLOB_EMULATED_TMP421_MASK 0x00001000
1078 #define NVM_CFG1_GLOB_EMULATED_TMP421_OFFSET 12
1079 #define NVM_CFG1_GLOB_EMULATED_TMP421_DISABLED 0x0
1080 #define NVM_CFG1_GLOB_EMULATED_TMP421_ENABLED 0x1
1081 /* GPIO which triggers when ASIC temperature reaches nvm option 286
1084 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_MASK 0x001FE000
1085 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_OFFSET 13
1086 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_NA 0x0
1087 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO0 0x1
1088 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO1 0x2
1089 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO2 0x3
1090 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO3 0x4
1091 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO4 0x5
1092 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO5 0x6
1093 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO6 0x7
1094 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO7 0x8
1095 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO8 0x9
1096 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO9 0xA
1097 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO10 0xB
1098 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO11 0xC
1099 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO12 0xD
1100 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO13 0xE
1101 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO14 0xF
1102 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO15 0x10
1103 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO16 0x11
1104 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO17 0x12
1105 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO18 0x13
1106 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO19 0x14
1107 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO20 0x15
1108 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO21 0x16
1109 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO22 0x17
1110 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO23 0x18
1111 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO24 0x19
1112 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO25 0x1A
1113 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO26 0x1B
1114 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO27 0x1C
1115 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO28 0x1D
1116 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO29 0x1E
1117 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO30 0x1F
1118 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO31 0x20
1119 /* Warning temperature threshold used with nvm option 286 */
1120 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_THRESHOLD_MASK 0x1FE00000
1121 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_THRESHOLD_OFFSET 21
1122 /* Disable PLDM protocol */
1123 #define NVM_CFG1_GLOB_DISABLE_PLDM_MASK 0x20000000
1124 #define NVM_CFG1_GLOB_DISABLE_PLDM_OFFSET 29
1125 #define NVM_CFG1_GLOB_DISABLE_PLDM_DISABLED 0x0
1126 #define NVM_CFG1_GLOB_DISABLE_PLDM_ENABLED 0x1
1127 /* Disable OCBB protocol */
1128 #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_MASK 0x40000000
1129 #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_OFFSET 30
1130 #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_DISABLED 0x0
1131 #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_ENABLED 0x1
1132 u32 preboot_debug_mode_std; /* 0x140 */
1133 u32 preboot_debug_mode_ext; /* 0x144 */
1134 u32 ext_phy_cfg1; /* 0x148 */
1135 /* Ext PHY MDI pair swap value */
1136 #define NVM_CFG1_GLOB_RESERVED_244_MASK 0x0000FFFF
1137 #define NVM_CFG1_GLOB_RESERVED_244_OFFSET 0
1138 /* Define for PGOOD signal Mapping for EXT PHY */
1139 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_MASK 0x00FF0000
1140 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_OFFSET 16
1141 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_NA 0x0
1142 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO0 0x1
1143 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO1 0x2
1144 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO2 0x3
1145 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO3 0x4
1146 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO4 0x5
1147 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO5 0x6
1148 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO6 0x7
1149 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO7 0x8
1150 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO8 0x9
1151 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO9 0xA
1152 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO10 0xB
1153 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO11 0xC
1154 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO12 0xD
1155 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO13 0xE
1156 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO14 0xF
1157 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO15 0x10
1158 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO16 0x11
1159 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO17 0x12
1160 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO18 0x13
1161 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO19 0x14
1162 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO20 0x15
1163 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO21 0x16
1164 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO22 0x17
1165 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO23 0x18
1166 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO24 0x19
1167 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO25 0x1A
1168 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO26 0x1B
1169 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO27 0x1C
1170 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO28 0x1D
1171 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO29 0x1E
1172 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO30 0x1F
1173 #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO31 0x20
1174 /* GPIO which trigger when PERST asserted */
1175 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_MASK 0xFF000000
1176 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_OFFSET 24
1177 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_NA 0x0
1178 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO0 0x1
1179 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO1 0x2
1180 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO2 0x3
1181 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO3 0x4
1182 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO4 0x5
1183 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO5 0x6
1184 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO6 0x7
1185 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO7 0x8
1186 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO8 0x9
1187 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO9 0xA
1188 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO10 0xB
1189 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO11 0xC
1190 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO12 0xD
1191 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO13 0xE
1192 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO14 0xF
1193 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO15 0x10
1194 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO16 0x11
1195 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO17 0x12
1196 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO18 0x13
1197 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO19 0x14
1198 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO20 0x15
1199 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO21 0x16
1200 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO22 0x17
1201 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO23 0x18
1202 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO24 0x19
1203 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO25 0x1A
1204 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO26 0x1B
1205 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO27 0x1C
1206 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO28 0x1D
1207 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO29 0x1E
1208 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO30 0x1F
1209 #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO31 0x20
1210 u32 clocks; /* 0x14C */
1211 /* Sets core clock frequency */
1212 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK 0x000000FF
1213 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET 0
1214 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT 0x0
1215 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375 0x1
1216 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350 0x2
1217 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325 0x3
1218 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300 0x4
1219 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280 0x5
1220 /* Sets MAC clock frequency */
1221 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK 0x0000FF00
1222 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_OFFSET 8
1223 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT 0x0
1224 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782 0x1
1225 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516 0x2
1226 /* Sets storm clock frequency */
1227 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK 0x00FF0000
1228 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_OFFSET 16
1229 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT 0x0
1230 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200 0x1
1231 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000 0x2
1232 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900 0x3
1233 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100 0x4
1234 /* Non zero value will override PCIe AGC threshold to improve
1237 #define NVM_CFG1_GLOB_OVERRIDE_AGC_THRESHOLD_MASK 0xFF000000
1238 #define NVM_CFG1_GLOB_OVERRIDE_AGC_THRESHOLD_OFFSET 24
1239 u32 pre2_generic_cont_1; /* 0x150 */
1240 #define NVM_CFG1_GLOB_50G_HLPC_PRE2_MASK 0x000000FF
1241 #define NVM_CFG1_GLOB_50G_HLPC_PRE2_OFFSET 0
1242 #define NVM_CFG1_GLOB_50G_MLPC_PRE2_MASK 0x0000FF00
1243 #define NVM_CFG1_GLOB_50G_MLPC_PRE2_OFFSET 8
1244 #define NVM_CFG1_GLOB_50G_LLPC_PRE2_MASK 0x00FF0000
1245 #define NVM_CFG1_GLOB_50G_LLPC_PRE2_OFFSET 16
1246 #define NVM_CFG1_GLOB_25G_HLPC_PRE2_MASK 0xFF000000
1247 #define NVM_CFG1_GLOB_25G_HLPC_PRE2_OFFSET 24
1248 u32 pre2_generic_cont_2; /* 0x154 */
1249 #define NVM_CFG1_GLOB_25G_LLPC_PRE2_MASK 0x000000FF
1250 #define NVM_CFG1_GLOB_25G_LLPC_PRE2_OFFSET 0
1251 #define NVM_CFG1_GLOB_25G_AC_PRE2_MASK 0x0000FF00
1252 #define NVM_CFG1_GLOB_25G_AC_PRE2_OFFSET 8
1253 #define NVM_CFG1_GLOB_10G_PC_PRE2_MASK 0x00FF0000
1254 #define NVM_CFG1_GLOB_10G_PC_PRE2_OFFSET 16
1255 #define NVM_CFG1_GLOB_PRE2_10G_AC_MASK 0xFF000000
1256 #define NVM_CFG1_GLOB_PRE2_10G_AC_OFFSET 24
1257 u32 pre2_generic_cont_3; /* 0x158 */
1258 #define NVM_CFG1_GLOB_1G_PRE2_MASK 0x000000FF
1259 #define NVM_CFG1_GLOB_1G_PRE2_OFFSET 0
1260 #define NVM_CFG1_GLOB_5G_BT_PRE2_MASK 0x0000FF00
1261 #define NVM_CFG1_GLOB_5G_BT_PRE2_OFFSET 8
1262 #define NVM_CFG1_GLOB_10G_BT_PRE2_MASK 0x00FF0000
1263 #define NVM_CFG1_GLOB_10G_BT_PRE2_OFFSET 16
1264 /* When temperature goes below (warning temperature - delta) warning
1267 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_DELTA_MASK 0xFF000000
1268 #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_DELTA_OFFSET 24
1269 u32 tx_rx_eq_50g_hlpc; /* 0x15C */
1270 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_HLPC_MASK 0x000000FF
1271 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_HLPC_OFFSET 0
1272 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_HLPC_MASK 0x0000FF00
1273 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_HLPC_OFFSET 8
1274 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_HLPC_MASK 0x00FF0000
1275 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_HLPC_OFFSET 16
1276 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_HLPC_MASK 0xFF000000
1277 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_HLPC_OFFSET 24
1278 u32 tx_rx_eq_50g_mlpc; /* 0x160 */
1279 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_MLPC_MASK 0x000000FF
1280 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_MLPC_OFFSET 0
1281 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_MLPC_MASK 0x0000FF00
1282 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_MLPC_OFFSET 8
1283 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_MLPC_MASK 0x00FF0000
1284 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_MLPC_OFFSET 16
1285 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_MLPC_MASK 0xFF000000
1286 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_MLPC_OFFSET 24
1287 u32 tx_rx_eq_50g_llpc; /* 0x164 */
1288 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_LLPC_MASK 0x000000FF
1289 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_LLPC_OFFSET 0
1290 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_LLPC_MASK 0x0000FF00
1291 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_LLPC_OFFSET 8
1292 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_LLPC_MASK 0x00FF0000
1293 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_LLPC_OFFSET 16
1294 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_LLPC_MASK 0xFF000000
1295 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_LLPC_OFFSET 24
1296 u32 tx_rx_eq_50g_ac; /* 0x168 */
1297 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_AC_MASK 0x000000FF
1298 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_AC_OFFSET 0
1299 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_AC_MASK 0x0000FF00
1300 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_AC_OFFSET 8
1301 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_AC_MASK 0x00FF0000
1302 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_AC_OFFSET 16
1303 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_AC_MASK 0xFF000000
1304 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_AC_OFFSET 24
1305 /* Set Trace Filter Modules Log Bit Mask */
1306 u32 trace_modules; /* 0x16C */
1307 #define NVM_CFG1_GLOB_TRACE_MODULES_ERROR 0x1
1308 #define NVM_CFG1_GLOB_TRACE_MODULES_DBG 0x2
1309 #define NVM_CFG1_GLOB_TRACE_MODULES_DRV_HSI 0x4
1310 #define NVM_CFG1_GLOB_TRACE_MODULES_INTERRUPT 0x8
1311 #define NVM_CFG1_GLOB_TRACE_MODULES_VPD 0x10
1312 #define NVM_CFG1_GLOB_TRACE_MODULES_FLR 0x20
1313 #define NVM_CFG1_GLOB_TRACE_MODULES_INIT 0x40
1314 #define NVM_CFG1_GLOB_TRACE_MODULES_NVM 0x80
1315 #define NVM_CFG1_GLOB_TRACE_MODULES_PIM 0x100
1316 #define NVM_CFG1_GLOB_TRACE_MODULES_NET 0x200
1317 #define NVM_CFG1_GLOB_TRACE_MODULES_POWER 0x400
1318 #define NVM_CFG1_GLOB_TRACE_MODULES_UTILS 0x800
1319 #define NVM_CFG1_GLOB_TRACE_MODULES_RESOURCES 0x1000
1320 #define NVM_CFG1_GLOB_TRACE_MODULES_SCHEDULER 0x2000
1321 #define NVM_CFG1_GLOB_TRACE_MODULES_PHYMOD 0x4000
1322 #define NVM_CFG1_GLOB_TRACE_MODULES_EVENTS 0x8000
1323 #define NVM_CFG1_GLOB_TRACE_MODULES_PMM 0x10000
1324 #define NVM_CFG1_GLOB_TRACE_MODULES_DBG_DRV 0x20000
1325 #define NVM_CFG1_GLOB_TRACE_MODULES_ETH 0x40000
1326 #define NVM_CFG1_GLOB_TRACE_MODULES_SECURITY 0x80000
1327 #define NVM_CFG1_GLOB_TRACE_MODULES_PCIE 0x100000
1328 #define NVM_CFG1_GLOB_TRACE_MODULES_TRACE 0x200000
1329 #define NVM_CFG1_GLOB_TRACE_MODULES_MANAGEMENT 0x400000
1330 #define NVM_CFG1_GLOB_TRACE_MODULES_SIM 0x800000
1331 u32 pcie_class_code_fcoe; /* 0x170 */
1332 /* Set PCIe FCoE Class Code */
1333 #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_FCOE_MASK 0x00FFFFFF
1334 #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_FCOE_OFFSET 0
1335 /* When temperature goes below (ALOM FAN ON AUX value - delta) ALOM
1336 * FAN ON AUX gpio is unset
1338 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_DELTA_MASK 0xFF000000
1339 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_DELTA_OFFSET 24
1340 u32 pcie_class_code_iscsi; /* 0x174 */
1341 /* Set PCIe iSCSI Class Code */
1342 #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_ISCSI_MASK 0x00FFFFFF
1343 #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_ISCSI_OFFSET 0
1344 /* When temperature goes below (Dead Temp TH - delta)Thermal Event
1347 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_DELTA_MASK 0xFF000000
1348 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_DELTA_OFFSET 24
1349 u32 no_provisioned_mac; /* 0x178 */
1350 /* Set number of provisioned MAC addresses */
1351 #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_MAC_MASK 0x0000FFFF
1352 #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_MAC_OFFSET 0
1353 /* Set number of provisioned VF MAC addresses */
1354 #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_VF_MAC_MASK 0x00FF0000
1355 #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_VF_MAC_OFFSET 16
1356 /* Enable/Disable BMC MAC */
1357 #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_MASK 0x01000000
1358 #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_OFFSET 24
1359 #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_DISABLED 0x0
1360 #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_ENABLED 0x1
1361 u32 reserved[43]; /* 0x17C */
1364 struct nvm_cfg1_path {
1365 u32 reserved[1]; /* 0x0 */
1368 struct nvm_cfg1_port {
1369 u32 reserved__m_relocated_to_option_123; /* 0x0 */
1370 u32 reserved__m_relocated_to_option_124; /* 0x4 */
1371 u32 generic_cont0; /* 0x8 */
1372 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
1373 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
1374 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
1375 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
1376 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
1377 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
1378 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
1379 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
1380 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
1381 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
1382 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
1383 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
1384 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
1385 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
1386 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
1387 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
1388 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
1389 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
1390 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
1391 #define NVM_CFG1_PORT_LED_MODE_OCP_3_0 0x11
1392 #define NVM_CFG1_PORT_LED_MODE_OCP_3_0_MAC2 0x12
1393 #define NVM_CFG1_PORT_LED_MODE_SW_DEF1 0x13
1394 #define NVM_CFG1_PORT_LED_MODE_SW_DEF1_MAC2 0x14
1395 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
1396 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
1397 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
1398 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
1399 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
1400 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
1401 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
1402 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
1403 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
1404 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
1405 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
1406 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
1407 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
1408 /* GPIO for HW reset the PHY. In case it is the same for all ports,
1409 * need to set same value for all ports
1411 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000
1412 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24
1413 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0
1414 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1
1415 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2
1416 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3
1417 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4
1418 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5
1419 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6
1420 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7
1421 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8
1422 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9
1423 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA
1424 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB
1425 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC
1426 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD
1427 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE
1428 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF
1429 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10
1430 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11
1431 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12
1432 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13
1433 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14
1434 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15
1435 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16
1436 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17
1437 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18
1438 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19
1439 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A
1440 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B
1441 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C
1442 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D
1443 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E
1444 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F
1445 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20
1446 u32 pcie_cfg; /* 0xC */
1447 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
1448 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
1449 u32 features; /* 0x10 */
1450 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
1451 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
1452 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
1453 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
1454 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
1455 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
1456 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
1457 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
1458 u32 speed_cap_mask; /* 0x14 */
1459 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1460 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1461 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1462 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1463 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1464 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1465 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1466 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1467 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1468 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1469 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1470 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1471 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1472 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1473 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1474 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1475 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1476 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1477 u32 link_settings; /* 0x18 */
1478 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
1479 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
1480 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
1481 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
1482 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
1483 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
1484 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
1485 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
1486 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
1487 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
1488 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
1489 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
1490 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
1491 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
1492 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
1493 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
1494 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
1495 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
1496 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
1497 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
1498 #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3
1499 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
1500 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
1501 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
1502 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
1503 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
1504 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
1505 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
1506 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
1507 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
1508 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \
1510 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
1511 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \
1513 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \
1515 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
1516 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
1517 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
1518 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
1519 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
1520 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
1521 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
1522 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
1523 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
1524 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
1525 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000
1526 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20
1527 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0
1528 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1
1529 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2
1530 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3
1531 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4
1532 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5
1533 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6
1534 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000
1535 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23
1536 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0
1537 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1
1538 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000
1539 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24
1540 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0
1541 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1
1542 /* Enable/Disable RX PAM-4 precoding */
1543 #define NVM_CFG1_PORT_RX_PRECODE_MASK 0x02000000
1544 #define NVM_CFG1_PORT_RX_PRECODE_OFFSET 25
1545 #define NVM_CFG1_PORT_RX_PRECODE_DISABLED 0x0
1546 #define NVM_CFG1_PORT_RX_PRECODE_ENABLED 0x1
1547 /* Enable/Disable TX PAM-4 precoding */
1548 #define NVM_CFG1_PORT_TX_PRECODE_MASK 0x04000000
1549 #define NVM_CFG1_PORT_TX_PRECODE_OFFSET 26
1550 #define NVM_CFG1_PORT_TX_PRECODE_DISABLED 0x0
1551 #define NVM_CFG1_PORT_TX_PRECODE_ENABLED 0x1
1552 u32 phy_cfg; /* 0x1C */
1553 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
1554 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
1555 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
1556 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
1557 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
1558 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
1559 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
1560 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
1561 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
1562 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
1563 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
1564 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
1565 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
1566 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
1567 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
1568 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
1569 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
1570 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
1571 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
1572 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
1573 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
1574 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
1575 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
1576 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
1577 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
1578 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
1579 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
1580 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
1581 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
1582 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
1583 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
1584 u32 mgmt_traffic; /* 0x20 */
1585 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
1586 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
1587 u32 ext_phy; /* 0x24 */
1588 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
1589 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
1590 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
1591 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1
1592 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2
1593 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_88X33X0 0x3
1594 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
1595 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
1596 /* EEE power saving mode */
1597 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
1598 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
1599 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
1600 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
1601 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
1602 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
1603 u32 mba_cfg1; /* 0x28 */
1604 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
1605 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
1606 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
1607 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
1608 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
1609 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
1610 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
1611 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
1612 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
1613 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
1614 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
1615 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
1616 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
1617 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
1618 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
1619 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
1620 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
1621 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
1622 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
1623 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
1624 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
1625 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
1626 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
1627 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3
1628 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
1629 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
1630 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
1631 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
1632 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
1634 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
1635 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK \
1637 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24
1638 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED \
1640 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1
1641 u32 mba_cfg2; /* 0x2C */
1642 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
1643 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
1644 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
1645 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
1646 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000
1647 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17
1648 u32 vf_cfg; /* 0x30 */
1649 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
1650 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
1651 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
1652 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
1653 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
1654 u32 led_port_settings; /* 0x3C */
1655 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
1656 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
1657 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
1658 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
1659 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
1660 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
1661 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
1662 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
1663 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4
1664 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8
1665 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8
1666 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10
1667 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10
1668 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20
1669 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
1670 /* UID LED Blink Mode Settings */
1671 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_MASK 0x0F000000
1672 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_OFFSET 24
1673 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_ACTIVITY_LED 0x1
1674 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED0 0x2
1675 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED1 0x4
1676 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED2 0x8
1677 u32 transceiver_00; /* 0x40 */
1678 /* Define for mapping of transceiver signal module absent */
1679 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
1680 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
1681 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
1682 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
1683 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
1684 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
1685 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
1686 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
1687 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
1688 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
1689 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
1690 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
1691 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
1692 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
1693 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
1694 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
1695 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
1696 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
1697 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
1698 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
1699 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
1700 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
1701 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
1702 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
1703 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
1704 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
1705 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
1706 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
1707 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
1708 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
1709 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
1710 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
1711 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
1712 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
1713 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
1714 /* Define the GPIO mux settings to switch i2c mux to this port */
1715 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
1716 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
1717 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
1718 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
1719 /* Option to override SmartAN FEC requirements */
1720 #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_MASK 0x00010000
1721 #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_OFFSET 16
1722 #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_DISABLED 0x0
1723 #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_ENABLED 0x1
1724 u32 device_ids; /* 0x44 */
1725 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
1726 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
1727 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
1728 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
1729 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
1730 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
1731 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
1732 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
1733 u32 board_cfg; /* 0x48 */
1734 /* This field defines the board technology
1735 * (backpane,transceiver,external PHY)
1737 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
1738 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
1739 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
1740 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
1741 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
1742 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
1743 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
1744 /* This field defines the GPIO mapped to tx_disable signal in SFP */
1745 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
1746 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
1747 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
1748 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
1749 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
1750 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
1751 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
1752 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
1753 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
1754 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
1755 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
1756 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
1757 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
1758 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
1759 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
1760 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
1761 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
1762 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
1763 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
1764 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
1765 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
1766 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
1767 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
1768 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
1769 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
1770 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
1771 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
1772 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
1773 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
1774 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
1775 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
1776 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
1777 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
1778 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
1779 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
1780 u32 mnm_10g_cap; /* 0x4C */
1781 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
1783 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1784 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1785 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1786 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1787 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1788 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1789 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1791 NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1792 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
1794 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1796 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1797 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1798 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1799 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1800 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1801 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1803 NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1804 u32 mnm_10g_ctrl; /* 0x50 */
1805 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
1806 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
1807 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
1808 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
1809 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
1810 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3
1811 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
1812 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
1813 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
1814 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
1815 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
1816 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
1817 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
1818 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
1819 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
1820 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3
1821 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
1822 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
1823 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
1824 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
1825 /* This field defines the board technology
1826 * (backpane,transceiver,external PHY)
1828 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
1829 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
1830 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
1831 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
1832 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
1833 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
1834 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
1835 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
1837 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
1838 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
1839 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
1840 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
1841 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
1842 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
1843 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
1844 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
1845 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
1846 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
1847 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
1848 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
1849 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
1850 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
1851 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
1852 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
1853 u32 mnm_10g_misc; /* 0x54 */
1854 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
1855 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
1856 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
1857 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
1858 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
1859 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7
1860 u32 mnm_25g_cap; /* 0x58 */
1861 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
1863 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1864 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1865 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1866 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1867 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1868 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1869 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1871 NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1872 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
1874 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1876 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1877 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1878 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1879 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1880 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1881 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1883 NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1884 u32 mnm_25g_ctrl; /* 0x5C */
1885 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
1886 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
1887 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
1888 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
1889 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
1890 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3
1891 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
1892 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
1893 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
1894 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
1895 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
1896 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
1897 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
1898 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
1899 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
1900 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3
1901 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
1902 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
1903 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
1904 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
1905 /* This field defines the board technology
1906 * (backpane,transceiver,external PHY)
1908 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
1909 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
1910 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
1911 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
1912 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
1913 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
1914 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
1915 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
1917 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
1918 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
1919 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
1920 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
1921 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
1922 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
1923 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
1924 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
1925 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
1926 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
1927 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
1928 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
1929 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
1930 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
1931 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
1932 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
1933 u32 mnm_25g_misc; /* 0x60 */
1934 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
1935 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
1936 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
1937 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
1938 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
1939 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7
1940 u32 mnm_40g_cap; /* 0x64 */
1941 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
1943 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1944 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1945 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1946 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1947 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1948 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1949 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1951 NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1952 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
1954 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
1956 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1957 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1958 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1959 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1960 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1961 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1963 NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1964 u32 mnm_40g_ctrl; /* 0x68 */
1965 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
1966 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
1967 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
1968 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
1969 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
1970 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3
1971 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
1972 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
1973 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
1974 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
1975 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
1976 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
1977 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
1978 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
1979 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
1980 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3
1981 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
1982 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
1983 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
1984 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
1985 /* This field defines the board technology
1986 * (backpane,transceiver,external PHY)
1988 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
1989 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
1990 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
1991 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
1992 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
1993 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
1994 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
1995 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
1997 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
1998 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
1999 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
2000 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
2001 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
2002 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
2003 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
2004 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
2005 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
2006 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
2007 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
2008 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
2009 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
2010 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
2011 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
2012 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
2013 u32 mnm_40g_misc; /* 0x6C */
2014 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
2015 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
2016 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
2017 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
2018 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
2019 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7
2020 u32 mnm_50g_cap; /* 0x70 */
2021 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
2023 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
2024 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
2025 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
2026 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
2027 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
2028 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
2029 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
2031 NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
2033 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
2035 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
2037 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
2038 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
2039 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
2040 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
2041 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
2042 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
2044 NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
2046 u32 mnm_50g_ctrl; /* 0x74 */
2047 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
2048 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
2049 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
2050 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
2051 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
2052 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3
2053 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
2054 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
2055 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
2056 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
2057 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
2058 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
2059 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
2060 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
2061 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
2062 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3
2063 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
2064 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
2065 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
2066 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
2067 /* This field defines the board technology
2068 * (backpane,transceiver,external PHY)
2070 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
2071 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
2072 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
2073 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
2074 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
2075 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
2076 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
2077 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
2079 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
2080 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
2081 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
2082 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
2083 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
2084 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
2085 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
2086 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
2087 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
2088 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
2089 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
2090 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
2091 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
2092 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
2093 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
2094 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
2095 u32 mnm_50g_misc; /* 0x78 */
2096 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
2097 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
2098 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
2099 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
2100 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
2101 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7
2102 u32 mnm_100g_cap; /* 0x7C */
2103 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
2105 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
2106 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
2107 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
2108 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4
2109 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
2110 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
2111 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
2112 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
2113 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
2115 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
2116 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
2117 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
2118 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4
2119 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
2120 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
2121 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
2122 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
2123 u32 mnm_100g_ctrl; /* 0x80 */
2124 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
2125 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
2126 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
2127 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
2128 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
2129 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3
2130 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
2131 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
2132 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
2133 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
2134 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
2135 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
2136 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
2137 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
2138 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
2139 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3
2140 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
2141 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
2142 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
2143 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
2144 /* This field defines the board technology
2145 * (backpane,transceiver,external PHY)
2147 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
2148 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
2149 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
2150 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
2151 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
2152 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
2153 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
2154 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
2156 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
2157 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
2158 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
2159 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
2160 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
2161 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
2162 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
2163 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
2164 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
2165 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
2166 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
2167 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
2168 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
2169 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
2170 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
2171 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
2172 u32 mnm_100g_misc; /* 0x84 */
2173 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
2174 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
2175 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
2176 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
2177 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
2178 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7
2179 u32 temperature; /* 0x88 */
2180 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF
2181 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0
2182 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK \
2184 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8
2185 /* Warning temperature threshold used with nvm option 235 */
2186 #define NVM_CFG1_PORT_PHY_MODULE_WARNING_TEMP_TH_MASK 0x00FF0000
2187 #define NVM_CFG1_PORT_PHY_MODULE_WARNING_TEMP_TH_OFFSET 16
2188 u32 ext_phy_cfg1; /* 0x8C */
2189 /* Ext PHY MDI pair swap value */
2190 #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF
2191 #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0
2192 u32 extended_speed; /* 0x90 */
2193 /* Sets speed in conjunction with legacy speed field */
2194 #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000FFFF
2195 #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
2196 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_NONE 0x1
2197 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
2198 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
2199 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x8
2200 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x10
2201 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x20
2202 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x40
2203 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x80
2204 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x100
2205 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x200
2206 /* Sets speed capabilities in conjunction with legacy capabilities
2209 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xFFFF0000
2210 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16
2211 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_NONE 0x1
2212 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
2213 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
2214 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x8
2215 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x10
2216 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x20
2217 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x40
2218 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x80
2219 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x100
2220 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x200
2221 /* Set speed specific FEC setting in conjunction with legacy FEC
2224 u32 extended_fec_mode; /* 0x94 */
2225 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_NONE 0x1
2226 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_10G_NONE 0x2
2227 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_10G_BASE_R 0x4
2228 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_NONE 0x8
2229 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_BASE_R 0x10
2230 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_RS528 0x20
2231 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_40G_NONE 0x40
2232 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_40G_BASE_R 0x80
2233 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_NONE 0x100
2234 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_BASE_R 0x200
2235 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_RS528 0x400
2236 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_RS544 0x800
2237 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_NONE 0x1000
2238 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_BASE_R 0x2000
2239 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_RS528 0x4000
2240 #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_RS544 0x8000
2241 u32 port_generic_cont_01; /* 0x98 */
2242 /* Define for GPIO mapping of SFP Rate Select 0 */
2243 #define NVM_CFG1_PORT_MODULE_RS0_MASK 0x000000FF
2244 #define NVM_CFG1_PORT_MODULE_RS0_OFFSET 0
2245 #define NVM_CFG1_PORT_MODULE_RS0_NA 0x0
2246 #define NVM_CFG1_PORT_MODULE_RS0_GPIO0 0x1
2247 #define NVM_CFG1_PORT_MODULE_RS0_GPIO1 0x2
2248 #define NVM_CFG1_PORT_MODULE_RS0_GPIO2 0x3
2249 #define NVM_CFG1_PORT_MODULE_RS0_GPIO3 0x4
2250 #define NVM_CFG1_PORT_MODULE_RS0_GPIO4 0x5
2251 #define NVM_CFG1_PORT_MODULE_RS0_GPIO5 0x6
2252 #define NVM_CFG1_PORT_MODULE_RS0_GPIO6 0x7
2253 #define NVM_CFG1_PORT_MODULE_RS0_GPIO7 0x8
2254 #define NVM_CFG1_PORT_MODULE_RS0_GPIO8 0x9
2255 #define NVM_CFG1_PORT_MODULE_RS0_GPIO9 0xA
2256 #define NVM_CFG1_PORT_MODULE_RS0_GPIO10 0xB
2257 #define NVM_CFG1_PORT_MODULE_RS0_GPIO11 0xC
2258 #define NVM_CFG1_PORT_MODULE_RS0_GPIO12 0xD
2259 #define NVM_CFG1_PORT_MODULE_RS0_GPIO13 0xE
2260 #define NVM_CFG1_PORT_MODULE_RS0_GPIO14 0xF
2261 #define NVM_CFG1_PORT_MODULE_RS0_GPIO15 0x10
2262 #define NVM_CFG1_PORT_MODULE_RS0_GPIO16 0x11
2263 #define NVM_CFG1_PORT_MODULE_RS0_GPIO17 0x12
2264 #define NVM_CFG1_PORT_MODULE_RS0_GPIO18 0x13
2265 #define NVM_CFG1_PORT_MODULE_RS0_GPIO19 0x14
2266 #define NVM_CFG1_PORT_MODULE_RS0_GPIO20 0x15
2267 #define NVM_CFG1_PORT_MODULE_RS0_GPIO21 0x16
2268 #define NVM_CFG1_PORT_MODULE_RS0_GPIO22 0x17
2269 #define NVM_CFG1_PORT_MODULE_RS0_GPIO23 0x18
2270 #define NVM_CFG1_PORT_MODULE_RS0_GPIO24 0x19
2271 #define NVM_CFG1_PORT_MODULE_RS0_GPIO25 0x1A
2272 #define NVM_CFG1_PORT_MODULE_RS0_GPIO26 0x1B
2273 #define NVM_CFG1_PORT_MODULE_RS0_GPIO27 0x1C
2274 #define NVM_CFG1_PORT_MODULE_RS0_GPIO28 0x1D
2275 #define NVM_CFG1_PORT_MODULE_RS0_GPIO29 0x1E
2276 #define NVM_CFG1_PORT_MODULE_RS0_GPIO30 0x1F
2277 #define NVM_CFG1_PORT_MODULE_RS0_GPIO31 0x20
2278 /* Define for GPIO mapping of SFP Rate Select 1 */
2279 #define NVM_CFG1_PORT_MODULE_RS1_MASK 0x0000FF00
2280 #define NVM_CFG1_PORT_MODULE_RS1_OFFSET 8
2281 #define NVM_CFG1_PORT_MODULE_RS1_NA 0x0
2282 #define NVM_CFG1_PORT_MODULE_RS1_GPIO0 0x1
2283 #define NVM_CFG1_PORT_MODULE_RS1_GPIO1 0x2
2284 #define NVM_CFG1_PORT_MODULE_RS1_GPIO2 0x3
2285 #define NVM_CFG1_PORT_MODULE_RS1_GPIO3 0x4
2286 #define NVM_CFG1_PORT_MODULE_RS1_GPIO4 0x5
2287 #define NVM_CFG1_PORT_MODULE_RS1_GPIO5 0x6
2288 #define NVM_CFG1_PORT_MODULE_RS1_GPIO6 0x7
2289 #define NVM_CFG1_PORT_MODULE_RS1_GPIO7 0x8
2290 #define NVM_CFG1_PORT_MODULE_RS1_GPIO8 0x9
2291 #define NVM_CFG1_PORT_MODULE_RS1_GPIO9 0xA
2292 #define NVM_CFG1_PORT_MODULE_RS1_GPIO10 0xB
2293 #define NVM_CFG1_PORT_MODULE_RS1_GPIO11 0xC
2294 #define NVM_CFG1_PORT_MODULE_RS1_GPIO12 0xD
2295 #define NVM_CFG1_PORT_MODULE_RS1_GPIO13 0xE
2296 #define NVM_CFG1_PORT_MODULE_RS1_GPIO14 0xF
2297 #define NVM_CFG1_PORT_MODULE_RS1_GPIO15 0x10
2298 #define NVM_CFG1_PORT_MODULE_RS1_GPIO16 0x11
2299 #define NVM_CFG1_PORT_MODULE_RS1_GPIO17 0x12
2300 #define NVM_CFG1_PORT_MODULE_RS1_GPIO18 0x13
2301 #define NVM_CFG1_PORT_MODULE_RS1_GPIO19 0x14
2302 #define NVM_CFG1_PORT_MODULE_RS1_GPIO20 0x15
2303 #define NVM_CFG1_PORT_MODULE_RS1_GPIO21 0x16
2304 #define NVM_CFG1_PORT_MODULE_RS1_GPIO22 0x17
2305 #define NVM_CFG1_PORT_MODULE_RS1_GPIO23 0x18
2306 #define NVM_CFG1_PORT_MODULE_RS1_GPIO24 0x19
2307 #define NVM_CFG1_PORT_MODULE_RS1_GPIO25 0x1A
2308 #define NVM_CFG1_PORT_MODULE_RS1_GPIO26 0x1B
2309 #define NVM_CFG1_PORT_MODULE_RS1_GPIO27 0x1C
2310 #define NVM_CFG1_PORT_MODULE_RS1_GPIO28 0x1D
2311 #define NVM_CFG1_PORT_MODULE_RS1_GPIO29 0x1E
2312 #define NVM_CFG1_PORT_MODULE_RS1_GPIO30 0x1F
2313 #define NVM_CFG1_PORT_MODULE_RS1_GPIO31 0x20
2314 /* Define for GPIO mapping of SFP Module TX Fault */
2315 #define NVM_CFG1_PORT_MODULE_TX_FAULT_MASK 0x00FF0000
2316 #define NVM_CFG1_PORT_MODULE_TX_FAULT_OFFSET 16
2317 #define NVM_CFG1_PORT_MODULE_TX_FAULT_NA 0x0
2318 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO0 0x1
2319 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO1 0x2
2320 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO2 0x3
2321 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO3 0x4
2322 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO4 0x5
2323 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO5 0x6
2324 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO6 0x7
2325 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO7 0x8
2326 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO8 0x9
2327 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO9 0xA
2328 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO10 0xB
2329 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO11 0xC
2330 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO12 0xD
2331 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO13 0xE
2332 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO14 0xF
2333 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO15 0x10
2334 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO16 0x11
2335 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO17 0x12
2336 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO18 0x13
2337 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO19 0x14
2338 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO20 0x15
2339 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO21 0x16
2340 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO22 0x17
2341 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO23 0x18
2342 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO24 0x19
2343 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO25 0x1A
2344 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO26 0x1B
2345 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO27 0x1C
2346 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO28 0x1D
2347 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO29 0x1E
2348 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO30 0x1F
2349 #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO31 0x20
2350 /* Define for GPIO mapping of QSFP Reset signal */
2351 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_MASK 0xFF000000
2352 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_OFFSET 24
2353 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_NA 0x0
2354 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO0 0x1
2355 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO1 0x2
2356 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO2 0x3
2357 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO3 0x4
2358 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO4 0x5
2359 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO5 0x6
2360 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO6 0x7
2361 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO7 0x8
2362 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO8 0x9
2363 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO9 0xA
2364 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO10 0xB
2365 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO11 0xC
2366 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO12 0xD
2367 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO13 0xE
2368 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO14 0xF
2369 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO15 0x10
2370 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO16 0x11
2371 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO17 0x12
2372 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO18 0x13
2373 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO19 0x14
2374 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO20 0x15
2375 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO21 0x16
2376 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO22 0x17
2377 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO23 0x18
2378 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO24 0x19
2379 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO25 0x1A
2380 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO26 0x1B
2381 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO27 0x1C
2382 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO28 0x1D
2383 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO29 0x1E
2384 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO30 0x1F
2385 #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO31 0x20
2386 u32 port_generic_cont_02; /* 0x9C */
2387 /* Define for GPIO mapping of QSFP Transceiver LP mode */
2388 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_MASK 0x000000FF
2389 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_OFFSET 0
2390 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_NA 0x0
2391 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO0 0x1
2392 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO1 0x2
2393 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO2 0x3
2394 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO3 0x4
2395 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO4 0x5
2396 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO5 0x6
2397 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO6 0x7
2398 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO7 0x8
2399 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO8 0x9
2400 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO9 0xA
2401 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO10 0xB
2402 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO11 0xC
2403 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO12 0xD
2404 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO13 0xE
2405 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO14 0xF
2406 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO15 0x10
2407 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO16 0x11
2408 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO17 0x12
2409 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO18 0x13
2410 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO19 0x14
2411 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO20 0x15
2412 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO21 0x16
2413 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO22 0x17
2414 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO23 0x18
2415 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO24 0x19
2416 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO25 0x1A
2417 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO26 0x1B
2418 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO27 0x1C
2419 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO28 0x1D
2420 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO29 0x1E
2421 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO30 0x1F
2422 #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO31 0x20
2423 /* Define for GPIO mapping of Transceiver Power Enable */
2424 #define NVM_CFG1_PORT_MODULE_POWER_MASK 0x0000FF00
2425 #define NVM_CFG1_PORT_MODULE_POWER_OFFSET 8
2426 #define NVM_CFG1_PORT_MODULE_POWER_NA 0x0
2427 #define NVM_CFG1_PORT_MODULE_POWER_GPIO0 0x1
2428 #define NVM_CFG1_PORT_MODULE_POWER_GPIO1 0x2
2429 #define NVM_CFG1_PORT_MODULE_POWER_GPIO2 0x3
2430 #define NVM_CFG1_PORT_MODULE_POWER_GPIO3 0x4
2431 #define NVM_CFG1_PORT_MODULE_POWER_GPIO4 0x5
2432 #define NVM_CFG1_PORT_MODULE_POWER_GPIO5 0x6
2433 #define NVM_CFG1_PORT_MODULE_POWER_GPIO6 0x7
2434 #define NVM_CFG1_PORT_MODULE_POWER_GPIO7 0x8
2435 #define NVM_CFG1_PORT_MODULE_POWER_GPIO8 0x9
2436 #define NVM_CFG1_PORT_MODULE_POWER_GPIO9 0xA
2437 #define NVM_CFG1_PORT_MODULE_POWER_GPIO10 0xB
2438 #define NVM_CFG1_PORT_MODULE_POWER_GPIO11 0xC
2439 #define NVM_CFG1_PORT_MODULE_POWER_GPIO12 0xD
2440 #define NVM_CFG1_PORT_MODULE_POWER_GPIO13 0xE
2441 #define NVM_CFG1_PORT_MODULE_POWER_GPIO14 0xF
2442 #define NVM_CFG1_PORT_MODULE_POWER_GPIO15 0x10
2443 #define NVM_CFG1_PORT_MODULE_POWER_GPIO16 0x11
2444 #define NVM_CFG1_PORT_MODULE_POWER_GPIO17 0x12
2445 #define NVM_CFG1_PORT_MODULE_POWER_GPIO18 0x13
2446 #define NVM_CFG1_PORT_MODULE_POWER_GPIO19 0x14
2447 #define NVM_CFG1_PORT_MODULE_POWER_GPIO20 0x15
2448 #define NVM_CFG1_PORT_MODULE_POWER_GPIO21 0x16
2449 #define NVM_CFG1_PORT_MODULE_POWER_GPIO22 0x17
2450 #define NVM_CFG1_PORT_MODULE_POWER_GPIO23 0x18
2451 #define NVM_CFG1_PORT_MODULE_POWER_GPIO24 0x19
2452 #define NVM_CFG1_PORT_MODULE_POWER_GPIO25 0x1A
2453 #define NVM_CFG1_PORT_MODULE_POWER_GPIO26 0x1B
2454 #define NVM_CFG1_PORT_MODULE_POWER_GPIO27 0x1C
2455 #define NVM_CFG1_PORT_MODULE_POWER_GPIO28 0x1D
2456 #define NVM_CFG1_PORT_MODULE_POWER_GPIO29 0x1E
2457 #define NVM_CFG1_PORT_MODULE_POWER_GPIO30 0x1F
2458 #define NVM_CFG1_PORT_MODULE_POWER_GPIO31 0x20
2459 /* Define for LASI Mapping of Interrupt from module or PHY */
2460 #define NVM_CFG1_PORT_LASI_INTR_IN_MASK 0x000F0000
2461 #define NVM_CFG1_PORT_LASI_INTR_IN_OFFSET 16
2462 #define NVM_CFG1_PORT_LASI_INTR_IN_NA 0x0
2463 #define NVM_CFG1_PORT_LASI_INTR_IN_LASI0 0x1
2464 #define NVM_CFG1_PORT_LASI_INTR_IN_LASI1 0x2
2465 #define NVM_CFG1_PORT_LASI_INTR_IN_LASI2 0x3
2466 #define NVM_CFG1_PORT_LASI_INTR_IN_LASI3 0x4
2467 u32 reserved[110]; /* 0xA0 */
2470 struct nvm_cfg1_func {
2471 struct nvm_cfg_mac_address mac_address; /* 0x0 */
2472 u32 rsrv1; /* 0x8 */
2473 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
2474 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
2475 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
2476 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
2477 u32 rsrv2; /* 0xC */
2478 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
2479 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
2480 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
2481 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
2482 u32 device_id; /* 0x10 */
2483 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
2484 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
2485 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
2486 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
2487 u32 cmn_cfg; /* 0x14 */
2488 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
2489 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
2490 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
2491 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
2492 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
2493 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
2494 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
2495 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
2496 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
2497 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
2498 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
2499 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
2500 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
2501 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
2502 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
2503 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
2504 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
2505 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
2506 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
2507 u32 pci_cfg; /* 0x18 */
2508 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
2509 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
2510 /* AH VF BAR2 size */
2511 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
2512 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
2513 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
2514 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
2515 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
2516 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
2517 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
2518 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
2519 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
2520 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
2521 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
2522 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
2523 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
2524 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
2525 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
2526 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
2527 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
2528 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
2529 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
2530 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
2531 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
2532 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
2533 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
2534 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
2535 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
2536 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
2537 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
2538 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
2539 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
2540 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
2541 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
2542 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
2543 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
2544 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
2545 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
2546 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
2547 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
2548 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
2549 /* Hide function in npar mode */
2550 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
2551 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
2552 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
2553 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
2554 /* AH BAR2 size (per function) */
2555 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
2556 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
2557 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
2558 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
2559 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
2560 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
2561 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
2562 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
2563 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
2564 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
2565 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
2566 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
2567 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
2568 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
2569 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
2570 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
2571 u32 preboot_generic_cfg; /* 0x2C */
2572 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
2573 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
2574 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
2575 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
2576 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000
2577 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17
2578 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1
2579 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2
2580 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4
2581 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8
2582 u32 reserved[8]; /* 0x30 */
2586 struct nvm_cfg1_glob glob; /* 0x0 */
2587 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */
2588 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
2589 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
2592 /******************************************
2594 ******************************************/
2602 char *friendly_name;
2605 enum nvm_cfg_sections {
2606 NVM_CFG_SECTION_NVM_CFG1,
2612 u32 sections_offset[NVM_CFG_SECTION_MAX];
2613 struct nvm_cfg1 cfg1;
2616 /******************************************
2618 ******************************************/
2620 #define NVM_CFG_ID_MAC_ADDRESS 1
2621 #define NVM_CFG_ID_BOARD_SWAP 8
2622 #define NVM_CFG_ID_MF_MODE 9
2623 #define NVM_CFG_ID_LED_MODE 10
2624 #define NVM_CFG_ID_FAN_FAILURE_ENFORCEMENT 11
2625 #define NVM_CFG_ID_ENGINEERING_CHANGE 12
2626 #define NVM_CFG_ID_MANUFACTURING_ID 13
2627 #define NVM_CFG_ID_SERIAL_NUMBER 14
2628 #define NVM_CFG_ID_PCI_GEN 15
2629 #define NVM_CFG_ID_BEACON_WOL_ENABLED 16
2630 #define NVM_CFG_ID_ASPM_SUPPORT 17
2631 #define NVM_CFG_ID_ROCE_PRIORITY 20
2632 #define NVM_CFG_ID_ENABLE_WOL_ON_ACPI_PATTERN 22
2633 #define NVM_CFG_ID_MAGIC_PACKET_WOL 23
2634 #define NVM_CFG_ID_AVS_MARGIN_LOW_BB 24
2635 #define NVM_CFG_ID_AVS_MARGIN_HIGH_BB 25
2636 #define NVM_CFG_ID_DCBX_MODE 26
2637 #define NVM_CFG_ID_DRV_SPEED_CAPABILITY_MASK 27
2638 #define NVM_CFG_ID_MFW_SPEED_CAPABILITY_MASK 28
2639 #define NVM_CFG_ID_DRV_LINK_SPEED 29
2640 #define NVM_CFG_ID_DRV_FLOW_CONTROL 30
2641 #define NVM_CFG_ID_MFW_LINK_SPEED 31
2642 #define NVM_CFG_ID_MFW_FLOW_CONTROL 32
2643 #define NVM_CFG_ID_OPTIC_MODULE_VENDOR_ENFORCEMENT 33
2644 #define NVM_CFG_ID_OPTIONAL_LINK_MODES_BB 34
2645 #define NVM_CFG_ID_MF_VENDOR_DEVICE_ID 37
2646 #define NVM_CFG_ID_NETWORK_PORT_MODE 38
2647 #define NVM_CFG_ID_MPS10_RX_LANE_SWAP_BB 39
2648 #define NVM_CFG_ID_MPS10_TX_LANE_SWAP_BB 40
2649 #define NVM_CFG_ID_MPS10_RX_LANE_POLARITY_BB 41
2650 #define NVM_CFG_ID_MPS10_TX_LANE_POLARITY_BB 42
2651 #define NVM_CFG_ID_MPS25_RX_LANE_SWAP_BB 43
2652 #define NVM_CFG_ID_MPS25_TX_LANE_SWAP_BB 44
2653 #define NVM_CFG_ID_MPS25_RX_LANE_POLARITY 45
2654 #define NVM_CFG_ID_MPS25_TX_LANE_POLARITY 46
2655 #define NVM_CFG_ID_MPS10_PREEMPHASIS_BB 47
2656 #define NVM_CFG_ID_MPS10_DRIVER_CURRENT_BB 48
2657 #define NVM_CFG_ID_MPS10_ENFORCE_TX_FIR_CFG_BB 49
2658 #define NVM_CFG_ID_MPS25_PREEMPHASIS 50
2659 #define NVM_CFG_ID_MPS25_DRIVER_CURRENT 51
2660 #define NVM_CFG_ID_MPS25_ENFORCE_TX_FIR_CFG 52
2661 #define NVM_CFG_ID_MPS10_CORE_ADDR_BB 53
2662 #define NVM_CFG_ID_MPS25_CORE_ADDR_BB 54
2663 #define NVM_CFG_ID_EXTERNAL_PHY_TYPE 55
2664 #define NVM_CFG_ID_EXTERNAL_PHY_ADDRESS 56
2665 #define NVM_CFG_ID_SERDES_NET_INTERFACE_BB 57
2666 #define NVM_CFG_ID_AN_MODE_BB 58
2667 #define NVM_CFG_ID_PREBOOT_OPROM 59
2668 #define NVM_CFG_ID_MBA_DELAY_TIME 61
2669 #define NVM_CFG_ID_MBA_SETUP_HOT_KEY 62
2670 #define NVM_CFG_ID_MBA_HIDE_SETUP_PROMPT 63
2671 #define NVM_CFG_ID_PREBOOT_LINK_SPEED 67
2672 #define NVM_CFG_ID_PREBOOT_BOOT_PROTOCOL 69
2673 #define NVM_CFG_ID_ENABLE_SRIOV 70
2674 #define NVM_CFG_ID_ENABLE_ATC 71
2675 #define NVM_CFG_ID_NUMBER_OF_VFS_PER_PF 74
2676 #define NVM_CFG_ID_VF_PCI_BAR2_SIZE_K2_E5 75
2677 #define NVM_CFG_ID_VENDOR_ID 76
2678 #define NVM_CFG_ID_SUBSYSTEM_VENDOR_ID 78
2679 #define NVM_CFG_ID_SUBSYSTEM_DEVICE_ID 79
2680 #define NVM_CFG_ID_VF_PCI_BAR2_SIZE_BB 81
2681 #define NVM_CFG_ID_BAR1_SIZE 82
2682 #define NVM_CFG_ID_BAR2_SIZE_BB 83
2683 #define NVM_CFG_ID_VF_PCI_DEVICE_ID 84
2684 #define NVM_CFG_ID_MPS10_TXFIR_MAIN_BB 85
2685 #define NVM_CFG_ID_MPS10_TXFIR_POST_BB 86
2686 #define NVM_CFG_ID_MPS25_TXFIR_MAIN 87
2687 #define NVM_CFG_ID_MPS25_TXFIR_POST 88
2688 #define NVM_CFG_ID_MANUFACTURE_KIT_VERSION 89
2689 #define NVM_CFG_ID_MANUFACTURE_TIMESTAMP 90
2690 #define NVM_CFG_ID_PERSONALITY 92
2691 #define NVM_CFG_ID_FCOE_NODE_WWN_MAC_ADDR 93
2692 #define NVM_CFG_ID_FCOE_PORT_WWN_MAC_ADDR 94
2693 #define NVM_CFG_ID_BANDWIDTH_WEIGHT 95
2694 #define NVM_CFG_ID_MAX_BANDWIDTH 96
2695 #define NVM_CFG_ID_PAUSE_ON_HOST_RING 97
2696 #define NVM_CFG_ID_PCIE_PREEMPHASIS 98
2697 #define NVM_CFG_ID_LLDP_MAC_ADDRESS 99
2698 #define NVM_CFG_ID_FCOE_WWN_NODE_PREFIX 100
2699 #define NVM_CFG_ID_FCOE_WWN_PORT_PREFIX 101
2700 #define NVM_CFG_ID_LED_SPEED_SELECT 102
2701 #define NVM_CFG_ID_LED_PORT_SWAP 103
2702 #define NVM_CFG_ID_AVS_MODE_BB 104
2703 #define NVM_CFG_ID_OVERRIDE_SECURE_MODE 105
2704 #define NVM_CFG_ID_AVS_DAC_CODE_BB 106
2705 #define NVM_CFG_ID_MBI_VERSION 107
2706 #define NVM_CFG_ID_MBI_DATE 108
2707 #define NVM_CFG_ID_SMBUS_ADDRESS 109
2708 #define NVM_CFG_ID_NCSI_PACKAGE_ID 110
2709 #define NVM_CFG_ID_SIDEBAND_MODE 111
2710 #define NVM_CFG_ID_SMBUS_MODE 112
2711 #define NVM_CFG_ID_NCSI 113
2712 #define NVM_CFG_ID_TRANSCEIVER_MODULE_ABSENT 114
2713 #define NVM_CFG_ID_I2C_MUX_SELECT_GPIO_BB 115
2714 #define NVM_CFG_ID_I2C_MUX_SELECT_VALUE_BB 116
2715 #define NVM_CFG_ID_DEVICE_CAPABILITIES 117
2716 #define NVM_CFG_ID_ETH_DID_SUFFIX 118
2717 #define NVM_CFG_ID_FCOE_DID_SUFFIX 119
2718 #define NVM_CFG_ID_ISCSI_DID_SUFFIX 120
2719 #define NVM_CFG_ID_DEFAULT_ENABLED_PROTOCOLS 122
2720 #define NVM_CFG_ID_POWER_DISSIPATED_BB 123
2721 #define NVM_CFG_ID_POWER_CONSUMED_BB 124
2722 #define NVM_CFG_ID_AUX_MODE 125
2723 #define NVM_CFG_ID_PORT_TYPE 126
2724 #define NVM_CFG_ID_TX_DISABLE 127
2725 #define NVM_CFG_ID_MAX_LINK_WIDTH 128
2726 #define NVM_CFG_ID_ASPM_L1_MODE 130
2727 #define NVM_CFG_ID_ON_CHIP_SENSOR_MODE 131
2728 #define NVM_CFG_ID_PREBOOT_VLAN_VALUE 132
2729 #define NVM_CFG_ID_PREBOOT_VLAN 133
2730 #define NVM_CFG_ID_TEMPERATURE_PERIOD_BETWEEN_CHECKS 134
2731 #define NVM_CFG_ID_SHUTDOWN_THRESHOLD_TEMPERATURE 135
2732 #define NVM_CFG_ID_MAX_COUNT_OPER_THRESHOLD 136
2733 #define NVM_CFG_ID_DEAD_TEMP_TH_TEMPERATURE 137
2734 #define NVM_CFG_ID_TEMPERATURE_MONITORING_MODE 139
2735 #define NVM_CFG_ID_AN_25G_50G_OUI 140
2736 #define NVM_CFG_ID_PLDM_SENSOR_MODE 141
2737 #define NVM_CFG_ID_EXTERNAL_THERMAL_SENSOR 142
2738 #define NVM_CFG_ID_EXTERNAL_THERMAL_SENSOR_ADDRESS 143
2739 #define NVM_CFG_ID_FAN_FAILURE_DURATION 144
2740 #define NVM_CFG_ID_FEC_FORCE_MODE 145
2741 #define NVM_CFG_ID_MULTI_NETWORK_MODES_CAPABILITY 146
2742 #define NVM_CFG_ID_MNM_10G_DRV_SPEED_CAPABILITY_MASK 147
2743 #define NVM_CFG_ID_MNM_10G_MFW_SPEED_CAPABILITY_MASK 148
2744 #define NVM_CFG_ID_MNM_10G_DRV_LINK_SPEED 149
2745 #define NVM_CFG_ID_MNM_10G_MFW_LINK_SPEED 150
2746 #define NVM_CFG_ID_MNM_10G_PORT_TYPE 151
2747 #define NVM_CFG_ID_MNM_10G_SERDES_NET_INTERFACE 152
2748 #define NVM_CFG_ID_MNM_10G_FEC_FORCE_MODE 153
2749 #define NVM_CFG_ID_MNM_10G_ETH_DID_SUFFIX 154
2750 #define NVM_CFG_ID_MNM_25G_DRV_SPEED_CAPABILITY_MASK 155
2751 #define NVM_CFG_ID_MNM_25G_MFW_SPEED_CAPABILITY_MASK 156
2752 #define NVM_CFG_ID_MNM_25G_DRV_LINK_SPEED 157
2753 #define NVM_CFG_ID_MNM_25G_MFW_LINK_SPEED 158
2754 #define NVM_CFG_ID_MNM_25G_PORT_TYPE 159
2755 #define NVM_CFG_ID_MNM_25G_SERDES_NET_INTERFACE 160
2756 #define NVM_CFG_ID_MNM_25G_ETH_DID_SUFFIX 161
2757 #define NVM_CFG_ID_MNM_25G_FEC_FORCE_MODE 162
2758 #define NVM_CFG_ID_MNM_40G_DRV_SPEED_CAPABILITY_MASK 163
2759 #define NVM_CFG_ID_MNM_40G_MFW_SPEED_CAPABILITY_MASK 164
2760 #define NVM_CFG_ID_MNM_40G_DRV_LINK_SPEED 165
2761 #define NVM_CFG_ID_MNM_40G_MFW_LINK_SPEED 166
2762 #define NVM_CFG_ID_MNM_40G_PORT_TYPE 167
2763 #define NVM_CFG_ID_MNM_40G_SERDES_NET_INTERFACE 168
2764 #define NVM_CFG_ID_MNM_40G_ETH_DID_SUFFIX 169
2765 #define NVM_CFG_ID_MNM_40G_FEC_FORCE_MODE 170
2766 #define NVM_CFG_ID_MNM_50G_DRV_SPEED_CAPABILITY_MASK 171
2767 #define NVM_CFG_ID_MNM_50G_MFW_SPEED_CAPABILITY_MASK 172
2768 #define NVM_CFG_ID_MNM_50G_DRV_LINK_SPEED 173
2769 #define NVM_CFG_ID_MNM_50G_MFW_LINK_SPEED 174
2770 #define NVM_CFG_ID_MNM_50G_PORT_TYPE 175
2771 #define NVM_CFG_ID_MNM_50G_SERDES_NET_INTERFACE 176
2772 #define NVM_CFG_ID_MNM_50G_ETH_DID_SUFFIX 177
2773 #define NVM_CFG_ID_MNM_50G_FEC_FORCE_MODE 178
2774 #define NVM_CFG_ID_MNM_100G_DRV_SPEED_CAP_MASK_BB 179
2775 #define NVM_CFG_ID_MNM_100G_MFW_SPEED_CAP_MASK_BB 180
2776 #define NVM_CFG_ID_MNM_100G_DRV_LINK_SPEED_BB 181
2777 #define NVM_CFG_ID_MNM_100G_MFW_LINK_SPEED_BB 182
2778 #define NVM_CFG_ID_MNM_100G_PORT_TYPE_BB 183
2779 #define NVM_CFG_ID_MNM_100G_SERDES_NET_INTERFACE_BB 184
2780 #define NVM_CFG_ID_MNM_100G_ETH_DID_SUFFIX_BB 185
2781 #define NVM_CFG_ID_MNM_100G_FEC_FORCE_MODE_BB 186
2782 #define NVM_CFG_ID_FUNCTION_HIDE 187
2783 #define NVM_CFG_ID_BAR2_TOTAL_BUDGET_BB 188
2784 #define NVM_CFG_ID_CRASH_DUMP_TRIGGER_ENABLE 189
2785 #define NVM_CFG_ID_MPS25_LANE_SWAP_K2_E5 190
2786 #define NVM_CFG_ID_BAR2_SIZE_K2_E5 191
2787 #define NVM_CFG_ID_EXT_PHY_RESET 192
2788 #define NVM_CFG_ID_EEE_POWER_SAVING_MODE 193
2789 #define NVM_CFG_ID_OVERRIDE_PCIE_PRESET_EQUAL_BB 194
2790 #define NVM_CFG_ID_PCIE_PRESET_VALUE_BB 195
2791 #define NVM_CFG_ID_MAX_MSIX 196
2792 #define NVM_CFG_ID_NVM_CFG_VERSION 197
2793 #define NVM_CFG_ID_NVM_CFG_NEW_OPTION_SEQ 198
2794 #define NVM_CFG_ID_NVM_CFG_REMOVED_OPTION_SEQ 199
2795 #define NVM_CFG_ID_NVM_CFG_UPDATED_VALUE_SEQ 200
2796 #define NVM_CFG_ID_EXTENDED_SERIAL_NUMBER 201
2797 #define NVM_CFG_ID_RDMA_ENABLEMENT 202
2798 #define NVM_CFG_ID_MAX_CONT_OPERATING_TEMP 203
2799 #define NVM_CFG_ID_RUNTIME_PORT_SWAP_GPIO 204
2800 #define NVM_CFG_ID_RUNTIME_PORT_SWAP_MAP 205
2801 #define NVM_CFG_ID_THERMAL_EVENT_GPIO 206
2802 #define NVM_CFG_ID_I2C_INTERRUPT_GPIO 207
2803 #define NVM_CFG_ID_DCI_SUPPORT 208
2804 #define NVM_CFG_ID_PCIE_VDM_ENABLED 209
2805 #define NVM_CFG_ID_OEM1_NUMBER 210
2806 #define NVM_CFG_ID_OEM2_NUMBER 211
2807 #define NVM_CFG_ID_FEC_AN_MODE_K2_E5 212
2808 #define NVM_CFG_ID_NPAR_ENABLED_PROTOCOL 213
2809 #define NVM_CFG_ID_MPS25_ACTIVE_TXFIR_PRE 214
2810 #define NVM_CFG_ID_MPS25_ACTIVE_TXFIR_MAIN 215
2811 #define NVM_CFG_ID_MPS25_ACTIVE_TXFIR_POST 216
2812 #define NVM_CFG_ID_ALOM_FAN_ON_AUX_GPIO 217
2813 #define NVM_CFG_ID_ALOM_FAN_ON_AUX_VALUE 218
2814 #define NVM_CFG_ID_SLOT_ID_GPIO 219
2815 #define NVM_CFG_ID_PMBUS_SCL_GPIO 220
2816 #define NVM_CFG_ID_PMBUS_SDA_GPIO 221
2817 #define NVM_CFG_ID_RESET_ON_LAN 222
2818 #define NVM_CFG_ID_NCSI_PACKAGE_ID_IO 223
2819 #define NVM_CFG_ID_TX_RX_EQ_25G_HLPC 224
2820 #define NVM_CFG_ID_TX_RX_EQ_25G_LLPC 225
2821 #define NVM_CFG_ID_TX_RX_EQ_25G_AC 226
2822 #define NVM_CFG_ID_TX_RX_EQ_10G_PC 227
2823 #define NVM_CFG_ID_TX_RX_EQ_10G_AC 228
2824 #define NVM_CFG_ID_TX_RX_EQ_1G 229
2825 #define NVM_CFG_ID_TX_RX_EQ_25G_BT 230
2826 #define NVM_CFG_ID_TX_RX_EQ_10G_BT 231
2827 #define NVM_CFG_ID_PF_MAPPING 232
2828 #define NVM_CFG_ID_RECOVERY_MODE 234
2829 #define NVM_CFG_ID_PHY_MODULE_DEAD_TEMP_TH 235
2830 #define NVM_CFG_ID_PHY_MODULE_ALOM_FAN_ON_TEMP_TH 236
2831 #define NVM_CFG_ID_PREBOOT_DEBUG_MODE_STD 237
2832 #define NVM_CFG_ID_PREBOOT_DEBUG_MODE_EXT 238
2833 #define NVM_CFG_ID_SMARTLINQ_MODE 239
2834 #define NVM_CFG_ID_PREBOOT_LINK_UP_DELAY 242
2835 #define NVM_CFG_ID_VOLTAGE_REGULATOR_TYPE 243
2836 #define NVM_CFG_ID_MAIN_CLOCK_FREQUENCY 245
2837 #define NVM_CFG_ID_MAC_CLOCK_FREQUENCY 246
2838 #define NVM_CFG_ID_STORM_CLOCK_FREQUENCY 247
2839 #define NVM_CFG_ID_PCIE_RELAXED_ORDERING 248
2840 #define NVM_CFG_ID_EXT_PHY_MDI_PAIR_SWAP 249
2841 #define NVM_CFG_ID_UID_LED_MODE_MASK 250
2842 #define NVM_CFG_ID_NCSI_AUX_LINK 251
2843 #define NVM_CFG_ID_SMARTAN_FEC_OVERRIDE 272
2844 #define NVM_CFG_ID_LLDP_DISABLE 273
2845 #define NVM_CFG_ID_SHORT_PERST_PROTECTION_K2_E5 274
2846 #define NVM_CFG_ID_TRANSCEIVER_RATE_SELECT_0 275
2847 #define NVM_CFG_ID_TRANSCEIVER_RATE_SELECT_1 276
2848 #define NVM_CFG_ID_TRANSCEIVER_MODULE_TX_FAULT 277
2849 #define NVM_CFG_ID_TRANSCEIVER_QSFP_MODULE_RESET 278
2850 #define NVM_CFG_ID_TRANSCEIVER_QSFP_LP_MODE 279
2851 #define NVM_CFG_ID_TRANSCEIVER_POWER_ENABLE 280
2852 #define NVM_CFG_ID_LASI_INTERRUPT_INPUT 281
2853 #define NVM_CFG_ID_EXT_PHY_PGOOD_INPUT 282
2854 #define NVM_CFG_ID_TRACE_LEVEL 283
2855 #define NVM_CFG_ID_TRACE_MODULES 284
2856 #define NVM_CFG_ID_EMULATED_TMP421 285
2857 #define NVM_CFG_ID_WARNING_TEMPERATURE_GPIO 286
2858 #define NVM_CFG_ID_WARNING_TEMPERATURE_THRESHOLD 287
2859 #define NVM_CFG_ID_PERST_INDICATION_GPIO 288
2860 #define NVM_CFG_ID_PCIE_CLASS_CODE_FCOE_K2_E5 289
2861 #define NVM_CFG_ID_PCIE_CLASS_CODE_ISCSI_K2_E5 290
2862 #define NVM_CFG_ID_NUMBER_OF_PROVISIONED_MAC 291
2863 #define NVM_CFG_ID_NUMBER_OF_PROVISIONED_VF_MAC 292
2864 #define NVM_CFG_ID_PROVISIONED_BMC_MAC 293
2865 #define NVM_CFG_ID_OVERRIDE_AGC_THRESHOLD_K2 294
2866 #define NVM_CFG_ID_WARNING_TEMPERATURE_DELTA 295
2867 #define NVM_CFG_ID_ALOM_FAN_ON_AUX_DELTA 296
2868 #define NVM_CFG_ID_DEAD_TEMP_TH_DELTA 297
2869 #define NVM_CFG_ID_PHY_MODULE_WARNING_TEMP_TH 298
2870 #define NVM_CFG_ID_DISABLE_PLDM 299
2871 #define NVM_CFG_ID_DISABLE_MCTP_OEM 300
2872 #endif /* NVM_CFG_H */