2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /****************************************************************************
13 * Description: NVM config file - Generated file from nvm cfg excel.
18 ****************************************************************************/
23 struct nvm_cfg_mac_address {
25 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
26 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
30 /******************************************
32 ******************************************/
33 struct nvm_cfg1_glob {
34 u32 generic_cont0; /* 0x0 */
35 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
36 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
37 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
38 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
39 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
40 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
41 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
42 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
43 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
44 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
45 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
46 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
47 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
48 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
49 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
50 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
51 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
52 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
53 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
54 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
55 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
56 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
57 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
58 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
59 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
60 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
61 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
62 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
63 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
64 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
65 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
66 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
67 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
68 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
69 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
70 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
71 u32 engineering_change[3]; /* 0x4 */
72 u32 manufacturing_id; /* 0x10 */
73 u32 serial_number[4]; /* 0x14 */
74 u32 pcie_cfg; /* 0x24 */
75 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
76 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
77 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
78 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
79 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
80 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
81 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
82 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
83 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
84 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
85 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
86 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
87 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
88 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020
89 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
90 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
91 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
92 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
93 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
94 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
95 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
96 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
97 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
98 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
99 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
100 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
101 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
102 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
103 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
104 /* Set the duration, in seconds, fan failure signal should be
107 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000
108 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
109 u32 mgmt_traffic; /* 0x28 */
110 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
111 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
112 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
113 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
114 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
115 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
116 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
117 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
118 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
119 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
120 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
121 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
122 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
123 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
124 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
125 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
126 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
127 /* Indicates whether external thermal sonsor is available */
128 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
129 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
130 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
131 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
132 u32 core_cfg; /* 0x2C */
133 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
134 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
135 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
136 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
137 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
138 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
139 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
140 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
141 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
142 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
143 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
144 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
145 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
146 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
147 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
148 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
149 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
150 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
151 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
152 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
153 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
154 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
155 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
156 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
157 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
158 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
159 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
160 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
161 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
162 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
163 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
164 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
165 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
166 u32 e_lane_cfg1; /* 0x30 */
167 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
168 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
169 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
170 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
171 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
172 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
173 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
174 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
175 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
176 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
177 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
178 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
179 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
180 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
181 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
182 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
183 u32 e_lane_cfg2; /* 0x34 */
184 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
185 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
186 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
187 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
188 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
189 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
190 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
191 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
192 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
193 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
194 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
195 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
196 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
197 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
198 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
199 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
200 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
201 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
202 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
203 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
204 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
205 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
206 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
207 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
208 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
209 /* Maximum advertised pcie link width */
210 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
211 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
212 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_16_LANES 0x0
213 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
214 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
215 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
216 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
218 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
219 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
220 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
221 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
222 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
223 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
224 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
225 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
226 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
227 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
228 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \
230 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
231 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
232 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
233 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
234 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
235 /* Set the PLDM sensor modes */
236 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
237 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
238 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
239 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
240 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
241 u32 f_lane_cfg1; /* 0x38 */
242 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
243 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
244 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
245 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
246 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
247 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
248 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
249 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
250 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
251 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
252 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
253 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
254 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
255 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
256 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
257 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
258 u32 f_lane_cfg2; /* 0x3C */
259 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
260 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
261 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
262 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
263 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
264 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
265 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
266 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
267 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
268 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
269 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
270 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
271 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
272 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
273 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
274 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
275 /* Control the period between two successive checks */
276 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \
278 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
279 /* Set shutdown temperature */
280 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \
282 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
283 /* Set max. count for over operational temperature */
284 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
285 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
286 u32 eagle_preemphasis; /* 0x40 */
287 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
288 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
289 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
290 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
291 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
292 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
293 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
294 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
295 u32 eagle_driver_current; /* 0x44 */
296 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
297 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
298 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
299 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
300 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
301 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
302 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
303 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
304 u32 falcon_preemphasis; /* 0x48 */
305 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
306 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
307 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
308 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
309 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
310 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
311 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
312 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
313 u32 falcon_driver_current; /* 0x4C */
314 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
315 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
316 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
317 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
318 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
319 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
320 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
321 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
322 u32 pci_id; /* 0x50 */
323 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
324 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
325 /* Set caution temperature */
326 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK \
328 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16
329 /* Set external thermal sensor I2C address */
330 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \
332 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
333 u32 pci_subsys_id; /* 0x54 */
334 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
335 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
336 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
337 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
339 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
340 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
341 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
342 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
343 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
344 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
345 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
346 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
347 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
348 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
349 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
350 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
351 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
352 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
353 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
354 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
355 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
356 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
357 /* BB VF BAR2 size */
358 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
359 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
360 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
361 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
362 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
363 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
364 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
365 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
366 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
367 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
368 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
369 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
370 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
371 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
372 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
373 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
374 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
375 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
376 /* BB BAR2 size (global) */
377 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
378 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
379 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
380 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
381 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
382 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
383 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
384 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
385 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
386 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
387 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
388 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
389 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
390 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
391 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
392 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
393 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
394 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
395 /* Set the duration, in seconds, fan failure signal should be
398 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
399 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
400 u32 eagle_txfir_main; /* 0x5C */
401 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
402 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
403 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
404 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
405 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
406 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
407 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
408 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
409 u32 eagle_txfir_post; /* 0x60 */
410 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
411 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
412 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
413 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
414 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
415 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
416 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
417 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
418 u32 falcon_txfir_main; /* 0x64 */
419 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
420 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
421 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
422 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
423 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
424 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
425 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
426 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
427 u32 falcon_txfir_post; /* 0x68 */
428 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
429 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
430 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
431 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
432 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
433 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
434 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
435 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
436 u32 manufacture_ver; /* 0x6C */
437 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
438 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
439 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
440 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
441 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
442 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
443 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
444 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
445 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
446 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
447 u32 manufacture_time; /* 0x70 */
448 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
449 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
450 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
451 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
452 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
453 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
454 u32 led_global_settings; /* 0x74 */
455 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
456 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
457 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
458 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
459 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
460 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
461 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
462 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
463 u32 generic_cont1; /* 0x78 */
464 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
465 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
466 u32 mbi_version; /* 0x7C */
467 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
468 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
469 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
470 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
471 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
472 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
473 u32 mbi_date; /* 0x80 */
474 u32 misc_sig; /* 0x84 */
475 /* Define the GPIO mapping to switch i2c mux */
476 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
477 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
478 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
479 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
480 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
481 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
482 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
483 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
484 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
485 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
486 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
487 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
488 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
489 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
490 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
491 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
492 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
493 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
494 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
495 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
496 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
497 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
498 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
499 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
500 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
501 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
502 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
503 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
504 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
505 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
506 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
507 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
508 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
509 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
510 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
511 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
512 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
513 u32 device_capabilities; /* 0x88 */
514 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
515 u32 power_dissipated; /* 0x8C */
516 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
517 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
518 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
519 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
520 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
521 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
522 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
523 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
524 u32 power_consumed; /* 0x90 */
525 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
526 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
527 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
528 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
529 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
530 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
531 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
532 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
533 u32 efi_version; /* 0x94 */
534 u32 reserved[42]; /* 0x98 */
537 struct nvm_cfg1_path {
538 u32 reserved[30]; /* 0x0 */
541 struct nvm_cfg1_port {
542 u32 reserved__m_relocated_to_option_123; /* 0x0 */
543 u32 reserved__m_relocated_to_option_124; /* 0x4 */
544 u32 generic_cont0; /* 0x8 */
545 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
546 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
547 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
548 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
549 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
550 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
551 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
552 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
553 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
554 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
555 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
556 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
557 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
558 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
559 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
560 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
561 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
562 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
563 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
564 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
565 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
566 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
567 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
568 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
569 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
570 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
571 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
572 u32 pcie_cfg; /* 0xC */
573 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
574 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
575 u32 features; /* 0x10 */
576 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
577 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
578 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
579 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
580 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
581 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
582 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
583 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
584 u32 speed_cap_mask; /* 0x14 */
585 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
586 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
587 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
588 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
589 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
590 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
591 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
592 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
593 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
594 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
595 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
596 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
597 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
598 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
599 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
600 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
601 u32 link_settings; /* 0x18 */
602 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
603 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
604 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
605 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
606 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
607 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
608 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
609 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
610 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
611 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
612 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
613 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
614 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
615 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
616 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
617 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
618 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
619 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
620 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
621 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
622 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
623 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
624 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
625 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
626 #define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
627 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
628 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
629 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
630 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
631 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
632 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
633 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
634 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
635 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
636 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
637 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
638 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
639 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
640 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
641 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
642 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_NONE 0x0
643 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_FIRECODE 0x1
644 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_RS 0x2
645 u32 phy_cfg; /* 0x1C */
646 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
647 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
648 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
649 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
650 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
651 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
652 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
653 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
654 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
655 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
656 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
657 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
658 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
659 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
660 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
661 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
662 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
663 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
664 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
665 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
666 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
667 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
668 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
669 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
670 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
671 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
672 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
673 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
674 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
675 #define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
676 #define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
677 u32 mgmt_traffic; /* 0x20 */
678 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
679 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
680 u32 ext_phy; /* 0x24 */
681 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
682 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
683 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
684 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
685 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
686 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
687 u32 mba_cfg1; /* 0x28 */
688 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
689 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
690 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
691 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
692 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
693 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
694 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
695 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
696 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
697 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
698 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
699 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
700 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
701 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
702 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
703 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
704 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
705 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
706 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
707 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
708 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
709 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
710 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
711 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
712 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
713 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
714 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
715 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
716 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
717 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
718 u32 mba_cfg2; /* 0x2C */
719 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
720 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
721 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
722 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
723 u32 vf_cfg; /* 0x30 */
724 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
725 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
726 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
727 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
728 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
729 u32 led_port_settings; /* 0x3C */
730 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
731 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
732 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
733 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
734 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
735 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
736 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
737 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
738 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
739 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
740 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
741 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
742 u32 transceiver_00; /* 0x40 */
743 /* Define for mapping of transceiver signal module absent */
744 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
745 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
746 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
747 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
748 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
749 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
750 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
751 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
752 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
753 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
754 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
755 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
756 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
757 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
758 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
759 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
760 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
761 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
762 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
763 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
764 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
765 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
766 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
767 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
768 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
769 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
770 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
771 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
772 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
773 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
774 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
775 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
776 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
777 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
778 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
779 /* Define the GPIO mux settings to switch i2c mux to this port */
780 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
781 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
782 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
783 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
784 u32 device_ids; /* 0x44 */
785 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
786 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
787 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
788 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
789 u32 board_cfg; /* 0x48 */
790 /* This field defines the board technology
791 * (backpane,transceiver,external PHY)
793 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
794 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
795 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
796 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
797 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
798 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
799 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
800 /* This field defines the GPIO mapped to tx_disable signal in SFP */
801 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
802 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
803 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
804 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
805 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
806 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
807 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
808 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
809 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
810 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
811 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
812 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
813 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
814 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
815 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
816 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
817 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
818 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
819 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
820 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
821 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
822 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
823 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
824 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
825 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
826 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
827 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
828 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
829 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
830 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
831 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
832 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
833 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
834 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
835 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
836 u32 reserved[131]; /* 0x4C */
839 struct nvm_cfg1_func {
840 struct nvm_cfg_mac_address mac_address; /* 0x0 */
842 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
843 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
844 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
845 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
847 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
848 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
849 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
850 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
851 u32 device_id; /* 0x10 */
852 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
853 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
854 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
855 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
856 u32 cmn_cfg; /* 0x14 */
857 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
858 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
859 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
860 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
861 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
862 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
863 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
864 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
865 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
866 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
867 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
868 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
869 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
870 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
871 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
872 u32 pci_cfg; /* 0x18 */
873 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
874 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
875 #define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
876 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
877 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
878 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
879 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
880 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
881 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
882 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
883 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
884 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
885 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
886 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
887 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
888 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
889 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
890 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
891 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
892 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
893 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
894 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
895 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
896 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
897 u32 preboot_generic_cfg; /* 0x2C */
898 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
899 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
900 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
901 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
902 u32 reserved[8]; /* 0x30 */
906 struct nvm_cfg1_glob glob; /* 0x0 */
907 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
908 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
909 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
912 /******************************************
914 ******************************************/
915 enum nvm_cfg_sections {
916 NVM_CFG_SECTION_NVM_CFG1,
922 u32 sections_offset[NVM_CFG_SECTION_MAX];
923 struct nvm_cfg1 cfg1;
926 #endif /* NVM_CFG_H */