2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
12 #include <rte_kvargs.h>
15 int qede_logtype_init;
16 int qede_logtype_driver;
18 static const struct qed_eth_ops *qed_ops;
19 static int64_t timer_period = 1;
21 /* VXLAN tunnel classification mapping */
22 const struct _qede_udp_tunn_types {
23 uint16_t rte_filter_type;
24 enum ecore_filter_ucast_type qede_type;
25 enum ecore_tunn_clss qede_tunn_clss;
27 } qede_tunn_types[] = {
29 ETH_TUNNEL_FILTER_OMAC,
31 ECORE_TUNN_CLSS_MAC_VLAN,
35 ETH_TUNNEL_FILTER_TENID,
37 ECORE_TUNN_CLSS_MAC_VNI,
41 ETH_TUNNEL_FILTER_IMAC,
42 ECORE_FILTER_INNER_MAC,
43 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
47 ETH_TUNNEL_FILTER_IVLAN,
48 ECORE_FILTER_INNER_VLAN,
49 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
53 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
54 ECORE_FILTER_MAC_VNI_PAIR,
55 ECORE_TUNN_CLSS_MAC_VNI,
59 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
62 "outer-mac and inner-mac"
65 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
68 "outer-mac and inner-vlan"
71 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
72 ECORE_FILTER_INNER_MAC_VNI_PAIR,
73 ECORE_TUNN_CLSS_INNER_MAC_VNI,
77 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
83 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
84 ECORE_FILTER_INNER_PAIR,
85 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
86 "inner-mac and inner-vlan",
89 ETH_TUNNEL_FILTER_OIP,
95 ETH_TUNNEL_FILTER_IIP,
101 RTE_TUNNEL_FILTER_IMAC_IVLAN,
107 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
113 RTE_TUNNEL_FILTER_IMAC_TENID,
119 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
126 struct rte_qede_xstats_name_off {
127 char name[RTE_ETH_XSTATS_NAME_SIZE];
131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
133 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
134 {"rx_multicast_bytes",
135 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
136 {"rx_broadcast_bytes",
137 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
138 {"rx_unicast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
140 {"rx_multicast_packets",
141 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
142 {"rx_broadcast_packets",
143 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
146 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
147 {"tx_multicast_bytes",
148 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
149 {"tx_broadcast_bytes",
150 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
151 {"tx_unicast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
153 {"tx_multicast_packets",
154 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
155 {"tx_broadcast_packets",
156 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
158 {"rx_64_byte_packets",
159 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
160 {"rx_65_to_127_byte_packets",
161 offsetof(struct ecore_eth_stats_common,
162 rx_65_to_127_byte_packets)},
163 {"rx_128_to_255_byte_packets",
164 offsetof(struct ecore_eth_stats_common,
165 rx_128_to_255_byte_packets)},
166 {"rx_256_to_511_byte_packets",
167 offsetof(struct ecore_eth_stats_common,
168 rx_256_to_511_byte_packets)},
169 {"rx_512_to_1023_byte_packets",
170 offsetof(struct ecore_eth_stats_common,
171 rx_512_to_1023_byte_packets)},
172 {"rx_1024_to_1518_byte_packets",
173 offsetof(struct ecore_eth_stats_common,
174 rx_1024_to_1518_byte_packets)},
175 {"tx_64_byte_packets",
176 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
177 {"tx_65_to_127_byte_packets",
178 offsetof(struct ecore_eth_stats_common,
179 tx_65_to_127_byte_packets)},
180 {"tx_128_to_255_byte_packets",
181 offsetof(struct ecore_eth_stats_common,
182 tx_128_to_255_byte_packets)},
183 {"tx_256_to_511_byte_packets",
184 offsetof(struct ecore_eth_stats_common,
185 tx_256_to_511_byte_packets)},
186 {"tx_512_to_1023_byte_packets",
187 offsetof(struct ecore_eth_stats_common,
188 tx_512_to_1023_byte_packets)},
189 {"tx_1024_to_1518_byte_packets",
190 offsetof(struct ecore_eth_stats_common,
191 tx_1024_to_1518_byte_packets)},
193 {"rx_mac_crtl_frames",
194 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
195 {"tx_mac_control_frames",
196 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
198 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
200 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
201 {"rx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
203 {"tx_priority_flow_control_frames",
204 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
207 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
209 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
210 {"rx_carrier_errors",
211 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
212 {"rx_oversize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
215 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
216 {"rx_undersize_packet_errors",
217 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
218 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
219 {"rx_host_buffer_not_available",
220 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
221 /* Number of packets discarded because they are bigger than MTU */
222 {"rx_packet_too_big_discards",
223 offsetof(struct ecore_eth_stats_common,
224 packet_too_big_discard)},
225 {"rx_ttl_zero_discards",
226 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
227 {"rx_multi_function_tag_filter_discards",
228 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
229 {"rx_mac_filter_discards",
230 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
231 {"rx_hw_buffer_truncates",
232 offsetof(struct ecore_eth_stats_common, brb_truncates)},
233 {"rx_hw_buffer_discards",
234 offsetof(struct ecore_eth_stats_common, brb_discards)},
235 {"tx_error_drop_packets",
236 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
239 {"rx_mac_unicast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
241 {"rx_mac_multicast_packets",
242 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
243 {"rx_mac_broadcast_packets",
244 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
246 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
248 {"tx_mac_unicast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
250 {"tx_mac_multicast_packets",
251 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
252 {"tx_mac_broadcast_packets",
253 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
255 {"lro_coalesced_packets",
256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
257 {"lro_coalesced_events",
258 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
260 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
261 {"lro_not_coalesced_packets",
262 offsetof(struct ecore_eth_stats_common,
263 tpa_not_coalesced_pkts)},
264 {"lro_coalesced_bytes",
265 offsetof(struct ecore_eth_stats_common,
266 tpa_coalesced_bytes)},
269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
270 {"rx_1519_to_1522_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_1522_byte_packets)},
274 {"rx_1519_to_2047_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_1519_to_2047_byte_packets)},
278 {"rx_2048_to_4095_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_2048_to_4095_byte_packets)},
282 {"rx_4096_to_9216_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_4096_to_9216_byte_packets)},
286 {"rx_9217_to_16383_byte_packets",
287 offsetof(struct ecore_eth_stats, bb) +
288 offsetof(struct ecore_eth_stats_bb,
289 rx_9217_to_16383_byte_packets)},
291 {"tx_1519_to_2047_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_1519_to_2047_byte_packets)},
295 {"tx_2048_to_4095_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_2048_to_4095_byte_packets)},
299 {"tx_4096_to_9216_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_4096_to_9216_byte_packets)},
303 {"tx_9217_to_16383_byte_packets",
304 offsetof(struct ecore_eth_stats, bb) +
305 offsetof(struct ecore_eth_stats_bb,
306 tx_9217_to_16383_byte_packets)},
308 {"tx_lpi_entry_count",
309 offsetof(struct ecore_eth_stats, bb) +
310 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
311 {"tx_total_collisions",
312 offsetof(struct ecore_eth_stats, bb) +
313 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
317 {"rx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 rx_1519_to_max_byte_packets)},
321 {"tx_1519_to_max_byte_packets",
322 offsetof(struct ecore_eth_stats, ah) +
323 offsetof(struct ecore_eth_stats_ah,
324 tx_1519_to_max_byte_packets)},
327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
329 offsetof(struct qede_rx_queue, rx_segs)},
331 offsetof(struct qede_rx_queue, rx_hw_errors)},
332 {"rx_q_allocation_errors",
333 offsetof(struct qede_rx_queue, rx_alloc_errors)}
336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
338 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
342 qede_interrupt_handler(void *param)
344 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
345 struct qede_dev *qdev = eth_dev->data->dev_private;
346 struct ecore_dev *edev = &qdev->edev;
348 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
349 if (rte_intr_enable(eth_dev->intr_handle))
350 DP_ERR(edev, "rte_intr_enable failed\n");
354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
356 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
360 static void qede_print_adapter_info(struct qede_dev *qdev)
362 struct ecore_dev *edev = &qdev->edev;
363 struct qed_dev_info *info = &qdev->dev_info.common;
364 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
365 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
367 DP_INFO(edev, "*********************************\n");
368 DP_INFO(edev, " DPDK version:%s\n", rte_version());
369 DP_INFO(edev, " Chip details : %s %c%d\n",
370 ECORE_IS_BB(edev) ? "BB" : "AH",
371 'A' + edev->chip_rev,
372 (int)edev->chip_metal);
373 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
374 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
375 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
376 ver_str, QEDE_PMD_VERSION);
377 DP_INFO(edev, " Driver version : %s\n", drv_ver);
378 DP_INFO(edev, " Firmware version : %s\n", ver_str);
380 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
382 (info->mfw_rev >> 24) & 0xff,
383 (info->mfw_rev >> 16) & 0xff,
384 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
385 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
386 DP_INFO(edev, " Firmware file : %s\n", fw_file);
387 DP_INFO(edev, "*********************************\n");
390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
393 unsigned int i = 0, j = 0, qid;
394 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
395 struct qede_tx_queue *txq;
397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
400 RTE_ETHDEV_QUEUE_STAT_CNTRS);
401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
402 RTE_ETHDEV_QUEUE_STAT_CNTRS);
405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
406 offsetof(struct qede_rx_queue, rcv_pkts), 0,
408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
409 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
417 OSAL_MEMSET((((char *)
418 (qdev->fp_array[qid].rxq)) +
419 qede_rxq_xstats_strings[j].offset),
424 if (i == rxq_stat_cntrs)
431 txq = qdev->fp_array[qid].txq;
433 OSAL_MEMSET((uint64_t *)(uintptr_t)
434 (((uint64_t)(uintptr_t)(txq)) +
435 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
439 if (i == txq_stat_cntrs)
445 qede_stop_vport(struct ecore_dev *edev)
447 struct ecore_hwfn *p_hwfn;
453 for_each_hwfn(edev, i) {
454 p_hwfn = &edev->hwfns[i];
455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
457 if (rc != ECORE_SUCCESS) {
458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
463 DP_INFO(edev, "vport stopped\n");
469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
472 struct ecore_sp_vport_start_params params;
473 struct ecore_hwfn *p_hwfn;
477 if (qdev->vport_started)
478 qede_stop_vport(edev);
480 memset(¶ms, 0, sizeof(params));
483 /* @DPDK - Disable FW placement */
484 params.zero_placement_offset = 1;
485 for_each_hwfn(edev, i) {
486 p_hwfn = &edev->hwfns[i];
487 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
488 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
489 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
490 if (rc != ECORE_SUCCESS) {
491 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
495 ecore_reset_vport_stats(edev);
496 qdev->vport_started = true;
497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
502 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
503 #define QEDE_VF_TX_SWITCHING "vf_tx_switching"
505 /* Activate or deactivate vport via vport-update */
506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
508 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
509 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
510 struct ecore_sp_vport_update_params params;
511 struct ecore_hwfn *p_hwfn;
515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
517 params.update_vport_active_rx_flg = 1;
518 params.update_vport_active_tx_flg = 1;
519 params.vport_active_rx_flg = flg;
520 params.vport_active_tx_flg = flg;
521 if (!qdev->enable_tx_switching) {
522 if ((QEDE_NPAR_TX_SWITCHING != NULL) ||
523 ((QEDE_VF_TX_SWITCHING != NULL) && IS_VF(edev))) {
524 params.update_tx_switching_flg = 1;
525 params.tx_switching_flg = !flg;
526 DP_INFO(edev, "%s tx-switching is disabled\n",
527 QEDE_NPAR_TX_SWITCHING ? "NPAR" : "VF");
530 for_each_hwfn(edev, i) {
531 p_hwfn = &edev->hwfns[i];
532 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
533 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
534 ECORE_SPQ_MODE_EBLOCK, NULL);
535 if (rc != ECORE_SUCCESS) {
536 DP_ERR(edev, "Failed to update vport\n");
540 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
546 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
547 uint16_t mtu, bool enable)
549 /* Enable LRO in split mode */
550 sge_tpa_params->tpa_ipv4_en_flg = enable;
551 sge_tpa_params->tpa_ipv6_en_flg = enable;
552 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
553 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
554 /* set if tpa enable changes */
555 sge_tpa_params->update_tpa_en_flg = 1;
556 /* set if tpa parameters should be handled */
557 sge_tpa_params->update_tpa_param_flg = enable;
559 sge_tpa_params->max_buffers_per_cqe = 20;
560 /* Enable TPA in split mode. In this mode each TPA segment
561 * starts on the new BD, so there is one BD per segment.
563 sge_tpa_params->tpa_pkt_split_flg = 1;
564 sge_tpa_params->tpa_hdr_data_split_flg = 0;
565 sge_tpa_params->tpa_gro_consistent_flg = 0;
566 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
567 sge_tpa_params->tpa_max_size = 0x7FFF;
568 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
569 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
572 /* Enable/disable LRO via vport-update */
573 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
575 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
576 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
577 struct ecore_sp_vport_update_params params;
578 struct ecore_sge_tpa_params tpa_params;
579 struct ecore_hwfn *p_hwfn;
583 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
584 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
585 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
587 params.sge_tpa_params = &tpa_params;
588 for_each_hwfn(edev, i) {
589 p_hwfn = &edev->hwfns[i];
590 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
591 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
592 ECORE_SPQ_MODE_EBLOCK, NULL);
593 if (rc != ECORE_SUCCESS) {
594 DP_ERR(edev, "Failed to update LRO\n");
598 qdev->enable_lro = flg;
599 eth_dev->data->lro = flg;
601 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
606 /* Update MTU via vport-update without doing port restart.
607 * The vport must be deactivated before calling this API.
609 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
611 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
612 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
613 struct ecore_sp_vport_update_params params;
614 struct ecore_hwfn *p_hwfn;
618 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
622 for_each_hwfn(edev, i) {
623 p_hwfn = &edev->hwfns[i];
624 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
625 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
626 ECORE_SPQ_MODE_EBLOCK, NULL);
627 if (rc != ECORE_SUCCESS) {
628 DP_ERR(edev, "Failed to update MTU\n");
632 DP_INFO(edev, "MTU updated to %u\n", mtu);
637 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
639 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
640 ucast->is_rx_filter = true;
641 ucast->is_tx_filter = true;
642 /* ucast->assert_on_error = true; - For debug */
646 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
647 enum qed_filter_rx_mode_type type)
649 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
650 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
651 struct ecore_filter_accept_flags flags;
653 memset(&flags, 0, sizeof(flags));
655 flags.update_rx_mode_config = 1;
656 flags.update_tx_mode_config = 1;
657 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
658 ECORE_ACCEPT_MCAST_MATCHED |
661 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
662 ECORE_ACCEPT_MCAST_MATCHED |
665 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
666 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
668 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
669 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
671 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
672 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
673 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
674 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
675 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
676 ECORE_ACCEPT_MCAST_UNMATCHED;
679 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
680 ECORE_SPQ_MODE_CB, NULL);
684 qede_tunnel_update(struct qede_dev *qdev,
685 struct ecore_tunnel_info *tunn_info)
687 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
688 enum _ecore_status_t rc = ECORE_INVAL;
689 struct ecore_hwfn *p_hwfn;
690 struct ecore_ptt *p_ptt;
693 for_each_hwfn(edev, i) {
694 p_hwfn = &edev->hwfns[i];
696 p_ptt = ecore_ptt_acquire(p_hwfn);
698 DP_ERR(p_hwfn, "Can't acquire PTT\n");
705 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
706 tunn_info, ECORE_SPQ_MODE_CB, NULL);
708 ecore_ptt_release(p_hwfn, p_ptt);
710 if (rc != ECORE_SUCCESS)
718 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
721 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
722 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
723 enum _ecore_status_t rc = ECORE_INVAL;
724 struct ecore_tunnel_info tunn;
726 if (qdev->vxlan.enable == enable)
727 return ECORE_SUCCESS;
729 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
730 tunn.vxlan.b_update_mode = true;
731 tunn.vxlan.b_mode_enabled = enable;
732 tunn.b_update_rx_cls = true;
733 tunn.b_update_tx_cls = true;
734 tunn.vxlan.tun_cls = clss;
736 tunn.vxlan_port.b_update_port = true;
737 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
739 rc = qede_tunnel_update(qdev, &tunn);
740 if (rc == ECORE_SUCCESS) {
741 qdev->vxlan.enable = enable;
742 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
743 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
744 enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
746 DP_ERR(edev, "Failed to update tunn_clss %u\n",
754 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
757 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
758 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
759 enum _ecore_status_t rc = ECORE_INVAL;
760 struct ecore_tunnel_info tunn;
762 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
763 tunn.l2_geneve.b_update_mode = true;
764 tunn.l2_geneve.b_mode_enabled = enable;
765 tunn.ip_geneve.b_update_mode = true;
766 tunn.ip_geneve.b_mode_enabled = enable;
767 tunn.l2_geneve.tun_cls = clss;
768 tunn.ip_geneve.tun_cls = clss;
769 tunn.b_update_rx_cls = true;
770 tunn.b_update_tx_cls = true;
772 tunn.geneve_port.b_update_port = true;
773 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
775 rc = qede_tunnel_update(qdev, &tunn);
776 if (rc == ECORE_SUCCESS) {
777 qdev->geneve.enable = enable;
778 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
779 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
780 enable ? "enabled" : "disabled", qdev->geneve.udp_port);
782 DP_ERR(edev, "Failed to update tunn_clss %u\n",
790 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
793 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
794 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
795 enum _ecore_status_t rc = ECORE_INVAL;
796 struct ecore_tunnel_info tunn;
798 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
799 tunn.ip_gre.b_update_mode = true;
800 tunn.ip_gre.b_mode_enabled = enable;
801 tunn.ip_gre.tun_cls = clss;
802 tunn.ip_gre.tun_cls = clss;
803 tunn.b_update_rx_cls = true;
804 tunn.b_update_tx_cls = true;
806 rc = qede_tunnel_update(qdev, &tunn);
807 if (rc == ECORE_SUCCESS) {
808 qdev->ipgre.enable = enable;
809 DP_INFO(edev, "IPGRE is %s\n",
810 enable ? "enabled" : "disabled");
812 DP_ERR(edev, "Failed to update tunn_clss %u\n",
820 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
821 enum rte_eth_tunnel_type tunn_type, bool enable)
826 case RTE_TUNNEL_TYPE_VXLAN:
827 rc = qede_vxlan_enable(eth_dev, clss, enable);
829 case RTE_TUNNEL_TYPE_GENEVE:
830 rc = qede_geneve_enable(eth_dev, clss, enable);
832 case RTE_TUNNEL_TYPE_IP_IN_GRE:
833 rc = qede_ipgre_enable(eth_dev, clss, enable);
844 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
847 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
848 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
849 struct qede_ucast_entry *tmp = NULL;
850 struct qede_ucast_entry *u;
851 struct ether_addr *mac_addr;
853 mac_addr = (struct ether_addr *)ucast->mac;
855 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
856 if ((memcmp(mac_addr, &tmp->mac,
857 ETHER_ADDR_LEN) == 0) &&
858 ucast->vni == tmp->vni &&
859 ucast->vlan == tmp->vlan) {
860 DP_ERR(edev, "Unicast MAC is already added"
861 " with vlan = %u, vni = %u\n",
862 ucast->vlan, ucast->vni);
866 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
867 RTE_CACHE_LINE_SIZE);
869 DP_ERR(edev, "Did not allocate memory for ucast\n");
872 ether_addr_copy(mac_addr, &u->mac);
873 u->vlan = ucast->vlan;
875 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
878 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
879 if ((memcmp(mac_addr, &tmp->mac,
880 ETHER_ADDR_LEN) == 0) &&
881 ucast->vlan == tmp->vlan &&
882 ucast->vni == tmp->vni)
886 DP_INFO(edev, "Unicast MAC is not found\n");
889 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
897 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
900 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
901 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
902 struct ether_addr *mac_addr;
903 struct qede_mcast_entry *tmp = NULL;
904 struct qede_mcast_entry *m;
906 mac_addr = (struct ether_addr *)mcast->mac;
908 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
909 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
911 "Multicast MAC is already added\n");
915 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
916 RTE_CACHE_LINE_SIZE);
919 "Did not allocate memory for mcast\n");
922 ether_addr_copy(mac_addr, &m->mac);
923 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
926 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
927 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
931 DP_INFO(edev, "Multicast mac is not found\n");
934 SLIST_REMOVE(&qdev->mc_list_head, tmp,
935 qede_mcast_entry, list);
942 static enum _ecore_status_t
943 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
946 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
947 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
948 enum _ecore_status_t rc;
949 struct ecore_filter_mcast mcast;
950 struct qede_mcast_entry *tmp;
954 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
956 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
958 "Mcast filter table limit exceeded, "
959 "Please enable mcast promisc mode\n");
963 rc = qede_mcast_filter(eth_dev, ucast, add);
965 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
966 memset(&mcast, 0, sizeof(mcast));
967 mcast.num_mc_addrs = qdev->num_mc_addr;
968 mcast.opcode = ECORE_FILTER_ADD;
969 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
970 ether_addr_copy(&tmp->mac,
971 (struct ether_addr *)&mcast.mac[j]);
974 rc = ecore_filter_mcast_cmd(edev, &mcast,
975 ECORE_SPQ_MODE_CB, NULL);
977 if (rc != ECORE_SUCCESS) {
978 DP_ERR(edev, "Failed to add multicast filter"
979 " rc = %d, op = %d\n", rc, add);
981 } else { /* Unicast */
983 if (qdev->num_uc_addr >=
984 qdev->dev_info.num_mac_filters) {
986 "Ucast filter table limit exceeded,"
987 " Please enable promisc mode\n");
991 rc = qede_ucast_filter(eth_dev, ucast, add);
993 rc = ecore_filter_ucast_cmd(edev, ucast,
994 ECORE_SPQ_MODE_CB, NULL);
995 if (rc != ECORE_SUCCESS) {
996 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
1005 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
1006 __rte_unused uint32_t index, __rte_unused uint32_t pool)
1008 struct ecore_filter_ucast ucast;
1011 qede_set_ucast_cmn_params(&ucast);
1012 ucast.type = ECORE_FILTER_MAC;
1013 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
1014 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
1019 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
1021 struct qede_dev *qdev = eth_dev->data->dev_private;
1022 struct ecore_dev *edev = &qdev->edev;
1023 struct ecore_filter_ucast ucast;
1025 PMD_INIT_FUNC_TRACE(edev);
1027 if (index >= qdev->dev_info.num_mac_filters) {
1028 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1029 index, qdev->dev_info.num_mac_filters);
1033 qede_set_ucast_cmn_params(&ucast);
1034 ucast.opcode = ECORE_FILTER_REMOVE;
1035 ucast.type = ECORE_FILTER_MAC;
1037 /* Use the index maintained by rte */
1038 ether_addr_copy(ð_dev->data->mac_addrs[index],
1039 (struct ether_addr *)&ucast.mac);
1041 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
1045 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1047 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1048 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1050 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1051 mac_addr->addr_bytes)) {
1052 DP_ERR(edev, "Setting MAC address is not allowed\n");
1053 ether_addr_copy(&qdev->primary_mac,
1054 ð_dev->data->mac_addrs[0]);
1058 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1061 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1063 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1064 struct ecore_sp_vport_update_params params;
1065 struct ecore_hwfn *p_hwfn;
1069 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1070 params.vport_id = 0;
1071 params.update_accept_any_vlan_flg = 1;
1072 params.accept_any_vlan = flg;
1073 for_each_hwfn(edev, i) {
1074 p_hwfn = &edev->hwfns[i];
1075 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1076 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1077 ECORE_SPQ_MODE_EBLOCK, NULL);
1078 if (rc != ECORE_SUCCESS) {
1079 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1084 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1087 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1089 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1090 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1091 struct ecore_sp_vport_update_params params;
1092 struct ecore_hwfn *p_hwfn;
1096 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1097 params.vport_id = 0;
1098 params.update_inner_vlan_removal_flg = 1;
1099 params.inner_vlan_removal_flg = flg;
1100 for_each_hwfn(edev, i) {
1101 p_hwfn = &edev->hwfns[i];
1102 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1103 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1104 ECORE_SPQ_MODE_EBLOCK, NULL);
1105 if (rc != ECORE_SUCCESS) {
1106 DP_ERR(edev, "Failed to update vport\n");
1111 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1115 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1116 uint16_t vlan_id, int on)
1118 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1119 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1120 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1121 struct qede_vlan_entry *tmp = NULL;
1122 struct qede_vlan_entry *vlan;
1123 struct ecore_filter_ucast ucast;
1127 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1128 DP_ERR(edev, "Reached max VLAN filter limit"
1129 " enabling accept_any_vlan\n");
1130 qede_config_accept_any_vlan(qdev, true);
1134 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1135 if (tmp->vid == vlan_id) {
1136 DP_ERR(edev, "VLAN %u already configured\n",
1142 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1143 RTE_CACHE_LINE_SIZE);
1146 DP_ERR(edev, "Did not allocate memory for VLAN\n");
1150 qede_set_ucast_cmn_params(&ucast);
1151 ucast.opcode = ECORE_FILTER_ADD;
1152 ucast.type = ECORE_FILTER_VLAN;
1153 ucast.vlan = vlan_id;
1154 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1157 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1161 vlan->vid = vlan_id;
1162 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1163 qdev->configured_vlans++;
1164 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1165 vlan_id, qdev->configured_vlans);
1168 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1169 if (tmp->vid == vlan_id)
1174 if (qdev->configured_vlans == 0) {
1176 "No VLAN filters configured yet\n");
1180 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1184 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1186 qede_set_ucast_cmn_params(&ucast);
1187 ucast.opcode = ECORE_FILTER_REMOVE;
1188 ucast.type = ECORE_FILTER_VLAN;
1189 ucast.vlan = vlan_id;
1190 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1193 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1196 qdev->configured_vlans--;
1197 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1198 vlan_id, qdev->configured_vlans);
1205 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1207 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1208 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1209 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1211 if (mask & ETH_VLAN_STRIP_MASK) {
1212 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1213 (void)qede_vlan_stripping(eth_dev, 1);
1215 (void)qede_vlan_stripping(eth_dev, 0);
1218 if (mask & ETH_VLAN_FILTER_MASK) {
1219 /* VLAN filtering kicks in when a VLAN is added */
1220 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1221 qede_vlan_filter_set(eth_dev, 0, 1);
1223 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1225 " Please remove existing VLAN filters"
1226 " before disabling VLAN filtering\n");
1227 /* Signal app that VLAN filtering is still
1230 eth_dev->data->dev_conf.rxmode.offloads |=
1231 DEV_RX_OFFLOAD_VLAN_FILTER;
1233 qede_vlan_filter_set(eth_dev, 0, 0);
1238 if (mask & ETH_VLAN_EXTEND_MASK)
1239 DP_ERR(edev, "Extend VLAN not supported\n");
1241 qdev->vlan_offload_mask = mask;
1243 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1248 static void qede_prandom_bytes(uint32_t *buff)
1252 srand((unsigned int)time(NULL));
1253 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1257 int qede_config_rss(struct rte_eth_dev *eth_dev)
1259 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1260 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1261 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1262 struct rte_eth_rss_reta_entry64 reta_conf[2];
1263 struct rte_eth_rss_conf rss_conf;
1264 uint32_t i, id, pos, q;
1266 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1267 if (!rss_conf.rss_key) {
1268 DP_INFO(edev, "Applying driver default key\n");
1269 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1270 qede_prandom_bytes(&def_rss_key[0]);
1271 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1274 /* Configure RSS hash */
1275 if (qede_rss_hash_update(eth_dev, &rss_conf))
1278 /* Configure default RETA */
1279 memset(reta_conf, 0, sizeof(reta_conf));
1280 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1281 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1283 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1284 id = i / RTE_RETA_GROUP_SIZE;
1285 pos = i % RTE_RETA_GROUP_SIZE;
1286 q = i % QEDE_RSS_COUNT(qdev);
1287 reta_conf[id].reta[pos] = q;
1289 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1290 ECORE_RSS_IND_TABLE_SIZE))
1296 static void qede_fastpath_start(struct ecore_dev *edev)
1298 struct ecore_hwfn *p_hwfn;
1301 for_each_hwfn(edev, i) {
1302 p_hwfn = &edev->hwfns[i];
1303 ecore_hw_start_fastpath(p_hwfn);
1307 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1309 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1310 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1311 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1313 PMD_INIT_FUNC_TRACE(edev);
1315 /* Configure TPA parameters */
1316 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1317 if (qede_enable_tpa(eth_dev, true))
1319 /* Enable scatter mode for LRO */
1320 if (!eth_dev->data->scattered_rx)
1321 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1325 if (qede_start_queues(eth_dev))
1329 qede_reset_queue_stats(qdev, true);
1331 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1332 * enabling RSS. Hence RSS configuration is deferred upto this point.
1333 * Also, we would like to retain similar behavior in PF case, so we
1334 * don't do PF/VF specific check here.
1336 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1337 if (qede_config_rss(eth_dev))
1341 if (qede_activate_vport(eth_dev, true))
1344 /* Update link status */
1345 qede_link_update(eth_dev, 0);
1347 /* Start/resume traffic */
1348 qede_fastpath_start(edev);
1350 DP_INFO(edev, "Device started\n");
1354 DP_ERR(edev, "Device start fails\n");
1355 return -1; /* common error code is < 0 */
1358 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1360 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1361 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1363 PMD_INIT_FUNC_TRACE(edev);
1366 if (qede_activate_vport(eth_dev, false))
1369 if (qdev->enable_lro)
1370 qede_enable_tpa(eth_dev, false);
1373 qede_stop_queues(eth_dev);
1375 /* Disable traffic */
1376 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1378 DP_INFO(edev, "Device is stopped\n");
1381 const char *valid_args[] = {
1382 QEDE_NPAR_TX_SWITCHING,
1383 QEDE_VF_TX_SWITCHING,
1387 static int qede_args_check(const char *key, const char *val, void *opaque)
1391 struct rte_eth_dev *eth_dev = opaque;
1392 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1393 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1396 tmp = strtoul(val, NULL, 0);
1398 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1402 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1403 (strcmp(QEDE_VF_TX_SWITCHING, key) == 0))
1404 qdev->enable_tx_switching = !!tmp;
1409 static int qede_args(struct rte_eth_dev *eth_dev)
1411 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1412 struct rte_kvargs *kvlist;
1413 struct rte_devargs *devargs;
1417 devargs = pci_dev->device.devargs;
1419 return 0; /* return success */
1421 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1425 /* Process parameters. */
1426 for (i = 0; (valid_args[i] != NULL); ++i) {
1427 if (rte_kvargs_count(kvlist, valid_args[i])) {
1428 ret = rte_kvargs_process(kvlist, valid_args[i],
1429 qede_args_check, eth_dev);
1430 if (ret != ECORE_SUCCESS) {
1431 rte_kvargs_free(kvlist);
1436 rte_kvargs_free(kvlist);
1441 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1443 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1444 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1445 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1448 PMD_INIT_FUNC_TRACE(edev);
1450 /* Check requirements for 100G mode */
1451 if (ECORE_IS_CMT(edev)) {
1452 if (eth_dev->data->nb_rx_queues < 2 ||
1453 eth_dev->data->nb_tx_queues < 2) {
1454 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1458 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1459 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1461 "100G mode needs even no. of RX/TX queues\n");
1466 /* We need to have min 1 RX queue.There is no min check in
1467 * rte_eth_dev_configure(), so we are checking it here.
1469 if (eth_dev->data->nb_rx_queues == 0) {
1470 DP_ERR(edev, "Minimum one RX queue is required\n");
1474 /* Enable Tx switching by default */
1475 qdev->enable_tx_switching = 1;
1477 /* Parse devargs and fix up rxmode */
1478 if (qede_args(eth_dev))
1481 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1482 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1483 DP_ERR(edev, "Unsupported multi-queue mode\n");
1486 /* Flow director mode check */
1487 if (qede_check_fdir_support(eth_dev))
1490 qede_dealloc_fp_resc(eth_dev);
1491 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1492 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1493 if (qede_alloc_fp_resc(qdev))
1496 /* If jumbo enabled adjust MTU */
1497 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1498 eth_dev->data->mtu =
1499 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1500 ETHER_HDR_LEN - ETHER_CRC_LEN;
1502 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1503 eth_dev->data->scattered_rx = 1;
1505 if (qede_start_vport(qdev, eth_dev->data->mtu))
1508 qdev->mtu = eth_dev->data->mtu;
1510 /* Enable VLAN offloads by default */
1511 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1512 ETH_VLAN_FILTER_MASK |
1513 ETH_VLAN_EXTEND_MASK);
1517 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1518 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1523 /* Info about HW descriptor ring limitations */
1524 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1525 .nb_max = 0x8000, /* 32K */
1527 .nb_align = 128 /* lowest common multiple */
1530 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1531 .nb_max = 0x8000, /* 32K */
1534 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1535 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1539 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1540 struct rte_eth_dev_info *dev_info)
1542 struct qede_dev *qdev = eth_dev->data->dev_private;
1543 struct ecore_dev *edev = &qdev->edev;
1544 struct qed_link_output link;
1545 uint32_t speed_cap = 0;
1547 PMD_INIT_FUNC_TRACE(edev);
1549 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1550 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1551 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1552 dev_info->rx_desc_lim = qede_rx_desc_lim;
1553 dev_info->tx_desc_lim = qede_tx_desc_lim;
1556 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1557 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1559 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1560 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1561 dev_info->max_tx_queues = dev_info->max_rx_queues;
1563 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1564 dev_info->max_vfs = 0;
1565 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1566 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1567 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1568 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1569 DEV_RX_OFFLOAD_UDP_CKSUM |
1570 DEV_RX_OFFLOAD_TCP_CKSUM |
1571 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1572 DEV_RX_OFFLOAD_TCP_LRO |
1573 DEV_RX_OFFLOAD_CRC_STRIP |
1574 DEV_RX_OFFLOAD_SCATTER |
1575 DEV_RX_OFFLOAD_JUMBO_FRAME |
1576 DEV_RX_OFFLOAD_VLAN_FILTER |
1577 DEV_RX_OFFLOAD_VLAN_STRIP);
1578 dev_info->rx_queue_offload_capa = 0;
1580 /* TX offloads are on a per-packet basis, so it is applicable
1581 * to both at port and queue levels.
1583 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1584 DEV_TX_OFFLOAD_IPV4_CKSUM |
1585 DEV_TX_OFFLOAD_UDP_CKSUM |
1586 DEV_TX_OFFLOAD_TCP_CKSUM |
1587 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1588 DEV_TX_OFFLOAD_QINQ_INSERT |
1589 DEV_TX_OFFLOAD_MULTI_SEGS |
1590 DEV_TX_OFFLOAD_TCP_TSO |
1591 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1592 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1593 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1595 dev_info->default_txconf = (struct rte_eth_txconf) {
1596 .txq_flags = DEV_TX_OFFLOAD_MULTI_SEGS,
1599 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1600 /* Packets are always dropped if no descriptors are available */
1602 /* The below RX offloads are always enabled */
1603 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP |
1604 DEV_RX_OFFLOAD_IPV4_CKSUM |
1605 DEV_RX_OFFLOAD_TCP_CKSUM |
1606 DEV_RX_OFFLOAD_UDP_CKSUM),
1609 memset(&link, 0, sizeof(struct qed_link_output));
1610 qdev->ops->common->get_link(edev, &link);
1611 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1612 speed_cap |= ETH_LINK_SPEED_1G;
1613 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1614 speed_cap |= ETH_LINK_SPEED_10G;
1615 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1616 speed_cap |= ETH_LINK_SPEED_25G;
1617 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1618 speed_cap |= ETH_LINK_SPEED_40G;
1619 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1620 speed_cap |= ETH_LINK_SPEED_50G;
1621 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1622 speed_cap |= ETH_LINK_SPEED_100G;
1623 dev_info->speed_capa = speed_cap;
1626 /* return 0 means link status changed, -1 means not changed */
1628 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1630 struct qede_dev *qdev = eth_dev->data->dev_private;
1631 struct ecore_dev *edev = &qdev->edev;
1632 uint16_t link_duplex;
1633 struct qed_link_output link;
1634 struct rte_eth_link *curr = ð_dev->data->dev_link;
1636 memset(&link, 0, sizeof(struct qed_link_output));
1637 qdev->ops->common->get_link(edev, &link);
1640 curr->link_speed = link.speed;
1643 switch (link.duplex) {
1644 case QEDE_DUPLEX_HALF:
1645 link_duplex = ETH_LINK_HALF_DUPLEX;
1647 case QEDE_DUPLEX_FULL:
1648 link_duplex = ETH_LINK_FULL_DUPLEX;
1650 case QEDE_DUPLEX_UNKNOWN:
1654 curr->link_duplex = link_duplex;
1657 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1660 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1661 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1663 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1664 curr->link_speed, curr->link_duplex,
1665 curr->link_autoneg, curr->link_status);
1667 /* return 0 means link status changed, -1 means not changed */
1668 return ((curr->link_status == link.link_up) ? -1 : 0);
1671 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1673 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1674 struct qede_dev *qdev = eth_dev->data->dev_private;
1675 struct ecore_dev *edev = &qdev->edev;
1677 PMD_INIT_FUNC_TRACE(edev);
1680 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1682 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1683 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1685 qed_configure_filter_rx_mode(eth_dev, type);
1688 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1690 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1691 struct qede_dev *qdev = eth_dev->data->dev_private;
1692 struct ecore_dev *edev = &qdev->edev;
1694 PMD_INIT_FUNC_TRACE(edev);
1697 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1698 qed_configure_filter_rx_mode(eth_dev,
1699 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1701 qed_configure_filter_rx_mode(eth_dev,
1702 QED_FILTER_RX_MODE_TYPE_REGULAR);
1705 static void qede_poll_sp_sb_cb(void *param)
1707 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1708 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1709 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1712 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1713 qede_interrupt_action(&edev->hwfns[1]);
1715 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1719 DP_ERR(edev, "Unable to start periodic"
1720 " timer rc %d\n", rc);
1721 assert(false && "Unable to start periodic timer");
1725 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1727 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1728 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1729 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1731 PMD_INIT_FUNC_TRACE(edev);
1733 /* dev_stop() shall cleanup fp resources in hw but without releasing
1734 * dma memories and sw structures so that dev_start() can be called
1735 * by the app without reconfiguration. However, in dev_close() we
1736 * can release all the resources and device can be brought up newly
1738 if (eth_dev->data->dev_started)
1739 qede_dev_stop(eth_dev);
1741 qede_stop_vport(edev);
1742 qdev->vport_started = false;
1743 qede_fdir_dealloc_resc(eth_dev);
1744 qede_dealloc_fp_resc(eth_dev);
1746 eth_dev->data->nb_rx_queues = 0;
1747 eth_dev->data->nb_tx_queues = 0;
1749 /* Bring the link down */
1750 qede_dev_set_link_state(eth_dev, false);
1751 qdev->ops->common->slowpath_stop(edev);
1752 qdev->ops->common->remove(edev);
1753 rte_intr_disable(&pci_dev->intr_handle);
1754 rte_intr_callback_unregister(&pci_dev->intr_handle,
1755 qede_interrupt_handler, (void *)eth_dev);
1756 if (ECORE_IS_CMT(edev))
1757 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1761 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1763 struct qede_dev *qdev = eth_dev->data->dev_private;
1764 struct ecore_dev *edev = &qdev->edev;
1765 struct ecore_eth_stats stats;
1766 unsigned int i = 0, j = 0, qid;
1767 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1768 struct qede_tx_queue *txq;
1770 ecore_get_vport_stats(edev, &stats);
1773 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1774 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1776 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1777 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1779 eth_stats->ierrors = stats.common.rx_crc_errors +
1780 stats.common.rx_align_errors +
1781 stats.common.rx_carrier_errors +
1782 stats.common.rx_oversize_packets +
1783 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1785 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1787 eth_stats->imissed = stats.common.mftag_filter_discards +
1788 stats.common.mac_filter_discards +
1789 stats.common.no_buff_discards +
1790 stats.common.brb_truncates + stats.common.brb_discards;
1793 eth_stats->opackets = stats.common.tx_ucast_pkts +
1794 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1796 eth_stats->obytes = stats.common.tx_ucast_bytes +
1797 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1799 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1802 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1803 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1804 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1805 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1806 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1807 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1808 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1809 "Not all the queue stats will be displayed. Set"
1810 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1811 " appropriately and retry.\n");
1814 eth_stats->q_ipackets[i] =
1816 ((char *)(qdev->fp_array[qid].rxq)) +
1817 offsetof(struct qede_rx_queue,
1819 eth_stats->q_errors[i] =
1821 ((char *)(qdev->fp_array[qid].rxq)) +
1822 offsetof(struct qede_rx_queue,
1825 ((char *)(qdev->fp_array[qid].rxq)) +
1826 offsetof(struct qede_rx_queue,
1829 if (i == rxq_stat_cntrs)
1834 txq = qdev->fp_array[qid].txq;
1835 eth_stats->q_opackets[j] =
1836 *((uint64_t *)(uintptr_t)
1837 (((uint64_t)(uintptr_t)(txq)) +
1838 offsetof(struct qede_tx_queue,
1841 if (j == txq_stat_cntrs)
1849 qede_get_xstats_count(struct qede_dev *qdev) {
1850 if (ECORE_IS_BB(&qdev->edev))
1851 return RTE_DIM(qede_xstats_strings) +
1852 RTE_DIM(qede_bb_xstats_strings) +
1853 (RTE_DIM(qede_rxq_xstats_strings) *
1854 RTE_MIN(QEDE_RSS_COUNT(qdev),
1855 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1857 return RTE_DIM(qede_xstats_strings) +
1858 RTE_DIM(qede_ah_xstats_strings) +
1859 (RTE_DIM(qede_rxq_xstats_strings) *
1860 RTE_MIN(QEDE_RSS_COUNT(qdev),
1861 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1865 qede_get_xstats_names(struct rte_eth_dev *dev,
1866 struct rte_eth_xstat_name *xstats_names,
1867 __rte_unused unsigned int limit)
1869 struct qede_dev *qdev = dev->data->dev_private;
1870 struct ecore_dev *edev = &qdev->edev;
1871 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1872 unsigned int i, qid, stat_idx = 0;
1873 unsigned int rxq_stat_cntrs;
1875 if (xstats_names != NULL) {
1876 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1877 snprintf(xstats_names[stat_idx].name,
1878 sizeof(xstats_names[stat_idx].name),
1880 qede_xstats_strings[i].name);
1884 if (ECORE_IS_BB(edev)) {
1885 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1886 snprintf(xstats_names[stat_idx].name,
1887 sizeof(xstats_names[stat_idx].name),
1889 qede_bb_xstats_strings[i].name);
1893 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1894 snprintf(xstats_names[stat_idx].name,
1895 sizeof(xstats_names[stat_idx].name),
1897 qede_ah_xstats_strings[i].name);
1902 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1903 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1904 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1905 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1906 snprintf(xstats_names[stat_idx].name,
1907 sizeof(xstats_names[stat_idx].name),
1909 qede_rxq_xstats_strings[i].name, qid,
1910 qede_rxq_xstats_strings[i].name + 4);
1920 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1923 struct qede_dev *qdev = dev->data->dev_private;
1924 struct ecore_dev *edev = &qdev->edev;
1925 struct ecore_eth_stats stats;
1926 const unsigned int num = qede_get_xstats_count(qdev);
1927 unsigned int i, qid, stat_idx = 0;
1928 unsigned int rxq_stat_cntrs;
1933 ecore_get_vport_stats(edev, &stats);
1935 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1936 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1937 qede_xstats_strings[i].offset);
1938 xstats[stat_idx].id = stat_idx;
1942 if (ECORE_IS_BB(edev)) {
1943 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1944 xstats[stat_idx].value =
1945 *(uint64_t *)(((char *)&stats) +
1946 qede_bb_xstats_strings[i].offset);
1947 xstats[stat_idx].id = stat_idx;
1951 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1952 xstats[stat_idx].value =
1953 *(uint64_t *)(((char *)&stats) +
1954 qede_ah_xstats_strings[i].offset);
1955 xstats[stat_idx].id = stat_idx;
1960 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1961 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1962 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1964 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1965 xstats[stat_idx].value = *(uint64_t *)(
1966 ((char *)(qdev->fp_array[qid].rxq)) +
1967 qede_rxq_xstats_strings[i].offset);
1968 xstats[stat_idx].id = stat_idx;
1978 qede_reset_xstats(struct rte_eth_dev *dev)
1980 struct qede_dev *qdev = dev->data->dev_private;
1981 struct ecore_dev *edev = &qdev->edev;
1983 ecore_reset_vport_stats(edev);
1984 qede_reset_queue_stats(qdev, true);
1987 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1989 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1990 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1991 struct qed_link_params link_params;
1994 DP_INFO(edev, "setting link state %d\n", link_up);
1995 memset(&link_params, 0, sizeof(link_params));
1996 link_params.link_up = link_up;
1997 rc = qdev->ops->common->set_link(edev, &link_params);
1998 if (rc != ECORE_SUCCESS)
1999 DP_ERR(edev, "Unable to set link state %d\n", link_up);
2004 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
2006 return qede_dev_set_link_state(eth_dev, true);
2009 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
2011 return qede_dev_set_link_state(eth_dev, false);
2014 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2016 struct qede_dev *qdev = eth_dev->data->dev_private;
2017 struct ecore_dev *edev = &qdev->edev;
2019 ecore_reset_vport_stats(edev);
2020 qede_reset_queue_stats(qdev, false);
2023 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2025 enum qed_filter_rx_mode_type type =
2026 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2028 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2029 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2031 qed_configure_filter_rx_mode(eth_dev, type);
2034 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2036 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2037 qed_configure_filter_rx_mode(eth_dev,
2038 QED_FILTER_RX_MODE_TYPE_PROMISC);
2040 qed_configure_filter_rx_mode(eth_dev,
2041 QED_FILTER_RX_MODE_TYPE_REGULAR);
2044 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2045 struct rte_eth_fc_conf *fc_conf)
2047 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2048 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2049 struct qed_link_output current_link;
2050 struct qed_link_params params;
2052 memset(¤t_link, 0, sizeof(current_link));
2053 qdev->ops->common->get_link(edev, ¤t_link);
2055 memset(¶ms, 0, sizeof(params));
2056 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2057 if (fc_conf->autoneg) {
2058 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2059 DP_ERR(edev, "Autoneg not supported\n");
2062 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2065 /* Pause is assumed to be supported (SUPPORTED_Pause) */
2066 if (fc_conf->mode == RTE_FC_FULL)
2067 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2068 QED_LINK_PAUSE_RX_ENABLE);
2069 if (fc_conf->mode == RTE_FC_TX_PAUSE)
2070 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2071 if (fc_conf->mode == RTE_FC_RX_PAUSE)
2072 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2074 params.link_up = true;
2075 (void)qdev->ops->common->set_link(edev, ¶ms);
2080 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2081 struct rte_eth_fc_conf *fc_conf)
2083 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2084 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2085 struct qed_link_output current_link;
2087 memset(¤t_link, 0, sizeof(current_link));
2088 qdev->ops->common->get_link(edev, ¤t_link);
2090 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2091 fc_conf->autoneg = true;
2093 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2094 QED_LINK_PAUSE_TX_ENABLE))
2095 fc_conf->mode = RTE_FC_FULL;
2096 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2097 fc_conf->mode = RTE_FC_RX_PAUSE;
2098 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2099 fc_conf->mode = RTE_FC_TX_PAUSE;
2101 fc_conf->mode = RTE_FC_NONE;
2106 static const uint32_t *
2107 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2109 static const uint32_t ptypes[] = {
2111 RTE_PTYPE_L2_ETHER_VLAN,
2116 RTE_PTYPE_TUNNEL_VXLAN,
2118 RTE_PTYPE_TUNNEL_GENEVE,
2119 RTE_PTYPE_TUNNEL_GRE,
2121 RTE_PTYPE_INNER_L2_ETHER,
2122 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2123 RTE_PTYPE_INNER_L3_IPV4,
2124 RTE_PTYPE_INNER_L3_IPV6,
2125 RTE_PTYPE_INNER_L4_TCP,
2126 RTE_PTYPE_INNER_L4_UDP,
2127 RTE_PTYPE_INNER_L4_FRAG,
2131 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2137 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2140 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2141 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2142 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2143 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2144 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2145 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2146 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2147 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2150 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2151 struct rte_eth_rss_conf *rss_conf)
2153 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2154 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2155 struct ecore_sp_vport_update_params vport_update_params;
2156 struct ecore_rss_params rss_params;
2157 struct ecore_hwfn *p_hwfn;
2158 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2159 uint64_t hf = rss_conf->rss_hf;
2160 uint8_t len = rss_conf->rss_key_len;
2165 memset(&vport_update_params, 0, sizeof(vport_update_params));
2166 memset(&rss_params, 0, sizeof(rss_params));
2168 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2169 (unsigned long)hf, len, key);
2173 DP_INFO(edev, "Enabling rss\n");
2176 qede_init_rss_caps(&rss_params.rss_caps, hf);
2177 rss_params.update_rss_capabilities = 1;
2181 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2182 DP_ERR(edev, "RSS key length exceeds limit\n");
2185 DP_INFO(edev, "Applying user supplied hash key\n");
2186 rss_params.update_rss_key = 1;
2187 memcpy(&rss_params.rss_key, key, len);
2189 rss_params.rss_enable = 1;
2192 rss_params.update_rss_config = 1;
2193 /* tbl_size has to be set with capabilities */
2194 rss_params.rss_table_size_log = 7;
2195 vport_update_params.vport_id = 0;
2196 /* pass the L2 handles instead of qids */
2197 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2198 idx = qdev->rss_ind_table[i];
2199 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2201 vport_update_params.rss_params = &rss_params;
2203 for_each_hwfn(edev, i) {
2204 p_hwfn = &edev->hwfns[i];
2205 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2206 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2207 ECORE_SPQ_MODE_EBLOCK, NULL);
2209 DP_ERR(edev, "vport-update for RSS failed\n");
2213 qdev->rss_enable = rss_params.rss_enable;
2215 /* Update local structure for hash query */
2216 qdev->rss_conf.rss_hf = hf;
2217 qdev->rss_conf.rss_key_len = len;
2218 if (qdev->rss_enable) {
2219 if (qdev->rss_conf.rss_key == NULL) {
2220 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2221 if (qdev->rss_conf.rss_key == NULL) {
2222 DP_ERR(edev, "No memory to store RSS key\n");
2227 DP_INFO(edev, "Storing RSS key\n");
2228 memcpy(qdev->rss_conf.rss_key, key, len);
2230 } else if (!qdev->rss_enable && len == 0) {
2231 if (qdev->rss_conf.rss_key) {
2232 free(qdev->rss_conf.rss_key);
2233 qdev->rss_conf.rss_key = NULL;
2234 DP_INFO(edev, "Free RSS key\n");
2241 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2242 struct rte_eth_rss_conf *rss_conf)
2244 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2246 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2247 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2249 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2250 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2251 rss_conf->rss_key_len);
2255 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2256 struct ecore_rss_params *rss)
2259 bool rss_mode = 1; /* enable */
2260 struct ecore_queue_cid *cid;
2261 struct ecore_rss_params *t_rss;
2263 /* In regular scenario, we'd simply need to take input handlers.
2264 * But in CMT, we'd have to split the handlers according to the
2265 * engine they were configured on. We'd then have to understand
2266 * whether RSS is really required, since 2-queues on CMT doesn't
2270 /* CMT should be round-robin */
2271 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2272 cid = rss->rss_ind_table[i];
2274 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2279 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2283 t_rss->update_rss_ind_table = 1;
2284 t_rss->rss_table_size_log = 7;
2285 t_rss->update_rss_config = 1;
2287 /* Make sure RSS is actually required */
2288 for_each_hwfn(edev, fn) {
2289 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2291 if (rss[fn].rss_ind_table[i] !=
2292 rss[fn].rss_ind_table[0])
2296 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2298 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2305 t_rss->rss_enable = rss_mode;
2310 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2311 struct rte_eth_rss_reta_entry64 *reta_conf,
2314 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2315 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2316 struct ecore_sp_vport_update_params vport_update_params;
2317 struct ecore_rss_params *params;
2318 struct ecore_hwfn *p_hwfn;
2319 uint16_t i, idx, shift;
2323 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2324 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2329 memset(&vport_update_params, 0, sizeof(vport_update_params));
2330 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2331 RTE_CACHE_LINE_SIZE);
2332 if (params == NULL) {
2333 DP_ERR(edev, "failed to allocate memory\n");
2337 for (i = 0; i < reta_size; i++) {
2338 idx = i / RTE_RETA_GROUP_SIZE;
2339 shift = i % RTE_RETA_GROUP_SIZE;
2340 if (reta_conf[idx].mask & (1ULL << shift)) {
2341 entry = reta_conf[idx].reta[shift];
2342 /* Pass rxq handles to ecore */
2343 params->rss_ind_table[i] =
2344 qdev->fp_array[entry].rxq->handle;
2345 /* Update the local copy for RETA query command */
2346 qdev->rss_ind_table[i] = entry;
2350 params->update_rss_ind_table = 1;
2351 params->rss_table_size_log = 7;
2352 params->update_rss_config = 1;
2354 /* Fix up RETA for CMT mode device */
2355 if (ECORE_IS_CMT(edev))
2356 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2358 vport_update_params.vport_id = 0;
2359 /* Use the current value of rss_enable */
2360 params->rss_enable = qdev->rss_enable;
2361 vport_update_params.rss_params = params;
2363 for_each_hwfn(edev, i) {
2364 p_hwfn = &edev->hwfns[i];
2365 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2366 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2367 ECORE_SPQ_MODE_EBLOCK, NULL);
2369 DP_ERR(edev, "vport-update for RSS failed\n");
2379 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2380 struct rte_eth_rss_reta_entry64 *reta_conf,
2383 struct qede_dev *qdev = eth_dev->data->dev_private;
2384 struct ecore_dev *edev = &qdev->edev;
2385 uint16_t i, idx, shift;
2388 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2389 DP_ERR(edev, "reta_size %d is not supported\n",
2394 for (i = 0; i < reta_size; i++) {
2395 idx = i / RTE_RETA_GROUP_SIZE;
2396 shift = i % RTE_RETA_GROUP_SIZE;
2397 if (reta_conf[idx].mask & (1ULL << shift)) {
2398 entry = qdev->rss_ind_table[i];
2399 reta_conf[idx].reta[shift] = entry;
2408 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2410 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2411 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2412 struct rte_eth_dev_info dev_info = {0};
2413 struct qede_fastpath *fp;
2414 uint32_t max_rx_pkt_len;
2415 uint32_t frame_size;
2416 uint16_t rx_buf_size;
2418 bool restart = false;
2421 PMD_INIT_FUNC_TRACE(edev);
2422 qede_dev_info_get(dev, &dev_info);
2423 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2424 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2425 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2426 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2427 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2428 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2431 if (!dev->data->scattered_rx &&
2432 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2433 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2434 dev->data->min_rx_buf_size);
2437 /* Temporarily replace I/O functions with dummy ones. It cannot
2438 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2440 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2441 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2442 if (dev->data->dev_started) {
2443 dev->data->dev_started = 0;
2448 qede_start_vport(qdev, mtu); /* Recreate vport */
2451 /* Fix up RX buf size for all queues of the port */
2453 fp = &qdev->fp_array[i];
2454 if (fp->rxq != NULL) {
2455 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2456 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2457 if (dev->data->scattered_rx)
2458 rx_buf_size = bufsz + ETHER_HDR_LEN +
2459 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2461 rx_buf_size = frame_size;
2462 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2463 fp->rxq->rx_buf_size = rx_buf_size;
2464 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2467 if (max_rx_pkt_len > ETHER_MAX_LEN)
2468 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2470 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2472 /* Restore config lost due to vport stop */
2473 qede_mac_addr_set(dev, &qdev->primary_mac);
2474 if (dev->data->promiscuous)
2475 qede_promiscuous_enable(dev);
2477 qede_promiscuous_disable(dev);
2479 if (dev->data->all_multicast)
2480 qede_allmulticast_enable(dev);
2482 qede_allmulticast_disable(dev);
2484 qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2486 if (!dev->data->dev_started && restart) {
2487 qede_dev_start(dev);
2488 dev->data->dev_started = 1;
2491 /* update max frame size */
2492 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2494 dev->rx_pkt_burst = qede_recv_pkts;
2495 dev->tx_pkt_burst = qede_xmit_pkts;
2501 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2502 struct rte_eth_udp_tunnel *tunnel_udp)
2504 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2505 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2506 struct ecore_tunnel_info tunn; /* @DPDK */
2510 PMD_INIT_FUNC_TRACE(edev);
2512 memset(&tunn, 0, sizeof(tunn));
2514 switch (tunnel_udp->prot_type) {
2515 case RTE_TUNNEL_TYPE_VXLAN:
2516 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2517 DP_ERR(edev, "UDP port %u doesn't exist\n",
2518 tunnel_udp->udp_port);
2523 tunn.vxlan_port.b_update_port = true;
2524 tunn.vxlan_port.port = udp_port;
2526 rc = qede_tunnel_update(qdev, &tunn);
2527 if (rc != ECORE_SUCCESS) {
2528 DP_ERR(edev, "Unable to config UDP port %u\n",
2529 tunn.vxlan_port.port);
2533 qdev->vxlan.udp_port = udp_port;
2534 /* If the request is to delete UDP port and if the number of
2535 * VXLAN filters have reached 0 then VxLAN offload can be be
2538 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2539 return qede_vxlan_enable(eth_dev,
2540 ECORE_TUNN_CLSS_MAC_VLAN, false);
2543 case RTE_TUNNEL_TYPE_GENEVE:
2544 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2545 DP_ERR(edev, "UDP port %u doesn't exist\n",
2546 tunnel_udp->udp_port);
2552 tunn.geneve_port.b_update_port = true;
2553 tunn.geneve_port.port = udp_port;
2555 rc = qede_tunnel_update(qdev, &tunn);
2556 if (rc != ECORE_SUCCESS) {
2557 DP_ERR(edev, "Unable to config UDP port %u\n",
2558 tunn.vxlan_port.port);
2562 qdev->vxlan.udp_port = udp_port;
2563 /* If the request is to delete UDP port and if the number of
2564 * GENEVE filters have reached 0 then GENEVE offload can be be
2567 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2568 return qede_geneve_enable(eth_dev,
2569 ECORE_TUNN_CLSS_MAC_VLAN, false);
2581 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2582 struct rte_eth_udp_tunnel *tunnel_udp)
2584 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2585 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2586 struct ecore_tunnel_info tunn; /* @DPDK */
2590 PMD_INIT_FUNC_TRACE(edev);
2592 memset(&tunn, 0, sizeof(tunn));
2594 switch (tunnel_udp->prot_type) {
2595 case RTE_TUNNEL_TYPE_VXLAN:
2596 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2598 "UDP port %u for VXLAN was already configured\n",
2599 tunnel_udp->udp_port);
2600 return ECORE_SUCCESS;
2603 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2604 * it was not enabled while adding VXLAN filter before UDP port
2607 if (!qdev->vxlan.enable) {
2608 rc = qede_vxlan_enable(eth_dev,
2609 ECORE_TUNN_CLSS_MAC_VLAN, true);
2610 if (rc != ECORE_SUCCESS) {
2611 DP_ERR(edev, "Failed to enable VXLAN "
2612 "prior to updating UDP port\n");
2616 udp_port = tunnel_udp->udp_port;
2618 tunn.vxlan_port.b_update_port = true;
2619 tunn.vxlan_port.port = udp_port;
2621 rc = qede_tunnel_update(qdev, &tunn);
2622 if (rc != ECORE_SUCCESS) {
2623 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2628 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2630 qdev->vxlan.udp_port = udp_port;
2632 case RTE_TUNNEL_TYPE_GENEVE:
2633 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2635 "UDP port %u for GENEVE was already configured\n",
2636 tunnel_udp->udp_port);
2637 return ECORE_SUCCESS;
2640 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2641 * it was not enabled while adding GENEVE filter before UDP port
2644 if (!qdev->geneve.enable) {
2645 rc = qede_geneve_enable(eth_dev,
2646 ECORE_TUNN_CLSS_MAC_VLAN, true);
2647 if (rc != ECORE_SUCCESS) {
2648 DP_ERR(edev, "Failed to enable GENEVE "
2649 "prior to updating UDP port\n");
2653 udp_port = tunnel_udp->udp_port;
2655 tunn.geneve_port.b_update_port = true;
2656 tunn.geneve_port.port = udp_port;
2658 rc = qede_tunnel_update(qdev, &tunn);
2659 if (rc != ECORE_SUCCESS) {
2660 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2665 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2667 qdev->geneve.udp_port = udp_port;
2676 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2677 uint32_t *clss, char *str)
2680 *clss = MAX_ECORE_TUNN_CLSS;
2682 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2683 if (filter == qede_tunn_types[j].rte_filter_type) {
2684 *type = qede_tunn_types[j].qede_type;
2685 *clss = qede_tunn_types[j].qede_tunn_clss;
2686 strcpy(str, qede_tunn_types[j].string);
2693 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2694 const struct rte_eth_tunnel_filter_conf *conf,
2697 /* Init commmon ucast params first */
2698 qede_set_ucast_cmn_params(ucast);
2700 /* Copy out the required fields based on classification type */
2704 case ECORE_FILTER_VNI:
2705 ucast->vni = conf->tenant_id;
2707 case ECORE_FILTER_INNER_VLAN:
2708 ucast->vlan = conf->inner_vlan;
2710 case ECORE_FILTER_MAC:
2711 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2714 case ECORE_FILTER_INNER_MAC:
2715 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2718 case ECORE_FILTER_MAC_VNI_PAIR:
2719 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2721 ucast->vni = conf->tenant_id;
2723 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2724 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2726 ucast->vni = conf->tenant_id;
2728 case ECORE_FILTER_INNER_PAIR:
2729 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2731 ucast->vlan = conf->inner_vlan;
2737 return ECORE_SUCCESS;
2741 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2742 const struct rte_eth_tunnel_filter_conf *conf,
2743 __attribute__((unused)) enum rte_filter_op filter_op,
2744 enum ecore_tunn_clss *clss,
2747 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2748 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2749 struct ecore_filter_ucast ucast = {0};
2750 enum ecore_filter_ucast_type type;
2751 uint16_t filter_type = 0;
2755 filter_type = conf->filter_type;
2756 /* Determine if the given filter classification is supported */
2757 qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2758 if (*clss == MAX_ECORE_TUNN_CLSS) {
2759 DP_ERR(edev, "Unsupported filter type\n");
2762 /* Init tunnel ucast params */
2763 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2764 if (rc != ECORE_SUCCESS) {
2765 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2769 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2770 str, filter_op, ucast.type);
2772 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2774 /* Skip MAC/VLAN if filter is based on VNI */
2775 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2776 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2777 if ((rc == 0) && add) {
2778 /* Enable accept anyvlan */
2779 qede_config_accept_any_vlan(qdev, true);
2782 rc = qede_ucast_filter(eth_dev, &ucast, add);
2784 rc = ecore_filter_ucast_cmd(edev, &ucast,
2785 ECORE_SPQ_MODE_CB, NULL);
2792 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2793 enum rte_filter_op filter_op,
2794 const struct rte_eth_tunnel_filter_conf *conf)
2796 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2797 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2798 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2802 PMD_INIT_FUNC_TRACE(edev);
2804 switch (filter_op) {
2805 case RTE_ETH_FILTER_ADD:
2808 case RTE_ETH_FILTER_DELETE:
2812 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2817 return qede_tunn_enable(eth_dev,
2818 ECORE_TUNN_CLSS_MAC_VLAN,
2819 conf->tunnel_type, add);
2821 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2822 if (rc != ECORE_SUCCESS)
2826 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2827 qdev->vxlan.num_filters++;
2828 qdev->vxlan.filter_type = conf->filter_type;
2829 } else { /* GENEVE */
2830 qdev->geneve.num_filters++;
2831 qdev->geneve.filter_type = conf->filter_type;
2834 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2835 !qdev->ipgre.enable)
2836 return qede_tunn_enable(eth_dev, clss,
2840 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2841 qdev->vxlan.num_filters--;
2843 qdev->geneve.num_filters--;
2845 /* Disable VXLAN if VXLAN filters become 0 */
2846 if ((qdev->vxlan.num_filters == 0) ||
2847 (qdev->geneve.num_filters == 0))
2848 return qede_tunn_enable(eth_dev, clss,
2856 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2857 enum rte_filter_type filter_type,
2858 enum rte_filter_op filter_op,
2861 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2862 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2863 struct rte_eth_tunnel_filter_conf *filter_conf =
2864 (struct rte_eth_tunnel_filter_conf *)arg;
2866 switch (filter_type) {
2867 case RTE_ETH_FILTER_TUNNEL:
2868 switch (filter_conf->tunnel_type) {
2869 case RTE_TUNNEL_TYPE_VXLAN:
2870 case RTE_TUNNEL_TYPE_GENEVE:
2871 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2873 "Packet steering to the specified Rx queue"
2874 " is not supported with UDP tunneling");
2875 return(qede_tunn_filter_config(eth_dev, filter_op,
2877 case RTE_TUNNEL_TYPE_TEREDO:
2878 case RTE_TUNNEL_TYPE_NVGRE:
2879 case RTE_L2_TUNNEL_TYPE_E_TAG:
2880 DP_ERR(edev, "Unsupported tunnel type %d\n",
2881 filter_conf->tunnel_type);
2883 case RTE_TUNNEL_TYPE_NONE:
2888 case RTE_ETH_FILTER_FDIR:
2889 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2890 case RTE_ETH_FILTER_NTUPLE:
2891 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2892 case RTE_ETH_FILTER_MACVLAN:
2893 case RTE_ETH_FILTER_ETHERTYPE:
2894 case RTE_ETH_FILTER_FLEXIBLE:
2895 case RTE_ETH_FILTER_SYN:
2896 case RTE_ETH_FILTER_HASH:
2897 case RTE_ETH_FILTER_L2_TUNNEL:
2898 case RTE_ETH_FILTER_MAX:
2900 DP_ERR(edev, "Unsupported filter type %d\n",
2908 static const struct eth_dev_ops qede_eth_dev_ops = {
2909 .dev_configure = qede_dev_configure,
2910 .dev_infos_get = qede_dev_info_get,
2911 .rx_queue_setup = qede_rx_queue_setup,
2912 .rx_queue_release = qede_rx_queue_release,
2913 .tx_queue_setup = qede_tx_queue_setup,
2914 .tx_queue_release = qede_tx_queue_release,
2915 .dev_start = qede_dev_start,
2916 .dev_set_link_up = qede_dev_set_link_up,
2917 .dev_set_link_down = qede_dev_set_link_down,
2918 .link_update = qede_link_update,
2919 .promiscuous_enable = qede_promiscuous_enable,
2920 .promiscuous_disable = qede_promiscuous_disable,
2921 .allmulticast_enable = qede_allmulticast_enable,
2922 .allmulticast_disable = qede_allmulticast_disable,
2923 .dev_stop = qede_dev_stop,
2924 .dev_close = qede_dev_close,
2925 .stats_get = qede_get_stats,
2926 .stats_reset = qede_reset_stats,
2927 .xstats_get = qede_get_xstats,
2928 .xstats_reset = qede_reset_xstats,
2929 .xstats_get_names = qede_get_xstats_names,
2930 .mac_addr_add = qede_mac_addr_add,
2931 .mac_addr_remove = qede_mac_addr_remove,
2932 .mac_addr_set = qede_mac_addr_set,
2933 .vlan_offload_set = qede_vlan_offload_set,
2934 .vlan_filter_set = qede_vlan_filter_set,
2935 .flow_ctrl_set = qede_flow_ctrl_set,
2936 .flow_ctrl_get = qede_flow_ctrl_get,
2937 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2938 .rss_hash_update = qede_rss_hash_update,
2939 .rss_hash_conf_get = qede_rss_hash_conf_get,
2940 .reta_update = qede_rss_reta_update,
2941 .reta_query = qede_rss_reta_query,
2942 .mtu_set = qede_set_mtu,
2943 .filter_ctrl = qede_dev_filter_ctrl,
2944 .udp_tunnel_port_add = qede_udp_dst_port_add,
2945 .udp_tunnel_port_del = qede_udp_dst_port_del,
2948 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2949 .dev_configure = qede_dev_configure,
2950 .dev_infos_get = qede_dev_info_get,
2951 .rx_queue_setup = qede_rx_queue_setup,
2952 .rx_queue_release = qede_rx_queue_release,
2953 .tx_queue_setup = qede_tx_queue_setup,
2954 .tx_queue_release = qede_tx_queue_release,
2955 .dev_start = qede_dev_start,
2956 .dev_set_link_up = qede_dev_set_link_up,
2957 .dev_set_link_down = qede_dev_set_link_down,
2958 .link_update = qede_link_update,
2959 .promiscuous_enable = qede_promiscuous_enable,
2960 .promiscuous_disable = qede_promiscuous_disable,
2961 .allmulticast_enable = qede_allmulticast_enable,
2962 .allmulticast_disable = qede_allmulticast_disable,
2963 .dev_stop = qede_dev_stop,
2964 .dev_close = qede_dev_close,
2965 .stats_get = qede_get_stats,
2966 .stats_reset = qede_reset_stats,
2967 .xstats_get = qede_get_xstats,
2968 .xstats_reset = qede_reset_xstats,
2969 .xstats_get_names = qede_get_xstats_names,
2970 .vlan_offload_set = qede_vlan_offload_set,
2971 .vlan_filter_set = qede_vlan_filter_set,
2972 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2973 .rss_hash_update = qede_rss_hash_update,
2974 .rss_hash_conf_get = qede_rss_hash_conf_get,
2975 .reta_update = qede_rss_reta_update,
2976 .reta_query = qede_rss_reta_query,
2977 .mtu_set = qede_set_mtu,
2978 .udp_tunnel_port_add = qede_udp_dst_port_add,
2979 .udp_tunnel_port_del = qede_udp_dst_port_del,
2982 static void qede_update_pf_params(struct ecore_dev *edev)
2984 struct ecore_pf_params pf_params;
2986 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2987 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2988 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2989 qed_ops->common->update_pf_params(edev, &pf_params);
2992 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2994 struct rte_pci_device *pci_dev;
2995 struct rte_pci_addr pci_addr;
2996 struct qede_dev *adapter;
2997 struct ecore_dev *edev;
2998 struct qed_dev_eth_info dev_info;
2999 struct qed_slowpath_params params;
3000 static bool do_once = true;
3001 uint8_t bulletin_change;
3002 uint8_t vf_mac[ETHER_ADDR_LEN];
3003 uint8_t is_mac_forced;
3005 /* Fix up ecore debug level */
3006 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3007 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3010 /* Extract key data structures */
3011 adapter = eth_dev->data->dev_private;
3012 adapter->ethdev = eth_dev;
3013 edev = &adapter->edev;
3014 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3015 pci_addr = pci_dev->addr;
3017 PMD_INIT_FUNC_TRACE(edev);
3019 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3020 pci_addr.bus, pci_addr.devid, pci_addr.function,
3021 eth_dev->data->port_id);
3023 eth_dev->rx_pkt_burst = qede_recv_pkts;
3024 eth_dev->tx_pkt_burst = qede_xmit_pkts;
3025 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3027 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3028 DP_ERR(edev, "Skipping device init from secondary process\n");
3032 rte_eth_copy_pci_info(eth_dev, pci_dev);
3035 edev->vendor_id = pci_dev->id.vendor_id;
3036 edev->device_id = pci_dev->id.device_id;
3038 qed_ops = qed_get_eth_ops();
3040 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3044 DP_INFO(edev, "Starting qede probe\n");
3045 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3048 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3051 qede_update_pf_params(edev);
3052 rte_intr_callback_register(&pci_dev->intr_handle,
3053 qede_interrupt_handler, (void *)eth_dev);
3054 if (rte_intr_enable(&pci_dev->intr_handle)) {
3055 DP_ERR(edev, "rte_intr_enable() failed\n");
3059 /* Start the Slowpath-process */
3060 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
3061 params.int_mode = ECORE_INT_MODE_MSIX;
3062 params.drv_major = QEDE_PMD_VERSION_MAJOR;
3063 params.drv_minor = QEDE_PMD_VERSION_MINOR;
3064 params.drv_rev = QEDE_PMD_VERSION_REVISION;
3065 params.drv_eng = QEDE_PMD_VERSION_PATCH;
3066 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3067 QEDE_PMD_DRV_VER_STR_SIZE);
3069 /* For CMT mode device do periodic polling for slowpath events.
3070 * This is required since uio device uses only one MSI-x
3071 * interrupt vector but we need one for each engine.
3073 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3074 rc = rte_eal_alarm_set(timer_period * US_PER_S,
3078 DP_ERR(edev, "Unable to start periodic"
3079 " timer rc %d\n", rc);
3084 rc = qed_ops->common->slowpath_start(edev, ¶ms);
3086 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3087 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3092 rc = qed_ops->fill_dev_info(edev, &dev_info);
3094 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3095 qed_ops->common->slowpath_stop(edev);
3096 qed_ops->common->remove(edev);
3097 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3102 qede_alloc_etherdev(adapter, &dev_info);
3104 adapter->ops->common->set_name(edev, edev->name);
3107 adapter->dev_info.num_mac_filters =
3108 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3111 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3112 (uint32_t *)&adapter->dev_info.num_mac_filters);
3114 /* Allocate memory for storing MAC addr */
3115 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3117 adapter->dev_info.num_mac_filters),
3118 RTE_CACHE_LINE_SIZE);
3120 if (eth_dev->data->mac_addrs == NULL) {
3121 DP_ERR(edev, "Failed to allocate MAC address\n");
3122 qed_ops->common->slowpath_stop(edev);
3123 qed_ops->common->remove(edev);
3124 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3130 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3131 hw_info.hw_mac_addr,
3132 ð_dev->data->mac_addrs[0]);
3133 ether_addr_copy(ð_dev->data->mac_addrs[0],
3134 &adapter->primary_mac);
3136 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3138 if (bulletin_change) {
3140 ecore_vf_bulletin_get_forced_mac(
3141 ECORE_LEADING_HWFN(edev),
3144 if (is_mac_exist && is_mac_forced) {
3145 DP_INFO(edev, "VF macaddr received from PF\n");
3146 ether_addr_copy((struct ether_addr *)&vf_mac,
3147 ð_dev->data->mac_addrs[0]);
3148 ether_addr_copy(ð_dev->data->mac_addrs[0],
3149 &adapter->primary_mac);
3151 DP_ERR(edev, "No VF macaddr assigned\n");
3156 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3159 qede_print_adapter_info(adapter);
3163 /* Bring-up the link */
3164 qede_dev_set_link_state(eth_dev, true);
3166 adapter->num_tx_queues = 0;
3167 adapter->num_rx_queues = 0;
3168 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3169 SLIST_INIT(&adapter->vlan_list_head);
3170 SLIST_INIT(&adapter->uc_list_head);
3171 adapter->mtu = ETHER_MTU;
3172 adapter->vport_started = false;
3174 /* VF tunnel offloads is enabled by default in PF driver */
3175 adapter->vxlan.num_filters = 0;
3176 adapter->geneve.num_filters = 0;
3177 adapter->ipgre.num_filters = 0;
3179 adapter->vxlan.enable = true;
3180 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3181 ETH_TUNNEL_FILTER_IVLAN;
3182 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3183 adapter->geneve.enable = true;
3184 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3185 ETH_TUNNEL_FILTER_IVLAN;
3186 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3187 adapter->ipgre.enable = true;
3188 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3189 ETH_TUNNEL_FILTER_IVLAN;
3191 adapter->vxlan.enable = false;
3192 adapter->geneve.enable = false;
3193 adapter->ipgre.enable = false;
3196 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3197 adapter->primary_mac.addr_bytes[0],
3198 adapter->primary_mac.addr_bytes[1],
3199 adapter->primary_mac.addr_bytes[2],
3200 adapter->primary_mac.addr_bytes[3],
3201 adapter->primary_mac.addr_bytes[4],
3202 adapter->primary_mac.addr_bytes[5]);
3204 DP_INFO(edev, "Device initialized\n");
3209 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3211 return qede_common_dev_init(eth_dev, 1);
3214 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3216 return qede_common_dev_init(eth_dev, 0);
3219 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3221 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3222 struct qede_dev *qdev = eth_dev->data->dev_private;
3223 struct ecore_dev *edev = &qdev->edev;
3225 PMD_INIT_FUNC_TRACE(edev);
3228 /* only uninitialize in the primary process */
3229 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3232 /* safe to close dev here */
3233 qede_dev_close(eth_dev);
3235 eth_dev->dev_ops = NULL;
3236 eth_dev->rx_pkt_burst = NULL;
3237 eth_dev->tx_pkt_burst = NULL;
3239 if (eth_dev->data->mac_addrs)
3240 rte_free(eth_dev->data->mac_addrs);
3242 eth_dev->data->mac_addrs = NULL;
3247 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3249 return qede_dev_common_uninit(eth_dev);
3252 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3254 return qede_dev_common_uninit(eth_dev);
3257 static const struct rte_pci_id pci_id_qedevf_map[] = {
3258 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3260 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3263 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3266 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3271 static const struct rte_pci_id pci_id_qede_map[] = {
3272 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3274 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3277 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3280 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3283 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3286 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3289 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3292 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3295 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3298 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3301 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3306 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3307 struct rte_pci_device *pci_dev)
3309 return rte_eth_dev_pci_generic_probe(pci_dev,
3310 sizeof(struct qede_dev), qedevf_eth_dev_init);
3313 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3315 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3318 static struct rte_pci_driver rte_qedevf_pmd = {
3319 .id_table = pci_id_qedevf_map,
3320 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3321 .probe = qedevf_eth_dev_pci_probe,
3322 .remove = qedevf_eth_dev_pci_remove,
3325 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3326 struct rte_pci_device *pci_dev)
3328 return rte_eth_dev_pci_generic_probe(pci_dev,
3329 sizeof(struct qede_dev), qede_eth_dev_init);
3332 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3334 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3337 static struct rte_pci_driver rte_qede_pmd = {
3338 .id_table = pci_id_qede_map,
3339 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3340 .probe = qede_eth_dev_pci_probe,
3341 .remove = qede_eth_dev_pci_remove,
3344 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3345 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3346 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3347 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3348 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3349 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3351 RTE_INIT(qede_init_log);
3355 qede_logtype_init = rte_log_register("pmd.net.qede.init");
3356 if (qede_logtype_init >= 0)
3357 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3358 qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3359 if (qede_logtype_driver >= 0)
3360 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);