drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 /* Get FW version string based on fw_size */
 236 static int
 237 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
 238 {
 239         struct qede_dev *qdev = dev->data->dev_private;
 240         struct ecore_dev *edev = &qdev->edev;
 241         struct qed_dev_info *info = &qdev->dev_info.common;
 242         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 243         size_t size;
 244
 245         if (fw_ver == NULL)
 246                 return 0;
 247
 248         if (IS_PF(edev))
 249                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 250                          QEDE_PMD_FW_VERSION);
 251         else
 252                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 253                          info->fw_major, info->fw_minor,
 254                          info->fw_rev, info->fw_eng);
 255         size = strlen(ver_str);
 256         if (size + 1 <= fw_size) /* Add 1 byte for "\0" */
 257                 strlcpy(fw_ver, ver_str, fw_size);
 258         else
 259                 return (size + 1);
 260
 261         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 262                  " MFW: %d.%d.%d.%d",
 263                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
 264                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
 265                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
 266                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
 267         size = strlen(ver_str);
 268         if (size + 1 <= fw_size)
 269                 strlcpy(fw_ver, ver_str, fw_size);
 270
 271         if (fw_size <= 32)
 272                 goto out;
 273
 274         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 275                  " MBI: %d.%d.%d",
 276                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
 277                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
 278                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
 279         size = strlen(ver_str);
 280         if (size + 1 <= fw_size)
 281                 strlcpy(fw_ver, ver_str, fw_size);
 282
 283 out:
 284         return 0;
 285 }
 286
 287 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 288 {
 289         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 290 }
 291
 292 static void
 293 qede_interrupt_handler_intx(void *param)
 294 {
 295         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 296         struct qede_dev *qdev = eth_dev->data->dev_private;
 297         struct ecore_dev *edev = &qdev->edev;
 298         u64 status;
 299
 300         /* Check if our device actually raised an interrupt */
 301         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 302         if (status & 0x1) {
 303                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 304
 305                 if (rte_intr_ack(eth_dev->intr_handle))
 306                         DP_ERR(edev, "rte_intr_ack failed\n");
 307         }
 308 }
 309
 310 static void
 311 qede_interrupt_handler(void *param)
 312 {
 313         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 314         struct qede_dev *qdev = eth_dev->data->dev_private;
 315         struct ecore_dev *edev = &qdev->edev;
 316
 317         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 318         if (rte_intr_ack(eth_dev->intr_handle))
 319                 DP_ERR(edev, "rte_intr_ack failed\n");
 320 }
 321
 322 static void
 323 qede_assign_rxtx_handlers(struct rte_eth_dev *dev)
 324 {
 325         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
 326         struct qede_dev *qdev = dev->data->dev_private;
 327         struct ecore_dev *edev = &qdev->edev;
 328         bool use_tx_offload = false;
 329
 330         if (ECORE_IS_CMT(edev)) {
 331                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
 332                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
 333                 return;
 334         }
 335
 336         if (dev->data->lro || dev->data->scattered_rx) {
 337                 DP_INFO(edev, "Assigning qede_recv_pkts\n");
 338                 dev->rx_pkt_burst = qede_recv_pkts;
 339         } else {
 340                 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
 341                 dev->rx_pkt_burst = qede_recv_pkts_regular;
 342         }
 343
 344         use_tx_offload = !!(tx_offloads &
 345                             (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
 346                              DEV_TX_OFFLOAD_TCP_TSO | /* tso */
 347                              DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
 348
 349         if (use_tx_offload) {
 350                 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
 351                 dev->tx_pkt_burst = qede_xmit_pkts;
 352         } else {
 353                 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
 354                 dev->tx_pkt_burst = qede_xmit_pkts_regular;
 355         }
 356 }
 357
 358 static void
 359 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 360 {
 361         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 362         qdev->ops = qed_ops;
 363 }
 364
 365 static void qede_print_adapter_info(struct rte_eth_dev *dev)
 366 {
 367         struct qede_dev *qdev = dev->data->dev_private;
 368         struct ecore_dev *edev = &qdev->edev;
 369         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 370
 371         DP_INFO(edev, "**************************************************\n");
 372         DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
 373         DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
 374                   ECORE_IS_BB(edev) ? "BB" : "AH",
 375                   'A' + edev->chip_rev,
 376                   (int)edev->chip_metal);
 377         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 378                  QEDE_PMD_DRV_VERSION);
 379         DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
 380         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 381                  QEDE_PMD_BASE_VERSION);
 382         DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
 383         qede_fw_version_get(dev, ver_str, sizeof(ver_str));
 384         DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
 385         DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
 386         DP_INFO(edev, "**************************************************\n");
 387 }
 388
 389 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 390 {
 391         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_stop_vport(struct ecore_dev *edev)
 446 {
 447         struct ecore_hwfn *p_hwfn;
 448         uint8_t vport_id;
 449         int rc;
 450         int i;
 451
 452         vport_id = 0;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 456                                          vport_id);
 457                 if (rc != ECORE_SUCCESS) {
 458                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 459                         return rc;
 460                 }
 461         }
 462
 463         DP_INFO(edev, "vport stopped\n");
 464
 465         return 0;
 466 }
 467
 468 static int
 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 470 {
 471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 472         struct ecore_sp_vport_start_params params;
 473         struct ecore_hwfn *p_hwfn;
 474         int rc;
 475         int i;
 476
 477         if (qdev->vport_started)
 478                 qede_stop_vport(edev);
 479
 480         memset(&params, 0, sizeof(params));
 481         params.vport_id = 0;
 482         params.mtu = mtu;
 483         /* @DPDK - Disable FW placement */
 484         params.zero_placement_offset = 1;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 488                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 489                 rc = ecore_sp_vport_start(p_hwfn, &params);
 490                 if (rc != ECORE_SUCCESS) {
 491                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 492                         return rc;
 493                 }
 494         }
 495         ecore_reset_vport_stats(edev);
 496         qdev->vport_started = true;
 497         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 498
 499         return 0;
 500 }
 501
 502 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 503 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 504
 505 /* Activate or deactivate vport via vport-update */
 506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 507 {
 508         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 509         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 510         struct ecore_sp_vport_update_params params;
 511         struct ecore_hwfn *p_hwfn;
 512         uint8_t i;
 513         int rc = -1;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         params.vport_id = 0;
 517         params.update_vport_active_rx_flg = 1;
 518         params.update_vport_active_tx_flg = 1;
 519         params.vport_active_rx_flg = flg;
 520         params.vport_active_tx_flg = flg;
 521         if ((qdev->enable_tx_switching == false) && (flg == true)) {
 522                 params.update_tx_switching_flg = 1;
 523                 params.tx_switching_flg = !flg;
 524         }
 525         for_each_hwfn(edev, i) {
 526                 p_hwfn = &edev->hwfns[i];
 527                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 528                 rc = ecore_sp_vport_update(p_hwfn, &params,
 529                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 530                 if (rc != ECORE_SUCCESS) {
 531                         DP_ERR(edev, "Failed to update vport\n");
 532                         break;
 533                 }
 534         }
 535         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 536
 537         return rc;
 538 }
 539
 540 static void
 541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 542                            uint16_t mtu, bool enable)
 543 {
 544         /* Enable LRO in split mode */
 545         sge_tpa_params->tpa_ipv4_en_flg = enable;
 546         sge_tpa_params->tpa_ipv6_en_flg = enable;
 547         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 548         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 549         /* set if tpa enable changes */
 550         sge_tpa_params->update_tpa_en_flg = 1;
 551         /* set if tpa parameters should be handled */
 552         sge_tpa_params->update_tpa_param_flg = enable;
 553
 554         sge_tpa_params->max_buffers_per_cqe = 20;
 555         /* Enable TPA in split mode. In this mode each TPA segment
 556          * starts on the new BD, so there is one BD per segment.
 557          */
 558         sge_tpa_params->tpa_pkt_split_flg = 1;
 559         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 560         sge_tpa_params->tpa_gro_consistent_flg = 0;
 561         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 562         sge_tpa_params->tpa_max_size = 0x7FFF;
 563         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 564         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 565 }
 566
 567 /* Enable/disable LRO via vport-update */
 568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 569 {
 570         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 571         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 572         struct ecore_sp_vport_update_params params;
 573         struct ecore_sge_tpa_params tpa_params;
 574         struct ecore_hwfn *p_hwfn;
 575         int rc;
 576         int i;
 577
 578         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 579         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 580         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 581         params.vport_id = 0;
 582         params.sge_tpa_params = &tpa_params;
 583         for_each_hwfn(edev, i) {
 584                 p_hwfn = &edev->hwfns[i];
 585                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 586                 rc = ecore_sp_vport_update(p_hwfn, &params,
 587                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 588                 if (rc != ECORE_SUCCESS) {
 589                         DP_ERR(edev, "Failed to update LRO\n");
 590                         return -1;
 591                 }
 592         }
 593         qdev->enable_lro = flg;
 594         eth_dev->data->lro = flg;
 595
 596         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 597
 598         return 0;
 599 }
 600
 601 static int
 602 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 603                              enum qed_filter_rx_mode_type type)
 604 {
 605         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 606         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 607         struct ecore_filter_accept_flags flags;
 608
 609         memset(&flags, 0, sizeof(flags));
 610
 611         flags.update_rx_mode_config = 1;
 612         flags.update_tx_mode_config = 1;
 613         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 614                 ECORE_ACCEPT_MCAST_MATCHED |
 615                 ECORE_ACCEPT_BCAST;
 616
 617         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 618                 ECORE_ACCEPT_MCAST_MATCHED |
 619                 ECORE_ACCEPT_BCAST;
 620
 621         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 622                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 623                 if (IS_VF(edev)) {
 624                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 625                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 626                 }
 627         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 628                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 629         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 630                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 631                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 632                         ECORE_ACCEPT_MCAST_UNMATCHED;
 633         }
 634
 635         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 636                         ECORE_SPQ_MODE_CB, NULL);
 637 }
 638
 639 int
 640 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 641                   bool add)
 642 {
 643         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 644         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 645         struct qede_ucast_entry *tmp = NULL;
 646         struct qede_ucast_entry *u;
 647         struct rte_ether_addr *mac_addr;
 648
 649         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 650         if (add) {
 651                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 652                         if ((memcmp(mac_addr, &tmp->mac,
 653                                     RTE_ETHER_ADDR_LEN) == 0) &&
 654                              ucast->vni == tmp->vni &&
 655                              ucast->vlan == tmp->vlan) {
 656                                 DP_INFO(edev, "Unicast MAC is already added"
 657                                         " with vlan = %u, vni = %u\n",
 658                                         ucast->vlan,  ucast->vni);
 659                                         return 0;
 660                         }
 661                 }
 662                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 663                                RTE_CACHE_LINE_SIZE);
 664                 if (!u) {
 665                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 666                         return -ENOMEM;
 667                 }
 668                 rte_ether_addr_copy(mac_addr, &u->mac);
 669                 u->vlan = ucast->vlan;
 670                 u->vni = ucast->vni;
 671                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 672                 qdev->num_uc_addr++;
 673         } else {
 674                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 675                         if ((memcmp(mac_addr, &tmp->mac,
 676                                     RTE_ETHER_ADDR_LEN) == 0) &&
 677                             ucast->vlan == tmp->vlan      &&
 678                             ucast->vni == tmp->vni)
 679                         break;
 680                 }
 681                 if (tmp == NULL) {
 682                         DP_INFO(edev, "Unicast MAC is not found\n");
 683                         return -EINVAL;
 684                 }
 685                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 686                 qdev->num_uc_addr--;
 687         }
 688
 689         return 0;
 690 }
 691
 692 static int
 693 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 694                 struct rte_ether_addr *mc_addrs,
 695                 uint32_t mc_addrs_num)
 696 {
 697         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 698         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 699         struct ecore_filter_mcast mcast;
 700         struct qede_mcast_entry *m = NULL;
 701         uint8_t i;
 702         int rc;
 703
 704         for (i = 0; i < mc_addrs_num; i++) {
 705                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 706                                RTE_CACHE_LINE_SIZE);
 707                 if (!m) {
 708                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 709                         return -ENOMEM;
 710                 }
 711                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 712                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 713         }
 714         memset(&mcast, 0, sizeof(mcast));
 715         mcast.num_mc_addrs = mc_addrs_num;
 716         mcast.opcode = ECORE_FILTER_ADD;
 717         for (i = 0; i < mc_addrs_num; i++)
 718                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 719                                                         &mcast.mac[i]);
 720         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 721         if (rc != ECORE_SUCCESS) {
 722                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 723                 return -1;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 730 {
 731         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 732         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 733         struct qede_mcast_entry *tmp = NULL;
 734         struct ecore_filter_mcast mcast;
 735         int j;
 736         int rc;
 737
 738         memset(&mcast, 0, sizeof(mcast));
 739         mcast.num_mc_addrs = qdev->num_mc_addr;
 740         mcast.opcode = ECORE_FILTER_REMOVE;
 741         j = 0;
 742         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 743                 rte_ether_addr_copy(&tmp->mac,
 744                                 (struct rte_ether_addr *)&mcast.mac[j]);
 745                 j++;
 746         }
 747         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 748         if (rc != ECORE_SUCCESS) {
 749                 DP_ERR(edev, "Failed to delete multicast filter\n");
 750                 return -1;
 751         }
 752         /* Init the list */
 753         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 754                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 755                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 756         }
 757         SLIST_INIT(&qdev->mc_list_head);
 758
 759         return 0;
 760 }
 761
 762 enum _ecore_status_t
 763 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 764                  bool add)
 765 {
 766         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 767         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 768         enum _ecore_status_t rc = ECORE_INVAL;
 769
 770         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 771                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 772                               " Please enable promisc mode\n");
 773                         return ECORE_INVAL;
 774         }
 775
 776         rc = qede_ucast_filter(eth_dev, ucast, add);
 777         if (rc == 0)
 778                 rc = ecore_filter_ucast_cmd(edev, ucast,
 779                                             ECORE_SPQ_MODE_CB, NULL);
 780         /* Indicate error only for add filter operation.
 781          * Delete filter operations are not severe.
 782          */
 783         if ((rc != ECORE_SUCCESS) && add)
 784                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 785                        rc, add);
 786
 787         return rc;
 788 }
 789
 790 static int
 791 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 792                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 793 {
 794         struct ecore_filter_ucast ucast;
 795         int re;
 796
 797         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 798                 return -EINVAL;
 799
 800         qede_set_ucast_cmn_params(&ucast);
 801         ucast.opcode = ECORE_FILTER_ADD;
 802         ucast.type = ECORE_FILTER_MAC;
 803         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 804         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 805         return re;
 806 }
 807
 808 static void
 809 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 810 {
 811         struct qede_dev *qdev = eth_dev->data->dev_private;
 812         struct ecore_dev *edev = &qdev->edev;
 813         struct ecore_filter_ucast ucast;
 814
 815         PMD_INIT_FUNC_TRACE(edev);
 816
 817         if (index >= qdev->dev_info.num_mac_filters) {
 818                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 819                        index, qdev->dev_info.num_mac_filters);
 820                 return;
 821         }
 822
 823         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 824                 return;
 825
 826         qede_set_ucast_cmn_params(&ucast);
 827         ucast.opcode = ECORE_FILTER_REMOVE;
 828         ucast.type = ECORE_FILTER_MAC;
 829
 830         /* Use the index maintained by rte */
 831         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 832                         (struct rte_ether_addr *)&ucast.mac);
 833
 834         qede_mac_int_ops(eth_dev, &ucast, false);
 835 }
 836
 837 static int
 838 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 839 {
 840         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 841         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 842
 843         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 844                                                mac_addr->addr_bytes)) {
 845                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 846                 return -EPERM;
 847         }
 848
 849         qede_mac_addr_remove(eth_dev, 0);
 850
 851         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 852 }
 853
 854 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 855 {
 856         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 857         struct ecore_sp_vport_update_params params;
 858         struct ecore_hwfn *p_hwfn;
 859         uint8_t i;
 860         int rc;
 861
 862         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 863         params.vport_id = 0;
 864         params.update_accept_any_vlan_flg = 1;
 865         params.accept_any_vlan = flg;
 866         for_each_hwfn(edev, i) {
 867                 p_hwfn = &edev->hwfns[i];
 868                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 869                 rc = ecore_sp_vport_update(p_hwfn, &params,
 870                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 871                 if (rc != ECORE_SUCCESS) {
 872                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 873                         return;
 874                 }
 875         }
 876
 877         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 878 }
 879
 880 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 881 {
 882         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 883         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 884         struct ecore_sp_vport_update_params params;
 885         struct ecore_hwfn *p_hwfn;
 886         uint8_t i;
 887         int rc;
 888
 889         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 890         params.vport_id = 0;
 891         params.update_inner_vlan_removal_flg = 1;
 892         params.inner_vlan_removal_flg = flg;
 893         for_each_hwfn(edev, i) {
 894                 p_hwfn = &edev->hwfns[i];
 895                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 896                 rc = ecore_sp_vport_update(p_hwfn, &params,
 897                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 898                 if (rc != ECORE_SUCCESS) {
 899                         DP_ERR(edev, "Failed to update vport\n");
 900                         return -1;
 901                 }
 902         }
 903
 904         qdev->vlan_strip_flg = flg;
 905
 906         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 907         return 0;
 908 }
 909
 910 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 911                                 uint16_t vlan_id, int on)
 912 {
 913         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 914         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 915         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 916         struct qede_vlan_entry *tmp = NULL;
 917         struct qede_vlan_entry *vlan;
 918         struct ecore_filter_ucast ucast;
 919         int rc;
 920
 921         if (on) {
 922                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 923                         DP_ERR(edev, "Reached max VLAN filter limit"
 924                                       " enabling accept_any_vlan\n");
 925                         qede_config_accept_any_vlan(qdev, true);
 926                         return 0;
 927                 }
 928
 929                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 930                         if (tmp->vid == vlan_id) {
 931                                 DP_INFO(edev, "VLAN %u already configured\n",
 932                                         vlan_id);
 933                                 return 0;
 934                         }
 935                 }
 936
 937                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 938                                   RTE_CACHE_LINE_SIZE);
 939
 940                 if (!vlan) {
 941                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 942                         return -ENOMEM;
 943                 }
 944
 945                 qede_set_ucast_cmn_params(&ucast);
 946                 ucast.opcode = ECORE_FILTER_ADD;
 947                 ucast.type = ECORE_FILTER_VLAN;
 948                 ucast.vlan = vlan_id;
 949                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 950                                             NULL);
 951                 if (rc != 0) {
 952                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 953                                rc);
 954                         rte_free(vlan);
 955                 } else {
 956                         vlan->vid = vlan_id;
 957                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 958                         qdev->configured_vlans++;
 959                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 960                                 vlan_id, qdev->configured_vlans);
 961                 }
 962         } else {
 963                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 964                         if (tmp->vid == vlan_id)
 965                                 break;
 966                 }
 967
 968                 if (!tmp) {
 969                         if (qdev->configured_vlans == 0) {
 970                                 DP_INFO(edev,
 971                                         "No VLAN filters configured yet\n");
 972                                 return 0;
 973                         }
 974
 975                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 976                         return -EINVAL;
 977                 }
 978
 979                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 980
 981                 qede_set_ucast_cmn_params(&ucast);
 982                 ucast.opcode = ECORE_FILTER_REMOVE;
 983                 ucast.type = ECORE_FILTER_VLAN;
 984                 ucast.vlan = vlan_id;
 985                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 986                                             NULL);
 987                 if (rc != 0) {
 988                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 989                                vlan_id, rc);
 990                 } else {
 991                         qdev->configured_vlans--;
 992                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 993                                 vlan_id, qdev->configured_vlans);
 994                 }
 995         }
 996
 997         return rc;
 998 }
 999
1000 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1001 {
1002         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1003         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1004         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005
1006         if (mask & ETH_VLAN_STRIP_MASK) {
1007                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1008                         (void)qede_vlan_stripping(eth_dev, 1);
1009                 else
1010                         (void)qede_vlan_stripping(eth_dev, 0);
1011         }
1012
1013         if (mask & ETH_VLAN_FILTER_MASK) {
1014                 /* VLAN filtering kicks in when a VLAN is added */
1015                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1016                         qede_vlan_filter_set(eth_dev, 0, 1);
1017                 } else {
1018                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1019                                 DP_ERR(edev,
1020                                   " Please remove existing VLAN filters"
1021                                   " before disabling VLAN filtering\n");
1022                                 /* Signal app that VLAN filtering is still
1023                                  * enabled
1024                                  */
1025                                 eth_dev->data->dev_conf.rxmode.offloads |=
1026                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1027                         } else {
1028                                 qede_vlan_filter_set(eth_dev, 0, 0);
1029                         }
1030                 }
1031         }
1032
1033         if (mask & ETH_VLAN_EXTEND_MASK)
1034                 DP_ERR(edev, "Extend VLAN not supported\n");
1035
1036         qdev->vlan_offload_mask = mask;
1037
1038         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1039
1040         return 0;
1041 }
1042
1043 static void qede_prandom_bytes(uint32_t *buff)
1044 {
1045         uint8_t i;
1046
1047         srand((unsigned int)time(NULL));
1048         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1049                 buff[i] = rand();
1050 }
1051
1052 int qede_config_rss(struct rte_eth_dev *eth_dev)
1053 {
1054         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1055         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1056         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1057         struct rte_eth_rss_reta_entry64 reta_conf[2];
1058         struct rte_eth_rss_conf rss_conf;
1059         uint32_t i, id, pos, q;
1060
1061         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1062         if (!rss_conf.rss_key) {
1063                 DP_INFO(edev, "Applying driver default key\n");
1064                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1065                 qede_prandom_bytes(&def_rss_key[0]);
1066                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1067         }
1068
1069         /* Configure RSS hash */
1070         if (qede_rss_hash_update(eth_dev, &rss_conf))
1071                 return -EINVAL;
1072
1073         /* Configure default RETA */
1074         memset(reta_conf, 0, sizeof(reta_conf));
1075         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1076                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1077
1078         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1079                 id = i / RTE_RETA_GROUP_SIZE;
1080                 pos = i % RTE_RETA_GROUP_SIZE;
1081                 q = i % QEDE_RSS_COUNT(eth_dev);
1082                 reta_conf[id].reta[pos] = q;
1083         }
1084         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1085                                  ECORE_RSS_IND_TABLE_SIZE))
1086                 return -EINVAL;
1087
1088         return 0;
1089 }
1090
1091 static void qede_fastpath_start(struct ecore_dev *edev)
1092 {
1093         struct ecore_hwfn *p_hwfn;
1094         int i;
1095
1096         for_each_hwfn(edev, i) {
1097                 p_hwfn = &edev->hwfns[i];
1098                 ecore_hw_start_fastpath(p_hwfn);
1099         }
1100 }
1101
1102 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1103 {
1104         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1105         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1106         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1107
1108         PMD_INIT_FUNC_TRACE(edev);
1109
1110         /* Update MTU only if it has changed */
1111         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1112                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1113                         goto err;
1114                 qdev->mtu = qdev->new_mtu;
1115                 qdev->new_mtu = 0;
1116         }
1117
1118         /* Configure TPA parameters */
1119         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1120                 if (qede_enable_tpa(eth_dev, true))
1121                         return -EINVAL;
1122                 /* Enable scatter mode for LRO */
1123                 if (!eth_dev->data->scattered_rx)
1124                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1125         }
1126
1127         /* Start queues */
1128         if (qede_start_queues(eth_dev))
1129                 goto err;
1130
1131         if (IS_PF(edev))
1132                 qede_reset_queue_stats(qdev, true);
1133
1134         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1135          * enabling RSS. Hence RSS configuration is deferred up to this point.
1136          * Also, we would like to retain similar behavior in PF case, so we
1137          * don't do PF/VF specific check here.
1138          */
1139         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1140                 if (qede_config_rss(eth_dev))
1141                         goto err;
1142
1143         /* Enable vport*/
1144         if (qede_activate_vport(eth_dev, true))
1145                 goto err;
1146
1147         /* Bring-up the link */
1148         qede_dev_set_link_state(eth_dev, true);
1149
1150         /* Update link status */
1151         qede_link_update(eth_dev, 0);
1152
1153         /* Start/resume traffic */
1154         qede_fastpath_start(edev);
1155
1156         qede_assign_rxtx_handlers(eth_dev);
1157         DP_INFO(edev, "Device started\n");
1158
1159         return 0;
1160 err:
1161         DP_ERR(edev, "Device start fails\n");
1162         return -1; /* common error code is < 0 */
1163 }
1164
1165 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1166 {
1167         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1168         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1169
1170         PMD_INIT_FUNC_TRACE(edev);
1171
1172         /* Bring the link down */
1173         qede_dev_set_link_state(eth_dev, false);
1174
1175         /* Update link status */
1176         qede_link_update(eth_dev, 0);
1177
1178         /* Disable vport */
1179         if (qede_activate_vport(eth_dev, false))
1180                 return;
1181
1182         if (qdev->enable_lro)
1183                 qede_enable_tpa(eth_dev, false);
1184
1185         /* Stop queues */
1186         qede_stop_queues(eth_dev);
1187
1188         /* Disable traffic */
1189         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1190
1191         DP_INFO(edev, "Device is stopped\n");
1192 }
1193
1194 static const char * const valid_args[] = {
1195         QEDE_NPAR_TX_SWITCHING,
1196         QEDE_VF_TX_SWITCHING,
1197         NULL,
1198 };
1199
1200 static int qede_args_check(const char *key, const char *val, void *opaque)
1201 {
1202         unsigned long tmp;
1203         int ret = 0;
1204         struct rte_eth_dev *eth_dev = opaque;
1205         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1206         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1207
1208         errno = 0;
1209         tmp = strtoul(val, NULL, 0);
1210         if (errno) {
1211                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1212                 return errno;
1213         }
1214
1215         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1216             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1217                 qdev->enable_tx_switching = !!tmp;
1218                 DP_INFO(edev, "Disabling %s tx-switching\n",
1219                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1220                         "VF" : "NPAR");
1221         }
1222
1223         return ret;
1224 }
1225
1226 static int qede_args(struct rte_eth_dev *eth_dev)
1227 {
1228         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1229         struct rte_kvargs *kvlist;
1230         struct rte_devargs *devargs;
1231         int ret;
1232         int i;
1233
1234         devargs = pci_dev->device.devargs;
1235         if (!devargs)
1236                 return 0; /* return success */
1237
1238         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1239         if (kvlist == NULL)
1240                 return -EINVAL;
1241
1242          /* Process parameters. */
1243         for (i = 0; (valid_args[i] != NULL); ++i) {
1244                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1245                         ret = rte_kvargs_process(kvlist, valid_args[i],
1246                                                  qede_args_check, eth_dev);
1247                         if (ret != ECORE_SUCCESS) {
1248                                 rte_kvargs_free(kvlist);
1249                                 return ret;
1250                         }
1251                 }
1252         }
1253         rte_kvargs_free(kvlist);
1254
1255         return 0;
1256 }
1257
1258 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1259 {
1260         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1261         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1262         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1263         int ret;
1264
1265         PMD_INIT_FUNC_TRACE(edev);
1266
1267         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1268                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1269
1270         /* We need to have min 1 RX queue.There is no min check in
1271          * rte_eth_dev_configure(), so we are checking it here.
1272          */
1273         if (eth_dev->data->nb_rx_queues == 0) {
1274                 DP_ERR(edev, "Minimum one RX queue is required\n");
1275                 return -EINVAL;
1276         }
1277
1278         /* Enable Tx switching by default */
1279         qdev->enable_tx_switching = 1;
1280
1281         /* Parse devargs and fix up rxmode */
1282         if (qede_args(eth_dev))
1283                 DP_NOTICE(edev, false,
1284                           "Invalid devargs supplied, requested change will not take effect\n");
1285
1286         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1287               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1288                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1289                 return -ENOTSUP;
1290         }
1291         /* Flow director mode check */
1292         if (qede_check_fdir_support(eth_dev))
1293                 return -ENOTSUP;
1294
1295         qede_dealloc_fp_resc(eth_dev);
1296         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1297         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1298
1299         if (qede_alloc_fp_resc(qdev))
1300                 return -ENOMEM;
1301
1302         /* If jumbo enabled adjust MTU */
1303         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1304                 eth_dev->data->mtu =
1305                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1306                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1307
1308         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1309                 eth_dev->data->scattered_rx = 1;
1310
1311         if (qede_start_vport(qdev, eth_dev->data->mtu))
1312                 return -1;
1313
1314         qdev->mtu = eth_dev->data->mtu;
1315
1316         /* Enable VLAN offloads by default */
1317         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1318                                              ETH_VLAN_FILTER_MASK);
1319         if (ret)
1320                 return ret;
1321
1322         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1323                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1324
1325         if (ECORE_IS_CMT(edev))
1326                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1327                         qdev->num_rx_queues, qdev->num_tx_queues);
1328
1329
1330         return 0;
1331 }
1332
1333 /* Info about HW descriptor ring limitations */
1334 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1335         .nb_max = 0x8000, /* 32K */
1336         .nb_min = 128,
1337         .nb_align = 128 /* lowest common multiple */
1338 };
1339
1340 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1341         .nb_max = 0x8000, /* 32K */
1342         .nb_min = 256,
1343         .nb_align = 256,
1344         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1345         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1346 };
1347
1348 static int
1349 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1350                   struct rte_eth_dev_info *dev_info)
1351 {
1352         struct qede_dev *qdev = eth_dev->data->dev_private;
1353         struct ecore_dev *edev = &qdev->edev;
1354         struct qed_link_output link;
1355         uint32_t speed_cap = 0;
1356
1357         PMD_INIT_FUNC_TRACE(edev);
1358
1359         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1360         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1361         dev_info->rx_desc_lim = qede_rx_desc_lim;
1362         dev_info->tx_desc_lim = qede_tx_desc_lim;
1363
1364         if (IS_PF(edev))
1365                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1366                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1367         else
1368                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1369                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1370         /* Since CMT mode internally doubles the number of queues */
1371         if (ECORE_IS_CMT(edev))
1372                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1373
1374         dev_info->max_tx_queues = dev_info->max_rx_queues;
1375
1376         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1377         dev_info->max_vfs = 0;
1378         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1379         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1380         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1381         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1382                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1383                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1384                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1385                                      DEV_RX_OFFLOAD_TCP_LRO     |
1386                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1387                                      DEV_RX_OFFLOAD_SCATTER     |
1388                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1389                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1390                                      DEV_RX_OFFLOAD_VLAN_STRIP  |
1391                                      DEV_RX_OFFLOAD_RSS_HASH);
1392         dev_info->rx_queue_offload_capa = 0;
1393
1394         /* TX offloads are on a per-packet basis, so it is applicable
1395          * to both at port and queue levels.
1396          */
1397         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1398                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1399                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1400                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1401                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1402                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1403                                      DEV_TX_OFFLOAD_TCP_TSO     |
1404                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1405                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1406         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1407
1408         dev_info->default_txconf = (struct rte_eth_txconf) {
1409                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1410         };
1411
1412         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1413                 /* Packets are always dropped if no descriptors are available */
1414                 .rx_drop_en = 1,
1415                 .offloads = 0,
1416         };
1417
1418         memset(&link, 0, sizeof(struct qed_link_output));
1419         qdev->ops->common->get_link(edev, &link);
1420         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1421                 speed_cap |= ETH_LINK_SPEED_1G;
1422         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1423                 speed_cap |= ETH_LINK_SPEED_10G;
1424         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1425                 speed_cap |= ETH_LINK_SPEED_25G;
1426         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1427                 speed_cap |= ETH_LINK_SPEED_40G;
1428         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1429                 speed_cap |= ETH_LINK_SPEED_50G;
1430         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1431                 speed_cap |= ETH_LINK_SPEED_100G;
1432         dev_info->speed_capa = speed_cap;
1433
1434         return 0;
1435 }
1436
1437 /* return 0 means link status changed, -1 means not changed */
1438 int
1439 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1440 {
1441         struct qede_dev *qdev = eth_dev->data->dev_private;
1442         struct ecore_dev *edev = &qdev->edev;
1443         struct qed_link_output q_link;
1444         struct rte_eth_link link;
1445         uint16_t link_duplex;
1446
1447         memset(&q_link, 0, sizeof(q_link));
1448         memset(&link, 0, sizeof(link));
1449
1450         qdev->ops->common->get_link(edev, &q_link);
1451
1452         /* Link Speed */
1453         link.link_speed = q_link.speed;
1454
1455         /* Link Mode */
1456         switch (q_link.duplex) {
1457         case QEDE_DUPLEX_HALF:
1458                 link_duplex = ETH_LINK_HALF_DUPLEX;
1459                 break;
1460         case QEDE_DUPLEX_FULL:
1461                 link_duplex = ETH_LINK_FULL_DUPLEX;
1462                 break;
1463         case QEDE_DUPLEX_UNKNOWN:
1464         default:
1465                 link_duplex = -1;
1466         }
1467         link.link_duplex = link_duplex;
1468
1469         /* Link Status */
1470         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1471
1472         /* AN */
1473         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1474                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1475
1476         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1477                 link.link_speed, link.link_duplex,
1478                 link.link_autoneg, link.link_status);
1479
1480         return rte_eth_linkstatus_set(eth_dev, &link);
1481 }
1482
1483 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1484 {
1485         struct qede_dev *qdev = eth_dev->data->dev_private;
1486         struct ecore_dev *edev = &qdev->edev;
1487         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1488         enum _ecore_status_t ecore_status;
1489
1490         PMD_INIT_FUNC_TRACE(edev);
1491
1492         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1493                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1494
1495         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1496
1497         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1498 }
1499
1500 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1501 {
1502         struct qede_dev *qdev = eth_dev->data->dev_private;
1503         struct ecore_dev *edev = &qdev->edev;
1504         enum _ecore_status_t ecore_status;
1505
1506         PMD_INIT_FUNC_TRACE(edev);
1507
1508         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1509                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1510                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1511         else
1512                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1513                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1514
1515         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1516 }
1517
1518 static void qede_poll_sp_sb_cb(void *param)
1519 {
1520         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1521         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1522         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1523         int rc;
1524
1525         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1526         qede_interrupt_action(&edev->hwfns[1]);
1527
1528         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1529                                qede_poll_sp_sb_cb,
1530                                (void *)eth_dev);
1531         if (rc != 0) {
1532                 DP_ERR(edev, "Unable to start periodic"
1533                              " timer rc %d\n", rc);
1534         }
1535 }
1536
1537 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1538 {
1539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1540         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1541         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1542
1543         PMD_INIT_FUNC_TRACE(edev);
1544
1545         /* dev_stop() shall cleanup fp resources in hw but without releasing
1546          * dma memories and sw structures so that dev_start() can be called
1547          * by the app without reconfiguration. However, in dev_close() we
1548          * can release all the resources and device can be brought up newly
1549          */
1550         if (eth_dev->data->dev_started)
1551                 qede_dev_stop(eth_dev);
1552
1553         if (qdev->vport_started)
1554                 qede_stop_vport(edev);
1555         qdev->vport_started = false;
1556         qede_fdir_dealloc_resc(eth_dev);
1557         qede_dealloc_fp_resc(eth_dev);
1558
1559         eth_dev->data->nb_rx_queues = 0;
1560         eth_dev->data->nb_tx_queues = 0;
1561
1562         qdev->ops->common->slowpath_stop(edev);
1563         qdev->ops->common->remove(edev);
1564         rte_intr_disable(&pci_dev->intr_handle);
1565
1566         switch (pci_dev->intr_handle.type) {
1567         case RTE_INTR_HANDLE_UIO_INTX:
1568         case RTE_INTR_HANDLE_VFIO_LEGACY:
1569                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1570                                              qede_interrupt_handler_intx,
1571                                              (void *)eth_dev);
1572                 break;
1573         default:
1574                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1575                                            qede_interrupt_handler,
1576                                            (void *)eth_dev);
1577         }
1578
1579         if (ECORE_IS_CMT(edev))
1580                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1581 }
1582
1583 static int
1584 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1585 {
1586         struct qede_dev *qdev = eth_dev->data->dev_private;
1587         struct ecore_dev *edev = &qdev->edev;
1588         struct ecore_eth_stats stats;
1589         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1590         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1591         struct qede_tx_queue *txq;
1592
1593         ecore_get_vport_stats(edev, &stats);
1594
1595         /* RX Stats */
1596         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1597             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1598
1599         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1600             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1601
1602         eth_stats->ierrors = stats.common.rx_crc_errors +
1603             stats.common.rx_align_errors +
1604             stats.common.rx_carrier_errors +
1605             stats.common.rx_oversize_packets +
1606             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1607
1608         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1609
1610         eth_stats->imissed = stats.common.mftag_filter_discards +
1611             stats.common.mac_filter_discards +
1612             stats.common.no_buff_discards +
1613             stats.common.brb_truncates + stats.common.brb_discards;
1614
1615         /* TX stats */
1616         eth_stats->opackets = stats.common.tx_ucast_pkts +
1617             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1618
1619         eth_stats->obytes = stats.common.tx_ucast_bytes +
1620             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1621
1622         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1623
1624         /* Queue stats */
1625         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1626                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1627         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1628                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1629         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1630             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1631                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1632                        "Not all the queue stats will be displayed. Set"
1633                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1634                        " appropriately and retry.\n");
1635
1636         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1637                 eth_stats->q_ipackets[i] = 0;
1638                 eth_stats->q_errors[i] = 0;
1639
1640                 for_each_hwfn(edev, hw_fn) {
1641                         idx = qid * edev->num_hwfns + hw_fn;
1642
1643                         eth_stats->q_ipackets[i] +=
1644                                 *(uint64_t *)
1645                                         (((char *)(qdev->fp_array[idx].rxq)) +
1646                                          offsetof(struct qede_rx_queue,
1647                                          rcv_pkts));
1648                         eth_stats->q_errors[i] +=
1649                                 *(uint64_t *)
1650                                         (((char *)(qdev->fp_array[idx].rxq)) +
1651                                          offsetof(struct qede_rx_queue,
1652                                          rx_hw_errors)) +
1653                                 *(uint64_t *)
1654                                         (((char *)(qdev->fp_array[idx].rxq)) +
1655                                          offsetof(struct qede_rx_queue,
1656                                          rx_alloc_errors));
1657                 }
1658
1659                 i++;
1660                 if (i == rxq_stat_cntrs)
1661                         break;
1662         }
1663
1664         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1665                 eth_stats->q_opackets[j] = 0;
1666
1667                 for_each_hwfn(edev, hw_fn) {
1668                         idx = qid * edev->num_hwfns + hw_fn;
1669
1670                         txq = qdev->fp_array[idx].txq;
1671                         eth_stats->q_opackets[j] +=
1672                                 *((uint64_t *)(uintptr_t)
1673                                         (((uint64_t)(uintptr_t)(txq)) +
1674                                          offsetof(struct qede_tx_queue,
1675                                                   xmit_pkts)));
1676                 }
1677
1678                 j++;
1679                 if (j == txq_stat_cntrs)
1680                         break;
1681         }
1682
1683         return 0;
1684 }
1685
1686 static unsigned
1687 qede_get_xstats_count(struct qede_dev *qdev) {
1688         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1689
1690         if (ECORE_IS_BB(&qdev->edev))
1691                 return RTE_DIM(qede_xstats_strings) +
1692                        RTE_DIM(qede_bb_xstats_strings) +
1693                        (RTE_DIM(qede_rxq_xstats_strings) *
1694                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1695         else
1696                 return RTE_DIM(qede_xstats_strings) +
1697                        RTE_DIM(qede_ah_xstats_strings) +
1698                        (RTE_DIM(qede_rxq_xstats_strings) *
1699                         QEDE_RSS_COUNT(dev));
1700 }
1701
1702 static int
1703 qede_get_xstats_names(struct rte_eth_dev *dev,
1704                       struct rte_eth_xstat_name *xstats_names,
1705                       __rte_unused unsigned int limit)
1706 {
1707         struct qede_dev *qdev = dev->data->dev_private;
1708         struct ecore_dev *edev = &qdev->edev;
1709         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1710         unsigned int i, qid, hw_fn, stat_idx = 0;
1711
1712         if (xstats_names == NULL)
1713                 return stat_cnt;
1714
1715         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1716                 strlcpy(xstats_names[stat_idx].name,
1717                         qede_xstats_strings[i].name,
1718                         sizeof(xstats_names[stat_idx].name));
1719                 stat_idx++;
1720         }
1721
1722         if (ECORE_IS_BB(edev)) {
1723                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1724                         strlcpy(xstats_names[stat_idx].name,
1725                                 qede_bb_xstats_strings[i].name,
1726                                 sizeof(xstats_names[stat_idx].name));
1727                         stat_idx++;
1728                 }
1729         } else {
1730                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1731                         strlcpy(xstats_names[stat_idx].name,
1732                                 qede_ah_xstats_strings[i].name,
1733                                 sizeof(xstats_names[stat_idx].name));
1734                         stat_idx++;
1735                 }
1736         }
1737
1738         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1739                 for_each_hwfn(edev, hw_fn) {
1740                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1741                                 snprintf(xstats_names[stat_idx].name,
1742                                          RTE_ETH_XSTATS_NAME_SIZE,
1743                                          "%.4s%d.%d%s",
1744                                          qede_rxq_xstats_strings[i].name,
1745                                          hw_fn, qid,
1746                                          qede_rxq_xstats_strings[i].name + 4);
1747                                 stat_idx++;
1748                         }
1749                 }
1750         }
1751
1752         return stat_cnt;
1753 }
1754
1755 static int
1756 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1757                 unsigned int n)
1758 {
1759         struct qede_dev *qdev = dev->data->dev_private;
1760         struct ecore_dev *edev = &qdev->edev;
1761         struct ecore_eth_stats stats;
1762         const unsigned int num = qede_get_xstats_count(qdev);
1763         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1764
1765         if (n < num)
1766                 return num;
1767
1768         ecore_get_vport_stats(edev, &stats);
1769
1770         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1771                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1772                                              qede_xstats_strings[i].offset);
1773                 xstats[stat_idx].id = stat_idx;
1774                 stat_idx++;
1775         }
1776
1777         if (ECORE_IS_BB(edev)) {
1778                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1779                         xstats[stat_idx].value =
1780                                         *(uint64_t *)(((char *)&stats) +
1781                                         qede_bb_xstats_strings[i].offset);
1782                         xstats[stat_idx].id = stat_idx;
1783                         stat_idx++;
1784                 }
1785         } else {
1786                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1787                         xstats[stat_idx].value =
1788                                         *(uint64_t *)(((char *)&stats) +
1789                                         qede_ah_xstats_strings[i].offset);
1790                         xstats[stat_idx].id = stat_idx;
1791                         stat_idx++;
1792                 }
1793         }
1794
1795         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1796                 for_each_hwfn(edev, hw_fn) {
1797                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1798                                 fpidx = qid * edev->num_hwfns + hw_fn;
1799                                 xstats[stat_idx].value = *(uint64_t *)
1800                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1801                                          qede_rxq_xstats_strings[i].offset);
1802                                 xstats[stat_idx].id = stat_idx;
1803                                 stat_idx++;
1804                         }
1805
1806                 }
1807         }
1808
1809         return stat_idx;
1810 }
1811
1812 static int
1813 qede_reset_xstats(struct rte_eth_dev *dev)
1814 {
1815         struct qede_dev *qdev = dev->data->dev_private;
1816         struct ecore_dev *edev = &qdev->edev;
1817
1818         ecore_reset_vport_stats(edev);
1819         qede_reset_queue_stats(qdev, true);
1820
1821         return 0;
1822 }
1823
1824 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1825 {
1826         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1827         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1828         struct qed_link_params link_params;
1829         int rc;
1830
1831         DP_INFO(edev, "setting link state %d\n", link_up);
1832         memset(&link_params, 0, sizeof(link_params));
1833         link_params.link_up = link_up;
1834         rc = qdev->ops->common->set_link(edev, &link_params);
1835         if (rc != ECORE_SUCCESS)
1836                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1837
1838         return rc;
1839 }
1840
1841 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1842 {
1843         return qede_dev_set_link_state(eth_dev, true);
1844 }
1845
1846 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1847 {
1848         return qede_dev_set_link_state(eth_dev, false);
1849 }
1850
1851 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1852 {
1853         struct qede_dev *qdev = eth_dev->data->dev_private;
1854         struct ecore_dev *edev = &qdev->edev;
1855
1856         ecore_reset_vport_stats(edev);
1857         qede_reset_queue_stats(qdev, false);
1858
1859         return 0;
1860 }
1861
1862 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1863 {
1864         enum qed_filter_rx_mode_type type =
1865             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1866         enum _ecore_status_t ecore_status;
1867
1868         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1869                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1870
1871         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1872
1873         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1874 }
1875
1876 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1877 {
1878         enum _ecore_status_t ecore_status;
1879
1880         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1881                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1882                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1883         else
1884                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1885                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1886
1887         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1888 }
1889
1890 static int
1891 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1892                 struct rte_ether_addr *mc_addrs,
1893                 uint32_t mc_addrs_num)
1894 {
1895         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1896         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1897         uint8_t i;
1898
1899         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1900                 DP_ERR(edev, "Reached max multicast filters limit,"
1901                              "Please enable multicast promisc mode\n");
1902                 return -ENOSPC;
1903         }
1904
1905         for (i = 0; i < mc_addrs_num; i++) {
1906                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1907                         DP_ERR(edev, "Not a valid multicast MAC\n");
1908                         return -EINVAL;
1909                 }
1910         }
1911
1912         /* Flush all existing entries */
1913         if (qede_del_mcast_filters(eth_dev))
1914                 return -1;
1915
1916         /* Set new mcast list */
1917         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1918 }
1919
1920 /* Update MTU via vport-update without doing port restart.
1921  * The vport must be deactivated before calling this API.
1922  */
1923 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1924 {
1925         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1926         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1927         struct ecore_hwfn *p_hwfn;
1928         int rc;
1929         int i;
1930
1931         if (IS_PF(edev)) {
1932                 struct ecore_sp_vport_update_params params;
1933
1934                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1935                 params.vport_id = 0;
1936                 params.mtu = mtu;
1937                 params.vport_id = 0;
1938                 for_each_hwfn(edev, i) {
1939                         p_hwfn = &edev->hwfns[i];
1940                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1941                         rc = ecore_sp_vport_update(p_hwfn, &params,
1942                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1943                         if (rc != ECORE_SUCCESS)
1944                                 goto err;
1945                 }
1946         } else {
1947                 for_each_hwfn(edev, i) {
1948                         p_hwfn = &edev->hwfns[i];
1949                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1950                         if (rc == ECORE_INVAL) {
1951                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1952                                 /* Recreate vport */
1953                                 rc = qede_start_vport(qdev, mtu);
1954                                 if (rc != ECORE_SUCCESS)
1955                                         goto err;
1956
1957                                 /* Restore config lost due to vport stop */
1958                                 if (eth_dev->data->promiscuous)
1959                                         qede_promiscuous_enable(eth_dev);
1960                                 else
1961                                         qede_promiscuous_disable(eth_dev);
1962
1963                                 if (eth_dev->data->all_multicast)
1964                                         qede_allmulticast_enable(eth_dev);
1965                                 else
1966                                         qede_allmulticast_disable(eth_dev);
1967
1968                                 qede_vlan_offload_set(eth_dev,
1969                                                       qdev->vlan_offload_mask);
1970                         } else if (rc != ECORE_SUCCESS) {
1971                                 goto err;
1972                         }
1973                 }
1974         }
1975         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1976
1977         return 0;
1978
1979 err:
1980         DP_ERR(edev, "Failed to update MTU\n");
1981         return -1;
1982 }
1983
1984 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1985                               struct rte_eth_fc_conf *fc_conf)
1986 {
1987         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1988         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1989         struct qed_link_output current_link;
1990         struct qed_link_params params;
1991
1992         memset(&current_link, 0, sizeof(current_link));
1993         qdev->ops->common->get_link(edev, &current_link);
1994
1995         memset(&params, 0, sizeof(params));
1996         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1997         if (fc_conf->autoneg) {
1998                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1999                         DP_ERR(edev, "Autoneg not supported\n");
2000                         return -EINVAL;
2001                 }
2002                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2003         }
2004
2005         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2006         if (fc_conf->mode == RTE_FC_FULL)
2007                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2008                                         QED_LINK_PAUSE_RX_ENABLE);
2009         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2010                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2011         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2012                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2013
2014         params.link_up = true;
2015         (void)qdev->ops->common->set_link(edev, &params);
2016
2017         return 0;
2018 }
2019
2020 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2021                               struct rte_eth_fc_conf *fc_conf)
2022 {
2023         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2024         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2025         struct qed_link_output current_link;
2026
2027         memset(&current_link, 0, sizeof(current_link));
2028         qdev->ops->common->get_link(edev, &current_link);
2029
2030         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2031                 fc_conf->autoneg = true;
2032
2033         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2034                                          QED_LINK_PAUSE_TX_ENABLE))
2035                 fc_conf->mode = RTE_FC_FULL;
2036         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2037                 fc_conf->mode = RTE_FC_RX_PAUSE;
2038         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2039                 fc_conf->mode = RTE_FC_TX_PAUSE;
2040         else
2041                 fc_conf->mode = RTE_FC_NONE;
2042
2043         return 0;
2044 }
2045
2046 static const uint32_t *
2047 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2048 {
2049         static const uint32_t ptypes[] = {
2050                 RTE_PTYPE_L2_ETHER,
2051                 RTE_PTYPE_L2_ETHER_VLAN,
2052                 RTE_PTYPE_L3_IPV4,
2053                 RTE_PTYPE_L3_IPV6,
2054                 RTE_PTYPE_L4_TCP,
2055                 RTE_PTYPE_L4_UDP,
2056                 RTE_PTYPE_TUNNEL_VXLAN,
2057                 RTE_PTYPE_L4_FRAG,
2058                 RTE_PTYPE_TUNNEL_GENEVE,
2059                 RTE_PTYPE_TUNNEL_GRE,
2060                 /* Inner */
2061                 RTE_PTYPE_INNER_L2_ETHER,
2062                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2063                 RTE_PTYPE_INNER_L3_IPV4,
2064                 RTE_PTYPE_INNER_L3_IPV6,
2065                 RTE_PTYPE_INNER_L4_TCP,
2066                 RTE_PTYPE_INNER_L4_UDP,
2067                 RTE_PTYPE_INNER_L4_FRAG,
2068                 RTE_PTYPE_UNKNOWN
2069         };
2070
2071         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2072             eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2073             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2074                 return ptypes;
2075
2076         return NULL;
2077 }
2078
2079 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2080 {
2081         *rss_caps = 0;
2082         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2083         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2084         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2085         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2086         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2087         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2088         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2089         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2090 }
2091
2092 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2093                          struct rte_eth_rss_conf *rss_conf)
2094 {
2095         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2096         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2097         struct ecore_sp_vport_update_params vport_update_params;
2098         struct ecore_rss_params rss_params;
2099         struct ecore_hwfn *p_hwfn;
2100         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2101         uint64_t hf = rss_conf->rss_hf;
2102         uint8_t len = rss_conf->rss_key_len;
2103         uint8_t idx, i, j, fpidx;
2104         int rc;
2105
2106         memset(&vport_update_params, 0, sizeof(vport_update_params));
2107         memset(&rss_params, 0, sizeof(rss_params));
2108
2109         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2110                 (unsigned long)hf, len, key);
2111
2112         if (hf != 0) {
2113                 /* Enabling RSS */
2114                 DP_INFO(edev, "Enabling rss\n");
2115
2116                 /* RSS caps */
2117                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2118                 rss_params.update_rss_capabilities = 1;
2119
2120                 /* RSS hash key */
2121                 if (key) {
2122                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2123                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2124                                 return -EINVAL;
2125                         }
2126                         DP_INFO(edev, "Applying user supplied hash key\n");
2127                         rss_params.update_rss_key = 1;
2128                         memcpy(&rss_params.rss_key, key, len);
2129                 }
2130                 rss_params.rss_enable = 1;
2131         }
2132
2133         rss_params.update_rss_config = 1;
2134         /* tbl_size has to be set with capabilities */
2135         rss_params.rss_table_size_log = 7;
2136         vport_update_params.vport_id = 0;
2137
2138         for_each_hwfn(edev, i) {
2139                 /* pass the L2 handles instead of qids */
2140                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2141                         idx = j % QEDE_RSS_COUNT(eth_dev);
2142                         fpidx = idx * edev->num_hwfns + i;
2143                         rss_params.rss_ind_table[j] =
2144                                 qdev->fp_array[fpidx].rxq->handle;
2145                 }
2146
2147                 vport_update_params.rss_params = &rss_params;
2148
2149                 p_hwfn = &edev->hwfns[i];
2150                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2151                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2152                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2153                 if (rc) {
2154                         DP_ERR(edev, "vport-update for RSS failed\n");
2155                         return rc;
2156                 }
2157         }
2158         qdev->rss_enable = rss_params.rss_enable;
2159
2160         /* Update local structure for hash query */
2161         qdev->rss_conf.rss_hf = hf;
2162         qdev->rss_conf.rss_key_len = len;
2163         if (qdev->rss_enable) {
2164                 if  (qdev->rss_conf.rss_key == NULL) {
2165                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2166                         if (qdev->rss_conf.rss_key == NULL) {
2167                                 DP_ERR(edev, "No memory to store RSS key\n");
2168                                 return -ENOMEM;
2169                         }
2170                 }
2171                 if (key && len) {
2172                         DP_INFO(edev, "Storing RSS key\n");
2173                         memcpy(qdev->rss_conf.rss_key, key, len);
2174                 }
2175         } else if (!qdev->rss_enable && len == 0) {
2176                 if (qdev->rss_conf.rss_key) {
2177                         free(qdev->rss_conf.rss_key);
2178                         qdev->rss_conf.rss_key = NULL;
2179                         DP_INFO(edev, "Free RSS key\n");
2180                 }
2181         }
2182
2183         return 0;
2184 }
2185
2186 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2187                            struct rte_eth_rss_conf *rss_conf)
2188 {
2189         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2190
2191         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2192         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2193
2194         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2195                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2196                        rss_conf->rss_key_len);
2197         return 0;
2198 }
2199
2200 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2201                          struct rte_eth_rss_reta_entry64 *reta_conf,
2202                          uint16_t reta_size)
2203 {
2204         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2205         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2206         struct ecore_sp_vport_update_params vport_update_params;
2207         struct ecore_rss_params *params;
2208         uint16_t i, j, idx, fid, shift;
2209         struct ecore_hwfn *p_hwfn;
2210         uint8_t entry;
2211         int rc = 0;
2212
2213         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2214                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2215                        reta_size);
2216                 return -EINVAL;
2217         }
2218
2219         memset(&vport_update_params, 0, sizeof(vport_update_params));
2220         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2221         if (params == NULL) {
2222                 DP_ERR(edev, "failed to allocate memory\n");
2223                 return -ENOMEM;
2224         }
2225
2226         params->update_rss_ind_table = 1;
2227         params->rss_table_size_log = 7;
2228         params->update_rss_config = 1;
2229
2230         vport_update_params.vport_id = 0;
2231         /* Use the current value of rss_enable */
2232         params->rss_enable = qdev->rss_enable;
2233         vport_update_params.rss_params = params;
2234
2235         for_each_hwfn(edev, i) {
2236                 for (j = 0; j < reta_size; j++) {
2237                         idx = j / RTE_RETA_GROUP_SIZE;
2238                         shift = j % RTE_RETA_GROUP_SIZE;
2239                         if (reta_conf[idx].mask & (1ULL << shift)) {
2240                                 entry = reta_conf[idx].reta[shift];
2241                                 fid = entry * edev->num_hwfns + i;
2242                                 /* Pass rxq handles to ecore */
2243                                 params->rss_ind_table[j] =
2244                                                 qdev->fp_array[fid].rxq->handle;
2245                                 /* Update the local copy for RETA query cmd */
2246                                 qdev->rss_ind_table[j] = entry;
2247                         }
2248                 }
2249
2250                 p_hwfn = &edev->hwfns[i];
2251                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2252                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2253                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2254                 if (rc) {
2255                         DP_ERR(edev, "vport-update for RSS failed\n");
2256                         goto out;
2257                 }
2258         }
2259
2260 out:
2261         rte_free(params);
2262         return rc;
2263 }
2264
2265 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2266                                struct rte_eth_rss_reta_entry64 *reta_conf,
2267                                uint16_t reta_size)
2268 {
2269         struct qede_dev *qdev = eth_dev->data->dev_private;
2270         struct ecore_dev *edev = &qdev->edev;
2271         uint16_t i, idx, shift;
2272         uint8_t entry;
2273
2274         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2275                 DP_ERR(edev, "reta_size %d is not supported\n",
2276                        reta_size);
2277                 return -EINVAL;
2278         }
2279
2280         for (i = 0; i < reta_size; i++) {
2281                 idx = i / RTE_RETA_GROUP_SIZE;
2282                 shift = i % RTE_RETA_GROUP_SIZE;
2283                 if (reta_conf[idx].mask & (1ULL << shift)) {
2284                         entry = qdev->rss_ind_table[i];
2285                         reta_conf[idx].reta[shift] = entry;
2286                 }
2287         }
2288
2289         return 0;
2290 }
2291
2292
2293
2294 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2295 {
2296         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2297         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2298         struct rte_eth_dev_info dev_info = {0};
2299         struct qede_fastpath *fp;
2300         uint32_t max_rx_pkt_len;
2301         uint32_t frame_size;
2302         uint16_t bufsz;
2303         bool restart = false;
2304         int i, rc;
2305
2306         PMD_INIT_FUNC_TRACE(edev);
2307         rc = qede_dev_info_get(dev, &dev_info);
2308         if (rc != 0) {
2309                 DP_ERR(edev, "Error during getting ethernet device info\n");
2310                 return rc;
2311         }
2312         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2313         frame_size = max_rx_pkt_len;
2314         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2315                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2316                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2317                        QEDE_ETH_OVERHEAD);
2318                 return -EINVAL;
2319         }
2320         if (!dev->data->scattered_rx &&
2321             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2322                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2323                         dev->data->min_rx_buf_size);
2324                 return -EINVAL;
2325         }
2326         /* Temporarily replace I/O functions with dummy ones. It cannot
2327          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2328          */
2329         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2330         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2331         if (dev->data->dev_started) {
2332                 dev->data->dev_started = 0;
2333                 qede_dev_stop(dev);
2334                 restart = true;
2335         }
2336         rte_delay_ms(1000);
2337         qdev->new_mtu = mtu;
2338
2339         /* Fix up RX buf size for all queues of the port */
2340         for (i = 0; i < qdev->num_rx_queues; i++) {
2341                 fp = &qdev->fp_array[i];
2342                 if (fp->rxq != NULL) {
2343                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2344                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2345                         /* cache align the mbuf size to simplfy rx_buf_size
2346                          * calculation
2347                          */
2348                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2349                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2350                         if (rc < 0)
2351                                 return rc;
2352
2353                         fp->rxq->rx_buf_size = rc;
2354                 }
2355         }
2356         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2357                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2358         else
2359                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2360
2361         if (!dev->data->dev_started && restart) {
2362                 qede_dev_start(dev);
2363                 dev->data->dev_started = 1;
2364         }
2365
2366         /* update max frame size */
2367         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2368
2369         /* Reassign back */
2370         qede_assign_rxtx_handlers(dev);
2371         if (ECORE_IS_CMT(edev)) {
2372                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2373                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2374         } else {
2375                 dev->rx_pkt_burst = qede_recv_pkts;
2376                 dev->tx_pkt_burst = qede_xmit_pkts;
2377         }
2378         return 0;
2379 }
2380
2381 static int
2382 qede_dev_reset(struct rte_eth_dev *dev)
2383 {
2384         int ret;
2385
2386         ret = qede_eth_dev_uninit(dev);
2387         if (ret)
2388                 return ret;
2389
2390         return qede_eth_dev_init(dev);
2391 }
2392
2393 static const struct eth_dev_ops qede_eth_dev_ops = {
2394         .dev_configure = qede_dev_configure,
2395         .dev_infos_get = qede_dev_info_get,
2396         .rx_queue_setup = qede_rx_queue_setup,
2397         .rx_queue_release = qede_rx_queue_release,
2398         .rx_descriptor_status = qede_rx_descriptor_status,
2399         .tx_queue_setup = qede_tx_queue_setup,
2400         .tx_queue_release = qede_tx_queue_release,
2401         .dev_start = qede_dev_start,
2402         .dev_reset = qede_dev_reset,
2403         .dev_set_link_up = qede_dev_set_link_up,
2404         .dev_set_link_down = qede_dev_set_link_down,
2405         .link_update = qede_link_update,
2406         .promiscuous_enable = qede_promiscuous_enable,
2407         .promiscuous_disable = qede_promiscuous_disable,
2408         .allmulticast_enable = qede_allmulticast_enable,
2409         .allmulticast_disable = qede_allmulticast_disable,
2410         .set_mc_addr_list = qede_set_mc_addr_list,
2411         .dev_stop = qede_dev_stop,
2412         .dev_close = qede_dev_close,
2413         .stats_get = qede_get_stats,
2414         .stats_reset = qede_reset_stats,
2415         .xstats_get = qede_get_xstats,
2416         .xstats_reset = qede_reset_xstats,
2417         .xstats_get_names = qede_get_xstats_names,
2418         .mac_addr_add = qede_mac_addr_add,
2419         .mac_addr_remove = qede_mac_addr_remove,
2420         .mac_addr_set = qede_mac_addr_set,
2421         .vlan_offload_set = qede_vlan_offload_set,
2422         .vlan_filter_set = qede_vlan_filter_set,
2423         .flow_ctrl_set = qede_flow_ctrl_set,
2424         .flow_ctrl_get = qede_flow_ctrl_get,
2425         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2426         .rss_hash_update = qede_rss_hash_update,
2427         .rss_hash_conf_get = qede_rss_hash_conf_get,
2428         .reta_update  = qede_rss_reta_update,
2429         .reta_query  = qede_rss_reta_query,
2430         .mtu_set = qede_set_mtu,
2431         .filter_ctrl = qede_dev_filter_ctrl,
2432         .udp_tunnel_port_add = qede_udp_dst_port_add,
2433         .udp_tunnel_port_del = qede_udp_dst_port_del,
2434         .fw_version_get = qede_fw_version_get,
2435 };
2436
2437 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2438         .dev_configure = qede_dev_configure,
2439         .dev_infos_get = qede_dev_info_get,
2440         .rx_queue_setup = qede_rx_queue_setup,
2441         .rx_queue_release = qede_rx_queue_release,
2442         .rx_descriptor_status = qede_rx_descriptor_status,
2443         .tx_queue_setup = qede_tx_queue_setup,
2444         .tx_queue_release = qede_tx_queue_release,
2445         .dev_start = qede_dev_start,
2446         .dev_reset = qede_dev_reset,
2447         .dev_set_link_up = qede_dev_set_link_up,
2448         .dev_set_link_down = qede_dev_set_link_down,
2449         .link_update = qede_link_update,
2450         .promiscuous_enable = qede_promiscuous_enable,
2451         .promiscuous_disable = qede_promiscuous_disable,
2452         .allmulticast_enable = qede_allmulticast_enable,
2453         .allmulticast_disable = qede_allmulticast_disable,
2454         .set_mc_addr_list = qede_set_mc_addr_list,
2455         .dev_stop = qede_dev_stop,
2456         .dev_close = qede_dev_close,
2457         .stats_get = qede_get_stats,
2458         .stats_reset = qede_reset_stats,
2459         .xstats_get = qede_get_xstats,
2460         .xstats_reset = qede_reset_xstats,
2461         .xstats_get_names = qede_get_xstats_names,
2462         .vlan_offload_set = qede_vlan_offload_set,
2463         .vlan_filter_set = qede_vlan_filter_set,
2464         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2465         .rss_hash_update = qede_rss_hash_update,
2466         .rss_hash_conf_get = qede_rss_hash_conf_get,
2467         .reta_update  = qede_rss_reta_update,
2468         .reta_query  = qede_rss_reta_query,
2469         .mtu_set = qede_set_mtu,
2470         .udp_tunnel_port_add = qede_udp_dst_port_add,
2471         .udp_tunnel_port_del = qede_udp_dst_port_del,
2472         .mac_addr_add = qede_mac_addr_add,
2473         .mac_addr_remove = qede_mac_addr_remove,
2474         .mac_addr_set = qede_mac_addr_set,
2475         .fw_version_get = qede_fw_version_get,
2476 };
2477
2478 static void qede_update_pf_params(struct ecore_dev *edev)
2479 {
2480         struct ecore_pf_params pf_params;
2481
2482         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2483         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2484         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2485         qed_ops->common->update_pf_params(edev, &pf_params);
2486 }
2487
2488 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2489 {
2490         struct rte_pci_device *pci_dev;
2491         struct rte_pci_addr pci_addr;
2492         struct qede_dev *adapter;
2493         struct ecore_dev *edev;
2494         struct qed_dev_eth_info dev_info;
2495         struct qed_slowpath_params params;
2496         static bool do_once = true;
2497         uint8_t bulletin_change;
2498         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2499         uint8_t is_mac_forced;
2500         bool is_mac_exist;
2501         /* Fix up ecore debug level */
2502         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2503         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2504         uint32_t int_mode;
2505         int rc;
2506
2507         /* Extract key data structures */
2508         adapter = eth_dev->data->dev_private;
2509         adapter->ethdev = eth_dev;
2510         edev = &adapter->edev;
2511         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2512         pci_addr = pci_dev->addr;
2513
2514         PMD_INIT_FUNC_TRACE(edev);
2515
2516         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2517                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2518                  eth_dev->data->port_id);
2519
2520         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2521                 DP_ERR(edev, "Skipping device init from secondary process\n");
2522                 return 0;
2523         }
2524
2525         rte_eth_copy_pci_info(eth_dev, pci_dev);
2526
2527         /* @DPDK */
2528         edev->vendor_id = pci_dev->id.vendor_id;
2529         edev->device_id = pci_dev->id.device_id;
2530
2531         qed_ops = qed_get_eth_ops();
2532         if (!qed_ops) {
2533                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2534                 rc = -EINVAL;
2535                 goto err;
2536         }
2537
2538         DP_INFO(edev, "Starting qede probe\n");
2539         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2540                                     dp_level, is_vf);
2541         if (rc != 0) {
2542                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2543                 rc = -ENODEV;
2544                 goto err;
2545         }
2546         qede_update_pf_params(edev);
2547
2548         switch (pci_dev->intr_handle.type) {
2549         case RTE_INTR_HANDLE_UIO_INTX:
2550         case RTE_INTR_HANDLE_VFIO_LEGACY:
2551                 int_mode = ECORE_INT_MODE_INTA;
2552                 rte_intr_callback_register(&pci_dev->intr_handle,
2553                                            qede_interrupt_handler_intx,
2554                                            (void *)eth_dev);
2555                 break;
2556         default:
2557                 int_mode = ECORE_INT_MODE_MSIX;
2558                 rte_intr_callback_register(&pci_dev->intr_handle,
2559                                            qede_interrupt_handler,
2560                                            (void *)eth_dev);
2561         }
2562
2563         if (rte_intr_enable(&pci_dev->intr_handle)) {
2564                 DP_ERR(edev, "rte_intr_enable() failed\n");
2565                 rc = -ENODEV;
2566                 goto err;
2567         }
2568
2569         /* Start the Slowpath-process */
2570         memset(&params, 0, sizeof(struct qed_slowpath_params));
2571
2572         params.int_mode = int_mode;
2573         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2574         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2575         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2576         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2577         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2578                 QEDE_PMD_DRV_VER_STR_SIZE);
2579
2580         qede_assign_rxtx_handlers(eth_dev);
2581         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2582
2583         /* For CMT mode device do periodic polling for slowpath events.
2584          * This is required since uio device uses only one MSI-x
2585          * interrupt vector but we need one for each engine.
2586          */
2587         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2588                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2589                                        qede_poll_sp_sb_cb,
2590                                        (void *)eth_dev);
2591                 if (rc != 0) {
2592                         DP_ERR(edev, "Unable to start periodic"
2593                                      " timer rc %d\n", rc);
2594                         rc = -EINVAL;
2595                         goto err;
2596                 }
2597         }
2598
2599         rc = qed_ops->common->slowpath_start(edev, &params);
2600         if (rc) {
2601                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2602                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2603                                      (void *)eth_dev);
2604                 rc = -ENODEV;
2605                 goto err;
2606         }
2607
2608         rc = qed_ops->fill_dev_info(edev, &dev_info);
2609         if (rc) {
2610                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2611                 qed_ops->common->slowpath_stop(edev);
2612                 qed_ops->common->remove(edev);
2613                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2614                                      (void *)eth_dev);
2615                 rc = -ENODEV;
2616                 goto err;
2617         }
2618
2619         qede_alloc_etherdev(adapter, &dev_info);
2620
2621         if (do_once) {
2622                 qede_print_adapter_info(eth_dev);
2623                 do_once = false;
2624         }
2625
2626         adapter->ops->common->set_name(edev, edev->name);
2627
2628         if (!is_vf)
2629                 adapter->dev_info.num_mac_filters =
2630                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2631                                             ECORE_MAC);
2632         else
2633                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2634                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2635
2636         /* Allocate memory for storing MAC addr */
2637         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2638                                         (RTE_ETHER_ADDR_LEN *
2639                                         adapter->dev_info.num_mac_filters),
2640                                         RTE_CACHE_LINE_SIZE);
2641
2642         if (eth_dev->data->mac_addrs == NULL) {
2643                 DP_ERR(edev, "Failed to allocate MAC address\n");
2644                 qed_ops->common->slowpath_stop(edev);
2645                 qed_ops->common->remove(edev);
2646                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2647                                      (void *)eth_dev);
2648                 return -ENOMEM;
2649         }
2650
2651         if (!is_vf) {
2652                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2653                                 hw_info.hw_mac_addr,
2654                                 &eth_dev->data->mac_addrs[0]);
2655                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2656                                 &adapter->primary_mac);
2657         } else {
2658                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2659                                        &bulletin_change);
2660                 if (bulletin_change) {
2661                         is_mac_exist =
2662                             ecore_vf_bulletin_get_forced_mac(
2663                                                 ECORE_LEADING_HWFN(edev),
2664                                                 vf_mac,
2665                                                 &is_mac_forced);
2666                         if (is_mac_exist) {
2667                                 DP_INFO(edev, "VF macaddr received from PF\n");
2668                                 rte_ether_addr_copy(
2669                                         (struct rte_ether_addr *)&vf_mac,
2670                                         &eth_dev->data->mac_addrs[0]);
2671                                 rte_ether_addr_copy(
2672                                         &eth_dev->data->mac_addrs[0],
2673                                         &adapter->primary_mac);
2674                         } else {
2675                                 DP_ERR(edev, "No VF macaddr assigned\n");
2676                         }
2677                 }
2678         }
2679
2680         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2681
2682         adapter->num_tx_queues = 0;
2683         adapter->num_rx_queues = 0;
2684         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2685         SLIST_INIT(&adapter->vlan_list_head);
2686         SLIST_INIT(&adapter->uc_list_head);
2687         SLIST_INIT(&adapter->mc_list_head);
2688         adapter->mtu = RTE_ETHER_MTU;
2689         adapter->vport_started = false;
2690
2691         /* VF tunnel offloads is enabled by default in PF driver */
2692         adapter->vxlan.num_filters = 0;
2693         adapter->geneve.num_filters = 0;
2694         adapter->ipgre.num_filters = 0;
2695         if (is_vf) {
2696                 adapter->vxlan.enable = true;
2697                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2698                                              ETH_TUNNEL_FILTER_IVLAN;
2699                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2700                 adapter->geneve.enable = true;
2701                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2702                                               ETH_TUNNEL_FILTER_IVLAN;
2703                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2704                 adapter->ipgre.enable = true;
2705                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2706                                              ETH_TUNNEL_FILTER_IVLAN;
2707         } else {
2708                 adapter->vxlan.enable = false;
2709                 adapter->geneve.enable = false;
2710                 adapter->ipgre.enable = false;
2711         }
2712
2713         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2714                 adapter->primary_mac.addr_bytes[0],
2715                 adapter->primary_mac.addr_bytes[1],
2716                 adapter->primary_mac.addr_bytes[2],
2717                 adapter->primary_mac.addr_bytes[3],
2718                 adapter->primary_mac.addr_bytes[4],
2719                 adapter->primary_mac.addr_bytes[5]);
2720
2721         DP_INFO(edev, "Device initialized\n");
2722
2723         return 0;
2724
2725 err:
2726         if (do_once) {
2727                 qede_print_adapter_info(eth_dev);
2728                 do_once = false;
2729         }
2730         return rc;
2731 }
2732
2733 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2734 {
2735         return qede_common_dev_init(eth_dev, 1);
2736 }
2737
2738 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2739 {
2740         return qede_common_dev_init(eth_dev, 0);
2741 }
2742
2743 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2744 {
2745         struct qede_dev *qdev = eth_dev->data->dev_private;
2746         struct ecore_dev *edev = &qdev->edev;
2747
2748         PMD_INIT_FUNC_TRACE(edev);
2749
2750         /* only uninitialize in the primary process */
2751         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2752                 return 0;
2753
2754         /* safe to close dev here */
2755         qede_dev_close(eth_dev);
2756
2757         eth_dev->dev_ops = NULL;
2758         eth_dev->rx_pkt_burst = NULL;
2759         eth_dev->tx_pkt_burst = NULL;
2760
2761         return 0;
2762 }
2763
2764 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2765 {
2766         return qede_dev_common_uninit(eth_dev);
2767 }
2768
2769 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2770 {
2771         return qede_dev_common_uninit(eth_dev);
2772 }
2773
2774 static const struct rte_pci_id pci_id_qedevf_map[] = {
2775 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2776         {
2777                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2778         },
2779         {
2780                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2781         },
2782         {
2783                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2784         },
2785         {.vendor_id = 0,}
2786 };
2787
2788 static const struct rte_pci_id pci_id_qede_map[] = {
2789 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2790         {
2791                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2792         },
2793         {
2794                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2795         },
2796         {
2797                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2798         },
2799         {
2800                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2801         },
2802         {
2803                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2804         },
2805         {
2806                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2807         },
2808         {
2809                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2810         },
2811         {
2812                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2813         },
2814         {
2815                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2816         },
2817         {
2818                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2819         },
2820         {.vendor_id = 0,}
2821 };
2822
2823 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2824         struct rte_pci_device *pci_dev)
2825 {
2826         return rte_eth_dev_pci_generic_probe(pci_dev,
2827                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2828 }
2829
2830 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2831 {
2832         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2833 }
2834
2835 static struct rte_pci_driver rte_qedevf_pmd = {
2836         .id_table = pci_id_qedevf_map,
2837         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2838         .probe = qedevf_eth_dev_pci_probe,
2839         .remove = qedevf_eth_dev_pci_remove,
2840 };
2841
2842 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2843         struct rte_pci_device *pci_dev)
2844 {
2845         return rte_eth_dev_pci_generic_probe(pci_dev,
2846                 sizeof(struct qede_dev), qede_eth_dev_init);
2847 }
2848
2849 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2850 {
2851         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2852 }
2853
2854 static struct rte_pci_driver rte_qede_pmd = {
2855         .id_table = pci_id_qede_map,
2856         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2857         .probe = qede_eth_dev_pci_probe,
2858         .remove = qede_eth_dev_pci_remove,
2859 };
2860
2861 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2862 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2863 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2864 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2865 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2866 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2867
2868 RTE_INIT(qede_init_log)
2869 {
2870         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2871         if (qede_logtype_init >= 0)
2872                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2873         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2874         if (qede_logtype_driver >= 0)
2875                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2876 }