2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
12 #include <rte_kvargs.h>
15 int qede_logtype_init;
16 int qede_logtype_driver;
18 static const struct qed_eth_ops *qed_ops;
19 static int64_t timer_period = 1;
21 /* VXLAN tunnel classification mapping */
22 const struct _qede_udp_tunn_types {
23 uint16_t rte_filter_type;
24 enum ecore_filter_ucast_type qede_type;
25 enum ecore_tunn_clss qede_tunn_clss;
27 } qede_tunn_types[] = {
29 ETH_TUNNEL_FILTER_OMAC,
31 ECORE_TUNN_CLSS_MAC_VLAN,
35 ETH_TUNNEL_FILTER_TENID,
37 ECORE_TUNN_CLSS_MAC_VNI,
41 ETH_TUNNEL_FILTER_IMAC,
42 ECORE_FILTER_INNER_MAC,
43 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
47 ETH_TUNNEL_FILTER_IVLAN,
48 ECORE_FILTER_INNER_VLAN,
49 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
53 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
54 ECORE_FILTER_MAC_VNI_PAIR,
55 ECORE_TUNN_CLSS_MAC_VNI,
59 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
62 "outer-mac and inner-mac"
65 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
68 "outer-mac and inner-vlan"
71 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
72 ECORE_FILTER_INNER_MAC_VNI_PAIR,
73 ECORE_TUNN_CLSS_INNER_MAC_VNI,
77 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
83 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
84 ECORE_FILTER_INNER_PAIR,
85 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
86 "inner-mac and inner-vlan",
89 ETH_TUNNEL_FILTER_OIP,
95 ETH_TUNNEL_FILTER_IIP,
101 RTE_TUNNEL_FILTER_IMAC_IVLAN,
107 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
113 RTE_TUNNEL_FILTER_IMAC_TENID,
119 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
126 struct rte_qede_xstats_name_off {
127 char name[RTE_ETH_XSTATS_NAME_SIZE];
131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
133 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
134 {"rx_multicast_bytes",
135 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
136 {"rx_broadcast_bytes",
137 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
138 {"rx_unicast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
140 {"rx_multicast_packets",
141 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
142 {"rx_broadcast_packets",
143 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
146 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
147 {"tx_multicast_bytes",
148 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
149 {"tx_broadcast_bytes",
150 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
151 {"tx_unicast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
153 {"tx_multicast_packets",
154 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
155 {"tx_broadcast_packets",
156 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
158 {"rx_64_byte_packets",
159 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
160 {"rx_65_to_127_byte_packets",
161 offsetof(struct ecore_eth_stats_common,
162 rx_65_to_127_byte_packets)},
163 {"rx_128_to_255_byte_packets",
164 offsetof(struct ecore_eth_stats_common,
165 rx_128_to_255_byte_packets)},
166 {"rx_256_to_511_byte_packets",
167 offsetof(struct ecore_eth_stats_common,
168 rx_256_to_511_byte_packets)},
169 {"rx_512_to_1023_byte_packets",
170 offsetof(struct ecore_eth_stats_common,
171 rx_512_to_1023_byte_packets)},
172 {"rx_1024_to_1518_byte_packets",
173 offsetof(struct ecore_eth_stats_common,
174 rx_1024_to_1518_byte_packets)},
175 {"tx_64_byte_packets",
176 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
177 {"tx_65_to_127_byte_packets",
178 offsetof(struct ecore_eth_stats_common,
179 tx_65_to_127_byte_packets)},
180 {"tx_128_to_255_byte_packets",
181 offsetof(struct ecore_eth_stats_common,
182 tx_128_to_255_byte_packets)},
183 {"tx_256_to_511_byte_packets",
184 offsetof(struct ecore_eth_stats_common,
185 tx_256_to_511_byte_packets)},
186 {"tx_512_to_1023_byte_packets",
187 offsetof(struct ecore_eth_stats_common,
188 tx_512_to_1023_byte_packets)},
189 {"tx_1024_to_1518_byte_packets",
190 offsetof(struct ecore_eth_stats_common,
191 tx_1024_to_1518_byte_packets)},
193 {"rx_mac_crtl_frames",
194 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
195 {"tx_mac_control_frames",
196 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
198 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
200 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
201 {"rx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
203 {"tx_priority_flow_control_frames",
204 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
207 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
209 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
210 {"rx_carrier_errors",
211 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
212 {"rx_oversize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
215 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
216 {"rx_undersize_packet_errors",
217 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
218 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
219 {"rx_host_buffer_not_available",
220 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
221 /* Number of packets discarded because they are bigger than MTU */
222 {"rx_packet_too_big_discards",
223 offsetof(struct ecore_eth_stats_common,
224 packet_too_big_discard)},
225 {"rx_ttl_zero_discards",
226 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
227 {"rx_multi_function_tag_filter_discards",
228 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
229 {"rx_mac_filter_discards",
230 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
231 {"rx_hw_buffer_truncates",
232 offsetof(struct ecore_eth_stats_common, brb_truncates)},
233 {"rx_hw_buffer_discards",
234 offsetof(struct ecore_eth_stats_common, brb_discards)},
235 {"tx_error_drop_packets",
236 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
239 {"rx_mac_unicast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
241 {"rx_mac_multicast_packets",
242 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
243 {"rx_mac_broadcast_packets",
244 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
246 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
248 {"tx_mac_unicast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
250 {"tx_mac_multicast_packets",
251 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
252 {"tx_mac_broadcast_packets",
253 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
255 {"lro_coalesced_packets",
256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
257 {"lro_coalesced_events",
258 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
260 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
261 {"lro_not_coalesced_packets",
262 offsetof(struct ecore_eth_stats_common,
263 tpa_not_coalesced_pkts)},
264 {"lro_coalesced_bytes",
265 offsetof(struct ecore_eth_stats_common,
266 tpa_coalesced_bytes)},
269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
270 {"rx_1519_to_1522_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_1522_byte_packets)},
274 {"rx_1519_to_2047_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_1519_to_2047_byte_packets)},
278 {"rx_2048_to_4095_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_2048_to_4095_byte_packets)},
282 {"rx_4096_to_9216_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_4096_to_9216_byte_packets)},
286 {"rx_9217_to_16383_byte_packets",
287 offsetof(struct ecore_eth_stats, bb) +
288 offsetof(struct ecore_eth_stats_bb,
289 rx_9217_to_16383_byte_packets)},
291 {"tx_1519_to_2047_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_1519_to_2047_byte_packets)},
295 {"tx_2048_to_4095_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_2048_to_4095_byte_packets)},
299 {"tx_4096_to_9216_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_4096_to_9216_byte_packets)},
303 {"tx_9217_to_16383_byte_packets",
304 offsetof(struct ecore_eth_stats, bb) +
305 offsetof(struct ecore_eth_stats_bb,
306 tx_9217_to_16383_byte_packets)},
308 {"tx_lpi_entry_count",
309 offsetof(struct ecore_eth_stats, bb) +
310 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
311 {"tx_total_collisions",
312 offsetof(struct ecore_eth_stats, bb) +
313 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
317 {"rx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 rx_1519_to_max_byte_packets)},
321 {"tx_1519_to_max_byte_packets",
322 offsetof(struct ecore_eth_stats, ah) +
323 offsetof(struct ecore_eth_stats_ah,
324 tx_1519_to_max_byte_packets)},
327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
329 offsetof(struct qede_rx_queue, rx_segs)},
331 offsetof(struct qede_rx_queue, rx_hw_errors)},
332 {"rx_q_allocation_errors",
333 offsetof(struct qede_rx_queue, rx_alloc_errors)}
336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
338 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
342 qede_interrupt_handler(void *param)
344 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
345 struct qede_dev *qdev = eth_dev->data->dev_private;
346 struct ecore_dev *edev = &qdev->edev;
348 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
349 if (rte_intr_enable(eth_dev->intr_handle))
350 DP_ERR(edev, "rte_intr_enable failed\n");
354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
356 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
360 static void qede_print_adapter_info(struct qede_dev *qdev)
362 struct ecore_dev *edev = &qdev->edev;
363 struct qed_dev_info *info = &qdev->dev_info.common;
364 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
365 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
367 DP_INFO(edev, "*********************************\n");
368 DP_INFO(edev, " DPDK version:%s\n", rte_version());
369 DP_INFO(edev, " Chip details : %s %c%d\n",
370 ECORE_IS_BB(edev) ? "BB" : "AH",
371 'A' + edev->chip_rev,
372 (int)edev->chip_metal);
373 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
374 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
375 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
376 ver_str, QEDE_PMD_VERSION);
377 DP_INFO(edev, " Driver version : %s\n", drv_ver);
378 DP_INFO(edev, " Firmware version : %s\n", ver_str);
380 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
382 (info->mfw_rev >> 24) & 0xff,
383 (info->mfw_rev >> 16) & 0xff,
384 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
385 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
386 DP_INFO(edev, " Firmware file : %s\n", fw_file);
387 DP_INFO(edev, "*********************************\n");
390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
393 unsigned int i = 0, j = 0, qid;
394 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
395 struct qede_tx_queue *txq;
397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
400 RTE_ETHDEV_QUEUE_STAT_CNTRS);
401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
402 RTE_ETHDEV_QUEUE_STAT_CNTRS);
405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
406 offsetof(struct qede_rx_queue, rcv_pkts), 0,
408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
409 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
417 OSAL_MEMSET((((char *)
418 (qdev->fp_array[qid].rxq)) +
419 qede_rxq_xstats_strings[j].offset),
424 if (i == rxq_stat_cntrs)
431 txq = qdev->fp_array[qid].txq;
433 OSAL_MEMSET((uint64_t *)(uintptr_t)
434 (((uint64_t)(uintptr_t)(txq)) +
435 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
439 if (i == txq_stat_cntrs)
445 qede_stop_vport(struct ecore_dev *edev)
447 struct ecore_hwfn *p_hwfn;
453 for_each_hwfn(edev, i) {
454 p_hwfn = &edev->hwfns[i];
455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
457 if (rc != ECORE_SUCCESS) {
458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
463 DP_INFO(edev, "vport stopped\n");
469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
472 struct ecore_sp_vport_start_params params;
473 struct ecore_hwfn *p_hwfn;
477 if (qdev->vport_started)
478 qede_stop_vport(edev);
480 memset(¶ms, 0, sizeof(params));
483 /* @DPDK - Disable FW placement */
484 params.zero_placement_offset = 1;
485 for_each_hwfn(edev, i) {
486 p_hwfn = &edev->hwfns[i];
487 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
488 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
489 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
490 if (rc != ECORE_SUCCESS) {
491 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
495 ecore_reset_vport_stats(edev);
496 qdev->vport_started = true;
497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
502 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
503 #define QEDE_VF_TX_SWITCHING "vf_tx_switching"
505 /* Activate or deactivate vport via vport-update */
506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
508 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
509 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
510 struct ecore_sp_vport_update_params params;
511 struct ecore_hwfn *p_hwfn;
515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
517 params.update_vport_active_rx_flg = 1;
518 params.update_vport_active_tx_flg = 1;
519 params.vport_active_rx_flg = flg;
520 params.vport_active_tx_flg = flg;
521 if (!qdev->enable_tx_switching) {
522 if ((QEDE_NPAR_TX_SWITCHING != NULL) ||
523 ((QEDE_VF_TX_SWITCHING != NULL) && IS_VF(edev))) {
524 params.update_tx_switching_flg = 1;
525 params.tx_switching_flg = !flg;
526 DP_INFO(edev, "%s tx-switching is disabled\n",
527 QEDE_NPAR_TX_SWITCHING ? "NPAR" : "VF");
530 for_each_hwfn(edev, i) {
531 p_hwfn = &edev->hwfns[i];
532 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
533 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
534 ECORE_SPQ_MODE_EBLOCK, NULL);
535 if (rc != ECORE_SUCCESS) {
536 DP_ERR(edev, "Failed to update vport\n");
540 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
546 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
547 uint16_t mtu, bool enable)
549 /* Enable LRO in split mode */
550 sge_tpa_params->tpa_ipv4_en_flg = enable;
551 sge_tpa_params->tpa_ipv6_en_flg = enable;
552 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
553 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
554 /* set if tpa enable changes */
555 sge_tpa_params->update_tpa_en_flg = 1;
556 /* set if tpa parameters should be handled */
557 sge_tpa_params->update_tpa_param_flg = enable;
559 sge_tpa_params->max_buffers_per_cqe = 20;
560 /* Enable TPA in split mode. In this mode each TPA segment
561 * starts on the new BD, so there is one BD per segment.
563 sge_tpa_params->tpa_pkt_split_flg = 1;
564 sge_tpa_params->tpa_hdr_data_split_flg = 0;
565 sge_tpa_params->tpa_gro_consistent_flg = 0;
566 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
567 sge_tpa_params->tpa_max_size = 0x7FFF;
568 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
569 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
572 /* Enable/disable LRO via vport-update */
573 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
575 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
576 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
577 struct ecore_sp_vport_update_params params;
578 struct ecore_sge_tpa_params tpa_params;
579 struct ecore_hwfn *p_hwfn;
583 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
584 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
585 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
587 params.sge_tpa_params = &tpa_params;
588 for_each_hwfn(edev, i) {
589 p_hwfn = &edev->hwfns[i];
590 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
591 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
592 ECORE_SPQ_MODE_EBLOCK, NULL);
593 if (rc != ECORE_SUCCESS) {
594 DP_ERR(edev, "Failed to update LRO\n");
598 qdev->enable_lro = flg;
599 eth_dev->data->lro = flg;
601 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
606 /* Update MTU via vport-update without doing port restart.
607 * The vport must be deactivated before calling this API.
609 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
611 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
612 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
613 struct ecore_sp_vport_update_params params;
614 struct ecore_hwfn *p_hwfn;
618 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
622 for_each_hwfn(edev, i) {
623 p_hwfn = &edev->hwfns[i];
624 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
625 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
626 ECORE_SPQ_MODE_EBLOCK, NULL);
627 if (rc != ECORE_SUCCESS) {
628 DP_ERR(edev, "Failed to update MTU\n");
632 DP_INFO(edev, "MTU updated to %u\n", mtu);
637 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
639 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
640 ucast->is_rx_filter = true;
641 ucast->is_tx_filter = true;
642 /* ucast->assert_on_error = true; - For debug */
646 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
647 enum qed_filter_rx_mode_type type)
649 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
650 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
651 struct ecore_filter_accept_flags flags;
653 memset(&flags, 0, sizeof(flags));
655 flags.update_rx_mode_config = 1;
656 flags.update_tx_mode_config = 1;
657 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
658 ECORE_ACCEPT_MCAST_MATCHED |
661 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
662 ECORE_ACCEPT_MCAST_MATCHED |
665 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
666 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
668 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
669 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
671 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
672 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
673 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
674 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
675 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
676 ECORE_ACCEPT_MCAST_UNMATCHED;
679 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
680 ECORE_SPQ_MODE_CB, NULL);
684 qede_tunnel_update(struct qede_dev *qdev,
685 struct ecore_tunnel_info *tunn_info)
687 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
688 enum _ecore_status_t rc = ECORE_INVAL;
689 struct ecore_hwfn *p_hwfn;
690 struct ecore_ptt *p_ptt;
693 for_each_hwfn(edev, i) {
694 p_hwfn = &edev->hwfns[i];
696 p_ptt = ecore_ptt_acquire(p_hwfn);
698 DP_ERR(p_hwfn, "Can't acquire PTT\n");
705 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
706 tunn_info, ECORE_SPQ_MODE_CB, NULL);
708 ecore_ptt_release(p_hwfn, p_ptt);
710 if (rc != ECORE_SUCCESS)
718 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
721 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
722 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
723 enum _ecore_status_t rc = ECORE_INVAL;
724 struct ecore_tunnel_info tunn;
726 if (qdev->vxlan.enable == enable)
727 return ECORE_SUCCESS;
729 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
730 tunn.vxlan.b_update_mode = true;
731 tunn.vxlan.b_mode_enabled = enable;
732 tunn.b_update_rx_cls = true;
733 tunn.b_update_tx_cls = true;
734 tunn.vxlan.tun_cls = clss;
736 tunn.vxlan_port.b_update_port = true;
737 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
739 rc = qede_tunnel_update(qdev, &tunn);
740 if (rc == ECORE_SUCCESS) {
741 qdev->vxlan.enable = enable;
742 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
743 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
744 enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
746 DP_ERR(edev, "Failed to update tunn_clss %u\n",
754 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
757 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
758 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
759 enum _ecore_status_t rc = ECORE_INVAL;
760 struct ecore_tunnel_info tunn;
762 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
763 tunn.l2_geneve.b_update_mode = true;
764 tunn.l2_geneve.b_mode_enabled = enable;
765 tunn.ip_geneve.b_update_mode = true;
766 tunn.ip_geneve.b_mode_enabled = enable;
767 tunn.l2_geneve.tun_cls = clss;
768 tunn.ip_geneve.tun_cls = clss;
769 tunn.b_update_rx_cls = true;
770 tunn.b_update_tx_cls = true;
772 tunn.geneve_port.b_update_port = true;
773 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
775 rc = qede_tunnel_update(qdev, &tunn);
776 if (rc == ECORE_SUCCESS) {
777 qdev->geneve.enable = enable;
778 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
779 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
780 enable ? "enabled" : "disabled", qdev->geneve.udp_port);
782 DP_ERR(edev, "Failed to update tunn_clss %u\n",
790 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
793 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
794 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
795 enum _ecore_status_t rc = ECORE_INVAL;
796 struct ecore_tunnel_info tunn;
798 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
799 tunn.ip_gre.b_update_mode = true;
800 tunn.ip_gre.b_mode_enabled = enable;
801 tunn.ip_gre.tun_cls = clss;
802 tunn.ip_gre.tun_cls = clss;
803 tunn.b_update_rx_cls = true;
804 tunn.b_update_tx_cls = true;
806 rc = qede_tunnel_update(qdev, &tunn);
807 if (rc == ECORE_SUCCESS) {
808 qdev->ipgre.enable = enable;
809 DP_INFO(edev, "IPGRE is %s\n",
810 enable ? "enabled" : "disabled");
812 DP_ERR(edev, "Failed to update tunn_clss %u\n",
820 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
821 enum rte_eth_tunnel_type tunn_type, bool enable)
826 case RTE_TUNNEL_TYPE_VXLAN:
827 rc = qede_vxlan_enable(eth_dev, clss, enable);
829 case RTE_TUNNEL_TYPE_GENEVE:
830 rc = qede_geneve_enable(eth_dev, clss, enable);
832 case RTE_TUNNEL_TYPE_IP_IN_GRE:
833 rc = qede_ipgre_enable(eth_dev, clss, enable);
844 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
847 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
848 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
849 struct qede_ucast_entry *tmp = NULL;
850 struct qede_ucast_entry *u;
851 struct ether_addr *mac_addr;
853 mac_addr = (struct ether_addr *)ucast->mac;
855 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
856 if ((memcmp(mac_addr, &tmp->mac,
857 ETHER_ADDR_LEN) == 0) &&
858 ucast->vni == tmp->vni &&
859 ucast->vlan == tmp->vlan) {
860 DP_ERR(edev, "Unicast MAC is already added"
861 " with vlan = %u, vni = %u\n",
862 ucast->vlan, ucast->vni);
866 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
867 RTE_CACHE_LINE_SIZE);
869 DP_ERR(edev, "Did not allocate memory for ucast\n");
872 ether_addr_copy(mac_addr, &u->mac);
873 u->vlan = ucast->vlan;
875 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
878 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
879 if ((memcmp(mac_addr, &tmp->mac,
880 ETHER_ADDR_LEN) == 0) &&
881 ucast->vlan == tmp->vlan &&
882 ucast->vni == tmp->vni)
886 DP_INFO(edev, "Unicast MAC is not found\n");
889 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
897 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
900 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
901 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
902 struct ether_addr *mac_addr;
903 struct qede_mcast_entry *tmp = NULL;
904 struct qede_mcast_entry *m;
906 mac_addr = (struct ether_addr *)mcast->mac;
908 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
909 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
911 "Multicast MAC is already added\n");
915 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
916 RTE_CACHE_LINE_SIZE);
919 "Did not allocate memory for mcast\n");
922 ether_addr_copy(mac_addr, &m->mac);
923 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
926 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
927 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
931 DP_INFO(edev, "Multicast mac is not found\n");
934 SLIST_REMOVE(&qdev->mc_list_head, tmp,
935 qede_mcast_entry, list);
942 static enum _ecore_status_t
943 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
946 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
947 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
948 enum _ecore_status_t rc;
949 struct ecore_filter_mcast mcast;
950 struct qede_mcast_entry *tmp;
954 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
956 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
958 "Mcast filter table limit exceeded, "
959 "Please enable mcast promisc mode\n");
963 rc = qede_mcast_filter(eth_dev, ucast, add);
965 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
966 memset(&mcast, 0, sizeof(mcast));
967 mcast.num_mc_addrs = qdev->num_mc_addr;
968 mcast.opcode = ECORE_FILTER_ADD;
969 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
970 ether_addr_copy(&tmp->mac,
971 (struct ether_addr *)&mcast.mac[j]);
974 rc = ecore_filter_mcast_cmd(edev, &mcast,
975 ECORE_SPQ_MODE_CB, NULL);
977 if (rc != ECORE_SUCCESS) {
978 DP_ERR(edev, "Failed to add multicast filter"
979 " rc = %d, op = %d\n", rc, add);
981 } else { /* Unicast */
983 if (qdev->num_uc_addr >=
984 qdev->dev_info.num_mac_filters) {
986 "Ucast filter table limit exceeded,"
987 " Please enable promisc mode\n");
991 rc = qede_ucast_filter(eth_dev, ucast, add);
993 rc = ecore_filter_ucast_cmd(edev, ucast,
994 ECORE_SPQ_MODE_CB, NULL);
995 if (rc != ECORE_SUCCESS) {
996 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
1005 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
1006 __rte_unused uint32_t index, __rte_unused uint32_t pool)
1008 struct ecore_filter_ucast ucast;
1011 qede_set_ucast_cmn_params(&ucast);
1012 ucast.type = ECORE_FILTER_MAC;
1013 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
1014 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
1019 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
1021 struct qede_dev *qdev = eth_dev->data->dev_private;
1022 struct ecore_dev *edev = &qdev->edev;
1023 struct ecore_filter_ucast ucast;
1025 PMD_INIT_FUNC_TRACE(edev);
1027 if (index >= qdev->dev_info.num_mac_filters) {
1028 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1029 index, qdev->dev_info.num_mac_filters);
1033 qede_set_ucast_cmn_params(&ucast);
1034 ucast.opcode = ECORE_FILTER_REMOVE;
1035 ucast.type = ECORE_FILTER_MAC;
1037 /* Use the index maintained by rte */
1038 ether_addr_copy(ð_dev->data->mac_addrs[index],
1039 (struct ether_addr *)&ucast.mac);
1041 qede_mac_int_ops(eth_dev, &ucast, false);
1045 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1047 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1048 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1050 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1051 mac_addr->addr_bytes)) {
1052 DP_ERR(edev, "Setting MAC address is not allowed\n");
1053 ether_addr_copy(&qdev->primary_mac,
1054 ð_dev->data->mac_addrs[0]);
1058 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1061 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1063 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1064 struct ecore_sp_vport_update_params params;
1065 struct ecore_hwfn *p_hwfn;
1069 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1070 params.vport_id = 0;
1071 params.update_accept_any_vlan_flg = 1;
1072 params.accept_any_vlan = flg;
1073 for_each_hwfn(edev, i) {
1074 p_hwfn = &edev->hwfns[i];
1075 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1076 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1077 ECORE_SPQ_MODE_EBLOCK, NULL);
1078 if (rc != ECORE_SUCCESS) {
1079 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1084 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1087 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1089 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1090 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1091 struct ecore_sp_vport_update_params params;
1092 struct ecore_hwfn *p_hwfn;
1096 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1097 params.vport_id = 0;
1098 params.update_inner_vlan_removal_flg = 1;
1099 params.inner_vlan_removal_flg = flg;
1100 for_each_hwfn(edev, i) {
1101 p_hwfn = &edev->hwfns[i];
1102 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1103 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1104 ECORE_SPQ_MODE_EBLOCK, NULL);
1105 if (rc != ECORE_SUCCESS) {
1106 DP_ERR(edev, "Failed to update vport\n");
1111 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1115 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1116 uint16_t vlan_id, int on)
1118 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1119 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1120 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1121 struct qede_vlan_entry *tmp = NULL;
1122 struct qede_vlan_entry *vlan;
1123 struct ecore_filter_ucast ucast;
1127 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1128 DP_ERR(edev, "Reached max VLAN filter limit"
1129 " enabling accept_any_vlan\n");
1130 qede_config_accept_any_vlan(qdev, true);
1134 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1135 if (tmp->vid == vlan_id) {
1136 DP_ERR(edev, "VLAN %u already configured\n",
1142 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1143 RTE_CACHE_LINE_SIZE);
1146 DP_ERR(edev, "Did not allocate memory for VLAN\n");
1150 qede_set_ucast_cmn_params(&ucast);
1151 ucast.opcode = ECORE_FILTER_ADD;
1152 ucast.type = ECORE_FILTER_VLAN;
1153 ucast.vlan = vlan_id;
1154 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1157 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1161 vlan->vid = vlan_id;
1162 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1163 qdev->configured_vlans++;
1164 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1165 vlan_id, qdev->configured_vlans);
1168 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1169 if (tmp->vid == vlan_id)
1174 if (qdev->configured_vlans == 0) {
1176 "No VLAN filters configured yet\n");
1180 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1184 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1186 qede_set_ucast_cmn_params(&ucast);
1187 ucast.opcode = ECORE_FILTER_REMOVE;
1188 ucast.type = ECORE_FILTER_VLAN;
1189 ucast.vlan = vlan_id;
1190 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1193 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1196 qdev->configured_vlans--;
1197 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1198 vlan_id, qdev->configured_vlans);
1205 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1207 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1208 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1209 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1211 if (mask & ETH_VLAN_STRIP_MASK) {
1212 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1213 (void)qede_vlan_stripping(eth_dev, 1);
1215 (void)qede_vlan_stripping(eth_dev, 0);
1218 if (mask & ETH_VLAN_FILTER_MASK) {
1219 /* VLAN filtering kicks in when a VLAN is added */
1220 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1221 qede_vlan_filter_set(eth_dev, 0, 1);
1223 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1225 " Please remove existing VLAN filters"
1226 " before disabling VLAN filtering\n");
1227 /* Signal app that VLAN filtering is still
1230 eth_dev->data->dev_conf.rxmode.offloads |=
1231 DEV_RX_OFFLOAD_VLAN_FILTER;
1233 qede_vlan_filter_set(eth_dev, 0, 0);
1238 if (mask & ETH_VLAN_EXTEND_MASK)
1239 DP_ERR(edev, "Extend VLAN not supported\n");
1241 qdev->vlan_offload_mask = mask;
1243 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1248 static void qede_prandom_bytes(uint32_t *buff)
1252 srand((unsigned int)time(NULL));
1253 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1257 int qede_config_rss(struct rte_eth_dev *eth_dev)
1259 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1260 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1261 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1262 struct rte_eth_rss_reta_entry64 reta_conf[2];
1263 struct rte_eth_rss_conf rss_conf;
1264 uint32_t i, id, pos, q;
1266 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1267 if (!rss_conf.rss_key) {
1268 DP_INFO(edev, "Applying driver default key\n");
1269 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1270 qede_prandom_bytes(&def_rss_key[0]);
1271 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1274 /* Configure RSS hash */
1275 if (qede_rss_hash_update(eth_dev, &rss_conf))
1278 /* Configure default RETA */
1279 memset(reta_conf, 0, sizeof(reta_conf));
1280 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1281 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1283 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1284 id = i / RTE_RETA_GROUP_SIZE;
1285 pos = i % RTE_RETA_GROUP_SIZE;
1286 q = i % QEDE_RSS_COUNT(qdev);
1287 reta_conf[id].reta[pos] = q;
1289 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1290 ECORE_RSS_IND_TABLE_SIZE))
1296 static void qede_fastpath_start(struct ecore_dev *edev)
1298 struct ecore_hwfn *p_hwfn;
1301 for_each_hwfn(edev, i) {
1302 p_hwfn = &edev->hwfns[i];
1303 ecore_hw_start_fastpath(p_hwfn);
1307 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1309 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1310 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1311 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1313 PMD_INIT_FUNC_TRACE(edev);
1315 /* Configure TPA parameters */
1316 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1317 if (qede_enable_tpa(eth_dev, true))
1319 /* Enable scatter mode for LRO */
1320 if (!eth_dev->data->scattered_rx)
1321 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1325 if (qede_start_queues(eth_dev))
1329 qede_reset_queue_stats(qdev, true);
1331 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1332 * enabling RSS. Hence RSS configuration is deferred upto this point.
1333 * Also, we would like to retain similar behavior in PF case, so we
1334 * don't do PF/VF specific check here.
1336 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1337 if (qede_config_rss(eth_dev))
1341 if (qede_activate_vport(eth_dev, true))
1344 /* Update link status */
1345 qede_link_update(eth_dev, 0);
1347 /* Start/resume traffic */
1348 qede_fastpath_start(edev);
1350 DP_INFO(edev, "Device started\n");
1354 DP_ERR(edev, "Device start fails\n");
1355 return -1; /* common error code is < 0 */
1358 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1360 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1361 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1363 PMD_INIT_FUNC_TRACE(edev);
1366 if (qede_activate_vport(eth_dev, false))
1369 if (qdev->enable_lro)
1370 qede_enable_tpa(eth_dev, false);
1373 qede_stop_queues(eth_dev);
1375 /* Disable traffic */
1376 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1379 qede_mac_addr_remove(eth_dev, 0);
1381 DP_INFO(edev, "Device is stopped\n");
1384 const char *valid_args[] = {
1385 QEDE_NPAR_TX_SWITCHING,
1386 QEDE_VF_TX_SWITCHING,
1390 static int qede_args_check(const char *key, const char *val, void *opaque)
1394 struct rte_eth_dev *eth_dev = opaque;
1395 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1396 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1399 tmp = strtoul(val, NULL, 0);
1401 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1405 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1406 (strcmp(QEDE_VF_TX_SWITCHING, key) == 0))
1407 qdev->enable_tx_switching = !!tmp;
1412 static int qede_args(struct rte_eth_dev *eth_dev)
1414 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1415 struct rte_kvargs *kvlist;
1416 struct rte_devargs *devargs;
1420 devargs = pci_dev->device.devargs;
1422 return 0; /* return success */
1424 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1428 /* Process parameters. */
1429 for (i = 0; (valid_args[i] != NULL); ++i) {
1430 if (rte_kvargs_count(kvlist, valid_args[i])) {
1431 ret = rte_kvargs_process(kvlist, valid_args[i],
1432 qede_args_check, eth_dev);
1433 if (ret != ECORE_SUCCESS) {
1434 rte_kvargs_free(kvlist);
1439 rte_kvargs_free(kvlist);
1444 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1446 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1447 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1448 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1451 PMD_INIT_FUNC_TRACE(edev);
1453 /* Check requirements for 100G mode */
1454 if (ECORE_IS_CMT(edev)) {
1455 if (eth_dev->data->nb_rx_queues < 2 ||
1456 eth_dev->data->nb_tx_queues < 2) {
1457 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1461 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1462 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1464 "100G mode needs even no. of RX/TX queues\n");
1469 /* We need to have min 1 RX queue.There is no min check in
1470 * rte_eth_dev_configure(), so we are checking it here.
1472 if (eth_dev->data->nb_rx_queues == 0) {
1473 DP_ERR(edev, "Minimum one RX queue is required\n");
1477 /* Enable Tx switching by default */
1478 qdev->enable_tx_switching = 1;
1480 /* Parse devargs and fix up rxmode */
1481 if (qede_args(eth_dev))
1484 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1485 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1486 DP_ERR(edev, "Unsupported multi-queue mode\n");
1489 /* Flow director mode check */
1490 if (qede_check_fdir_support(eth_dev))
1493 qede_dealloc_fp_resc(eth_dev);
1494 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1495 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1496 if (qede_alloc_fp_resc(qdev))
1499 /* If jumbo enabled adjust MTU */
1500 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1501 eth_dev->data->mtu =
1502 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1503 ETHER_HDR_LEN - ETHER_CRC_LEN;
1505 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1506 eth_dev->data->scattered_rx = 1;
1508 if (qede_start_vport(qdev, eth_dev->data->mtu))
1511 qdev->mtu = eth_dev->data->mtu;
1513 /* Enable VLAN offloads by default */
1514 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1515 ETH_VLAN_FILTER_MASK |
1516 ETH_VLAN_EXTEND_MASK);
1520 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1521 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1526 /* Info about HW descriptor ring limitations */
1527 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1528 .nb_max = 0x8000, /* 32K */
1530 .nb_align = 128 /* lowest common multiple */
1533 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1534 .nb_max = 0x8000, /* 32K */
1537 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1538 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1542 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1543 struct rte_eth_dev_info *dev_info)
1545 struct qede_dev *qdev = eth_dev->data->dev_private;
1546 struct ecore_dev *edev = &qdev->edev;
1547 struct qed_link_output link;
1548 uint32_t speed_cap = 0;
1550 PMD_INIT_FUNC_TRACE(edev);
1552 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1553 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1554 dev_info->rx_desc_lim = qede_rx_desc_lim;
1555 dev_info->tx_desc_lim = qede_tx_desc_lim;
1558 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1559 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1561 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1562 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1563 dev_info->max_tx_queues = dev_info->max_rx_queues;
1565 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1566 dev_info->max_vfs = 0;
1567 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1568 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1569 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1570 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1571 DEV_RX_OFFLOAD_UDP_CKSUM |
1572 DEV_RX_OFFLOAD_TCP_CKSUM |
1573 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1574 DEV_RX_OFFLOAD_TCP_LRO |
1575 DEV_RX_OFFLOAD_CRC_STRIP |
1576 DEV_RX_OFFLOAD_SCATTER |
1577 DEV_RX_OFFLOAD_JUMBO_FRAME |
1578 DEV_RX_OFFLOAD_VLAN_FILTER |
1579 DEV_RX_OFFLOAD_VLAN_STRIP);
1580 dev_info->rx_queue_offload_capa = 0;
1582 /* TX offloads are on a per-packet basis, so it is applicable
1583 * to both at port and queue levels.
1585 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1586 DEV_TX_OFFLOAD_IPV4_CKSUM |
1587 DEV_TX_OFFLOAD_UDP_CKSUM |
1588 DEV_TX_OFFLOAD_TCP_CKSUM |
1589 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1590 DEV_TX_OFFLOAD_QINQ_INSERT |
1591 DEV_TX_OFFLOAD_MULTI_SEGS |
1592 DEV_TX_OFFLOAD_TCP_TSO |
1593 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1594 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1595 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1597 dev_info->default_txconf = (struct rte_eth_txconf) {
1598 .txq_flags = DEV_TX_OFFLOAD_MULTI_SEGS,
1601 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1602 /* Packets are always dropped if no descriptors are available */
1604 /* The below RX offloads are always enabled */
1605 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP |
1606 DEV_RX_OFFLOAD_IPV4_CKSUM |
1607 DEV_RX_OFFLOAD_TCP_CKSUM |
1608 DEV_RX_OFFLOAD_UDP_CKSUM),
1611 memset(&link, 0, sizeof(struct qed_link_output));
1612 qdev->ops->common->get_link(edev, &link);
1613 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1614 speed_cap |= ETH_LINK_SPEED_1G;
1615 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1616 speed_cap |= ETH_LINK_SPEED_10G;
1617 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1618 speed_cap |= ETH_LINK_SPEED_25G;
1619 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1620 speed_cap |= ETH_LINK_SPEED_40G;
1621 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1622 speed_cap |= ETH_LINK_SPEED_50G;
1623 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1624 speed_cap |= ETH_LINK_SPEED_100G;
1625 dev_info->speed_capa = speed_cap;
1628 /* return 0 means link status changed, -1 means not changed */
1630 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1632 struct qede_dev *qdev = eth_dev->data->dev_private;
1633 struct ecore_dev *edev = &qdev->edev;
1634 uint16_t link_duplex;
1635 struct qed_link_output link;
1636 struct rte_eth_link *curr = ð_dev->data->dev_link;
1638 memset(&link, 0, sizeof(struct qed_link_output));
1639 qdev->ops->common->get_link(edev, &link);
1642 curr->link_speed = link.speed;
1645 switch (link.duplex) {
1646 case QEDE_DUPLEX_HALF:
1647 link_duplex = ETH_LINK_HALF_DUPLEX;
1649 case QEDE_DUPLEX_FULL:
1650 link_duplex = ETH_LINK_FULL_DUPLEX;
1652 case QEDE_DUPLEX_UNKNOWN:
1656 curr->link_duplex = link_duplex;
1659 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1662 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1663 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1665 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1666 curr->link_speed, curr->link_duplex,
1667 curr->link_autoneg, curr->link_status);
1669 /* return 0 means link status changed, -1 means not changed */
1670 return ((curr->link_status == link.link_up) ? -1 : 0);
1673 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1675 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1676 struct qede_dev *qdev = eth_dev->data->dev_private;
1677 struct ecore_dev *edev = &qdev->edev;
1679 PMD_INIT_FUNC_TRACE(edev);
1682 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1684 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1685 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1687 qed_configure_filter_rx_mode(eth_dev, type);
1690 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1692 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1693 struct qede_dev *qdev = eth_dev->data->dev_private;
1694 struct ecore_dev *edev = &qdev->edev;
1696 PMD_INIT_FUNC_TRACE(edev);
1699 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1700 qed_configure_filter_rx_mode(eth_dev,
1701 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1703 qed_configure_filter_rx_mode(eth_dev,
1704 QED_FILTER_RX_MODE_TYPE_REGULAR);
1707 static void qede_poll_sp_sb_cb(void *param)
1709 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1710 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1711 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1714 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1715 qede_interrupt_action(&edev->hwfns[1]);
1717 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1721 DP_ERR(edev, "Unable to start periodic"
1722 " timer rc %d\n", rc);
1723 assert(false && "Unable to start periodic timer");
1727 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1729 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1730 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1731 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1733 PMD_INIT_FUNC_TRACE(edev);
1735 /* dev_stop() shall cleanup fp resources in hw but without releasing
1736 * dma memories and sw structures so that dev_start() can be called
1737 * by the app without reconfiguration. However, in dev_close() we
1738 * can release all the resources and device can be brought up newly
1740 if (eth_dev->data->dev_started)
1741 qede_dev_stop(eth_dev);
1743 qede_stop_vport(edev);
1744 qdev->vport_started = false;
1745 qede_fdir_dealloc_resc(eth_dev);
1746 qede_dealloc_fp_resc(eth_dev);
1748 eth_dev->data->nb_rx_queues = 0;
1749 eth_dev->data->nb_tx_queues = 0;
1751 /* Bring the link down */
1752 qede_dev_set_link_state(eth_dev, false);
1753 qdev->ops->common->slowpath_stop(edev);
1754 qdev->ops->common->remove(edev);
1755 rte_intr_disable(&pci_dev->intr_handle);
1756 rte_intr_callback_unregister(&pci_dev->intr_handle,
1757 qede_interrupt_handler, (void *)eth_dev);
1758 if (ECORE_IS_CMT(edev))
1759 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1763 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1765 struct qede_dev *qdev = eth_dev->data->dev_private;
1766 struct ecore_dev *edev = &qdev->edev;
1767 struct ecore_eth_stats stats;
1768 unsigned int i = 0, j = 0, qid;
1769 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1770 struct qede_tx_queue *txq;
1772 ecore_get_vport_stats(edev, &stats);
1775 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1776 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1778 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1779 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1781 eth_stats->ierrors = stats.common.rx_crc_errors +
1782 stats.common.rx_align_errors +
1783 stats.common.rx_carrier_errors +
1784 stats.common.rx_oversize_packets +
1785 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1787 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1789 eth_stats->imissed = stats.common.mftag_filter_discards +
1790 stats.common.mac_filter_discards +
1791 stats.common.no_buff_discards +
1792 stats.common.brb_truncates + stats.common.brb_discards;
1795 eth_stats->opackets = stats.common.tx_ucast_pkts +
1796 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1798 eth_stats->obytes = stats.common.tx_ucast_bytes +
1799 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1801 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1804 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1805 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1806 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1807 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1808 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1809 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1810 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1811 "Not all the queue stats will be displayed. Set"
1812 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1813 " appropriately and retry.\n");
1816 eth_stats->q_ipackets[i] =
1818 ((char *)(qdev->fp_array[qid].rxq)) +
1819 offsetof(struct qede_rx_queue,
1821 eth_stats->q_errors[i] =
1823 ((char *)(qdev->fp_array[qid].rxq)) +
1824 offsetof(struct qede_rx_queue,
1827 ((char *)(qdev->fp_array[qid].rxq)) +
1828 offsetof(struct qede_rx_queue,
1831 if (i == rxq_stat_cntrs)
1836 txq = qdev->fp_array[qid].txq;
1837 eth_stats->q_opackets[j] =
1838 *((uint64_t *)(uintptr_t)
1839 (((uint64_t)(uintptr_t)(txq)) +
1840 offsetof(struct qede_tx_queue,
1843 if (j == txq_stat_cntrs)
1851 qede_get_xstats_count(struct qede_dev *qdev) {
1852 if (ECORE_IS_BB(&qdev->edev))
1853 return RTE_DIM(qede_xstats_strings) +
1854 RTE_DIM(qede_bb_xstats_strings) +
1855 (RTE_DIM(qede_rxq_xstats_strings) *
1856 RTE_MIN(QEDE_RSS_COUNT(qdev),
1857 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1859 return RTE_DIM(qede_xstats_strings) +
1860 RTE_DIM(qede_ah_xstats_strings) +
1861 (RTE_DIM(qede_rxq_xstats_strings) *
1862 RTE_MIN(QEDE_RSS_COUNT(qdev),
1863 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1867 qede_get_xstats_names(struct rte_eth_dev *dev,
1868 struct rte_eth_xstat_name *xstats_names,
1869 __rte_unused unsigned int limit)
1871 struct qede_dev *qdev = dev->data->dev_private;
1872 struct ecore_dev *edev = &qdev->edev;
1873 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1874 unsigned int i, qid, stat_idx = 0;
1875 unsigned int rxq_stat_cntrs;
1877 if (xstats_names != NULL) {
1878 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1879 snprintf(xstats_names[stat_idx].name,
1880 sizeof(xstats_names[stat_idx].name),
1882 qede_xstats_strings[i].name);
1886 if (ECORE_IS_BB(edev)) {
1887 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1888 snprintf(xstats_names[stat_idx].name,
1889 sizeof(xstats_names[stat_idx].name),
1891 qede_bb_xstats_strings[i].name);
1895 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1896 snprintf(xstats_names[stat_idx].name,
1897 sizeof(xstats_names[stat_idx].name),
1899 qede_ah_xstats_strings[i].name);
1904 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1905 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1906 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1907 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1908 snprintf(xstats_names[stat_idx].name,
1909 sizeof(xstats_names[stat_idx].name),
1911 qede_rxq_xstats_strings[i].name, qid,
1912 qede_rxq_xstats_strings[i].name + 4);
1922 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1925 struct qede_dev *qdev = dev->data->dev_private;
1926 struct ecore_dev *edev = &qdev->edev;
1927 struct ecore_eth_stats stats;
1928 const unsigned int num = qede_get_xstats_count(qdev);
1929 unsigned int i, qid, stat_idx = 0;
1930 unsigned int rxq_stat_cntrs;
1935 ecore_get_vport_stats(edev, &stats);
1937 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1938 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1939 qede_xstats_strings[i].offset);
1940 xstats[stat_idx].id = stat_idx;
1944 if (ECORE_IS_BB(edev)) {
1945 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1946 xstats[stat_idx].value =
1947 *(uint64_t *)(((char *)&stats) +
1948 qede_bb_xstats_strings[i].offset);
1949 xstats[stat_idx].id = stat_idx;
1953 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1954 xstats[stat_idx].value =
1955 *(uint64_t *)(((char *)&stats) +
1956 qede_ah_xstats_strings[i].offset);
1957 xstats[stat_idx].id = stat_idx;
1962 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1963 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1964 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1966 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1967 xstats[stat_idx].value = *(uint64_t *)(
1968 ((char *)(qdev->fp_array[qid].rxq)) +
1969 qede_rxq_xstats_strings[i].offset);
1970 xstats[stat_idx].id = stat_idx;
1980 qede_reset_xstats(struct rte_eth_dev *dev)
1982 struct qede_dev *qdev = dev->data->dev_private;
1983 struct ecore_dev *edev = &qdev->edev;
1985 ecore_reset_vport_stats(edev);
1986 qede_reset_queue_stats(qdev, true);
1989 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1991 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1992 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1993 struct qed_link_params link_params;
1996 DP_INFO(edev, "setting link state %d\n", link_up);
1997 memset(&link_params, 0, sizeof(link_params));
1998 link_params.link_up = link_up;
1999 rc = qdev->ops->common->set_link(edev, &link_params);
2000 if (rc != ECORE_SUCCESS)
2001 DP_ERR(edev, "Unable to set link state %d\n", link_up);
2006 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
2008 return qede_dev_set_link_state(eth_dev, true);
2011 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
2013 return qede_dev_set_link_state(eth_dev, false);
2016 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2018 struct qede_dev *qdev = eth_dev->data->dev_private;
2019 struct ecore_dev *edev = &qdev->edev;
2021 ecore_reset_vport_stats(edev);
2022 qede_reset_queue_stats(qdev, false);
2025 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2027 enum qed_filter_rx_mode_type type =
2028 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2030 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2031 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2033 qed_configure_filter_rx_mode(eth_dev, type);
2036 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2038 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2039 qed_configure_filter_rx_mode(eth_dev,
2040 QED_FILTER_RX_MODE_TYPE_PROMISC);
2042 qed_configure_filter_rx_mode(eth_dev,
2043 QED_FILTER_RX_MODE_TYPE_REGULAR);
2046 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2047 struct rte_eth_fc_conf *fc_conf)
2049 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2050 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2051 struct qed_link_output current_link;
2052 struct qed_link_params params;
2054 memset(¤t_link, 0, sizeof(current_link));
2055 qdev->ops->common->get_link(edev, ¤t_link);
2057 memset(¶ms, 0, sizeof(params));
2058 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2059 if (fc_conf->autoneg) {
2060 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2061 DP_ERR(edev, "Autoneg not supported\n");
2064 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2067 /* Pause is assumed to be supported (SUPPORTED_Pause) */
2068 if (fc_conf->mode == RTE_FC_FULL)
2069 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2070 QED_LINK_PAUSE_RX_ENABLE);
2071 if (fc_conf->mode == RTE_FC_TX_PAUSE)
2072 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2073 if (fc_conf->mode == RTE_FC_RX_PAUSE)
2074 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2076 params.link_up = true;
2077 (void)qdev->ops->common->set_link(edev, ¶ms);
2082 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2083 struct rte_eth_fc_conf *fc_conf)
2085 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2086 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2087 struct qed_link_output current_link;
2089 memset(¤t_link, 0, sizeof(current_link));
2090 qdev->ops->common->get_link(edev, ¤t_link);
2092 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2093 fc_conf->autoneg = true;
2095 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2096 QED_LINK_PAUSE_TX_ENABLE))
2097 fc_conf->mode = RTE_FC_FULL;
2098 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2099 fc_conf->mode = RTE_FC_RX_PAUSE;
2100 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2101 fc_conf->mode = RTE_FC_TX_PAUSE;
2103 fc_conf->mode = RTE_FC_NONE;
2108 static const uint32_t *
2109 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2111 static const uint32_t ptypes[] = {
2113 RTE_PTYPE_L2_ETHER_VLAN,
2118 RTE_PTYPE_TUNNEL_VXLAN,
2120 RTE_PTYPE_TUNNEL_GENEVE,
2121 RTE_PTYPE_TUNNEL_GRE,
2123 RTE_PTYPE_INNER_L2_ETHER,
2124 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2125 RTE_PTYPE_INNER_L3_IPV4,
2126 RTE_PTYPE_INNER_L3_IPV6,
2127 RTE_PTYPE_INNER_L4_TCP,
2128 RTE_PTYPE_INNER_L4_UDP,
2129 RTE_PTYPE_INNER_L4_FRAG,
2133 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2139 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2142 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2143 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2144 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2145 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2146 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2147 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2148 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2149 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2152 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2153 struct rte_eth_rss_conf *rss_conf)
2155 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2156 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2157 struct ecore_sp_vport_update_params vport_update_params;
2158 struct ecore_rss_params rss_params;
2159 struct ecore_hwfn *p_hwfn;
2160 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2161 uint64_t hf = rss_conf->rss_hf;
2162 uint8_t len = rss_conf->rss_key_len;
2167 memset(&vport_update_params, 0, sizeof(vport_update_params));
2168 memset(&rss_params, 0, sizeof(rss_params));
2170 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2171 (unsigned long)hf, len, key);
2175 DP_INFO(edev, "Enabling rss\n");
2178 qede_init_rss_caps(&rss_params.rss_caps, hf);
2179 rss_params.update_rss_capabilities = 1;
2183 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2184 DP_ERR(edev, "RSS key length exceeds limit\n");
2187 DP_INFO(edev, "Applying user supplied hash key\n");
2188 rss_params.update_rss_key = 1;
2189 memcpy(&rss_params.rss_key, key, len);
2191 rss_params.rss_enable = 1;
2194 rss_params.update_rss_config = 1;
2195 /* tbl_size has to be set with capabilities */
2196 rss_params.rss_table_size_log = 7;
2197 vport_update_params.vport_id = 0;
2198 /* pass the L2 handles instead of qids */
2199 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2200 idx = qdev->rss_ind_table[i];
2201 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2203 vport_update_params.rss_params = &rss_params;
2205 for_each_hwfn(edev, i) {
2206 p_hwfn = &edev->hwfns[i];
2207 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2208 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2209 ECORE_SPQ_MODE_EBLOCK, NULL);
2211 DP_ERR(edev, "vport-update for RSS failed\n");
2215 qdev->rss_enable = rss_params.rss_enable;
2217 /* Update local structure for hash query */
2218 qdev->rss_conf.rss_hf = hf;
2219 qdev->rss_conf.rss_key_len = len;
2220 if (qdev->rss_enable) {
2221 if (qdev->rss_conf.rss_key == NULL) {
2222 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2223 if (qdev->rss_conf.rss_key == NULL) {
2224 DP_ERR(edev, "No memory to store RSS key\n");
2229 DP_INFO(edev, "Storing RSS key\n");
2230 memcpy(qdev->rss_conf.rss_key, key, len);
2232 } else if (!qdev->rss_enable && len == 0) {
2233 if (qdev->rss_conf.rss_key) {
2234 free(qdev->rss_conf.rss_key);
2235 qdev->rss_conf.rss_key = NULL;
2236 DP_INFO(edev, "Free RSS key\n");
2243 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2244 struct rte_eth_rss_conf *rss_conf)
2246 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2248 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2249 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2251 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2252 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2253 rss_conf->rss_key_len);
2257 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2258 struct ecore_rss_params *rss)
2261 bool rss_mode = 1; /* enable */
2262 struct ecore_queue_cid *cid;
2263 struct ecore_rss_params *t_rss;
2265 /* In regular scenario, we'd simply need to take input handlers.
2266 * But in CMT, we'd have to split the handlers according to the
2267 * engine they were configured on. We'd then have to understand
2268 * whether RSS is really required, since 2-queues on CMT doesn't
2272 /* CMT should be round-robin */
2273 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2274 cid = rss->rss_ind_table[i];
2276 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2281 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2285 t_rss->update_rss_ind_table = 1;
2286 t_rss->rss_table_size_log = 7;
2287 t_rss->update_rss_config = 1;
2289 /* Make sure RSS is actually required */
2290 for_each_hwfn(edev, fn) {
2291 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2293 if (rss[fn].rss_ind_table[i] !=
2294 rss[fn].rss_ind_table[0])
2298 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2300 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2307 t_rss->rss_enable = rss_mode;
2312 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2313 struct rte_eth_rss_reta_entry64 *reta_conf,
2316 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2317 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2318 struct ecore_sp_vport_update_params vport_update_params;
2319 struct ecore_rss_params *params;
2320 struct ecore_hwfn *p_hwfn;
2321 uint16_t i, idx, shift;
2325 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2326 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2331 memset(&vport_update_params, 0, sizeof(vport_update_params));
2332 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2333 RTE_CACHE_LINE_SIZE);
2334 if (params == NULL) {
2335 DP_ERR(edev, "failed to allocate memory\n");
2339 for (i = 0; i < reta_size; i++) {
2340 idx = i / RTE_RETA_GROUP_SIZE;
2341 shift = i % RTE_RETA_GROUP_SIZE;
2342 if (reta_conf[idx].mask & (1ULL << shift)) {
2343 entry = reta_conf[idx].reta[shift];
2344 /* Pass rxq handles to ecore */
2345 params->rss_ind_table[i] =
2346 qdev->fp_array[entry].rxq->handle;
2347 /* Update the local copy for RETA query command */
2348 qdev->rss_ind_table[i] = entry;
2352 params->update_rss_ind_table = 1;
2353 params->rss_table_size_log = 7;
2354 params->update_rss_config = 1;
2356 /* Fix up RETA for CMT mode device */
2357 if (ECORE_IS_CMT(edev))
2358 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2360 vport_update_params.vport_id = 0;
2361 /* Use the current value of rss_enable */
2362 params->rss_enable = qdev->rss_enable;
2363 vport_update_params.rss_params = params;
2365 for_each_hwfn(edev, i) {
2366 p_hwfn = &edev->hwfns[i];
2367 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2368 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2369 ECORE_SPQ_MODE_EBLOCK, NULL);
2371 DP_ERR(edev, "vport-update for RSS failed\n");
2381 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2382 struct rte_eth_rss_reta_entry64 *reta_conf,
2385 struct qede_dev *qdev = eth_dev->data->dev_private;
2386 struct ecore_dev *edev = &qdev->edev;
2387 uint16_t i, idx, shift;
2390 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2391 DP_ERR(edev, "reta_size %d is not supported\n",
2396 for (i = 0; i < reta_size; i++) {
2397 idx = i / RTE_RETA_GROUP_SIZE;
2398 shift = i % RTE_RETA_GROUP_SIZE;
2399 if (reta_conf[idx].mask & (1ULL << shift)) {
2400 entry = qdev->rss_ind_table[i];
2401 reta_conf[idx].reta[shift] = entry;
2410 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2412 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2413 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2414 struct rte_eth_dev_info dev_info = {0};
2415 struct qede_fastpath *fp;
2416 uint32_t max_rx_pkt_len;
2417 uint32_t frame_size;
2418 uint16_t rx_buf_size;
2420 bool restart = false;
2423 PMD_INIT_FUNC_TRACE(edev);
2424 qede_dev_info_get(dev, &dev_info);
2425 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2426 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2427 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2428 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2429 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2430 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2433 if (!dev->data->scattered_rx &&
2434 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2435 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2436 dev->data->min_rx_buf_size);
2439 /* Temporarily replace I/O functions with dummy ones. It cannot
2440 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2442 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2443 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2444 if (dev->data->dev_started) {
2445 dev->data->dev_started = 0;
2450 qede_mac_addr_remove(dev, 0);
2453 qede_start_vport(qdev, mtu); /* Recreate vport */
2456 /* Fix up RX buf size for all queues of the port */
2458 fp = &qdev->fp_array[i];
2459 if (fp->rxq != NULL) {
2460 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2461 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2462 if (dev->data->scattered_rx)
2463 rx_buf_size = bufsz + ETHER_HDR_LEN +
2464 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2466 rx_buf_size = frame_size;
2467 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2468 fp->rxq->rx_buf_size = rx_buf_size;
2469 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2472 if (max_rx_pkt_len > ETHER_MAX_LEN)
2473 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2475 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2477 /* Restore config lost due to vport stop */
2479 qede_mac_addr_set(dev, &qdev->primary_mac);
2481 if (dev->data->promiscuous)
2482 qede_promiscuous_enable(dev);
2484 qede_promiscuous_disable(dev);
2486 if (dev->data->all_multicast)
2487 qede_allmulticast_enable(dev);
2489 qede_allmulticast_disable(dev);
2491 qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2493 if (!dev->data->dev_started && restart) {
2494 qede_dev_start(dev);
2495 dev->data->dev_started = 1;
2498 /* update max frame size */
2499 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2501 dev->rx_pkt_burst = qede_recv_pkts;
2502 dev->tx_pkt_burst = qede_xmit_pkts;
2508 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2509 struct rte_eth_udp_tunnel *tunnel_udp)
2511 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2512 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2513 struct ecore_tunnel_info tunn; /* @DPDK */
2517 PMD_INIT_FUNC_TRACE(edev);
2519 memset(&tunn, 0, sizeof(tunn));
2521 switch (tunnel_udp->prot_type) {
2522 case RTE_TUNNEL_TYPE_VXLAN:
2523 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2524 DP_ERR(edev, "UDP port %u doesn't exist\n",
2525 tunnel_udp->udp_port);
2530 tunn.vxlan_port.b_update_port = true;
2531 tunn.vxlan_port.port = udp_port;
2533 rc = qede_tunnel_update(qdev, &tunn);
2534 if (rc != ECORE_SUCCESS) {
2535 DP_ERR(edev, "Unable to config UDP port %u\n",
2536 tunn.vxlan_port.port);
2540 qdev->vxlan.udp_port = udp_port;
2541 /* If the request is to delete UDP port and if the number of
2542 * VXLAN filters have reached 0 then VxLAN offload can be be
2545 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2546 return qede_vxlan_enable(eth_dev,
2547 ECORE_TUNN_CLSS_MAC_VLAN, false);
2550 case RTE_TUNNEL_TYPE_GENEVE:
2551 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2552 DP_ERR(edev, "UDP port %u doesn't exist\n",
2553 tunnel_udp->udp_port);
2559 tunn.geneve_port.b_update_port = true;
2560 tunn.geneve_port.port = udp_port;
2562 rc = qede_tunnel_update(qdev, &tunn);
2563 if (rc != ECORE_SUCCESS) {
2564 DP_ERR(edev, "Unable to config UDP port %u\n",
2565 tunn.vxlan_port.port);
2569 qdev->vxlan.udp_port = udp_port;
2570 /* If the request is to delete UDP port and if the number of
2571 * GENEVE filters have reached 0 then GENEVE offload can be be
2574 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2575 return qede_geneve_enable(eth_dev,
2576 ECORE_TUNN_CLSS_MAC_VLAN, false);
2588 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2589 struct rte_eth_udp_tunnel *tunnel_udp)
2591 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2592 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2593 struct ecore_tunnel_info tunn; /* @DPDK */
2597 PMD_INIT_FUNC_TRACE(edev);
2599 memset(&tunn, 0, sizeof(tunn));
2601 switch (tunnel_udp->prot_type) {
2602 case RTE_TUNNEL_TYPE_VXLAN:
2603 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2605 "UDP port %u for VXLAN was already configured\n",
2606 tunnel_udp->udp_port);
2607 return ECORE_SUCCESS;
2610 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2611 * it was not enabled while adding VXLAN filter before UDP port
2614 if (!qdev->vxlan.enable) {
2615 rc = qede_vxlan_enable(eth_dev,
2616 ECORE_TUNN_CLSS_MAC_VLAN, true);
2617 if (rc != ECORE_SUCCESS) {
2618 DP_ERR(edev, "Failed to enable VXLAN "
2619 "prior to updating UDP port\n");
2623 udp_port = tunnel_udp->udp_port;
2625 tunn.vxlan_port.b_update_port = true;
2626 tunn.vxlan_port.port = udp_port;
2628 rc = qede_tunnel_update(qdev, &tunn);
2629 if (rc != ECORE_SUCCESS) {
2630 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2635 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2637 qdev->vxlan.udp_port = udp_port;
2639 case RTE_TUNNEL_TYPE_GENEVE:
2640 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2642 "UDP port %u for GENEVE was already configured\n",
2643 tunnel_udp->udp_port);
2644 return ECORE_SUCCESS;
2647 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2648 * it was not enabled while adding GENEVE filter before UDP port
2651 if (!qdev->geneve.enable) {
2652 rc = qede_geneve_enable(eth_dev,
2653 ECORE_TUNN_CLSS_MAC_VLAN, true);
2654 if (rc != ECORE_SUCCESS) {
2655 DP_ERR(edev, "Failed to enable GENEVE "
2656 "prior to updating UDP port\n");
2660 udp_port = tunnel_udp->udp_port;
2662 tunn.geneve_port.b_update_port = true;
2663 tunn.geneve_port.port = udp_port;
2665 rc = qede_tunnel_update(qdev, &tunn);
2666 if (rc != ECORE_SUCCESS) {
2667 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2672 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2674 qdev->geneve.udp_port = udp_port;
2683 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2684 uint32_t *clss, char *str)
2687 *clss = MAX_ECORE_TUNN_CLSS;
2689 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2690 if (filter == qede_tunn_types[j].rte_filter_type) {
2691 *type = qede_tunn_types[j].qede_type;
2692 *clss = qede_tunn_types[j].qede_tunn_clss;
2693 strcpy(str, qede_tunn_types[j].string);
2700 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2701 const struct rte_eth_tunnel_filter_conf *conf,
2704 /* Init commmon ucast params first */
2705 qede_set_ucast_cmn_params(ucast);
2707 /* Copy out the required fields based on classification type */
2711 case ECORE_FILTER_VNI:
2712 ucast->vni = conf->tenant_id;
2714 case ECORE_FILTER_INNER_VLAN:
2715 ucast->vlan = conf->inner_vlan;
2717 case ECORE_FILTER_MAC:
2718 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2721 case ECORE_FILTER_INNER_MAC:
2722 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2725 case ECORE_FILTER_MAC_VNI_PAIR:
2726 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2728 ucast->vni = conf->tenant_id;
2730 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2731 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2733 ucast->vni = conf->tenant_id;
2735 case ECORE_FILTER_INNER_PAIR:
2736 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2738 ucast->vlan = conf->inner_vlan;
2744 return ECORE_SUCCESS;
2748 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2749 const struct rte_eth_tunnel_filter_conf *conf,
2750 __attribute__((unused)) enum rte_filter_op filter_op,
2751 enum ecore_tunn_clss *clss,
2754 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2755 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2756 struct ecore_filter_ucast ucast = {0};
2757 enum ecore_filter_ucast_type type;
2758 uint16_t filter_type = 0;
2762 filter_type = conf->filter_type;
2763 /* Determine if the given filter classification is supported */
2764 qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2765 if (*clss == MAX_ECORE_TUNN_CLSS) {
2766 DP_ERR(edev, "Unsupported filter type\n");
2769 /* Init tunnel ucast params */
2770 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2771 if (rc != ECORE_SUCCESS) {
2772 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2776 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2777 str, filter_op, ucast.type);
2779 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2781 /* Skip MAC/VLAN if filter is based on VNI */
2782 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2783 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2784 if ((rc == 0) && add) {
2785 /* Enable accept anyvlan */
2786 qede_config_accept_any_vlan(qdev, true);
2789 rc = qede_ucast_filter(eth_dev, &ucast, add);
2791 rc = ecore_filter_ucast_cmd(edev, &ucast,
2792 ECORE_SPQ_MODE_CB, NULL);
2799 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2800 enum rte_filter_op filter_op,
2801 const struct rte_eth_tunnel_filter_conf *conf)
2803 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2804 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2805 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2809 PMD_INIT_FUNC_TRACE(edev);
2811 switch (filter_op) {
2812 case RTE_ETH_FILTER_ADD:
2815 case RTE_ETH_FILTER_DELETE:
2819 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2824 return qede_tunn_enable(eth_dev,
2825 ECORE_TUNN_CLSS_MAC_VLAN,
2826 conf->tunnel_type, add);
2828 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2829 if (rc != ECORE_SUCCESS)
2833 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2834 qdev->vxlan.num_filters++;
2835 qdev->vxlan.filter_type = conf->filter_type;
2836 } else { /* GENEVE */
2837 qdev->geneve.num_filters++;
2838 qdev->geneve.filter_type = conf->filter_type;
2841 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2842 !qdev->ipgre.enable)
2843 return qede_tunn_enable(eth_dev, clss,
2847 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2848 qdev->vxlan.num_filters--;
2850 qdev->geneve.num_filters--;
2852 /* Disable VXLAN if VXLAN filters become 0 */
2853 if ((qdev->vxlan.num_filters == 0) ||
2854 (qdev->geneve.num_filters == 0))
2855 return qede_tunn_enable(eth_dev, clss,
2863 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2864 enum rte_filter_type filter_type,
2865 enum rte_filter_op filter_op,
2868 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2869 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2870 struct rte_eth_tunnel_filter_conf *filter_conf =
2871 (struct rte_eth_tunnel_filter_conf *)arg;
2873 switch (filter_type) {
2874 case RTE_ETH_FILTER_TUNNEL:
2875 switch (filter_conf->tunnel_type) {
2876 case RTE_TUNNEL_TYPE_VXLAN:
2877 case RTE_TUNNEL_TYPE_GENEVE:
2878 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2880 "Packet steering to the specified Rx queue"
2881 " is not supported with UDP tunneling");
2882 return(qede_tunn_filter_config(eth_dev, filter_op,
2884 case RTE_TUNNEL_TYPE_TEREDO:
2885 case RTE_TUNNEL_TYPE_NVGRE:
2886 case RTE_L2_TUNNEL_TYPE_E_TAG:
2887 DP_ERR(edev, "Unsupported tunnel type %d\n",
2888 filter_conf->tunnel_type);
2890 case RTE_TUNNEL_TYPE_NONE:
2895 case RTE_ETH_FILTER_FDIR:
2896 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2897 case RTE_ETH_FILTER_NTUPLE:
2898 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2899 case RTE_ETH_FILTER_MACVLAN:
2900 case RTE_ETH_FILTER_ETHERTYPE:
2901 case RTE_ETH_FILTER_FLEXIBLE:
2902 case RTE_ETH_FILTER_SYN:
2903 case RTE_ETH_FILTER_HASH:
2904 case RTE_ETH_FILTER_L2_TUNNEL:
2905 case RTE_ETH_FILTER_MAX:
2907 DP_ERR(edev, "Unsupported filter type %d\n",
2915 static const struct eth_dev_ops qede_eth_dev_ops = {
2916 .dev_configure = qede_dev_configure,
2917 .dev_infos_get = qede_dev_info_get,
2918 .rx_queue_setup = qede_rx_queue_setup,
2919 .rx_queue_release = qede_rx_queue_release,
2920 .tx_queue_setup = qede_tx_queue_setup,
2921 .tx_queue_release = qede_tx_queue_release,
2922 .dev_start = qede_dev_start,
2923 .dev_set_link_up = qede_dev_set_link_up,
2924 .dev_set_link_down = qede_dev_set_link_down,
2925 .link_update = qede_link_update,
2926 .promiscuous_enable = qede_promiscuous_enable,
2927 .promiscuous_disable = qede_promiscuous_disable,
2928 .allmulticast_enable = qede_allmulticast_enable,
2929 .allmulticast_disable = qede_allmulticast_disable,
2930 .dev_stop = qede_dev_stop,
2931 .dev_close = qede_dev_close,
2932 .stats_get = qede_get_stats,
2933 .stats_reset = qede_reset_stats,
2934 .xstats_get = qede_get_xstats,
2935 .xstats_reset = qede_reset_xstats,
2936 .xstats_get_names = qede_get_xstats_names,
2937 .mac_addr_add = qede_mac_addr_add,
2938 .mac_addr_remove = qede_mac_addr_remove,
2939 .mac_addr_set = qede_mac_addr_set,
2940 .vlan_offload_set = qede_vlan_offload_set,
2941 .vlan_filter_set = qede_vlan_filter_set,
2942 .flow_ctrl_set = qede_flow_ctrl_set,
2943 .flow_ctrl_get = qede_flow_ctrl_get,
2944 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2945 .rss_hash_update = qede_rss_hash_update,
2946 .rss_hash_conf_get = qede_rss_hash_conf_get,
2947 .reta_update = qede_rss_reta_update,
2948 .reta_query = qede_rss_reta_query,
2949 .mtu_set = qede_set_mtu,
2950 .filter_ctrl = qede_dev_filter_ctrl,
2951 .udp_tunnel_port_add = qede_udp_dst_port_add,
2952 .udp_tunnel_port_del = qede_udp_dst_port_del,
2955 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2956 .dev_configure = qede_dev_configure,
2957 .dev_infos_get = qede_dev_info_get,
2958 .rx_queue_setup = qede_rx_queue_setup,
2959 .rx_queue_release = qede_rx_queue_release,
2960 .tx_queue_setup = qede_tx_queue_setup,
2961 .tx_queue_release = qede_tx_queue_release,
2962 .dev_start = qede_dev_start,
2963 .dev_set_link_up = qede_dev_set_link_up,
2964 .dev_set_link_down = qede_dev_set_link_down,
2965 .link_update = qede_link_update,
2966 .promiscuous_enable = qede_promiscuous_enable,
2967 .promiscuous_disable = qede_promiscuous_disable,
2968 .allmulticast_enable = qede_allmulticast_enable,
2969 .allmulticast_disable = qede_allmulticast_disable,
2970 .dev_stop = qede_dev_stop,
2971 .dev_close = qede_dev_close,
2972 .stats_get = qede_get_stats,
2973 .stats_reset = qede_reset_stats,
2974 .xstats_get = qede_get_xstats,
2975 .xstats_reset = qede_reset_xstats,
2976 .xstats_get_names = qede_get_xstats_names,
2977 .vlan_offload_set = qede_vlan_offload_set,
2978 .vlan_filter_set = qede_vlan_filter_set,
2979 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2980 .rss_hash_update = qede_rss_hash_update,
2981 .rss_hash_conf_get = qede_rss_hash_conf_get,
2982 .reta_update = qede_rss_reta_update,
2983 .reta_query = qede_rss_reta_query,
2984 .mtu_set = qede_set_mtu,
2985 .udp_tunnel_port_add = qede_udp_dst_port_add,
2986 .udp_tunnel_port_del = qede_udp_dst_port_del,
2989 static void qede_update_pf_params(struct ecore_dev *edev)
2991 struct ecore_pf_params pf_params;
2993 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2994 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2995 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2996 qed_ops->common->update_pf_params(edev, &pf_params);
2999 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3001 struct rte_pci_device *pci_dev;
3002 struct rte_pci_addr pci_addr;
3003 struct qede_dev *adapter;
3004 struct ecore_dev *edev;
3005 struct qed_dev_eth_info dev_info;
3006 struct qed_slowpath_params params;
3007 static bool do_once = true;
3008 uint8_t bulletin_change;
3009 uint8_t vf_mac[ETHER_ADDR_LEN];
3010 uint8_t is_mac_forced;
3012 /* Fix up ecore debug level */
3013 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3014 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3017 /* Extract key data structures */
3018 adapter = eth_dev->data->dev_private;
3019 adapter->ethdev = eth_dev;
3020 edev = &adapter->edev;
3021 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3022 pci_addr = pci_dev->addr;
3024 PMD_INIT_FUNC_TRACE(edev);
3026 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3027 pci_addr.bus, pci_addr.devid, pci_addr.function,
3028 eth_dev->data->port_id);
3030 eth_dev->rx_pkt_burst = qede_recv_pkts;
3031 eth_dev->tx_pkt_burst = qede_xmit_pkts;
3032 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3034 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3035 DP_ERR(edev, "Skipping device init from secondary process\n");
3039 rte_eth_copy_pci_info(eth_dev, pci_dev);
3042 edev->vendor_id = pci_dev->id.vendor_id;
3043 edev->device_id = pci_dev->id.device_id;
3045 qed_ops = qed_get_eth_ops();
3047 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3051 DP_INFO(edev, "Starting qede probe\n");
3052 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3055 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3058 qede_update_pf_params(edev);
3059 rte_intr_callback_register(&pci_dev->intr_handle,
3060 qede_interrupt_handler, (void *)eth_dev);
3061 if (rte_intr_enable(&pci_dev->intr_handle)) {
3062 DP_ERR(edev, "rte_intr_enable() failed\n");
3066 /* Start the Slowpath-process */
3067 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
3068 params.int_mode = ECORE_INT_MODE_MSIX;
3069 params.drv_major = QEDE_PMD_VERSION_MAJOR;
3070 params.drv_minor = QEDE_PMD_VERSION_MINOR;
3071 params.drv_rev = QEDE_PMD_VERSION_REVISION;
3072 params.drv_eng = QEDE_PMD_VERSION_PATCH;
3073 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3074 QEDE_PMD_DRV_VER_STR_SIZE);
3076 /* For CMT mode device do periodic polling for slowpath events.
3077 * This is required since uio device uses only one MSI-x
3078 * interrupt vector but we need one for each engine.
3080 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3081 rc = rte_eal_alarm_set(timer_period * US_PER_S,
3085 DP_ERR(edev, "Unable to start periodic"
3086 " timer rc %d\n", rc);
3091 rc = qed_ops->common->slowpath_start(edev, ¶ms);
3093 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3094 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3099 rc = qed_ops->fill_dev_info(edev, &dev_info);
3101 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3102 qed_ops->common->slowpath_stop(edev);
3103 qed_ops->common->remove(edev);
3104 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3109 qede_alloc_etherdev(adapter, &dev_info);
3111 adapter->ops->common->set_name(edev, edev->name);
3114 adapter->dev_info.num_mac_filters =
3115 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3118 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3119 (uint32_t *)&adapter->dev_info.num_mac_filters);
3121 /* Allocate memory for storing MAC addr */
3122 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3124 adapter->dev_info.num_mac_filters),
3125 RTE_CACHE_LINE_SIZE);
3127 if (eth_dev->data->mac_addrs == NULL) {
3128 DP_ERR(edev, "Failed to allocate MAC address\n");
3129 qed_ops->common->slowpath_stop(edev);
3130 qed_ops->common->remove(edev);
3131 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3137 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3138 hw_info.hw_mac_addr,
3139 ð_dev->data->mac_addrs[0]);
3140 ether_addr_copy(ð_dev->data->mac_addrs[0],
3141 &adapter->primary_mac);
3143 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3145 if (bulletin_change) {
3147 ecore_vf_bulletin_get_forced_mac(
3148 ECORE_LEADING_HWFN(edev),
3151 if (is_mac_exist && is_mac_forced) {
3152 DP_INFO(edev, "VF macaddr received from PF\n");
3153 ether_addr_copy((struct ether_addr *)&vf_mac,
3154 ð_dev->data->mac_addrs[0]);
3155 ether_addr_copy(ð_dev->data->mac_addrs[0],
3156 &adapter->primary_mac);
3158 DP_ERR(edev, "No VF macaddr assigned\n");
3163 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3166 qede_print_adapter_info(adapter);
3170 /* Bring-up the link */
3171 qede_dev_set_link_state(eth_dev, true);
3173 adapter->num_tx_queues = 0;
3174 adapter->num_rx_queues = 0;
3175 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3176 SLIST_INIT(&adapter->vlan_list_head);
3177 SLIST_INIT(&adapter->uc_list_head);
3178 adapter->mtu = ETHER_MTU;
3179 adapter->vport_started = false;
3181 /* VF tunnel offloads is enabled by default in PF driver */
3182 adapter->vxlan.num_filters = 0;
3183 adapter->geneve.num_filters = 0;
3184 adapter->ipgre.num_filters = 0;
3186 adapter->vxlan.enable = true;
3187 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3188 ETH_TUNNEL_FILTER_IVLAN;
3189 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3190 adapter->geneve.enable = true;
3191 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3192 ETH_TUNNEL_FILTER_IVLAN;
3193 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3194 adapter->ipgre.enable = true;
3195 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3196 ETH_TUNNEL_FILTER_IVLAN;
3198 adapter->vxlan.enable = false;
3199 adapter->geneve.enable = false;
3200 adapter->ipgre.enable = false;
3203 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3204 adapter->primary_mac.addr_bytes[0],
3205 adapter->primary_mac.addr_bytes[1],
3206 adapter->primary_mac.addr_bytes[2],
3207 adapter->primary_mac.addr_bytes[3],
3208 adapter->primary_mac.addr_bytes[4],
3209 adapter->primary_mac.addr_bytes[5]);
3211 DP_INFO(edev, "Device initialized\n");
3216 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3218 return qede_common_dev_init(eth_dev, 1);
3221 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3223 return qede_common_dev_init(eth_dev, 0);
3226 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3228 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3229 struct qede_dev *qdev = eth_dev->data->dev_private;
3230 struct ecore_dev *edev = &qdev->edev;
3232 PMD_INIT_FUNC_TRACE(edev);
3235 /* only uninitialize in the primary process */
3236 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3239 /* safe to close dev here */
3240 qede_dev_close(eth_dev);
3242 eth_dev->dev_ops = NULL;
3243 eth_dev->rx_pkt_burst = NULL;
3244 eth_dev->tx_pkt_burst = NULL;
3246 if (eth_dev->data->mac_addrs)
3247 rte_free(eth_dev->data->mac_addrs);
3249 eth_dev->data->mac_addrs = NULL;
3254 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3256 return qede_dev_common_uninit(eth_dev);
3259 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3261 return qede_dev_common_uninit(eth_dev);
3264 static const struct rte_pci_id pci_id_qedevf_map[] = {
3265 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3267 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3270 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3273 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3278 static const struct rte_pci_id pci_id_qede_map[] = {
3279 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3281 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3284 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3287 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3290 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3293 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3296 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3299 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3302 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3305 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3308 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3313 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3314 struct rte_pci_device *pci_dev)
3316 return rte_eth_dev_pci_generic_probe(pci_dev,
3317 sizeof(struct qede_dev), qedevf_eth_dev_init);
3320 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3322 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3325 static struct rte_pci_driver rte_qedevf_pmd = {
3326 .id_table = pci_id_qedevf_map,
3327 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3328 .probe = qedevf_eth_dev_pci_probe,
3329 .remove = qedevf_eth_dev_pci_remove,
3332 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3333 struct rte_pci_device *pci_dev)
3335 return rte_eth_dev_pci_generic_probe(pci_dev,
3336 sizeof(struct qede_dev), qede_eth_dev_init);
3339 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3341 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3344 static struct rte_pci_driver rte_qede_pmd = {
3345 .id_table = pci_id_qede_map,
3346 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3347 .probe = qede_eth_dev_pci_probe,
3348 .remove = qede_eth_dev_pci_remove,
3351 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3352 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3353 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3354 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3355 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3356 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3358 RTE_INIT(qede_init_log);
3362 qede_logtype_init = rte_log_register("pmd.net.qede.init");
3363 if (qede_logtype_init >= 0)
3364 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3365 qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3366 if (qede_logtype_driver >= 0)
3367 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);