2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static int64_t timer_period = 1;
17 /* VXLAN tunnel classification mapping */
18 const struct _qede_vxlan_tunn_types {
19 uint16_t rte_filter_type;
20 enum ecore_filter_ucast_type qede_type;
21 enum ecore_tunn_clss qede_tunn_clss;
23 } qede_tunn_types[] = {
25 ETH_TUNNEL_FILTER_OMAC,
27 ECORE_TUNN_CLSS_MAC_VLAN,
31 ETH_TUNNEL_FILTER_TENID,
33 ECORE_TUNN_CLSS_MAC_VNI,
37 ETH_TUNNEL_FILTER_IMAC,
38 ECORE_FILTER_INNER_MAC,
39 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
43 ETH_TUNNEL_FILTER_IVLAN,
44 ECORE_FILTER_INNER_VLAN,
45 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
50 ECORE_FILTER_MAC_VNI_PAIR,
51 ECORE_TUNN_CLSS_MAC_VNI,
55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
58 "outer-mac and inner-mac"
61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
64 "outer-mac and inner-vlan"
67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
68 ECORE_FILTER_INNER_MAC_VNI_PAIR,
69 ECORE_TUNN_CLSS_INNER_MAC_VNI,
73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
80 ECORE_FILTER_INNER_PAIR,
81 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
82 "inner-mac and inner-vlan",
85 ETH_TUNNEL_FILTER_OIP,
91 ETH_TUNNEL_FILTER_IIP,
97 RTE_TUNNEL_FILTER_IMAC_IVLAN,
103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
109 RTE_TUNNEL_FILTER_IMAC_TENID,
115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
122 struct rte_qede_xstats_name_off {
123 char name[RTE_ETH_XSTATS_NAME_SIZE];
127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
128 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
129 {"rx_multicast_bytes",
130 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
131 {"rx_broadcast_bytes",
132 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
133 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
134 {"rx_multicast_packets",
135 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
136 {"rx_broadcast_packets",
137 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
139 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
140 {"tx_multicast_bytes",
141 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
142 {"tx_broadcast_bytes",
143 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
144 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
145 {"tx_multicast_packets",
146 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
147 {"tx_broadcast_packets",
148 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
150 {"rx_64_byte_packets",
151 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
152 {"rx_65_to_127_byte_packets",
153 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
154 {"rx_128_to_255_byte_packets",
155 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
156 {"rx_256_to_511_byte_packets",
157 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
158 {"rx_512_to_1023_byte_packets",
159 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
160 {"rx_1024_to_1518_byte_packets",
161 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
162 {"rx_1519_to_1522_byte_packets",
163 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
164 {"rx_1519_to_2047_byte_packets",
165 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
166 {"rx_2048_to_4095_byte_packets",
167 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
168 {"rx_4096_to_9216_byte_packets",
169 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
170 {"rx_9217_to_16383_byte_packets",
171 offsetof(struct ecore_eth_stats,
172 rx_9217_to_16383_byte_packets)},
173 {"tx_64_byte_packets",
174 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
175 {"tx_65_to_127_byte_packets",
176 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
177 {"tx_128_to_255_byte_packets",
178 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
179 {"tx_256_to_511_byte_packets",
180 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
181 {"tx_512_to_1023_byte_packets",
182 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
183 {"tx_1024_to_1518_byte_packets",
184 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
185 {"trx_1519_to_1522_byte_packets",
186 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
187 {"tx_2048_to_4095_byte_packets",
188 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
189 {"tx_4096_to_9216_byte_packets",
190 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
191 {"tx_9217_to_16383_byte_packets",
192 offsetof(struct ecore_eth_stats,
193 tx_9217_to_16383_byte_packets)},
195 {"rx_mac_crtl_frames",
196 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
197 {"tx_mac_control_frames",
198 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
199 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
200 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
201 {"rx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
203 {"tx_priority_flow_control_frames",
204 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
206 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
207 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
208 {"rx_carrier_errors",
209 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
210 {"rx_oversize_packet_errors",
211 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
212 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
213 {"rx_undersize_packet_errors",
214 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
215 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
216 {"rx_host_buffer_not_available",
217 offsetof(struct ecore_eth_stats, no_buff_discards)},
218 /* Number of packets discarded because they are bigger than MTU */
219 {"rx_packet_too_big_discards",
220 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
221 {"rx_ttl_zero_discards",
222 offsetof(struct ecore_eth_stats, ttl0_discard)},
223 {"rx_multi_function_tag_filter_discards",
224 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
225 {"rx_mac_filter_discards",
226 offsetof(struct ecore_eth_stats, mac_filter_discards)},
227 {"rx_hw_buffer_truncates",
228 offsetof(struct ecore_eth_stats, brb_truncates)},
229 {"rx_hw_buffer_discards",
230 offsetof(struct ecore_eth_stats, brb_discards)},
231 {"tx_lpi_entry_count",
232 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
233 {"tx_total_collisions",
234 offsetof(struct ecore_eth_stats, tx_total_collisions)},
235 {"tx_error_drop_packets",
236 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
239 {"rx_mac_unicast_packets",
240 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
241 {"rx_mac_multicast_packets",
242 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
243 {"rx_mac_broadcast_packets",
244 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
246 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
248 {"tx_mac_unicast_packets",
249 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
250 {"tx_mac_multicast_packets",
251 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
252 {"tx_mac_broadcast_packets",
253 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
255 {"lro_coalesced_packets",
256 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
257 {"lro_coalesced_events",
258 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
260 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
261 {"lro_not_coalesced_packets",
262 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
263 {"lro_coalesced_bytes",
264 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
269 offsetof(struct qede_rx_queue, rx_segs)},
271 offsetof(struct qede_rx_queue, rx_hw_errors)},
272 {"rx_q_allocation_errors",
273 offsetof(struct qede_rx_queue, rx_alloc_errors)}
276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
278 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
282 qede_interrupt_handler(struct rte_intr_handle *handle, void *param)
284 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
285 struct qede_dev *qdev = eth_dev->data->dev_private;
286 struct ecore_dev *edev = &qdev->edev;
288 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
289 if (rte_intr_enable(handle))
290 DP_ERR(edev, "rte_intr_enable failed\n");
294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
296 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
297 qdev->num_tc = qdev->dev_info.num_tc;
301 static void qede_print_adapter_info(struct qede_dev *qdev)
303 struct ecore_dev *edev = &qdev->edev;
304 struct qed_dev_info *info = &qdev->dev_info.common;
305 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
306 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
308 DP_INFO(edev, "*********************************\n");
309 DP_INFO(edev, " DPDK version:%s\n", rte_version());
310 DP_INFO(edev, " Chip details : %s%d\n",
311 ECORE_IS_BB(edev) ? "BB" : "AH",
312 CHIP_REV_IS_A0(edev) ? 0 : 1);
313 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
314 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
315 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
316 ver_str, QEDE_PMD_VERSION);
317 DP_INFO(edev, " Driver version : %s\n", drv_ver);
318 DP_INFO(edev, " Firmware version : %s\n", ver_str);
320 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
322 (info->mfw_rev >> 24) & 0xff,
323 (info->mfw_rev >> 16) & 0xff,
324 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
325 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
326 DP_INFO(edev, " Firmware file : %s\n", fw_file);
327 DP_INFO(edev, "*********************************\n");
330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
332 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
333 ucast->is_rx_filter = true;
334 ucast->is_tx_filter = true;
335 /* ucast->assert_on_error = true; - For debug */
338 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
339 uint8_t clss, bool mode, bool mask)
341 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
342 p_tunn->vxlan.b_update_mode = mode;
343 p_tunn->vxlan.b_mode_enabled = mask;
344 p_tunn->b_update_rx_cls = true;
345 p_tunn->b_update_tx_cls = true;
346 p_tunn->vxlan.tun_cls = clss;
350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
353 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
354 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
355 struct qede_ucast_entry *tmp = NULL;
356 struct qede_ucast_entry *u;
357 struct ether_addr *mac_addr;
359 mac_addr = (struct ether_addr *)ucast->mac;
361 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
362 if ((memcmp(mac_addr, &tmp->mac,
363 ETHER_ADDR_LEN) == 0) &&
364 ucast->vlan == tmp->vlan) {
365 DP_ERR(edev, "Unicast MAC is already added"
366 " with vlan = %u, vni = %u\n",
367 ucast->vlan, ucast->vni);
371 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
372 RTE_CACHE_LINE_SIZE);
374 DP_ERR(edev, "Did not allocate memory for ucast\n");
377 ether_addr_copy(mac_addr, &u->mac);
378 u->vlan = ucast->vlan;
380 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
383 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
384 if ((memcmp(mac_addr, &tmp->mac,
385 ETHER_ADDR_LEN) == 0) &&
386 ucast->vlan == tmp->vlan &&
387 ucast->vni == tmp->vni)
391 DP_INFO(edev, "Unicast MAC is not found\n");
394 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
405 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
406 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
407 struct ether_addr *mac_addr;
408 struct qede_mcast_entry *tmp = NULL;
409 struct qede_mcast_entry *m;
411 mac_addr = (struct ether_addr *)mcast->mac;
413 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
414 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
416 "Multicast MAC is already added\n");
420 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
421 RTE_CACHE_LINE_SIZE);
424 "Did not allocate memory for mcast\n");
427 ether_addr_copy(mac_addr, &m->mac);
428 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
431 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
432 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
436 DP_INFO(edev, "Multicast mac is not found\n");
439 SLIST_REMOVE(&qdev->mc_list_head, tmp,
440 qede_mcast_entry, list);
447 static enum _ecore_status_t
448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
451 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
452 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
453 enum _ecore_status_t rc;
454 struct ecore_filter_mcast mcast;
455 struct qede_mcast_entry *tmp;
459 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
461 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
463 "Mcast filter table limit exceeded, "
464 "Please enable mcast promisc mode\n");
468 rc = qede_mcast_filter(eth_dev, ucast, add);
470 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
471 memset(&mcast, 0, sizeof(mcast));
472 mcast.num_mc_addrs = qdev->num_mc_addr;
473 mcast.opcode = ECORE_FILTER_ADD;
474 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
475 ether_addr_copy(&tmp->mac,
476 (struct ether_addr *)&mcast.mac[j]);
479 rc = ecore_filter_mcast_cmd(edev, &mcast,
480 ECORE_SPQ_MODE_CB, NULL);
482 if (rc != ECORE_SUCCESS) {
483 DP_ERR(edev, "Failed to add multicast filter"
484 " rc = %d, op = %d\n", rc, add);
486 } else { /* Unicast */
488 if (qdev->num_uc_addr >=
489 qdev->dev_info.num_mac_filters) {
491 "Ucast filter table limit exceeded,"
492 " Please enable promisc mode\n");
496 rc = qede_ucast_filter(eth_dev, ucast, add);
498 rc = ecore_filter_ucast_cmd(edev, ucast,
499 ECORE_SPQ_MODE_CB, NULL);
500 if (rc != ECORE_SUCCESS) {
501 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
510 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
511 uint32_t index, __rte_unused uint32_t pool)
513 struct ecore_filter_ucast ucast;
515 qede_set_ucast_cmn_params(&ucast);
516 ucast.type = ECORE_FILTER_MAC;
517 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
518 (void)qede_mac_int_ops(eth_dev, &ucast, 1);
522 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
524 struct qede_dev *qdev = eth_dev->data->dev_private;
525 struct ecore_dev *edev = &qdev->edev;
526 struct ether_addr mac_addr;
527 struct ecore_filter_ucast ucast;
530 PMD_INIT_FUNC_TRACE(edev);
532 if (index >= qdev->dev_info.num_mac_filters) {
533 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
534 index, qdev->dev_info.num_mac_filters);
538 qede_set_ucast_cmn_params(&ucast);
539 ucast.opcode = ECORE_FILTER_REMOVE;
540 ucast.type = ECORE_FILTER_MAC;
542 /* Use the index maintained by rte */
543 ether_addr_copy(ð_dev->data->mac_addrs[index],
544 (struct ether_addr *)&ucast.mac);
546 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
550 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
552 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
553 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
554 struct ecore_filter_ucast ucast;
557 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
558 mac_addr->addr_bytes)) {
559 DP_ERR(edev, "Setting MAC address is not allowed\n");
560 ether_addr_copy(&qdev->primary_mac,
561 ð_dev->data->mac_addrs[0]);
565 /* First remove the primary mac */
566 qede_set_ucast_cmn_params(&ucast);
567 ucast.opcode = ECORE_FILTER_REMOVE;
568 ucast.type = ECORE_FILTER_MAC;
569 ether_addr_copy(&qdev->primary_mac,
570 (struct ether_addr *)&ucast.mac);
571 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
573 DP_ERR(edev, "Unable to remove current macaddr"
574 " Reverting to previous default mac\n");
575 ether_addr_copy(&qdev->primary_mac,
576 ð_dev->data->mac_addrs[0]);
581 ucast.opcode = ECORE_FILTER_ADD;
582 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
583 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
585 DP_ERR(edev, "Unable to add new default mac\n");
587 ether_addr_copy(mac_addr, &qdev->primary_mac);
590 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
592 struct ecore_dev *edev = &qdev->edev;
593 struct qed_update_vport_params params = {
595 .accept_any_vlan = action,
596 .update_accept_any_vlan_flg = 1,
600 /* Proceed only if action actually needs to be performed */
601 if (qdev->accept_any_vlan == action)
604 rc = qdev->ops->vport_update(edev, ¶ms);
606 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
607 action ? "enable" : "disable");
609 DP_INFO(edev, "%s accept-any-vlan\n",
610 action ? "enabled" : "disabled");
611 qdev->accept_any_vlan = action;
615 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
617 struct qed_update_vport_params vport_update_params;
618 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
619 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
622 memset(&vport_update_params, 0, sizeof(vport_update_params));
623 vport_update_params.vport_id = 0;
624 vport_update_params.update_inner_vlan_removal_flg = 1;
625 vport_update_params.inner_vlan_removal_flg = set_stripping;
626 rc = qdev->ops->vport_update(edev, &vport_update_params);
628 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
635 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
637 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
638 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
639 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
641 if (mask & ETH_VLAN_STRIP_MASK) {
642 if (rxmode->hw_vlan_strip)
643 (void)qede_vlan_stripping(eth_dev, 1);
645 (void)qede_vlan_stripping(eth_dev, 0);
648 if (mask & ETH_VLAN_FILTER_MASK) {
649 /* VLAN filtering kicks in when a VLAN is added */
650 if (rxmode->hw_vlan_filter) {
651 qede_vlan_filter_set(eth_dev, 0, 1);
653 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
655 " Please remove existing VLAN filters"
656 " before disabling VLAN filtering\n");
657 /* Signal app that VLAN filtering is still
660 rxmode->hw_vlan_filter = true;
662 qede_vlan_filter_set(eth_dev, 0, 0);
667 if (mask & ETH_VLAN_EXTEND_MASK)
668 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
669 " and classification is based on outer tag only\n");
671 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
672 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
675 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
676 uint16_t vlan_id, int on)
678 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
679 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
680 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
681 struct qede_vlan_entry *tmp = NULL;
682 struct qede_vlan_entry *vlan;
683 struct ecore_filter_ucast ucast;
687 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
688 DP_ERR(edev, "Reached max VLAN filter limit"
689 " enabling accept_any_vlan\n");
690 qede_config_accept_any_vlan(qdev, true);
694 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
695 if (tmp->vid == vlan_id) {
696 DP_ERR(edev, "VLAN %u already configured\n",
702 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
703 RTE_CACHE_LINE_SIZE);
706 DP_ERR(edev, "Did not allocate memory for VLAN\n");
710 qede_set_ucast_cmn_params(&ucast);
711 ucast.opcode = ECORE_FILTER_ADD;
712 ucast.type = ECORE_FILTER_VLAN;
713 ucast.vlan = vlan_id;
714 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
717 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
722 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
723 qdev->configured_vlans++;
724 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
725 vlan_id, qdev->configured_vlans);
728 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
729 if (tmp->vid == vlan_id)
734 if (qdev->configured_vlans == 0) {
736 "No VLAN filters configured yet\n");
740 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
744 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
746 qede_set_ucast_cmn_params(&ucast);
747 ucast.opcode = ECORE_FILTER_REMOVE;
748 ucast.type = ECORE_FILTER_VLAN;
749 ucast.vlan = vlan_id;
750 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
753 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
756 qdev->configured_vlans--;
757 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
758 vlan_id, qdev->configured_vlans);
765 static int qede_init_vport(struct qede_dev *qdev)
767 struct ecore_dev *edev = &qdev->edev;
768 struct qed_start_vport_params start = {0};
771 start.remove_inner_vlan = 1;
772 start.gro_enable = 0;
773 start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
775 start.drop_ttl0 = false;
776 start.clear_stats = 1;
777 start.handle_ptp_pkts = 0;
779 rc = qdev->ops->vport_start(edev, &start);
781 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
786 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
787 start.vport_id, ETHER_MTU);
792 static void qede_prandom_bytes(uint32_t *buff)
796 srand((unsigned int)time(NULL));
797 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
801 static int qede_config_rss(struct rte_eth_dev *eth_dev)
803 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
804 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
805 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
806 struct rte_eth_rss_reta_entry64 reta_conf[2];
807 struct rte_eth_rss_conf rss_conf;
808 uint32_t i, id, pos, q;
810 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
811 if (!rss_conf.rss_key) {
812 DP_INFO(edev, "Applying driver default key\n");
813 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
814 qede_prandom_bytes(&def_rss_key[0]);
815 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
818 /* Configure RSS hash */
819 if (qede_rss_hash_update(eth_dev, &rss_conf))
822 /* Configure default RETA */
823 memset(reta_conf, 0, sizeof(reta_conf));
824 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
825 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
827 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
828 id = i / RTE_RETA_GROUP_SIZE;
829 pos = i % RTE_RETA_GROUP_SIZE;
830 q = i % QEDE_RSS_COUNT(qdev);
831 reta_conf[id].reta[pos] = q;
833 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
834 ECORE_RSS_IND_TABLE_SIZE))
840 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
842 struct qede_dev *qdev = eth_dev->data->dev_private;
843 struct ecore_dev *edev = &qdev->edev;
844 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
847 PMD_INIT_FUNC_TRACE(edev);
849 /* Check requirements for 100G mode */
850 if (edev->num_hwfns > 1) {
851 if (eth_dev->data->nb_rx_queues < 2 ||
852 eth_dev->data->nb_tx_queues < 2) {
853 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
857 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
858 (eth_dev->data->nb_tx_queues % 2 != 0)) {
860 "100G mode needs even no. of RX/TX queues\n");
865 /* Sanity checks and throw warnings */
866 if (rxmode->enable_scatter == 1)
867 eth_dev->data->scattered_rx = 1;
869 if (rxmode->enable_lro == 1) {
870 DP_ERR(edev, "LRO is not supported\n");
874 if (!rxmode->hw_strip_crc)
875 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
877 if (!rxmode->hw_ip_checksum)
878 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
881 /* Check for the port restart case */
882 if (qdev->state != QEDE_DEV_INIT) {
883 rc = qdev->ops->vport_stop(edev, 0);
886 qede_dealloc_fp_resc(eth_dev);
889 qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
890 qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
891 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
893 /* Fastpath status block should be initialized before sending
894 * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
896 rc = qede_alloc_fp_resc(qdev);
900 /* Issue VPORT-START with default config values to allow
901 * other port configurations early on.
903 rc = qede_init_vport(qdev);
907 /* Do RSS configuration after vport-start */
908 switch (rxmode->mq_mode) {
910 rc = qede_config_rss(eth_dev);
912 qdev->ops->vport_stop(edev, 0);
913 qede_dealloc_fp_resc(eth_dev);
918 DP_INFO(edev, "RSS is disabled\n");
921 DP_ERR(edev, "Unsupported RSS mode\n");
922 qdev->ops->vport_stop(edev, 0);
923 qede_dealloc_fp_resc(eth_dev);
927 SLIST_INIT(&qdev->vlan_list_head);
929 /* Add primary mac for PF */
931 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
933 /* Enable VLAN offloads by default */
934 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
935 ETH_VLAN_FILTER_MASK |
936 ETH_VLAN_EXTEND_MASK);
938 qdev->state = QEDE_DEV_CONFIG;
940 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
941 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
947 /* Info about HW descriptor ring limitations */
948 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
949 .nb_max = NUM_RX_BDS_MAX,
951 .nb_align = 128 /* lowest common multiple */
954 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
955 .nb_max = NUM_TX_BDS_MAX,
961 qede_dev_info_get(struct rte_eth_dev *eth_dev,
962 struct rte_eth_dev_info *dev_info)
964 struct qede_dev *qdev = eth_dev->data->dev_private;
965 struct ecore_dev *edev = &qdev->edev;
966 struct qed_link_output link;
967 uint32_t speed_cap = 0;
969 PMD_INIT_FUNC_TRACE(edev);
971 dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
972 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
973 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
974 dev_info->rx_desc_lim = qede_rx_desc_lim;
975 dev_info->tx_desc_lim = qede_tx_desc_lim;
978 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
979 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
981 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
982 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
983 dev_info->max_tx_queues = dev_info->max_rx_queues;
985 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
986 dev_info->max_vfs = 0;
987 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
988 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
989 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
991 dev_info->default_txconf = (struct rte_eth_txconf) {
992 .txq_flags = QEDE_TXQ_FLAGS,
995 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
996 DEV_RX_OFFLOAD_IPV4_CKSUM |
997 DEV_RX_OFFLOAD_UDP_CKSUM |
998 DEV_RX_OFFLOAD_TCP_CKSUM |
999 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM);
1000 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1001 DEV_TX_OFFLOAD_IPV4_CKSUM |
1002 DEV_TX_OFFLOAD_UDP_CKSUM |
1003 DEV_TX_OFFLOAD_TCP_CKSUM |
1004 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM);
1006 memset(&link, 0, sizeof(struct qed_link_output));
1007 qdev->ops->common->get_link(edev, &link);
1008 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1009 speed_cap |= ETH_LINK_SPEED_1G;
1010 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1011 speed_cap |= ETH_LINK_SPEED_10G;
1012 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1013 speed_cap |= ETH_LINK_SPEED_25G;
1014 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1015 speed_cap |= ETH_LINK_SPEED_40G;
1016 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1017 speed_cap |= ETH_LINK_SPEED_50G;
1018 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1019 speed_cap |= ETH_LINK_SPEED_100G;
1020 dev_info->speed_capa = speed_cap;
1023 /* return 0 means link status changed, -1 means not changed */
1025 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1027 struct qede_dev *qdev = eth_dev->data->dev_private;
1028 struct ecore_dev *edev = &qdev->edev;
1029 uint16_t link_duplex;
1030 struct qed_link_output link;
1031 struct rte_eth_link *curr = ð_dev->data->dev_link;
1033 memset(&link, 0, sizeof(struct qed_link_output));
1034 qdev->ops->common->get_link(edev, &link);
1037 curr->link_speed = link.speed;
1040 switch (link.duplex) {
1041 case QEDE_DUPLEX_HALF:
1042 link_duplex = ETH_LINK_HALF_DUPLEX;
1044 case QEDE_DUPLEX_FULL:
1045 link_duplex = ETH_LINK_FULL_DUPLEX;
1047 case QEDE_DUPLEX_UNKNOWN:
1051 curr->link_duplex = link_duplex;
1054 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1057 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1058 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1060 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1061 curr->link_speed, curr->link_duplex,
1062 curr->link_autoneg, curr->link_status);
1064 /* return 0 means link status changed, -1 means not changed */
1065 return ((curr->link_status == link.link_up) ? -1 : 0);
1068 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1070 struct qede_dev *qdev = eth_dev->data->dev_private;
1071 struct ecore_dev *edev = &qdev->edev;
1073 PMD_INIT_FUNC_TRACE(edev);
1075 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1077 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1078 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1080 qed_configure_filter_rx_mode(eth_dev, type);
1083 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1085 struct qede_dev *qdev = eth_dev->data->dev_private;
1086 struct ecore_dev *edev = &qdev->edev;
1088 PMD_INIT_FUNC_TRACE(edev);
1090 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1091 qed_configure_filter_rx_mode(eth_dev,
1092 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1094 qed_configure_filter_rx_mode(eth_dev,
1095 QED_FILTER_RX_MODE_TYPE_REGULAR);
1098 static void qede_poll_sp_sb_cb(void *param)
1100 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1101 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1102 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1105 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1106 qede_interrupt_action(&edev->hwfns[1]);
1108 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1112 DP_ERR(edev, "Unable to start periodic"
1113 " timer rc %d\n", rc);
1114 assert(false && "Unable to start periodic timer");
1118 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1120 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1121 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1122 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1125 PMD_INIT_FUNC_TRACE(edev);
1127 /* dev_stop() shall cleanup fp resources in hw but without releasing
1128 * dma memories and sw structures so that dev_start() can be called
1129 * by the app without reconfiguration. However, in dev_close() we
1130 * can release all the resources and device can be brought up newly
1132 if (qdev->state != QEDE_DEV_STOP)
1133 qede_dev_stop(eth_dev);
1135 DP_INFO(edev, "Device is already stopped\n");
1137 rc = qdev->ops->vport_stop(edev, 0);
1139 DP_ERR(edev, "Failed to stop VPORT\n");
1141 qede_dealloc_fp_resc(eth_dev);
1143 qdev->ops->common->slowpath_stop(edev);
1145 qdev->ops->common->remove(edev);
1147 rte_intr_disable(&pci_dev->intr_handle);
1149 rte_intr_callback_unregister(&pci_dev->intr_handle,
1150 qede_interrupt_handler, (void *)eth_dev);
1152 if (edev->num_hwfns > 1)
1153 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1155 qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1159 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1161 struct qede_dev *qdev = eth_dev->data->dev_private;
1162 struct ecore_dev *edev = &qdev->edev;
1163 struct ecore_eth_stats stats;
1164 unsigned int i = 0, j = 0, qid;
1165 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1166 struct qede_tx_queue *txq;
1168 qdev->ops->get_vport_stats(edev, &stats);
1171 eth_stats->ipackets = stats.rx_ucast_pkts +
1172 stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1174 eth_stats->ibytes = stats.rx_ucast_bytes +
1175 stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1177 eth_stats->ierrors = stats.rx_crc_errors +
1178 stats.rx_align_errors +
1179 stats.rx_carrier_errors +
1180 stats.rx_oversize_packets +
1181 stats.rx_jabbers + stats.rx_undersize_packets;
1183 eth_stats->rx_nombuf = stats.no_buff_discards;
1185 eth_stats->imissed = stats.mftag_filter_discards +
1186 stats.mac_filter_discards +
1187 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1190 eth_stats->opackets = stats.tx_ucast_pkts +
1191 stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1193 eth_stats->obytes = stats.tx_ucast_bytes +
1194 stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1196 eth_stats->oerrors = stats.tx_err_drop_pkts;
1199 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1200 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1201 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1202 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1203 if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) ||
1204 (txq_stat_cntrs != QEDE_TSS_COUNT(qdev)))
1205 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1206 "Not all the queue stats will be displayed. Set"
1207 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1208 " appropriately and retry.\n");
1210 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1211 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1212 eth_stats->q_ipackets[i] =
1214 ((char *)(qdev->fp_array[(qid)].rxq)) +
1215 offsetof(struct qede_rx_queue,
1217 eth_stats->q_errors[i] =
1219 ((char *)(qdev->fp_array[(qid)].rxq)) +
1220 offsetof(struct qede_rx_queue,
1223 ((char *)(qdev->fp_array[(qid)].rxq)) +
1224 offsetof(struct qede_rx_queue,
1228 if (i == rxq_stat_cntrs)
1232 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1233 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1234 txq = qdev->fp_array[(qid)].txqs[0];
1235 eth_stats->q_opackets[j] =
1236 *((uint64_t *)(uintptr_t)
1237 (((uint64_t)(uintptr_t)(txq)) +
1238 offsetof(struct qede_tx_queue,
1242 if (j == txq_stat_cntrs)
1248 qede_get_xstats_count(struct qede_dev *qdev) {
1249 return RTE_DIM(qede_xstats_strings) +
1250 (RTE_DIM(qede_rxq_xstats_strings) *
1251 RTE_MIN(QEDE_RSS_COUNT(qdev),
1252 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1256 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1257 struct rte_eth_xstat_name *xstats_names, unsigned limit)
1259 struct qede_dev *qdev = dev->data->dev_private;
1260 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1261 unsigned int i, qid, stat_idx = 0;
1262 unsigned int rxq_stat_cntrs;
1264 if (xstats_names != NULL) {
1265 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1266 snprintf(xstats_names[stat_idx].name,
1267 sizeof(xstats_names[stat_idx].name),
1269 qede_xstats_strings[i].name);
1273 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1274 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1275 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1276 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1277 snprintf(xstats_names[stat_idx].name,
1278 sizeof(xstats_names[stat_idx].name),
1280 qede_rxq_xstats_strings[i].name, qid,
1281 qede_rxq_xstats_strings[i].name + 4);
1291 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1294 struct qede_dev *qdev = dev->data->dev_private;
1295 struct ecore_dev *edev = &qdev->edev;
1296 struct ecore_eth_stats stats;
1297 const unsigned int num = qede_get_xstats_count(qdev);
1298 unsigned int i, qid, stat_idx = 0;
1299 unsigned int rxq_stat_cntrs;
1304 qdev->ops->get_vport_stats(edev, &stats);
1306 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1307 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1308 qede_xstats_strings[i].offset);
1309 xstats[stat_idx].id = stat_idx;
1313 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1314 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1315 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1316 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1317 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1318 xstats[stat_idx].value = *(uint64_t *)(
1319 ((char *)(qdev->fp_array[(qid)].rxq)) +
1320 qede_rxq_xstats_strings[i].offset);
1321 xstats[stat_idx].id = stat_idx;
1331 qede_reset_xstats(struct rte_eth_dev *dev)
1333 struct qede_dev *qdev = dev->data->dev_private;
1334 struct ecore_dev *edev = &qdev->edev;
1336 ecore_reset_vport_stats(edev);
1339 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1341 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1342 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1343 struct qed_link_params link_params;
1346 DP_INFO(edev, "setting link state %d\n", link_up);
1347 memset(&link_params, 0, sizeof(link_params));
1348 link_params.link_up = link_up;
1349 rc = qdev->ops->common->set_link(edev, &link_params);
1350 if (rc != ECORE_SUCCESS)
1351 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1356 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1358 return qede_dev_set_link_state(eth_dev, true);
1361 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1363 return qede_dev_set_link_state(eth_dev, false);
1366 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1368 struct qede_dev *qdev = eth_dev->data->dev_private;
1369 struct ecore_dev *edev = &qdev->edev;
1371 ecore_reset_vport_stats(edev);
1374 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1376 enum qed_filter_rx_mode_type type =
1377 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1379 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1380 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1382 qed_configure_filter_rx_mode(eth_dev, type);
1385 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1387 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1388 qed_configure_filter_rx_mode(eth_dev,
1389 QED_FILTER_RX_MODE_TYPE_PROMISC);
1391 qed_configure_filter_rx_mode(eth_dev,
1392 QED_FILTER_RX_MODE_TYPE_REGULAR);
1395 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1396 struct rte_eth_fc_conf *fc_conf)
1398 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1399 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1400 struct qed_link_output current_link;
1401 struct qed_link_params params;
1403 memset(¤t_link, 0, sizeof(current_link));
1404 qdev->ops->common->get_link(edev, ¤t_link);
1406 memset(¶ms, 0, sizeof(params));
1407 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1408 if (fc_conf->autoneg) {
1409 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1410 DP_ERR(edev, "Autoneg not supported\n");
1413 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1416 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1417 if (fc_conf->mode == RTE_FC_FULL)
1418 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1419 QED_LINK_PAUSE_RX_ENABLE);
1420 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1421 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1422 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1423 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1425 params.link_up = true;
1426 (void)qdev->ops->common->set_link(edev, ¶ms);
1431 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1432 struct rte_eth_fc_conf *fc_conf)
1434 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1435 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1436 struct qed_link_output current_link;
1438 memset(¤t_link, 0, sizeof(current_link));
1439 qdev->ops->common->get_link(edev, ¤t_link);
1441 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1442 fc_conf->autoneg = true;
1444 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1445 QED_LINK_PAUSE_TX_ENABLE))
1446 fc_conf->mode = RTE_FC_FULL;
1447 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1448 fc_conf->mode = RTE_FC_RX_PAUSE;
1449 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1450 fc_conf->mode = RTE_FC_TX_PAUSE;
1452 fc_conf->mode = RTE_FC_NONE;
1457 static const uint32_t *
1458 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1460 static const uint32_t ptypes[] = {
1466 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1472 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1475 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1476 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1477 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1478 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1479 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1480 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1483 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1484 struct rte_eth_rss_conf *rss_conf)
1486 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1487 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1488 struct ecore_sp_vport_update_params vport_update_params;
1489 struct ecore_rss_params rss_params;
1490 struct ecore_rss_params params;
1491 struct ecore_hwfn *p_hwfn;
1492 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1493 uint64_t hf = rss_conf->rss_hf;
1494 uint8_t len = rss_conf->rss_key_len;
1498 memset(&vport_update_params, 0, sizeof(vport_update_params));
1499 memset(&rss_params, 0, sizeof(rss_params));
1501 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1502 (unsigned long)hf, len, key);
1506 DP_INFO(edev, "Enabling rss\n");
1509 qede_init_rss_caps(&rss_params.rss_caps, hf);
1510 rss_params.update_rss_capabilities = 1;
1514 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1515 DP_ERR(edev, "RSS key length exceeds limit\n");
1518 DP_INFO(edev, "Applying user supplied hash key\n");
1519 rss_params.update_rss_key = 1;
1520 memcpy(&rss_params.rss_key, key, len);
1522 rss_params.rss_enable = 1;
1525 rss_params.update_rss_config = 1;
1526 /* tbl_size has to be set with capabilities */
1527 rss_params.rss_table_size_log = 7;
1528 vport_update_params.vport_id = 0;
1529 vport_update_params.rss_params = &rss_params;
1531 for_each_hwfn(edev, i) {
1532 p_hwfn = &edev->hwfns[i];
1533 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1534 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1535 ECORE_SPQ_MODE_EBLOCK, NULL);
1537 DP_ERR(edev, "vport-update for RSS failed\n");
1541 qdev->rss_enable = rss_params.rss_enable;
1543 /* Update local structure for hash query */
1544 qdev->rss_conf.rss_hf = hf;
1545 qdev->rss_conf.rss_key_len = len;
1546 if (qdev->rss_enable) {
1547 if (qdev->rss_conf.rss_key == NULL) {
1548 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1549 if (qdev->rss_conf.rss_key == NULL) {
1550 DP_ERR(edev, "No memory to store RSS key\n");
1555 DP_INFO(edev, "Storing RSS key\n");
1556 memcpy(qdev->rss_conf.rss_key, key, len);
1558 } else if (!qdev->rss_enable && len == 0) {
1559 if (qdev->rss_conf.rss_key) {
1560 free(qdev->rss_conf.rss_key);
1561 qdev->rss_conf.rss_key = NULL;
1562 DP_INFO(edev, "Free RSS key\n");
1569 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1570 struct rte_eth_rss_conf *rss_conf)
1572 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1574 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1575 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1577 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1578 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1579 rss_conf->rss_key_len);
1583 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1584 struct rte_eth_rss_reta_entry64 *reta_conf,
1587 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1588 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1589 struct ecore_sp_vport_update_params vport_update_params;
1590 struct ecore_rss_params params;
1591 struct ecore_hwfn *p_hwfn;
1592 uint16_t i, idx, shift;
1596 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1597 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1602 memset(&vport_update_params, 0, sizeof(vport_update_params));
1603 memset(¶ms, 0, sizeof(params));
1605 for (i = 0; i < reta_size; i++) {
1606 idx = i / RTE_RETA_GROUP_SIZE;
1607 shift = i % RTE_RETA_GROUP_SIZE;
1608 if (reta_conf[idx].mask & (1ULL << shift)) {
1609 entry = reta_conf[idx].reta[shift];
1610 params.rss_ind_table[i] = entry;
1614 /* Fix up RETA for CMT mode device */
1615 if (edev->num_hwfns > 1)
1616 qdev->rss_enable = qed_update_rss_parm_cmt(edev,
1617 ¶ms.rss_ind_table[0]);
1618 params.update_rss_ind_table = 1;
1619 params.rss_table_size_log = 7;
1620 params.update_rss_config = 1;
1621 vport_update_params.vport_id = 0;
1622 /* Use the current value of rss_enable */
1623 params.rss_enable = qdev->rss_enable;
1624 vport_update_params.rss_params = ¶ms;
1626 for_each_hwfn(edev, i) {
1627 p_hwfn = &edev->hwfns[i];
1628 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1629 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1630 ECORE_SPQ_MODE_EBLOCK, NULL);
1632 DP_ERR(edev, "vport-update for RSS failed\n");
1637 /* Update the local copy for RETA query command */
1638 memcpy(qdev->rss_ind_table, params.rss_ind_table,
1639 sizeof(params.rss_ind_table));
1644 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1645 struct rte_eth_rss_reta_entry64 *reta_conf,
1648 struct qede_dev *qdev = eth_dev->data->dev_private;
1649 struct ecore_dev *edev = &qdev->edev;
1650 uint16_t i, idx, shift;
1653 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1654 DP_ERR(edev, "reta_size %d is not supported\n",
1659 for (i = 0; i < reta_size; i++) {
1660 idx = i / RTE_RETA_GROUP_SIZE;
1661 shift = i % RTE_RETA_GROUP_SIZE;
1662 if (reta_conf[idx].mask & (1ULL << shift)) {
1663 entry = qdev->rss_ind_table[i];
1664 reta_conf[idx].reta[shift] = entry;
1671 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1673 uint32_t frame_size;
1674 struct qede_dev *qdev = dev->data->dev_private;
1675 struct rte_eth_dev_info dev_info = {0};
1677 qede_dev_info_get(dev, &dev_info);
1680 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1682 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1685 if (!dev->data->scattered_rx &&
1686 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1689 if (frame_size > ETHER_MAX_LEN)
1690 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1692 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1694 /* update max frame size */
1695 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1698 qede_dev_start(dev);
1704 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1705 struct rte_eth_udp_tunnel *tunnel_udp,
1708 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1709 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1710 struct ecore_tunnel_info tunn; /* @DPDK */
1711 struct ecore_hwfn *p_hwfn;
1714 PMD_INIT_FUNC_TRACE(edev);
1716 memset(&tunn, 0, sizeof(tunn));
1717 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1718 tunn.vxlan_port.b_update_port = true;
1719 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
1720 QEDE_VXLAN_DEF_PORT;
1721 for_each_hwfn(edev, i) {
1722 p_hwfn = &edev->hwfns[i];
1723 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1724 ECORE_SPQ_MODE_CB, NULL);
1725 if (rc != ECORE_SUCCESS) {
1726 DP_ERR(edev, "Unable to config UDP port %u\n",
1727 tunn.vxlan_port.port);
1737 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1738 struct rte_eth_udp_tunnel *tunnel_udp)
1740 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1744 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1745 struct rte_eth_udp_tunnel *tunnel_udp)
1747 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1750 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1751 uint32_t *clss, char *str)
1754 *clss = MAX_ECORE_TUNN_CLSS;
1756 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1757 if (filter == qede_tunn_types[j].rte_filter_type) {
1758 *type = qede_tunn_types[j].qede_type;
1759 *clss = qede_tunn_types[j].qede_tunn_clss;
1760 strcpy(str, qede_tunn_types[j].string);
1767 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1768 const struct rte_eth_tunnel_filter_conf *conf,
1771 /* Init commmon ucast params first */
1772 qede_set_ucast_cmn_params(ucast);
1774 /* Copy out the required fields based on classification type */
1778 case ECORE_FILTER_VNI:
1779 ucast->vni = conf->tenant_id;
1781 case ECORE_FILTER_INNER_VLAN:
1782 ucast->vlan = conf->inner_vlan;
1784 case ECORE_FILTER_MAC:
1785 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1788 case ECORE_FILTER_INNER_MAC:
1789 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1792 case ECORE_FILTER_MAC_VNI_PAIR:
1793 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1795 ucast->vni = conf->tenant_id;
1797 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1798 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1800 ucast->vni = conf->tenant_id;
1802 case ECORE_FILTER_INNER_PAIR:
1803 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1805 ucast->vlan = conf->inner_vlan;
1811 return ECORE_SUCCESS;
1814 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1815 enum rte_filter_op filter_op,
1816 const struct rte_eth_tunnel_filter_conf *conf)
1818 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1819 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1820 struct ecore_tunnel_info tunn;
1821 struct ecore_hwfn *p_hwfn;
1822 enum ecore_filter_ucast_type type;
1823 enum ecore_tunn_clss clss;
1824 struct ecore_filter_ucast ucast;
1826 uint16_t filter_type;
1829 filter_type = conf->filter_type | qdev->vxlan_filter_type;
1830 /* First determine if the given filter classification is supported */
1831 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1832 if (clss == MAX_ECORE_TUNN_CLSS) {
1833 DP_ERR(edev, "Wrong filter type\n");
1836 /* Init tunnel ucast params */
1837 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1838 if (rc != ECORE_SUCCESS) {
1839 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1843 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1844 str, filter_op, ucast.type);
1845 switch (filter_op) {
1846 case RTE_ETH_FILTER_ADD:
1847 ucast.opcode = ECORE_FILTER_ADD;
1849 /* Skip MAC/VLAN if filter is based on VNI */
1850 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1851 rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1853 /* Enable accept anyvlan */
1854 qede_config_accept_any_vlan(qdev, true);
1857 rc = qede_ucast_filter(eth_dev, &ucast, 1);
1859 rc = ecore_filter_ucast_cmd(edev, &ucast,
1860 ECORE_SPQ_MODE_CB, NULL);
1863 if (rc != ECORE_SUCCESS)
1866 qdev->vxlan_filter_type = filter_type;
1868 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1869 qede_set_cmn_tunn_param(&tunn, clss, true, true);
1870 for_each_hwfn(edev, i) {
1871 p_hwfn = &edev->hwfns[i];
1872 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1873 &tunn, ECORE_SPQ_MODE_CB, NULL);
1874 if (rc != ECORE_SUCCESS) {
1875 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1876 tunn.vxlan.tun_cls);
1879 qdev->num_tunn_filters++; /* Filter added successfully */
1881 case RTE_ETH_FILTER_DELETE:
1882 ucast.opcode = ECORE_FILTER_REMOVE;
1884 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1885 rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1887 rc = qede_ucast_filter(eth_dev, &ucast, 0);
1889 rc = ecore_filter_ucast_cmd(edev, &ucast,
1890 ECORE_SPQ_MODE_CB, NULL);
1892 if (rc != ECORE_SUCCESS)
1895 qdev->vxlan_filter_type = filter_type;
1896 qdev->num_tunn_filters--;
1898 /* Disable VXLAN if VXLAN filters become 0 */
1899 if (qdev->num_tunn_filters == 0) {
1900 DP_INFO(edev, "Disabling VXLAN tunneling\n");
1902 /* Use 0 as tunnel mode */
1903 qede_set_cmn_tunn_param(&tunn, clss, false, true);
1904 for_each_hwfn(edev, i) {
1905 p_hwfn = &edev->hwfns[i];
1906 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1907 ECORE_SPQ_MODE_CB, NULL);
1908 if (rc != ECORE_SUCCESS) {
1910 "Failed to update tunn_clss %u\n",
1911 tunn.vxlan.tun_cls);
1918 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1921 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1926 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1927 enum rte_filter_type filter_type,
1928 enum rte_filter_op filter_op,
1931 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1932 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1933 struct rte_eth_tunnel_filter_conf *filter_conf =
1934 (struct rte_eth_tunnel_filter_conf *)arg;
1936 switch (filter_type) {
1937 case RTE_ETH_FILTER_TUNNEL:
1938 switch (filter_conf->tunnel_type) {
1939 case RTE_TUNNEL_TYPE_VXLAN:
1941 "Packet steering to the specified Rx queue"
1942 " is not supported with VXLAN tunneling");
1943 return(qede_vxlan_tunn_config(eth_dev, filter_op,
1945 /* Place holders for future tunneling support */
1946 case RTE_TUNNEL_TYPE_GENEVE:
1947 case RTE_TUNNEL_TYPE_TEREDO:
1948 case RTE_TUNNEL_TYPE_NVGRE:
1949 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1950 case RTE_L2_TUNNEL_TYPE_E_TAG:
1951 DP_ERR(edev, "Unsupported tunnel type %d\n",
1952 filter_conf->tunnel_type);
1954 case RTE_TUNNEL_TYPE_NONE:
1959 case RTE_ETH_FILTER_FDIR:
1960 case RTE_ETH_FILTER_MACVLAN:
1961 case RTE_ETH_FILTER_ETHERTYPE:
1962 case RTE_ETH_FILTER_FLEXIBLE:
1963 case RTE_ETH_FILTER_SYN:
1964 case RTE_ETH_FILTER_NTUPLE:
1965 case RTE_ETH_FILTER_HASH:
1966 case RTE_ETH_FILTER_L2_TUNNEL:
1967 case RTE_ETH_FILTER_MAX:
1969 DP_ERR(edev, "Unsupported filter type %d\n",
1977 static const struct eth_dev_ops qede_eth_dev_ops = {
1978 .dev_configure = qede_dev_configure,
1979 .dev_infos_get = qede_dev_info_get,
1980 .rx_queue_setup = qede_rx_queue_setup,
1981 .rx_queue_release = qede_rx_queue_release,
1982 .tx_queue_setup = qede_tx_queue_setup,
1983 .tx_queue_release = qede_tx_queue_release,
1984 .dev_start = qede_dev_start,
1985 .dev_set_link_up = qede_dev_set_link_up,
1986 .dev_set_link_down = qede_dev_set_link_down,
1987 .link_update = qede_link_update,
1988 .promiscuous_enable = qede_promiscuous_enable,
1989 .promiscuous_disable = qede_promiscuous_disable,
1990 .allmulticast_enable = qede_allmulticast_enable,
1991 .allmulticast_disable = qede_allmulticast_disable,
1992 .dev_stop = qede_dev_stop,
1993 .dev_close = qede_dev_close,
1994 .stats_get = qede_get_stats,
1995 .stats_reset = qede_reset_stats,
1996 .xstats_get = qede_get_xstats,
1997 .xstats_reset = qede_reset_xstats,
1998 .xstats_get_names = qede_get_xstats_names,
1999 .mac_addr_add = qede_mac_addr_add,
2000 .mac_addr_remove = qede_mac_addr_remove,
2001 .mac_addr_set = qede_mac_addr_set,
2002 .vlan_offload_set = qede_vlan_offload_set,
2003 .vlan_filter_set = qede_vlan_filter_set,
2004 .flow_ctrl_set = qede_flow_ctrl_set,
2005 .flow_ctrl_get = qede_flow_ctrl_get,
2006 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2007 .rss_hash_update = qede_rss_hash_update,
2008 .rss_hash_conf_get = qede_rss_hash_conf_get,
2009 .reta_update = qede_rss_reta_update,
2010 .reta_query = qede_rss_reta_query,
2011 .mtu_set = qede_set_mtu,
2012 .filter_ctrl = qede_dev_filter_ctrl,
2013 .udp_tunnel_port_add = qede_udp_dst_port_add,
2014 .udp_tunnel_port_del = qede_udp_dst_port_del,
2017 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2018 .dev_configure = qede_dev_configure,
2019 .dev_infos_get = qede_dev_info_get,
2020 .rx_queue_setup = qede_rx_queue_setup,
2021 .rx_queue_release = qede_rx_queue_release,
2022 .tx_queue_setup = qede_tx_queue_setup,
2023 .tx_queue_release = qede_tx_queue_release,
2024 .dev_start = qede_dev_start,
2025 .dev_set_link_up = qede_dev_set_link_up,
2026 .dev_set_link_down = qede_dev_set_link_down,
2027 .link_update = qede_link_update,
2028 .promiscuous_enable = qede_promiscuous_enable,
2029 .promiscuous_disable = qede_promiscuous_disable,
2030 .allmulticast_enable = qede_allmulticast_enable,
2031 .allmulticast_disable = qede_allmulticast_disable,
2032 .dev_stop = qede_dev_stop,
2033 .dev_close = qede_dev_close,
2034 .stats_get = qede_get_stats,
2035 .stats_reset = qede_reset_stats,
2036 .xstats_get = qede_get_xstats,
2037 .xstats_reset = qede_reset_xstats,
2038 .xstats_get_names = qede_get_xstats_names,
2039 .vlan_offload_set = qede_vlan_offload_set,
2040 .vlan_filter_set = qede_vlan_filter_set,
2041 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2042 .rss_hash_update = qede_rss_hash_update,
2043 .rss_hash_conf_get = qede_rss_hash_conf_get,
2044 .reta_update = qede_rss_reta_update,
2045 .reta_query = qede_rss_reta_query,
2046 .mtu_set = qede_set_mtu,
2049 static void qede_update_pf_params(struct ecore_dev *edev)
2051 struct ecore_pf_params pf_params;
2053 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2054 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2055 qed_ops->common->update_pf_params(edev, &pf_params);
2058 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2060 struct rte_pci_device *pci_dev;
2061 struct rte_pci_addr pci_addr;
2062 struct qede_dev *adapter;
2063 struct ecore_dev *edev;
2064 struct qed_dev_eth_info dev_info;
2065 struct qed_slowpath_params params;
2066 static bool do_once = true;
2067 uint8_t bulletin_change;
2068 uint8_t vf_mac[ETHER_ADDR_LEN];
2069 uint8_t is_mac_forced;
2071 /* Fix up ecore debug level */
2072 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2073 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2074 uint32_t max_mac_addrs;
2077 /* Extract key data structures */
2078 adapter = eth_dev->data->dev_private;
2079 edev = &adapter->edev;
2080 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2081 pci_addr = pci_dev->addr;
2083 PMD_INIT_FUNC_TRACE(edev);
2085 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2086 pci_addr.bus, pci_addr.devid, pci_addr.function,
2087 eth_dev->data->port_id);
2089 eth_dev->rx_pkt_burst = qede_recv_pkts;
2090 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2092 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2093 DP_NOTICE(edev, false,
2094 "Skipping device init from secondary process\n");
2098 rte_eth_copy_pci_info(eth_dev, pci_dev);
2101 edev->vendor_id = pci_dev->id.vendor_id;
2102 edev->device_id = pci_dev->id.device_id;
2104 qed_ops = qed_get_eth_ops();
2106 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2110 DP_INFO(edev, "Starting qede probe\n");
2112 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
2113 dp_module, dp_level, is_vf);
2116 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2120 qede_update_pf_params(edev);
2122 rte_intr_callback_register(&pci_dev->intr_handle,
2123 qede_interrupt_handler, (void *)eth_dev);
2125 if (rte_intr_enable(&pci_dev->intr_handle)) {
2126 DP_ERR(edev, "rte_intr_enable() failed\n");
2130 /* Start the Slowpath-process */
2131 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2132 params.int_mode = ECORE_INT_MODE_MSIX;
2133 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2134 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2135 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2136 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2137 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2138 QEDE_PMD_DRV_VER_STR_SIZE);
2140 /* For CMT mode device do periodic polling for slowpath events.
2141 * This is required since uio device uses only one MSI-x
2142 * interrupt vector but we need one for each engine.
2144 if (edev->num_hwfns > 1 && IS_PF(edev)) {
2145 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2149 DP_ERR(edev, "Unable to start periodic"
2150 " timer rc %d\n", rc);
2155 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2157 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2158 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2163 rc = qed_ops->fill_dev_info(edev, &dev_info);
2165 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2166 qed_ops->common->slowpath_stop(edev);
2167 qed_ops->common->remove(edev);
2168 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2173 qede_alloc_etherdev(adapter, &dev_info);
2175 adapter->ops->common->set_name(edev, edev->name);
2178 adapter->dev_info.num_mac_filters =
2179 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2182 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2183 (uint32_t *)&adapter->dev_info.num_mac_filters);
2185 /* Allocate memory for storing MAC addr */
2186 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2188 adapter->dev_info.num_mac_filters),
2189 RTE_CACHE_LINE_SIZE);
2191 if (eth_dev->data->mac_addrs == NULL) {
2192 DP_ERR(edev, "Failed to allocate MAC address\n");
2193 qed_ops->common->slowpath_stop(edev);
2194 qed_ops->common->remove(edev);
2195 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2201 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2202 hw_info.hw_mac_addr,
2203 ð_dev->data->mac_addrs[0]);
2204 ether_addr_copy(ð_dev->data->mac_addrs[0],
2205 &adapter->primary_mac);
2207 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2209 if (bulletin_change) {
2211 ecore_vf_bulletin_get_forced_mac(
2212 ECORE_LEADING_HWFN(edev),
2215 if (is_mac_exist && is_mac_forced) {
2216 DP_INFO(edev, "VF macaddr received from PF\n");
2217 ether_addr_copy((struct ether_addr *)&vf_mac,
2218 ð_dev->data->mac_addrs[0]);
2219 ether_addr_copy(ð_dev->data->mac_addrs[0],
2220 &adapter->primary_mac);
2222 DP_NOTICE(edev, false,
2223 "No VF macaddr assigned\n");
2228 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2231 qede_print_adapter_info(adapter);
2235 adapter->state = QEDE_DEV_INIT;
2237 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2238 adapter->primary_mac.addr_bytes[0],
2239 adapter->primary_mac.addr_bytes[1],
2240 adapter->primary_mac.addr_bytes[2],
2241 adapter->primary_mac.addr_bytes[3],
2242 adapter->primary_mac.addr_bytes[4],
2243 adapter->primary_mac.addr_bytes[5]);
2248 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2250 return qede_common_dev_init(eth_dev, 1);
2253 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2255 return qede_common_dev_init(eth_dev, 0);
2258 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2260 /* only uninitialize in the primary process */
2261 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2264 /* safe to close dev here */
2265 qede_dev_close(eth_dev);
2267 eth_dev->dev_ops = NULL;
2268 eth_dev->rx_pkt_burst = NULL;
2269 eth_dev->tx_pkt_burst = NULL;
2271 if (eth_dev->data->mac_addrs)
2272 rte_free(eth_dev->data->mac_addrs);
2274 eth_dev->data->mac_addrs = NULL;
2279 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2281 return qede_dev_common_uninit(eth_dev);
2284 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2286 return qede_dev_common_uninit(eth_dev);
2289 static const struct rte_pci_id pci_id_qedevf_map[] = {
2290 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2292 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2295 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2298 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2303 static const struct rte_pci_id pci_id_qede_map[] = {
2304 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2306 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2309 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2312 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2315 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2318 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2321 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2324 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2327 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2330 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2333 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2338 static struct eth_driver rte_qedevf_pmd = {
2340 .id_table = pci_id_qedevf_map,
2342 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2343 .probe = rte_eth_dev_pci_probe,
2344 .remove = rte_eth_dev_pci_remove,
2346 .eth_dev_init = qedevf_eth_dev_init,
2347 .eth_dev_uninit = qedevf_eth_dev_uninit,
2348 .dev_private_size = sizeof(struct qede_dev),
2351 static struct eth_driver rte_qede_pmd = {
2353 .id_table = pci_id_qede_map,
2355 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2356 .probe = rte_eth_dev_pci_probe,
2357 .remove = rte_eth_dev_pci_remove,
2359 .eth_dev_init = qede_eth_dev_init,
2360 .eth_dev_uninit = qede_eth_dev_uninit,
2361 .dev_private_size = sizeof(struct qede_dev),
2364 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
2365 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2366 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2367 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
2368 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2369 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");