2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
12 #include <rte_kvargs.h>
15 int qede_logtype_init;
16 int qede_logtype_driver;
18 static const struct qed_eth_ops *qed_ops;
19 static int64_t timer_period = 1;
21 /* VXLAN tunnel classification mapping */
22 const struct _qede_udp_tunn_types {
23 uint16_t rte_filter_type;
24 enum ecore_filter_ucast_type qede_type;
25 enum ecore_tunn_clss qede_tunn_clss;
27 } qede_tunn_types[] = {
29 ETH_TUNNEL_FILTER_OMAC,
31 ECORE_TUNN_CLSS_MAC_VLAN,
35 ETH_TUNNEL_FILTER_TENID,
37 ECORE_TUNN_CLSS_MAC_VNI,
41 ETH_TUNNEL_FILTER_IMAC,
42 ECORE_FILTER_INNER_MAC,
43 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
47 ETH_TUNNEL_FILTER_IVLAN,
48 ECORE_FILTER_INNER_VLAN,
49 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
53 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
54 ECORE_FILTER_MAC_VNI_PAIR,
55 ECORE_TUNN_CLSS_MAC_VNI,
59 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
62 "outer-mac and inner-mac"
65 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
68 "outer-mac and inner-vlan"
71 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
72 ECORE_FILTER_INNER_MAC_VNI_PAIR,
73 ECORE_TUNN_CLSS_INNER_MAC_VNI,
77 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
83 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
84 ECORE_FILTER_INNER_PAIR,
85 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
86 "inner-mac and inner-vlan",
89 ETH_TUNNEL_FILTER_OIP,
95 ETH_TUNNEL_FILTER_IIP,
101 RTE_TUNNEL_FILTER_IMAC_IVLAN,
107 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
113 RTE_TUNNEL_FILTER_IMAC_TENID,
119 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
126 struct rte_qede_xstats_name_off {
127 char name[RTE_ETH_XSTATS_NAME_SIZE];
131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
133 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
134 {"rx_multicast_bytes",
135 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
136 {"rx_broadcast_bytes",
137 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
138 {"rx_unicast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
140 {"rx_multicast_packets",
141 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
142 {"rx_broadcast_packets",
143 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
146 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
147 {"tx_multicast_bytes",
148 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
149 {"tx_broadcast_bytes",
150 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
151 {"tx_unicast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
153 {"tx_multicast_packets",
154 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
155 {"tx_broadcast_packets",
156 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
158 {"rx_64_byte_packets",
159 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
160 {"rx_65_to_127_byte_packets",
161 offsetof(struct ecore_eth_stats_common,
162 rx_65_to_127_byte_packets)},
163 {"rx_128_to_255_byte_packets",
164 offsetof(struct ecore_eth_stats_common,
165 rx_128_to_255_byte_packets)},
166 {"rx_256_to_511_byte_packets",
167 offsetof(struct ecore_eth_stats_common,
168 rx_256_to_511_byte_packets)},
169 {"rx_512_to_1023_byte_packets",
170 offsetof(struct ecore_eth_stats_common,
171 rx_512_to_1023_byte_packets)},
172 {"rx_1024_to_1518_byte_packets",
173 offsetof(struct ecore_eth_stats_common,
174 rx_1024_to_1518_byte_packets)},
175 {"tx_64_byte_packets",
176 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
177 {"tx_65_to_127_byte_packets",
178 offsetof(struct ecore_eth_stats_common,
179 tx_65_to_127_byte_packets)},
180 {"tx_128_to_255_byte_packets",
181 offsetof(struct ecore_eth_stats_common,
182 tx_128_to_255_byte_packets)},
183 {"tx_256_to_511_byte_packets",
184 offsetof(struct ecore_eth_stats_common,
185 tx_256_to_511_byte_packets)},
186 {"tx_512_to_1023_byte_packets",
187 offsetof(struct ecore_eth_stats_common,
188 tx_512_to_1023_byte_packets)},
189 {"tx_1024_to_1518_byte_packets",
190 offsetof(struct ecore_eth_stats_common,
191 tx_1024_to_1518_byte_packets)},
193 {"rx_mac_crtl_frames",
194 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
195 {"tx_mac_control_frames",
196 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
198 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
200 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
201 {"rx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
203 {"tx_priority_flow_control_frames",
204 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
207 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
209 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
210 {"rx_carrier_errors",
211 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
212 {"rx_oversize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
215 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
216 {"rx_undersize_packet_errors",
217 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
218 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
219 {"rx_host_buffer_not_available",
220 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
221 /* Number of packets discarded because they are bigger than MTU */
222 {"rx_packet_too_big_discards",
223 offsetof(struct ecore_eth_stats_common,
224 packet_too_big_discard)},
225 {"rx_ttl_zero_discards",
226 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
227 {"rx_multi_function_tag_filter_discards",
228 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
229 {"rx_mac_filter_discards",
230 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
231 {"rx_hw_buffer_truncates",
232 offsetof(struct ecore_eth_stats_common, brb_truncates)},
233 {"rx_hw_buffer_discards",
234 offsetof(struct ecore_eth_stats_common, brb_discards)},
235 {"tx_error_drop_packets",
236 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
239 {"rx_mac_unicast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
241 {"rx_mac_multicast_packets",
242 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
243 {"rx_mac_broadcast_packets",
244 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
246 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
248 {"tx_mac_unicast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
250 {"tx_mac_multicast_packets",
251 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
252 {"tx_mac_broadcast_packets",
253 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
255 {"lro_coalesced_packets",
256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
257 {"lro_coalesced_events",
258 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
260 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
261 {"lro_not_coalesced_packets",
262 offsetof(struct ecore_eth_stats_common,
263 tpa_not_coalesced_pkts)},
264 {"lro_coalesced_bytes",
265 offsetof(struct ecore_eth_stats_common,
266 tpa_coalesced_bytes)},
269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
270 {"rx_1519_to_1522_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_1522_byte_packets)},
274 {"rx_1519_to_2047_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_1519_to_2047_byte_packets)},
278 {"rx_2048_to_4095_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_2048_to_4095_byte_packets)},
282 {"rx_4096_to_9216_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_4096_to_9216_byte_packets)},
286 {"rx_9217_to_16383_byte_packets",
287 offsetof(struct ecore_eth_stats, bb) +
288 offsetof(struct ecore_eth_stats_bb,
289 rx_9217_to_16383_byte_packets)},
291 {"tx_1519_to_2047_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_1519_to_2047_byte_packets)},
295 {"tx_2048_to_4095_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_2048_to_4095_byte_packets)},
299 {"tx_4096_to_9216_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_4096_to_9216_byte_packets)},
303 {"tx_9217_to_16383_byte_packets",
304 offsetof(struct ecore_eth_stats, bb) +
305 offsetof(struct ecore_eth_stats_bb,
306 tx_9217_to_16383_byte_packets)},
308 {"tx_lpi_entry_count",
309 offsetof(struct ecore_eth_stats, bb) +
310 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
311 {"tx_total_collisions",
312 offsetof(struct ecore_eth_stats, bb) +
313 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
317 {"rx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 rx_1519_to_max_byte_packets)},
321 {"tx_1519_to_max_byte_packets",
322 offsetof(struct ecore_eth_stats, ah) +
323 offsetof(struct ecore_eth_stats_ah,
324 tx_1519_to_max_byte_packets)},
327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
329 offsetof(struct qede_rx_queue, rx_segs)},
331 offsetof(struct qede_rx_queue, rx_hw_errors)},
332 {"rx_q_allocation_errors",
333 offsetof(struct qede_rx_queue, rx_alloc_errors)}
336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
338 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
342 qede_interrupt_handler(void *param)
344 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
345 struct qede_dev *qdev = eth_dev->data->dev_private;
346 struct ecore_dev *edev = &qdev->edev;
348 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
349 if (rte_intr_enable(eth_dev->intr_handle))
350 DP_ERR(edev, "rte_intr_enable failed\n");
354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
356 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
360 static void qede_print_adapter_info(struct qede_dev *qdev)
362 struct ecore_dev *edev = &qdev->edev;
363 struct qed_dev_info *info = &qdev->dev_info.common;
364 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
365 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
367 DP_INFO(edev, "*********************************\n");
368 DP_INFO(edev, " DPDK version:%s\n", rte_version());
369 DP_INFO(edev, " Chip details : %s %c%d\n",
370 ECORE_IS_BB(edev) ? "BB" : "AH",
371 'A' + edev->chip_rev,
372 (int)edev->chip_metal);
373 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
374 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
375 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
376 ver_str, QEDE_PMD_VERSION);
377 DP_INFO(edev, " Driver version : %s\n", drv_ver);
378 DP_INFO(edev, " Firmware version : %s\n", ver_str);
380 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
382 (info->mfw_rev >> 24) & 0xff,
383 (info->mfw_rev >> 16) & 0xff,
384 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
385 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
386 DP_INFO(edev, " Firmware file : %s\n", fw_file);
387 DP_INFO(edev, "*********************************\n");
391 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
393 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
394 struct ecore_sp_vport_start_params params;
395 struct ecore_hwfn *p_hwfn;
399 memset(¶ms, 0, sizeof(params));
402 /* @DPDK - Disable FW placement */
403 params.zero_placement_offset = 1;
404 for_each_hwfn(edev, i) {
405 p_hwfn = &edev->hwfns[i];
406 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
407 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
408 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
409 if (rc != ECORE_SUCCESS) {
410 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
414 ecore_reset_vport_stats(edev);
415 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
421 qede_stop_vport(struct ecore_dev *edev)
423 struct ecore_hwfn *p_hwfn;
429 for_each_hwfn(edev, i) {
430 p_hwfn = &edev->hwfns[i];
431 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
433 if (rc != ECORE_SUCCESS) {
434 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
442 /* Activate or deactivate vport via vport-update */
443 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
445 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
446 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
447 struct ecore_sp_vport_update_params params;
448 struct ecore_hwfn *p_hwfn;
452 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
454 params.update_vport_active_rx_flg = 1;
455 params.update_vport_active_tx_flg = 1;
456 params.vport_active_rx_flg = flg;
457 params.vport_active_tx_flg = flg;
458 if (!qdev->enable_tx_switching) {
460 params.update_tx_switching_flg = 1;
461 params.tx_switching_flg = !flg;
462 DP_INFO(edev, "VF tx-switching is disabled\n");
465 for_each_hwfn(edev, i) {
466 p_hwfn = &edev->hwfns[i];
467 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
468 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
469 ECORE_SPQ_MODE_EBLOCK, NULL);
470 if (rc != ECORE_SUCCESS) {
471 DP_ERR(edev, "Failed to update vport\n");
475 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
481 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
482 uint16_t mtu, bool enable)
484 /* Enable LRO in split mode */
485 sge_tpa_params->tpa_ipv4_en_flg = enable;
486 sge_tpa_params->tpa_ipv6_en_flg = enable;
487 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
488 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
489 /* set if tpa enable changes */
490 sge_tpa_params->update_tpa_en_flg = 1;
491 /* set if tpa parameters should be handled */
492 sge_tpa_params->update_tpa_param_flg = enable;
494 sge_tpa_params->max_buffers_per_cqe = 20;
495 /* Enable TPA in split mode. In this mode each TPA segment
496 * starts on the new BD, so there is one BD per segment.
498 sge_tpa_params->tpa_pkt_split_flg = 1;
499 sge_tpa_params->tpa_hdr_data_split_flg = 0;
500 sge_tpa_params->tpa_gro_consistent_flg = 0;
501 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
502 sge_tpa_params->tpa_max_size = 0x7FFF;
503 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
504 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
507 /* Enable/disable LRO via vport-update */
508 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
510 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
511 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
512 struct ecore_sp_vport_update_params params;
513 struct ecore_sge_tpa_params tpa_params;
514 struct ecore_hwfn *p_hwfn;
518 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
519 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
520 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
522 params.sge_tpa_params = &tpa_params;
523 for_each_hwfn(edev, i) {
524 p_hwfn = &edev->hwfns[i];
525 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
526 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
527 ECORE_SPQ_MODE_EBLOCK, NULL);
528 if (rc != ECORE_SUCCESS) {
529 DP_ERR(edev, "Failed to update LRO\n");
533 qdev->enable_lro = flg;
534 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
539 /* Update MTU via vport-update without doing port restart.
540 * The vport must be deactivated before calling this API.
542 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
544 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
545 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
546 struct ecore_sp_vport_update_params params;
547 struct ecore_hwfn *p_hwfn;
551 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
555 for_each_hwfn(edev, i) {
556 p_hwfn = &edev->hwfns[i];
557 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
558 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
559 ECORE_SPQ_MODE_EBLOCK, NULL);
560 if (rc != ECORE_SUCCESS) {
561 DP_ERR(edev, "Failed to update MTU\n");
565 DP_INFO(edev, "MTU updated to %u\n", mtu);
570 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
572 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
573 ucast->is_rx_filter = true;
574 ucast->is_tx_filter = true;
575 /* ucast->assert_on_error = true; - For debug */
579 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
580 enum qed_filter_rx_mode_type type)
582 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
583 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
584 struct ecore_filter_accept_flags flags;
586 memset(&flags, 0, sizeof(flags));
588 flags.update_rx_mode_config = 1;
589 flags.update_tx_mode_config = 1;
590 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
591 ECORE_ACCEPT_MCAST_MATCHED |
594 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
595 ECORE_ACCEPT_MCAST_MATCHED |
598 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
599 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
601 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
602 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
604 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
605 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
606 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
607 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
608 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
609 ECORE_ACCEPT_MCAST_UNMATCHED;
612 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
613 ECORE_SPQ_MODE_CB, NULL);
617 qede_tunnel_update(struct qede_dev *qdev,
618 struct ecore_tunnel_info *tunn_info)
620 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
621 enum _ecore_status_t rc = ECORE_INVAL;
622 struct ecore_hwfn *p_hwfn;
623 struct ecore_ptt *p_ptt;
626 for_each_hwfn(edev, i) {
627 p_hwfn = &edev->hwfns[i];
628 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
629 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
630 tunn_info, ECORE_SPQ_MODE_CB, NULL);
632 ecore_ptt_release(p_hwfn, p_ptt);
634 if (rc != ECORE_SUCCESS)
642 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
645 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
646 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
647 enum _ecore_status_t rc = ECORE_INVAL;
648 struct ecore_tunnel_info tunn;
650 if (qdev->vxlan.enable == enable)
651 return ECORE_SUCCESS;
653 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
654 tunn.vxlan.b_update_mode = true;
655 tunn.vxlan.b_mode_enabled = enable;
656 tunn.b_update_rx_cls = true;
657 tunn.b_update_tx_cls = true;
658 tunn.vxlan.tun_cls = clss;
660 tunn.vxlan_port.b_update_port = true;
661 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
663 rc = qede_tunnel_update(qdev, &tunn);
664 if (rc == ECORE_SUCCESS) {
665 qdev->vxlan.enable = enable;
666 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
667 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
668 enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
670 DP_ERR(edev, "Failed to update tunn_clss %u\n",
678 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
681 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
682 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
683 enum _ecore_status_t rc = ECORE_INVAL;
684 struct ecore_tunnel_info tunn;
686 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
687 tunn.l2_geneve.b_update_mode = true;
688 tunn.l2_geneve.b_mode_enabled = enable;
689 tunn.ip_geneve.b_update_mode = true;
690 tunn.ip_geneve.b_mode_enabled = enable;
691 tunn.l2_geneve.tun_cls = clss;
692 tunn.ip_geneve.tun_cls = clss;
693 tunn.b_update_rx_cls = true;
694 tunn.b_update_tx_cls = true;
696 tunn.geneve_port.b_update_port = true;
697 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
699 rc = qede_tunnel_update(qdev, &tunn);
700 if (rc == ECORE_SUCCESS) {
701 qdev->geneve.enable = enable;
702 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
703 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
704 enable ? "enabled" : "disabled", qdev->geneve.udp_port);
706 DP_ERR(edev, "Failed to update tunn_clss %u\n",
714 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
715 enum rte_eth_tunnel_type tunn_type, bool enable)
720 case RTE_TUNNEL_TYPE_VXLAN:
721 rc = qede_vxlan_enable(eth_dev, clss, enable);
723 case RTE_TUNNEL_TYPE_GENEVE:
724 rc = qede_geneve_enable(eth_dev, clss, enable);
735 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
738 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
739 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
740 struct qede_ucast_entry *tmp = NULL;
741 struct qede_ucast_entry *u;
742 struct ether_addr *mac_addr;
744 mac_addr = (struct ether_addr *)ucast->mac;
746 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
747 if ((memcmp(mac_addr, &tmp->mac,
748 ETHER_ADDR_LEN) == 0) &&
749 ucast->vni == tmp->vni &&
750 ucast->vlan == tmp->vlan) {
751 DP_ERR(edev, "Unicast MAC is already added"
752 " with vlan = %u, vni = %u\n",
753 ucast->vlan, ucast->vni);
757 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
758 RTE_CACHE_LINE_SIZE);
760 DP_ERR(edev, "Did not allocate memory for ucast\n");
763 ether_addr_copy(mac_addr, &u->mac);
764 u->vlan = ucast->vlan;
766 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
769 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
770 if ((memcmp(mac_addr, &tmp->mac,
771 ETHER_ADDR_LEN) == 0) &&
772 ucast->vlan == tmp->vlan &&
773 ucast->vni == tmp->vni)
777 DP_INFO(edev, "Unicast MAC is not found\n");
780 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
788 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
791 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
792 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
793 struct ether_addr *mac_addr;
794 struct qede_mcast_entry *tmp = NULL;
795 struct qede_mcast_entry *m;
797 mac_addr = (struct ether_addr *)mcast->mac;
799 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
800 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
802 "Multicast MAC is already added\n");
806 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
807 RTE_CACHE_LINE_SIZE);
810 "Did not allocate memory for mcast\n");
813 ether_addr_copy(mac_addr, &m->mac);
814 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
817 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
818 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
822 DP_INFO(edev, "Multicast mac is not found\n");
825 SLIST_REMOVE(&qdev->mc_list_head, tmp,
826 qede_mcast_entry, list);
833 static enum _ecore_status_t
834 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
837 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
838 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
839 enum _ecore_status_t rc;
840 struct ecore_filter_mcast mcast;
841 struct qede_mcast_entry *tmp;
845 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
847 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
849 "Mcast filter table limit exceeded, "
850 "Please enable mcast promisc mode\n");
854 rc = qede_mcast_filter(eth_dev, ucast, add);
856 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
857 memset(&mcast, 0, sizeof(mcast));
858 mcast.num_mc_addrs = qdev->num_mc_addr;
859 mcast.opcode = ECORE_FILTER_ADD;
860 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
861 ether_addr_copy(&tmp->mac,
862 (struct ether_addr *)&mcast.mac[j]);
865 rc = ecore_filter_mcast_cmd(edev, &mcast,
866 ECORE_SPQ_MODE_CB, NULL);
868 if (rc != ECORE_SUCCESS) {
869 DP_ERR(edev, "Failed to add multicast filter"
870 " rc = %d, op = %d\n", rc, add);
872 } else { /* Unicast */
874 if (qdev->num_uc_addr >=
875 qdev->dev_info.num_mac_filters) {
877 "Ucast filter table limit exceeded,"
878 " Please enable promisc mode\n");
882 rc = qede_ucast_filter(eth_dev, ucast, add);
884 rc = ecore_filter_ucast_cmd(edev, ucast,
885 ECORE_SPQ_MODE_CB, NULL);
886 if (rc != ECORE_SUCCESS) {
887 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
896 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
897 __rte_unused uint32_t index, __rte_unused uint32_t pool)
899 struct ecore_filter_ucast ucast;
902 qede_set_ucast_cmn_params(&ucast);
903 ucast.type = ECORE_FILTER_MAC;
904 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
905 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
910 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
912 struct qede_dev *qdev = eth_dev->data->dev_private;
913 struct ecore_dev *edev = &qdev->edev;
914 struct ecore_filter_ucast ucast;
916 PMD_INIT_FUNC_TRACE(edev);
918 if (index >= qdev->dev_info.num_mac_filters) {
919 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
920 index, qdev->dev_info.num_mac_filters);
924 qede_set_ucast_cmn_params(&ucast);
925 ucast.opcode = ECORE_FILTER_REMOVE;
926 ucast.type = ECORE_FILTER_MAC;
928 /* Use the index maintained by rte */
929 ether_addr_copy(ð_dev->data->mac_addrs[index],
930 (struct ether_addr *)&ucast.mac);
932 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
936 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
938 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
939 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
941 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
942 mac_addr->addr_bytes)) {
943 DP_ERR(edev, "Setting MAC address is not allowed\n");
944 ether_addr_copy(&qdev->primary_mac,
945 ð_dev->data->mac_addrs[0]);
949 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
952 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
954 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
955 struct ecore_sp_vport_update_params params;
956 struct ecore_hwfn *p_hwfn;
960 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
962 params.update_accept_any_vlan_flg = 1;
963 params.accept_any_vlan = flg;
964 for_each_hwfn(edev, i) {
965 p_hwfn = &edev->hwfns[i];
966 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
967 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
968 ECORE_SPQ_MODE_EBLOCK, NULL);
969 if (rc != ECORE_SUCCESS) {
970 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
975 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
978 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
980 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
981 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
982 struct ecore_sp_vport_update_params params;
983 struct ecore_hwfn *p_hwfn;
987 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
989 params.update_inner_vlan_removal_flg = 1;
990 params.inner_vlan_removal_flg = flg;
991 for_each_hwfn(edev, i) {
992 p_hwfn = &edev->hwfns[i];
993 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
994 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
995 ECORE_SPQ_MODE_EBLOCK, NULL);
996 if (rc != ECORE_SUCCESS) {
997 DP_ERR(edev, "Failed to update vport\n");
1002 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1006 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1007 uint16_t vlan_id, int on)
1009 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1010 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1011 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1012 struct qede_vlan_entry *tmp = NULL;
1013 struct qede_vlan_entry *vlan;
1014 struct ecore_filter_ucast ucast;
1018 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1019 DP_ERR(edev, "Reached max VLAN filter limit"
1020 " enabling accept_any_vlan\n");
1021 qede_config_accept_any_vlan(qdev, true);
1025 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1026 if (tmp->vid == vlan_id) {
1027 DP_ERR(edev, "VLAN %u already configured\n",
1033 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1034 RTE_CACHE_LINE_SIZE);
1037 DP_ERR(edev, "Did not allocate memory for VLAN\n");
1041 qede_set_ucast_cmn_params(&ucast);
1042 ucast.opcode = ECORE_FILTER_ADD;
1043 ucast.type = ECORE_FILTER_VLAN;
1044 ucast.vlan = vlan_id;
1045 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1048 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1052 vlan->vid = vlan_id;
1053 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1054 qdev->configured_vlans++;
1055 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1056 vlan_id, qdev->configured_vlans);
1059 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1060 if (tmp->vid == vlan_id)
1065 if (qdev->configured_vlans == 0) {
1067 "No VLAN filters configured yet\n");
1071 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1075 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1077 qede_set_ucast_cmn_params(&ucast);
1078 ucast.opcode = ECORE_FILTER_REMOVE;
1079 ucast.type = ECORE_FILTER_VLAN;
1080 ucast.vlan = vlan_id;
1081 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1084 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1087 qdev->configured_vlans--;
1088 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1089 vlan_id, qdev->configured_vlans);
1096 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1098 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1099 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1100 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1102 if (mask & ETH_VLAN_STRIP_MASK) {
1103 if (rxmode->hw_vlan_strip)
1104 (void)qede_vlan_stripping(eth_dev, 1);
1106 (void)qede_vlan_stripping(eth_dev, 0);
1109 if (mask & ETH_VLAN_FILTER_MASK) {
1110 /* VLAN filtering kicks in when a VLAN is added */
1111 if (rxmode->hw_vlan_filter) {
1112 qede_vlan_filter_set(eth_dev, 0, 1);
1114 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1116 " Please remove existing VLAN filters"
1117 " before disabling VLAN filtering\n");
1118 /* Signal app that VLAN filtering is still
1121 rxmode->hw_vlan_filter = true;
1123 qede_vlan_filter_set(eth_dev, 0, 0);
1128 if (mask & ETH_VLAN_EXTEND_MASK)
1129 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1130 " and classification is based on outer tag only\n");
1132 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1133 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1138 static void qede_prandom_bytes(uint32_t *buff)
1142 srand((unsigned int)time(NULL));
1143 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1147 int qede_config_rss(struct rte_eth_dev *eth_dev)
1149 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1150 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1151 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1152 struct rte_eth_rss_reta_entry64 reta_conf[2];
1153 struct rte_eth_rss_conf rss_conf;
1154 uint32_t i, id, pos, q;
1156 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1157 if (!rss_conf.rss_key) {
1158 DP_INFO(edev, "Applying driver default key\n");
1159 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1160 qede_prandom_bytes(&def_rss_key[0]);
1161 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1164 /* Configure RSS hash */
1165 if (qede_rss_hash_update(eth_dev, &rss_conf))
1168 /* Configure default RETA */
1169 memset(reta_conf, 0, sizeof(reta_conf));
1170 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1171 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1173 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1174 id = i / RTE_RETA_GROUP_SIZE;
1175 pos = i % RTE_RETA_GROUP_SIZE;
1176 q = i % QEDE_RSS_COUNT(qdev);
1177 reta_conf[id].reta[pos] = q;
1179 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1180 ECORE_RSS_IND_TABLE_SIZE))
1186 static void qede_fastpath_start(struct ecore_dev *edev)
1188 struct ecore_hwfn *p_hwfn;
1191 for_each_hwfn(edev, i) {
1192 p_hwfn = &edev->hwfns[i];
1193 ecore_hw_start_fastpath(p_hwfn);
1197 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1199 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1200 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1201 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1203 PMD_INIT_FUNC_TRACE(edev);
1205 /* Update MTU only if it has changed */
1206 if (qdev->mtu != qdev->new_mtu) {
1207 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1209 qdev->mtu = qdev->new_mtu;
1212 /* Configure TPA parameters */
1213 if (rxmode->enable_lro) {
1214 if (qede_enable_tpa(eth_dev, true))
1216 /* Enable scatter mode for LRO */
1217 if (!rxmode->enable_scatter)
1218 eth_dev->data->scattered_rx = 1;
1222 if (qede_start_queues(eth_dev))
1225 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1226 * enabling RSS. Hence RSS configuration is deferred upto this point.
1227 * Also, we would like to retain similar behavior in PF case, so we
1228 * don't do PF/VF specific check here.
1230 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1231 if (qede_config_rss(eth_dev))
1235 if (qede_activate_vport(eth_dev, true))
1238 /* Bring-up the link */
1239 qede_dev_set_link_state(eth_dev, true);
1241 /* Update link status */
1242 qede_link_update(eth_dev, 0);
1244 /* Start/resume traffic */
1245 qede_fastpath_start(edev);
1247 DP_INFO(edev, "Device started\n");
1251 DP_ERR(edev, "Device start fails\n");
1252 return -1; /* common error code is < 0 */
1255 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1257 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1258 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1260 PMD_INIT_FUNC_TRACE(edev);
1263 if (qede_activate_vport(eth_dev, false))
1266 if (qdev->enable_lro)
1267 qede_enable_tpa(eth_dev, false);
1270 qede_stop_queues(eth_dev);
1272 /* Disable traffic */
1273 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1275 /* Bring the link down */
1276 qede_dev_set_link_state(eth_dev, false);
1278 DP_INFO(edev, "Device is stopped\n");
1281 #define QEDE_TX_SWITCHING "vf_txswitch"
1283 const char *valid_args[] = {
1288 static int qede_args_check(const char *key, const char *val, void *opaque)
1292 struct rte_eth_dev *eth_dev = opaque;
1293 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1294 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1297 tmp = strtoul(val, NULL, 0);
1299 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1303 if (strcmp(QEDE_TX_SWITCHING, key) == 0)
1304 qdev->enable_tx_switching = !!tmp;
1309 static int qede_args(struct rte_eth_dev *eth_dev)
1311 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1312 struct rte_kvargs *kvlist;
1313 struct rte_devargs *devargs;
1317 devargs = pci_dev->device.devargs;
1319 return 0; /* return success */
1321 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1325 /* Process parameters. */
1326 for (i = 0; (valid_args[i] != NULL); ++i) {
1327 if (rte_kvargs_count(kvlist, valid_args[i])) {
1328 ret = rte_kvargs_process(kvlist, valid_args[i],
1329 qede_args_check, eth_dev);
1330 if (ret != ECORE_SUCCESS) {
1331 rte_kvargs_free(kvlist);
1336 rte_kvargs_free(kvlist);
1341 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1343 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1344 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1345 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1348 PMD_INIT_FUNC_TRACE(edev);
1350 /* Check requirements for 100G mode */
1351 if (ECORE_IS_CMT(edev)) {
1352 if (eth_dev->data->nb_rx_queues < 2 ||
1353 eth_dev->data->nb_tx_queues < 2) {
1354 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1358 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1359 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1361 "100G mode needs even no. of RX/TX queues\n");
1366 /* We need to have min 1 RX queue.There is no min check in
1367 * rte_eth_dev_configure(), so we are checking it here.
1369 if (eth_dev->data->nb_rx_queues == 0) {
1370 DP_ERR(edev, "Minimum one RX queue is required\n");
1374 /* Enable Tx switching by default */
1375 qdev->enable_tx_switching = 1;
1377 /* Parse devargs and fix up rxmode */
1378 if (qede_args(eth_dev))
1381 /* Sanity checks and throw warnings */
1382 if (rxmode->enable_scatter)
1383 eth_dev->data->scattered_rx = 1;
1385 if (!rxmode->hw_strip_crc)
1386 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1388 if (!rxmode->hw_ip_checksum)
1389 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1391 if (rxmode->header_split)
1392 DP_INFO(edev, "Header split enable is not supported\n");
1393 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1395 DP_ERR(edev, "Unsupported multi-queue mode\n");
1398 /* Flow director mode check */
1399 if (qede_check_fdir_support(eth_dev))
1402 /* Deallocate resources if held previously. It is needed only if the
1403 * queue count has been changed from previous configuration. If its
1404 * going to change then it means RX/TX queue setup will be called
1405 * again and the fastpath pointers will be reinitialized there.
1407 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1408 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1409 qede_dealloc_fp_resc(eth_dev);
1410 /* Proceed with updated queue count */
1411 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1412 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1413 if (qede_alloc_fp_resc(qdev))
1417 /* VF's MTU has to be set using vport-start where as
1418 * PF's MTU can be updated via vport-update.
1421 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1424 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1428 qdev->mtu = rxmode->max_rx_pkt_len;
1429 qdev->new_mtu = qdev->mtu;
1431 /* Enable VLAN offloads by default */
1432 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1433 ETH_VLAN_FILTER_MASK |
1434 ETH_VLAN_EXTEND_MASK);
1438 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1439 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1444 /* Info about HW descriptor ring limitations */
1445 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1446 .nb_max = 0x8000, /* 32K */
1448 .nb_align = 128 /* lowest common multiple */
1451 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1452 .nb_max = 0x8000, /* 32K */
1455 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1456 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1460 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1461 struct rte_eth_dev_info *dev_info)
1463 struct qede_dev *qdev = eth_dev->data->dev_private;
1464 struct ecore_dev *edev = &qdev->edev;
1465 struct qed_link_output link;
1466 uint32_t speed_cap = 0;
1468 PMD_INIT_FUNC_TRACE(edev);
1470 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1471 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1472 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1473 dev_info->rx_desc_lim = qede_rx_desc_lim;
1474 dev_info->tx_desc_lim = qede_tx_desc_lim;
1477 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1478 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1480 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1481 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1482 dev_info->max_tx_queues = dev_info->max_rx_queues;
1484 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1485 dev_info->max_vfs = 0;
1486 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1487 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1488 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1490 dev_info->default_txconf = (struct rte_eth_txconf) {
1491 .txq_flags = QEDE_TXQ_FLAGS,
1494 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
1495 DEV_RX_OFFLOAD_IPV4_CKSUM |
1496 DEV_RX_OFFLOAD_UDP_CKSUM |
1497 DEV_RX_OFFLOAD_TCP_CKSUM |
1498 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1499 DEV_RX_OFFLOAD_TCP_LRO);
1501 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1502 DEV_TX_OFFLOAD_IPV4_CKSUM |
1503 DEV_TX_OFFLOAD_UDP_CKSUM |
1504 DEV_TX_OFFLOAD_TCP_CKSUM |
1505 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1506 DEV_TX_OFFLOAD_TCP_TSO |
1507 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1508 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1510 memset(&link, 0, sizeof(struct qed_link_output));
1511 qdev->ops->common->get_link(edev, &link);
1512 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1513 speed_cap |= ETH_LINK_SPEED_1G;
1514 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1515 speed_cap |= ETH_LINK_SPEED_10G;
1516 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1517 speed_cap |= ETH_LINK_SPEED_25G;
1518 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1519 speed_cap |= ETH_LINK_SPEED_40G;
1520 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1521 speed_cap |= ETH_LINK_SPEED_50G;
1522 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1523 speed_cap |= ETH_LINK_SPEED_100G;
1524 dev_info->speed_capa = speed_cap;
1527 /* return 0 means link status changed, -1 means not changed */
1529 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1531 struct qede_dev *qdev = eth_dev->data->dev_private;
1532 struct ecore_dev *edev = &qdev->edev;
1533 uint16_t link_duplex;
1534 struct qed_link_output link;
1535 struct rte_eth_link *curr = ð_dev->data->dev_link;
1537 memset(&link, 0, sizeof(struct qed_link_output));
1538 qdev->ops->common->get_link(edev, &link);
1541 curr->link_speed = link.speed;
1544 switch (link.duplex) {
1545 case QEDE_DUPLEX_HALF:
1546 link_duplex = ETH_LINK_HALF_DUPLEX;
1548 case QEDE_DUPLEX_FULL:
1549 link_duplex = ETH_LINK_FULL_DUPLEX;
1551 case QEDE_DUPLEX_UNKNOWN:
1555 curr->link_duplex = link_duplex;
1558 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1561 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1562 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1564 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1565 curr->link_speed, curr->link_duplex,
1566 curr->link_autoneg, curr->link_status);
1568 /* return 0 means link status changed, -1 means not changed */
1569 return ((curr->link_status == link.link_up) ? -1 : 0);
1572 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1574 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1575 struct qede_dev *qdev = eth_dev->data->dev_private;
1576 struct ecore_dev *edev = &qdev->edev;
1578 PMD_INIT_FUNC_TRACE(edev);
1581 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1583 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1584 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1586 qed_configure_filter_rx_mode(eth_dev, type);
1589 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1591 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1592 struct qede_dev *qdev = eth_dev->data->dev_private;
1593 struct ecore_dev *edev = &qdev->edev;
1595 PMD_INIT_FUNC_TRACE(edev);
1598 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1599 qed_configure_filter_rx_mode(eth_dev,
1600 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1602 qed_configure_filter_rx_mode(eth_dev,
1603 QED_FILTER_RX_MODE_TYPE_REGULAR);
1606 static void qede_poll_sp_sb_cb(void *param)
1608 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1609 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1610 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1613 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1614 qede_interrupt_action(&edev->hwfns[1]);
1616 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1620 DP_ERR(edev, "Unable to start periodic"
1621 " timer rc %d\n", rc);
1622 assert(false && "Unable to start periodic timer");
1626 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1628 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1629 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1630 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1632 PMD_INIT_FUNC_TRACE(edev);
1634 /* dev_stop() shall cleanup fp resources in hw but without releasing
1635 * dma memories and sw structures so that dev_start() can be called
1636 * by the app without reconfiguration. However, in dev_close() we
1637 * can release all the resources and device can be brought up newly
1639 if (eth_dev->data->dev_started)
1640 qede_dev_stop(eth_dev);
1642 qede_stop_vport(edev);
1643 qede_fdir_dealloc_resc(eth_dev);
1644 qede_dealloc_fp_resc(eth_dev);
1646 eth_dev->data->nb_rx_queues = 0;
1647 eth_dev->data->nb_tx_queues = 0;
1649 qdev->ops->common->slowpath_stop(edev);
1650 qdev->ops->common->remove(edev);
1651 rte_intr_disable(&pci_dev->intr_handle);
1652 rte_intr_callback_unregister(&pci_dev->intr_handle,
1653 qede_interrupt_handler, (void *)eth_dev);
1654 if (ECORE_IS_CMT(edev))
1655 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1659 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1661 struct qede_dev *qdev = eth_dev->data->dev_private;
1662 struct ecore_dev *edev = &qdev->edev;
1663 struct ecore_eth_stats stats;
1664 unsigned int i = 0, j = 0, qid;
1665 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1666 struct qede_tx_queue *txq;
1668 ecore_get_vport_stats(edev, &stats);
1671 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1672 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1674 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1675 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1677 eth_stats->ierrors = stats.common.rx_crc_errors +
1678 stats.common.rx_align_errors +
1679 stats.common.rx_carrier_errors +
1680 stats.common.rx_oversize_packets +
1681 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1683 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1685 eth_stats->imissed = stats.common.mftag_filter_discards +
1686 stats.common.mac_filter_discards +
1687 stats.common.no_buff_discards +
1688 stats.common.brb_truncates + stats.common.brb_discards;
1691 eth_stats->opackets = stats.common.tx_ucast_pkts +
1692 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1694 eth_stats->obytes = stats.common.tx_ucast_bytes +
1695 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1697 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1700 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1701 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1702 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1703 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1704 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1705 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1706 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1707 "Not all the queue stats will be displayed. Set"
1708 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1709 " appropriately and retry.\n");
1712 eth_stats->q_ipackets[i] =
1714 ((char *)(qdev->fp_array[qid].rxq)) +
1715 offsetof(struct qede_rx_queue,
1717 eth_stats->q_errors[i] =
1719 ((char *)(qdev->fp_array[qid].rxq)) +
1720 offsetof(struct qede_rx_queue,
1723 ((char *)(qdev->fp_array[qid].rxq)) +
1724 offsetof(struct qede_rx_queue,
1727 if (i == rxq_stat_cntrs)
1732 txq = qdev->fp_array[qid].txq;
1733 eth_stats->q_opackets[j] =
1734 *((uint64_t *)(uintptr_t)
1735 (((uint64_t)(uintptr_t)(txq)) +
1736 offsetof(struct qede_tx_queue,
1739 if (j == txq_stat_cntrs)
1747 qede_get_xstats_count(struct qede_dev *qdev) {
1748 if (ECORE_IS_BB(&qdev->edev))
1749 return RTE_DIM(qede_xstats_strings) +
1750 RTE_DIM(qede_bb_xstats_strings) +
1751 (RTE_DIM(qede_rxq_xstats_strings) *
1752 RTE_MIN(QEDE_RSS_COUNT(qdev),
1753 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1755 return RTE_DIM(qede_xstats_strings) +
1756 RTE_DIM(qede_ah_xstats_strings) +
1757 (RTE_DIM(qede_rxq_xstats_strings) *
1758 RTE_MIN(QEDE_RSS_COUNT(qdev),
1759 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1763 qede_get_xstats_names(struct rte_eth_dev *dev,
1764 struct rte_eth_xstat_name *xstats_names,
1765 __rte_unused unsigned int limit)
1767 struct qede_dev *qdev = dev->data->dev_private;
1768 struct ecore_dev *edev = &qdev->edev;
1769 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1770 unsigned int i, qid, stat_idx = 0;
1771 unsigned int rxq_stat_cntrs;
1773 if (xstats_names != NULL) {
1774 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1775 snprintf(xstats_names[stat_idx].name,
1776 sizeof(xstats_names[stat_idx].name),
1778 qede_xstats_strings[i].name);
1782 if (ECORE_IS_BB(edev)) {
1783 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1784 snprintf(xstats_names[stat_idx].name,
1785 sizeof(xstats_names[stat_idx].name),
1787 qede_bb_xstats_strings[i].name);
1791 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1792 snprintf(xstats_names[stat_idx].name,
1793 sizeof(xstats_names[stat_idx].name),
1795 qede_ah_xstats_strings[i].name);
1800 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1801 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1802 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1803 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1804 snprintf(xstats_names[stat_idx].name,
1805 sizeof(xstats_names[stat_idx].name),
1807 qede_rxq_xstats_strings[i].name, qid,
1808 qede_rxq_xstats_strings[i].name + 4);
1818 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1821 struct qede_dev *qdev = dev->data->dev_private;
1822 struct ecore_dev *edev = &qdev->edev;
1823 struct ecore_eth_stats stats;
1824 const unsigned int num = qede_get_xstats_count(qdev);
1825 unsigned int i, qid, stat_idx = 0;
1826 unsigned int rxq_stat_cntrs;
1831 ecore_get_vport_stats(edev, &stats);
1833 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1834 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1835 qede_xstats_strings[i].offset);
1836 xstats[stat_idx].id = stat_idx;
1840 if (ECORE_IS_BB(edev)) {
1841 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1842 xstats[stat_idx].value =
1843 *(uint64_t *)(((char *)&stats) +
1844 qede_bb_xstats_strings[i].offset);
1845 xstats[stat_idx].id = stat_idx;
1849 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1850 xstats[stat_idx].value =
1851 *(uint64_t *)(((char *)&stats) +
1852 qede_ah_xstats_strings[i].offset);
1853 xstats[stat_idx].id = stat_idx;
1858 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1859 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1860 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1862 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1863 xstats[stat_idx].value = *(uint64_t *)(
1864 ((char *)(qdev->fp_array[qid].rxq)) +
1865 qede_rxq_xstats_strings[i].offset);
1866 xstats[stat_idx].id = stat_idx;
1876 qede_reset_xstats(struct rte_eth_dev *dev)
1878 struct qede_dev *qdev = dev->data->dev_private;
1879 struct ecore_dev *edev = &qdev->edev;
1881 ecore_reset_vport_stats(edev);
1884 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1886 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1887 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1888 struct qed_link_params link_params;
1891 DP_INFO(edev, "setting link state %d\n", link_up);
1892 memset(&link_params, 0, sizeof(link_params));
1893 link_params.link_up = link_up;
1894 rc = qdev->ops->common->set_link(edev, &link_params);
1895 if (rc != ECORE_SUCCESS)
1896 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1901 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1903 return qede_dev_set_link_state(eth_dev, true);
1906 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1908 return qede_dev_set_link_state(eth_dev, false);
1911 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1913 struct qede_dev *qdev = eth_dev->data->dev_private;
1914 struct ecore_dev *edev = &qdev->edev;
1916 ecore_reset_vport_stats(edev);
1919 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1921 enum qed_filter_rx_mode_type type =
1922 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1924 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1925 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1927 qed_configure_filter_rx_mode(eth_dev, type);
1930 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1932 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1933 qed_configure_filter_rx_mode(eth_dev,
1934 QED_FILTER_RX_MODE_TYPE_PROMISC);
1936 qed_configure_filter_rx_mode(eth_dev,
1937 QED_FILTER_RX_MODE_TYPE_REGULAR);
1940 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1941 struct rte_eth_fc_conf *fc_conf)
1943 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1944 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1945 struct qed_link_output current_link;
1946 struct qed_link_params params;
1948 memset(¤t_link, 0, sizeof(current_link));
1949 qdev->ops->common->get_link(edev, ¤t_link);
1951 memset(¶ms, 0, sizeof(params));
1952 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1953 if (fc_conf->autoneg) {
1954 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1955 DP_ERR(edev, "Autoneg not supported\n");
1958 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1961 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1962 if (fc_conf->mode == RTE_FC_FULL)
1963 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1964 QED_LINK_PAUSE_RX_ENABLE);
1965 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1966 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1967 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1968 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1970 params.link_up = true;
1971 (void)qdev->ops->common->set_link(edev, ¶ms);
1976 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1977 struct rte_eth_fc_conf *fc_conf)
1979 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1980 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1981 struct qed_link_output current_link;
1983 memset(¤t_link, 0, sizeof(current_link));
1984 qdev->ops->common->get_link(edev, ¤t_link);
1986 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1987 fc_conf->autoneg = true;
1989 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1990 QED_LINK_PAUSE_TX_ENABLE))
1991 fc_conf->mode = RTE_FC_FULL;
1992 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1993 fc_conf->mode = RTE_FC_RX_PAUSE;
1994 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1995 fc_conf->mode = RTE_FC_TX_PAUSE;
1997 fc_conf->mode = RTE_FC_NONE;
2002 static const uint32_t *
2003 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2005 static const uint32_t ptypes[] = {
2007 RTE_PTYPE_L2_ETHER_VLAN,
2012 RTE_PTYPE_TUNNEL_VXLAN,
2014 RTE_PTYPE_TUNNEL_GENEVE,
2016 RTE_PTYPE_INNER_L2_ETHER,
2017 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2018 RTE_PTYPE_INNER_L3_IPV4,
2019 RTE_PTYPE_INNER_L3_IPV6,
2020 RTE_PTYPE_INNER_L4_TCP,
2021 RTE_PTYPE_INNER_L4_UDP,
2022 RTE_PTYPE_INNER_L4_FRAG,
2026 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2032 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2035 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2036 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2037 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2038 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2039 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2040 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2041 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2042 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2045 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2046 struct rte_eth_rss_conf *rss_conf)
2048 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2049 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2050 struct ecore_sp_vport_update_params vport_update_params;
2051 struct ecore_rss_params rss_params;
2052 struct ecore_hwfn *p_hwfn;
2053 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2054 uint64_t hf = rss_conf->rss_hf;
2055 uint8_t len = rss_conf->rss_key_len;
2060 memset(&vport_update_params, 0, sizeof(vport_update_params));
2061 memset(&rss_params, 0, sizeof(rss_params));
2063 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2064 (unsigned long)hf, len, key);
2068 DP_INFO(edev, "Enabling rss\n");
2071 qede_init_rss_caps(&rss_params.rss_caps, hf);
2072 rss_params.update_rss_capabilities = 1;
2076 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2077 DP_ERR(edev, "RSS key length exceeds limit\n");
2080 DP_INFO(edev, "Applying user supplied hash key\n");
2081 rss_params.update_rss_key = 1;
2082 memcpy(&rss_params.rss_key, key, len);
2084 rss_params.rss_enable = 1;
2087 rss_params.update_rss_config = 1;
2088 /* tbl_size has to be set with capabilities */
2089 rss_params.rss_table_size_log = 7;
2090 vport_update_params.vport_id = 0;
2091 /* pass the L2 handles instead of qids */
2092 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2093 idx = qdev->rss_ind_table[i];
2094 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2096 vport_update_params.rss_params = &rss_params;
2098 for_each_hwfn(edev, i) {
2099 p_hwfn = &edev->hwfns[i];
2100 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2101 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2102 ECORE_SPQ_MODE_EBLOCK, NULL);
2104 DP_ERR(edev, "vport-update for RSS failed\n");
2108 qdev->rss_enable = rss_params.rss_enable;
2110 /* Update local structure for hash query */
2111 qdev->rss_conf.rss_hf = hf;
2112 qdev->rss_conf.rss_key_len = len;
2113 if (qdev->rss_enable) {
2114 if (qdev->rss_conf.rss_key == NULL) {
2115 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2116 if (qdev->rss_conf.rss_key == NULL) {
2117 DP_ERR(edev, "No memory to store RSS key\n");
2122 DP_INFO(edev, "Storing RSS key\n");
2123 memcpy(qdev->rss_conf.rss_key, key, len);
2125 } else if (!qdev->rss_enable && len == 0) {
2126 if (qdev->rss_conf.rss_key) {
2127 free(qdev->rss_conf.rss_key);
2128 qdev->rss_conf.rss_key = NULL;
2129 DP_INFO(edev, "Free RSS key\n");
2136 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2137 struct rte_eth_rss_conf *rss_conf)
2139 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2141 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2142 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2144 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2145 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2146 rss_conf->rss_key_len);
2150 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2151 struct ecore_rss_params *rss)
2154 bool rss_mode = 1; /* enable */
2155 struct ecore_queue_cid *cid;
2156 struct ecore_rss_params *t_rss;
2158 /* In regular scenario, we'd simply need to take input handlers.
2159 * But in CMT, we'd have to split the handlers according to the
2160 * engine they were configured on. We'd then have to understand
2161 * whether RSS is really required, since 2-queues on CMT doesn't
2165 /* CMT should be round-robin */
2166 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2167 cid = rss->rss_ind_table[i];
2169 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2174 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2178 t_rss->update_rss_ind_table = 1;
2179 t_rss->rss_table_size_log = 7;
2180 t_rss->update_rss_config = 1;
2182 /* Make sure RSS is actually required */
2183 for_each_hwfn(edev, fn) {
2184 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2186 if (rss[fn].rss_ind_table[i] !=
2187 rss[fn].rss_ind_table[0])
2191 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2193 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2200 t_rss->rss_enable = rss_mode;
2205 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2206 struct rte_eth_rss_reta_entry64 *reta_conf,
2209 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2210 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2211 struct ecore_sp_vport_update_params vport_update_params;
2212 struct ecore_rss_params *params;
2213 struct ecore_hwfn *p_hwfn;
2214 uint16_t i, idx, shift;
2218 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2219 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2224 memset(&vport_update_params, 0, sizeof(vport_update_params));
2225 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2226 RTE_CACHE_LINE_SIZE);
2227 if (params == NULL) {
2228 DP_ERR(edev, "failed to allocate memory\n");
2232 for (i = 0; i < reta_size; i++) {
2233 idx = i / RTE_RETA_GROUP_SIZE;
2234 shift = i % RTE_RETA_GROUP_SIZE;
2235 if (reta_conf[idx].mask & (1ULL << shift)) {
2236 entry = reta_conf[idx].reta[shift];
2237 /* Pass rxq handles to ecore */
2238 params->rss_ind_table[i] =
2239 qdev->fp_array[entry].rxq->handle;
2240 /* Update the local copy for RETA query command */
2241 qdev->rss_ind_table[i] = entry;
2245 params->update_rss_ind_table = 1;
2246 params->rss_table_size_log = 7;
2247 params->update_rss_config = 1;
2249 /* Fix up RETA for CMT mode device */
2250 if (ECORE_IS_CMT(edev))
2251 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2253 vport_update_params.vport_id = 0;
2254 /* Use the current value of rss_enable */
2255 params->rss_enable = qdev->rss_enable;
2256 vport_update_params.rss_params = params;
2258 for_each_hwfn(edev, i) {
2259 p_hwfn = &edev->hwfns[i];
2260 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2261 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2262 ECORE_SPQ_MODE_EBLOCK, NULL);
2264 DP_ERR(edev, "vport-update for RSS failed\n");
2274 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2275 struct rte_eth_rss_reta_entry64 *reta_conf,
2278 struct qede_dev *qdev = eth_dev->data->dev_private;
2279 struct ecore_dev *edev = &qdev->edev;
2280 uint16_t i, idx, shift;
2283 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2284 DP_ERR(edev, "reta_size %d is not supported\n",
2289 for (i = 0; i < reta_size; i++) {
2290 idx = i / RTE_RETA_GROUP_SIZE;
2291 shift = i % RTE_RETA_GROUP_SIZE;
2292 if (reta_conf[idx].mask & (1ULL << shift)) {
2293 entry = qdev->rss_ind_table[i];
2294 reta_conf[idx].reta[shift] = entry;
2303 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2305 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2306 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2307 struct rte_eth_dev_info dev_info = {0};
2308 struct qede_fastpath *fp;
2309 uint32_t frame_size;
2310 uint16_t rx_buf_size;
2314 PMD_INIT_FUNC_TRACE(edev);
2315 qede_dev_info_get(dev, &dev_info);
2316 frame_size = mtu + QEDE_ETH_OVERHEAD;
2317 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2318 DP_ERR(edev, "MTU %u out of range\n", mtu);
2321 if (!dev->data->scattered_rx &&
2322 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2323 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2324 dev->data->min_rx_buf_size);
2327 /* Temporarily replace I/O functions with dummy ones. It cannot
2328 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2330 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2331 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2335 /* Fix up RX buf size for all queues of the port */
2337 fp = &qdev->fp_array[i];
2338 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2339 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2340 if (dev->data->scattered_rx)
2341 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2343 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2344 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2345 fp->rxq->rx_buf_size = rx_buf_size;
2346 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2348 qede_dev_start(dev);
2349 if (frame_size > ETHER_MAX_LEN)
2350 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2352 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2353 /* update max frame size */
2354 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2356 dev->rx_pkt_burst = qede_recv_pkts;
2357 dev->tx_pkt_burst = qede_xmit_pkts;
2363 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2364 struct rte_eth_udp_tunnel *tunnel_udp)
2366 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2367 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2368 struct ecore_tunnel_info tunn; /* @DPDK */
2372 PMD_INIT_FUNC_TRACE(edev);
2374 memset(&tunn, 0, sizeof(tunn));
2376 switch (tunnel_udp->prot_type) {
2377 case RTE_TUNNEL_TYPE_VXLAN:
2378 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2379 DP_ERR(edev, "UDP port %u doesn't exist\n",
2380 tunnel_udp->udp_port);
2385 tunn.vxlan_port.b_update_port = true;
2386 tunn.vxlan_port.port = udp_port;
2388 rc = qede_tunnel_update(qdev, &tunn);
2389 if (rc != ECORE_SUCCESS) {
2390 DP_ERR(edev, "Unable to config UDP port %u\n",
2391 tunn.vxlan_port.port);
2395 qdev->vxlan.udp_port = udp_port;
2396 /* If the request is to delete UDP port and if the number of
2397 * VXLAN filters have reached 0 then VxLAN offload can be be
2400 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2401 return qede_vxlan_enable(eth_dev,
2402 ECORE_TUNN_CLSS_MAC_VLAN, false);
2406 case RTE_TUNNEL_TYPE_GENEVE:
2407 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2408 DP_ERR(edev, "UDP port %u doesn't exist\n",
2409 tunnel_udp->udp_port);
2415 tunn.geneve_port.b_update_port = true;
2416 tunn.geneve_port.port = udp_port;
2418 rc = qede_tunnel_update(qdev, &tunn);
2419 if (rc != ECORE_SUCCESS) {
2420 DP_ERR(edev, "Unable to config UDP port %u\n",
2421 tunn.vxlan_port.port);
2425 qdev->vxlan.udp_port = udp_port;
2426 /* If the request is to delete UDP port and if the number of
2427 * GENEVE filters have reached 0 then GENEVE offload can be be
2430 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2431 return qede_geneve_enable(eth_dev,
2432 ECORE_TUNN_CLSS_MAC_VLAN, false);
2444 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2445 struct rte_eth_udp_tunnel *tunnel_udp)
2447 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2448 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2449 struct ecore_tunnel_info tunn; /* @DPDK */
2453 PMD_INIT_FUNC_TRACE(edev);
2455 memset(&tunn, 0, sizeof(tunn));
2457 switch (tunnel_udp->prot_type) {
2458 case RTE_TUNNEL_TYPE_VXLAN:
2459 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2461 "UDP port %u for VXLAN was already configured\n",
2462 tunnel_udp->udp_port);
2463 return ECORE_SUCCESS;
2466 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2467 * it was not enabled while adding VXLAN filter before UDP port
2470 if (!qdev->vxlan.enable) {
2471 rc = qede_vxlan_enable(eth_dev,
2472 ECORE_TUNN_CLSS_MAC_VLAN, true);
2473 if (rc != ECORE_SUCCESS) {
2474 DP_ERR(edev, "Failed to enable VXLAN "
2475 "prior to updating UDP port\n");
2479 udp_port = tunnel_udp->udp_port;
2481 tunn.vxlan_port.b_update_port = true;
2482 tunn.vxlan_port.port = udp_port;
2484 rc = qede_tunnel_update(qdev, &tunn);
2485 if (rc != ECORE_SUCCESS) {
2486 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2491 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2493 qdev->vxlan.udp_port = udp_port;
2496 case RTE_TUNNEL_TYPE_GENEVE:
2497 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2499 "UDP port %u for GENEVE was already configured\n",
2500 tunnel_udp->udp_port);
2501 return ECORE_SUCCESS;
2504 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2505 * it was not enabled while adding GENEVE filter before UDP port
2508 if (!qdev->geneve.enable) {
2509 rc = qede_geneve_enable(eth_dev,
2510 ECORE_TUNN_CLSS_MAC_VLAN, true);
2511 if (rc != ECORE_SUCCESS) {
2512 DP_ERR(edev, "Failed to enable GENEVE "
2513 "prior to updating UDP port\n");
2517 udp_port = tunnel_udp->udp_port;
2519 tunn.geneve_port.b_update_port = true;
2520 tunn.geneve_port.port = udp_port;
2522 rc = qede_tunnel_update(qdev, &tunn);
2523 if (rc != ECORE_SUCCESS) {
2524 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2529 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2531 qdev->geneve.udp_port = udp_port;
2541 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2542 uint32_t *clss, char *str)
2545 *clss = MAX_ECORE_TUNN_CLSS;
2547 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2548 if (filter == qede_tunn_types[j].rte_filter_type) {
2549 *type = qede_tunn_types[j].qede_type;
2550 *clss = qede_tunn_types[j].qede_tunn_clss;
2551 strcpy(str, qede_tunn_types[j].string);
2558 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2559 const struct rte_eth_tunnel_filter_conf *conf,
2562 /* Init commmon ucast params first */
2563 qede_set_ucast_cmn_params(ucast);
2565 /* Copy out the required fields based on classification type */
2569 case ECORE_FILTER_VNI:
2570 ucast->vni = conf->tenant_id;
2572 case ECORE_FILTER_INNER_VLAN:
2573 ucast->vlan = conf->inner_vlan;
2575 case ECORE_FILTER_MAC:
2576 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2579 case ECORE_FILTER_INNER_MAC:
2580 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2583 case ECORE_FILTER_MAC_VNI_PAIR:
2584 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2586 ucast->vni = conf->tenant_id;
2588 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2589 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2591 ucast->vni = conf->tenant_id;
2593 case ECORE_FILTER_INNER_PAIR:
2594 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2596 ucast->vlan = conf->inner_vlan;
2602 return ECORE_SUCCESS;
2606 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2607 const struct rte_eth_tunnel_filter_conf *conf,
2608 __attribute__((unused)) enum rte_filter_op filter_op,
2609 enum ecore_tunn_clss *clss,
2612 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2613 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2614 struct ecore_filter_ucast ucast = {0};
2615 enum ecore_filter_ucast_type type;
2616 uint16_t filter_type = 0;
2620 filter_type = conf->filter_type;
2621 /* Determine if the given filter classification is supported */
2622 qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2623 if (*clss == MAX_ECORE_TUNN_CLSS) {
2624 DP_ERR(edev, "Unsupported filter type\n");
2627 /* Init tunnel ucast params */
2628 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2629 if (rc != ECORE_SUCCESS) {
2630 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2634 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2635 str, filter_op, ucast.type);
2637 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2639 /* Skip MAC/VLAN if filter is based on VNI */
2640 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2641 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2642 if ((rc == 0) && add) {
2643 /* Enable accept anyvlan */
2644 qede_config_accept_any_vlan(qdev, true);
2647 rc = qede_ucast_filter(eth_dev, &ucast, add);
2649 rc = ecore_filter_ucast_cmd(edev, &ucast,
2650 ECORE_SPQ_MODE_CB, NULL);
2657 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2658 enum rte_filter_op filter_op,
2659 const struct rte_eth_tunnel_filter_conf *conf)
2661 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2662 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2663 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2667 PMD_INIT_FUNC_TRACE(edev);
2669 switch (filter_op) {
2670 case RTE_ETH_FILTER_ADD:
2673 case RTE_ETH_FILTER_DELETE:
2677 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2682 return qede_tunn_enable(eth_dev,
2683 ECORE_TUNN_CLSS_MAC_VLAN,
2684 conf->tunnel_type, add);
2686 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2687 if (rc != ECORE_SUCCESS)
2691 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2692 qdev->vxlan.num_filters++;
2693 qdev->vxlan.filter_type = conf->filter_type;
2694 } else { /* GENEVE */
2695 qdev->geneve.num_filters++;
2696 qdev->geneve.filter_type = conf->filter_type;
2699 if (!qdev->vxlan.enable || !qdev->geneve.enable)
2700 return qede_tunn_enable(eth_dev, clss,
2704 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2705 qdev->vxlan.num_filters--;
2707 qdev->geneve.num_filters--;
2709 /* Disable VXLAN if VXLAN filters become 0 */
2710 if ((qdev->vxlan.num_filters == 0) ||
2711 (qdev->geneve.num_filters == 0))
2712 return qede_tunn_enable(eth_dev, clss,
2720 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2721 enum rte_filter_type filter_type,
2722 enum rte_filter_op filter_op,
2725 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2726 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2727 struct rte_eth_tunnel_filter_conf *filter_conf =
2728 (struct rte_eth_tunnel_filter_conf *)arg;
2730 switch (filter_type) {
2731 case RTE_ETH_FILTER_TUNNEL:
2732 switch (filter_conf->tunnel_type) {
2733 case RTE_TUNNEL_TYPE_VXLAN:
2734 case RTE_TUNNEL_TYPE_GENEVE:
2736 "Packet steering to the specified Rx queue"
2737 " is not supported with UDP tunneling");
2738 return(qede_tunn_filter_config(eth_dev, filter_op,
2740 /* Place holders for future tunneling support */
2741 case RTE_TUNNEL_TYPE_TEREDO:
2742 case RTE_TUNNEL_TYPE_NVGRE:
2743 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2744 case RTE_L2_TUNNEL_TYPE_E_TAG:
2745 DP_ERR(edev, "Unsupported tunnel type %d\n",
2746 filter_conf->tunnel_type);
2748 case RTE_TUNNEL_TYPE_NONE:
2753 case RTE_ETH_FILTER_FDIR:
2754 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2755 case RTE_ETH_FILTER_NTUPLE:
2756 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2757 case RTE_ETH_FILTER_MACVLAN:
2758 case RTE_ETH_FILTER_ETHERTYPE:
2759 case RTE_ETH_FILTER_FLEXIBLE:
2760 case RTE_ETH_FILTER_SYN:
2761 case RTE_ETH_FILTER_HASH:
2762 case RTE_ETH_FILTER_L2_TUNNEL:
2763 case RTE_ETH_FILTER_MAX:
2765 DP_ERR(edev, "Unsupported filter type %d\n",
2773 static const struct eth_dev_ops qede_eth_dev_ops = {
2774 .dev_configure = qede_dev_configure,
2775 .dev_infos_get = qede_dev_info_get,
2776 .rx_queue_setup = qede_rx_queue_setup,
2777 .rx_queue_release = qede_rx_queue_release,
2778 .tx_queue_setup = qede_tx_queue_setup,
2779 .tx_queue_release = qede_tx_queue_release,
2780 .dev_start = qede_dev_start,
2781 .dev_set_link_up = qede_dev_set_link_up,
2782 .dev_set_link_down = qede_dev_set_link_down,
2783 .link_update = qede_link_update,
2784 .promiscuous_enable = qede_promiscuous_enable,
2785 .promiscuous_disable = qede_promiscuous_disable,
2786 .allmulticast_enable = qede_allmulticast_enable,
2787 .allmulticast_disable = qede_allmulticast_disable,
2788 .dev_stop = qede_dev_stop,
2789 .dev_close = qede_dev_close,
2790 .stats_get = qede_get_stats,
2791 .stats_reset = qede_reset_stats,
2792 .xstats_get = qede_get_xstats,
2793 .xstats_reset = qede_reset_xstats,
2794 .xstats_get_names = qede_get_xstats_names,
2795 .mac_addr_add = qede_mac_addr_add,
2796 .mac_addr_remove = qede_mac_addr_remove,
2797 .mac_addr_set = qede_mac_addr_set,
2798 .vlan_offload_set = qede_vlan_offload_set,
2799 .vlan_filter_set = qede_vlan_filter_set,
2800 .flow_ctrl_set = qede_flow_ctrl_set,
2801 .flow_ctrl_get = qede_flow_ctrl_get,
2802 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2803 .rss_hash_update = qede_rss_hash_update,
2804 .rss_hash_conf_get = qede_rss_hash_conf_get,
2805 .reta_update = qede_rss_reta_update,
2806 .reta_query = qede_rss_reta_query,
2807 .mtu_set = qede_set_mtu,
2808 .filter_ctrl = qede_dev_filter_ctrl,
2809 .udp_tunnel_port_add = qede_udp_dst_port_add,
2810 .udp_tunnel_port_del = qede_udp_dst_port_del,
2813 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2814 .dev_configure = qede_dev_configure,
2815 .dev_infos_get = qede_dev_info_get,
2816 .rx_queue_setup = qede_rx_queue_setup,
2817 .rx_queue_release = qede_rx_queue_release,
2818 .tx_queue_setup = qede_tx_queue_setup,
2819 .tx_queue_release = qede_tx_queue_release,
2820 .dev_start = qede_dev_start,
2821 .dev_set_link_up = qede_dev_set_link_up,
2822 .dev_set_link_down = qede_dev_set_link_down,
2823 .link_update = qede_link_update,
2824 .promiscuous_enable = qede_promiscuous_enable,
2825 .promiscuous_disable = qede_promiscuous_disable,
2826 .allmulticast_enable = qede_allmulticast_enable,
2827 .allmulticast_disable = qede_allmulticast_disable,
2828 .dev_stop = qede_dev_stop,
2829 .dev_close = qede_dev_close,
2830 .stats_get = qede_get_stats,
2831 .stats_reset = qede_reset_stats,
2832 .xstats_get = qede_get_xstats,
2833 .xstats_reset = qede_reset_xstats,
2834 .xstats_get_names = qede_get_xstats_names,
2835 .vlan_offload_set = qede_vlan_offload_set,
2836 .vlan_filter_set = qede_vlan_filter_set,
2837 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2838 .rss_hash_update = qede_rss_hash_update,
2839 .rss_hash_conf_get = qede_rss_hash_conf_get,
2840 .reta_update = qede_rss_reta_update,
2841 .reta_query = qede_rss_reta_query,
2842 .mtu_set = qede_set_mtu,
2843 .udp_tunnel_port_add = qede_udp_dst_port_add,
2844 .udp_tunnel_port_del = qede_udp_dst_port_del,
2847 static void qede_update_pf_params(struct ecore_dev *edev)
2849 struct ecore_pf_params pf_params;
2851 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2852 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2853 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2854 qed_ops->common->update_pf_params(edev, &pf_params);
2857 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2859 struct rte_pci_device *pci_dev;
2860 struct rte_pci_addr pci_addr;
2861 struct qede_dev *adapter;
2862 struct ecore_dev *edev;
2863 struct qed_dev_eth_info dev_info;
2864 struct qed_slowpath_params params;
2865 static bool do_once = true;
2866 uint8_t bulletin_change;
2867 uint8_t vf_mac[ETHER_ADDR_LEN];
2868 uint8_t is_mac_forced;
2870 /* Fix up ecore debug level */
2871 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2872 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2875 /* Extract key data structures */
2876 adapter = eth_dev->data->dev_private;
2877 adapter->ethdev = eth_dev;
2878 edev = &adapter->edev;
2879 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2880 pci_addr = pci_dev->addr;
2882 PMD_INIT_FUNC_TRACE(edev);
2884 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2885 pci_addr.bus, pci_addr.devid, pci_addr.function,
2886 eth_dev->data->port_id);
2888 eth_dev->rx_pkt_burst = qede_recv_pkts;
2889 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2890 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2892 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2893 DP_ERR(edev, "Skipping device init from secondary process\n");
2897 rte_eth_copy_pci_info(eth_dev, pci_dev);
2900 edev->vendor_id = pci_dev->id.vendor_id;
2901 edev->device_id = pci_dev->id.device_id;
2903 qed_ops = qed_get_eth_ops();
2905 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2909 DP_INFO(edev, "Starting qede probe\n");
2910 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2913 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2916 qede_update_pf_params(edev);
2917 rte_intr_callback_register(&pci_dev->intr_handle,
2918 qede_interrupt_handler, (void *)eth_dev);
2919 if (rte_intr_enable(&pci_dev->intr_handle)) {
2920 DP_ERR(edev, "rte_intr_enable() failed\n");
2924 /* Start the Slowpath-process */
2925 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2926 params.int_mode = ECORE_INT_MODE_MSIX;
2927 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2928 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2929 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2930 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2931 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2932 QEDE_PMD_DRV_VER_STR_SIZE);
2934 /* For CMT mode device do periodic polling for slowpath events.
2935 * This is required since uio device uses only one MSI-x
2936 * interrupt vector but we need one for each engine.
2938 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2939 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2943 DP_ERR(edev, "Unable to start periodic"
2944 " timer rc %d\n", rc);
2949 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2951 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2952 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2957 rc = qed_ops->fill_dev_info(edev, &dev_info);
2959 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2960 qed_ops->common->slowpath_stop(edev);
2961 qed_ops->common->remove(edev);
2962 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2967 qede_alloc_etherdev(adapter, &dev_info);
2969 adapter->ops->common->set_name(edev, edev->name);
2972 adapter->dev_info.num_mac_filters =
2973 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2976 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2977 (uint32_t *)&adapter->dev_info.num_mac_filters);
2979 /* Allocate memory for storing MAC addr */
2980 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2982 adapter->dev_info.num_mac_filters),
2983 RTE_CACHE_LINE_SIZE);
2985 if (eth_dev->data->mac_addrs == NULL) {
2986 DP_ERR(edev, "Failed to allocate MAC address\n");
2987 qed_ops->common->slowpath_stop(edev);
2988 qed_ops->common->remove(edev);
2989 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2995 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2996 hw_info.hw_mac_addr,
2997 ð_dev->data->mac_addrs[0]);
2998 ether_addr_copy(ð_dev->data->mac_addrs[0],
2999 &adapter->primary_mac);
3001 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3003 if (bulletin_change) {
3005 ecore_vf_bulletin_get_forced_mac(
3006 ECORE_LEADING_HWFN(edev),
3009 if (is_mac_exist && is_mac_forced) {
3010 DP_INFO(edev, "VF macaddr received from PF\n");
3011 ether_addr_copy((struct ether_addr *)&vf_mac,
3012 ð_dev->data->mac_addrs[0]);
3013 ether_addr_copy(ð_dev->data->mac_addrs[0],
3014 &adapter->primary_mac);
3016 DP_ERR(edev, "No VF macaddr assigned\n");
3021 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3024 qede_print_adapter_info(adapter);
3028 adapter->num_tx_queues = 0;
3029 adapter->num_rx_queues = 0;
3030 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3031 SLIST_INIT(&adapter->vlan_list_head);
3032 SLIST_INIT(&adapter->uc_list_head);
3033 adapter->mtu = ETHER_MTU;
3034 adapter->new_mtu = ETHER_MTU;
3036 if (qede_start_vport(adapter, adapter->mtu))
3039 /* VF tunnel offloads is enabled by default in PF driver */
3040 adapter->vxlan.enable = true;
3041 adapter->vxlan.num_filters = 0;
3042 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3043 ETH_TUNNEL_FILTER_IVLAN;
3044 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3045 adapter->geneve.enable = true;
3046 adapter->vxlan.num_filters = 0;
3047 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3048 ETH_TUNNEL_FILTER_IVLAN;
3049 adapter->vxlan.udp_port = QEDE_GENEVE_DEF_PORT;
3052 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3053 adapter->primary_mac.addr_bytes[0],
3054 adapter->primary_mac.addr_bytes[1],
3055 adapter->primary_mac.addr_bytes[2],
3056 adapter->primary_mac.addr_bytes[3],
3057 adapter->primary_mac.addr_bytes[4],
3058 adapter->primary_mac.addr_bytes[5]);
3060 DP_INFO(edev, "Device initialized\n");
3065 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3067 return qede_common_dev_init(eth_dev, 1);
3070 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3072 return qede_common_dev_init(eth_dev, 0);
3075 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3077 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3078 struct qede_dev *qdev = eth_dev->data->dev_private;
3079 struct ecore_dev *edev = &qdev->edev;
3081 PMD_INIT_FUNC_TRACE(edev);
3084 /* only uninitialize in the primary process */
3085 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3088 /* safe to close dev here */
3089 qede_dev_close(eth_dev);
3091 eth_dev->dev_ops = NULL;
3092 eth_dev->rx_pkt_burst = NULL;
3093 eth_dev->tx_pkt_burst = NULL;
3095 if (eth_dev->data->mac_addrs)
3096 rte_free(eth_dev->data->mac_addrs);
3098 eth_dev->data->mac_addrs = NULL;
3103 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3105 return qede_dev_common_uninit(eth_dev);
3108 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3110 return qede_dev_common_uninit(eth_dev);
3113 static const struct rte_pci_id pci_id_qedevf_map[] = {
3114 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3116 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3119 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3122 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3127 static const struct rte_pci_id pci_id_qede_map[] = {
3128 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3130 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3133 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3136 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3139 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3142 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3145 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3148 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3151 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3154 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3157 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3162 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3163 struct rte_pci_device *pci_dev)
3165 return rte_eth_dev_pci_generic_probe(pci_dev,
3166 sizeof(struct qede_dev), qedevf_eth_dev_init);
3169 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3171 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3174 static struct rte_pci_driver rte_qedevf_pmd = {
3175 .id_table = pci_id_qedevf_map,
3176 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3177 .probe = qedevf_eth_dev_pci_probe,
3178 .remove = qedevf_eth_dev_pci_remove,
3181 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3182 struct rte_pci_device *pci_dev)
3184 return rte_eth_dev_pci_generic_probe(pci_dev,
3185 sizeof(struct qede_dev), qede_eth_dev_init);
3188 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3190 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3193 static struct rte_pci_driver rte_qede_pmd = {
3194 .id_table = pci_id_qede_map,
3195 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3196 .probe = qede_eth_dev_pci_probe,
3197 .remove = qede_eth_dev_pci_remove,
3200 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3201 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3202 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3203 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3204 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3205 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3207 RTE_INIT(qede_init_log);
3211 qede_logtype_init = rte_log_register("pmd.qede.init");
3212 if (qede_logtype_init >= 0)
3213 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3214 qede_logtype_driver = rte_log_register("pmd.qede.driver");
3215 if (qede_logtype_driver >= 0)
3216 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);