drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes",
 129                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 130         {"rx_multicast_bytes",
 131                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 132         {"rx_broadcast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 134         {"rx_unicast_packets",
 135                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 136         {"rx_multicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 138         {"rx_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 140
 141         {"tx_unicast_bytes",
 142                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 143         {"tx_multicast_bytes",
 144                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 145         {"tx_broadcast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 147         {"tx_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 149         {"tx_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 151         {"tx_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 153
 154         {"rx_64_byte_packets",
 155                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 156         {"rx_65_to_127_byte_packets",
 157                 offsetof(struct ecore_eth_stats_common,
 158                          rx_65_to_127_byte_packets)},
 159         {"rx_128_to_255_byte_packets",
 160                 offsetof(struct ecore_eth_stats_common,
 161                          rx_128_to_255_byte_packets)},
 162         {"rx_256_to_511_byte_packets",
 163                 offsetof(struct ecore_eth_stats_common,
 164                          rx_256_to_511_byte_packets)},
 165         {"rx_512_to_1023_byte_packets",
 166                 offsetof(struct ecore_eth_stats_common,
 167                          rx_512_to_1023_byte_packets)},
 168         {"rx_1024_to_1518_byte_packets",
 169                 offsetof(struct ecore_eth_stats_common,
 170                          rx_1024_to_1518_byte_packets)},
 171         {"tx_64_byte_packets",
 172                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 173         {"tx_65_to_127_byte_packets",
 174                 offsetof(struct ecore_eth_stats_common,
 175                          tx_65_to_127_byte_packets)},
 176         {"tx_128_to_255_byte_packets",
 177                 offsetof(struct ecore_eth_stats_common,
 178                          tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats_common,
 181                          tx_256_to_511_byte_packets)},
 182         {"tx_512_to_1023_byte_packets",
 183                 offsetof(struct ecore_eth_stats_common,
 184                          tx_512_to_1023_byte_packets)},
 185         {"tx_1024_to_1518_byte_packets",
 186                 offsetof(struct ecore_eth_stats_common,
 187                          tx_1024_to_1518_byte_packets)},
 188
 189         {"rx_mac_crtl_frames",
 190                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 191         {"tx_mac_control_frames",
 192                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 193         {"rx_pause_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 195         {"tx_pause_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 197         {"rx_priority_flow_control_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 199         {"tx_priority_flow_control_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 201
 202         {"rx_crc_errors",
 203                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 204         {"rx_align_errors",
 205                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 206         {"rx_carrier_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 208         {"rx_oversize_packet_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 210         {"rx_jabber_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 212         {"rx_undersize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 214         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 215         {"rx_host_buffer_not_available",
 216                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 217         /* Number of packets discarded because they are bigger than MTU */
 218         {"rx_packet_too_big_discards",
 219                 offsetof(struct ecore_eth_stats_common,
 220                          packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 231         {"tx_error_drop_packets",
 232                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 233
 234         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 235         {"rx_mac_unicast_packets",
 236                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 237         {"rx_mac_multicast_packets",
 238                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 239         {"rx_mac_broadcast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 241         {"rx_mac_frames_ok",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 243         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 244         {"tx_mac_unicast_packets",
 245                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 246         {"tx_mac_multicast_packets",
 247                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 248         {"tx_mac_broadcast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 250
 251         {"lro_coalesced_packets",
 252                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 253         {"lro_coalesced_events",
 254                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 255         {"lro_aborts_num",
 256                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 257         {"lro_not_coalesced_packets",
 258                 offsetof(struct ecore_eth_stats_common,
 259                          tpa_not_coalesced_pkts)},
 260         {"lro_coalesced_bytes",
 261                 offsetof(struct ecore_eth_stats_common,
 262                          tpa_coalesced_bytes)},
 263 };
 264
 265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 266         {"rx_1519_to_1522_byte_packets",
 267                 offsetof(struct ecore_eth_stats, bb) +
 268                 offsetof(struct ecore_eth_stats_bb,
 269                          rx_1519_to_1522_byte_packets)},
 270         {"rx_1519_to_2047_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_2047_byte_packets)},
 274         {"rx_2048_to_4095_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_2048_to_4095_byte_packets)},
 278         {"rx_4096_to_9216_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_4096_to_9216_byte_packets)},
 282         {"rx_9217_to_16383_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_9217_to_16383_byte_packets)},
 286
 287         {"tx_1519_to_2047_byte_packets",
 288                 offsetof(struct ecore_eth_stats, bb) +
 289                 offsetof(struct ecore_eth_stats_bb,
 290                          tx_1519_to_2047_byte_packets)},
 291         {"tx_2048_to_4095_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_2048_to_4095_byte_packets)},
 295         {"tx_4096_to_9216_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_4096_to_9216_byte_packets)},
 299         {"tx_9217_to_16383_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_9217_to_16383_byte_packets)},
 303
 304         {"tx_lpi_entry_count",
 305                 offsetof(struct ecore_eth_stats, bb) +
 306                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 307         {"tx_total_collisions",
 308                 offsetof(struct ecore_eth_stats, bb) +
 309                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 310 };
 311
 312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 313         {"rx_1519_to_max_byte_packets",
 314                 offsetof(struct ecore_eth_stats, ah) +
 315                 offsetof(struct ecore_eth_stats_ah,
 316                          rx_1519_to_max_byte_packets)},
 317         {"tx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          tx_1519_to_max_byte_packets)},
 321 };
 322
 323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 324         {"rx_q_segments",
 325                 offsetof(struct qede_rx_queue, rx_segs)},
 326         {"rx_q_hw_errors",
 327                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 328         {"rx_q_allocation_errors",
 329                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 330 };
 331
 332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 333 {
 334         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 335 }
 336
 337 static void
 338 qede_interrupt_handler(void *param)
 339 {
 340         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 341         struct qede_dev *qdev = eth_dev->data->dev_private;
 342         struct ecore_dev *edev = &qdev->edev;
 343
 344         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 345         if (rte_intr_enable(eth_dev->intr_handle))
 346                 DP_ERR(edev, "rte_intr_enable failed\n");
 347 }
 348
 349 static void
 350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 351 {
 352         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 353         qdev->ops = qed_ops;
 354 }
 355
 356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 357 static void qede_print_adapter_info(struct qede_dev *qdev)
 358 {
 359         struct ecore_dev *edev = &qdev->edev;
 360         struct qed_dev_info *info = &qdev->dev_info.common;
 361         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 362         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 363
 364         DP_INFO(edev, "*********************************\n");
 365         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 366         DP_INFO(edev, " Chip details : %s %c%d\n",
 367                   ECORE_IS_BB(edev) ? "BB" : "AH",
 368                   'A' + edev->chip_rev,
 369                   (int)edev->chip_metal);
 370         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 371                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 372         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 373                  ver_str, QEDE_PMD_VERSION);
 374         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 375         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 376
 377         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 378                  "%d.%d.%d.%d",
 379                 (info->mfw_rev >> 24) & 0xff,
 380                 (info->mfw_rev >> 16) & 0xff,
 381                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 382         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 383         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 384         DP_INFO(edev, "*********************************\n");
 385 }
 386 #endif
 387
 388 static int
 389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 390 {
 391         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 392         struct ecore_sp_vport_start_params params;
 393         struct ecore_hwfn *p_hwfn;
 394         int rc;
 395         int i;
 396
 397         memset(&params, 0, sizeof(params));
 398         params.vport_id = 0;
 399         params.mtu = mtu;
 400         /* @DPDK - Disable FW placement */
 401         params.zero_placement_offset = 1;
 402         for_each_hwfn(edev, i) {
 403                 p_hwfn = &edev->hwfns[i];
 404                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 405                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 406                 rc = ecore_sp_vport_start(p_hwfn, &params);
 407                 if (rc != ECORE_SUCCESS) {
 408                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 409                         return rc;
 410                 }
 411         }
 412         ecore_reset_vport_stats(edev);
 413         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 414
 415         return 0;
 416 }
 417
 418 static int
 419 qede_stop_vport(struct ecore_dev *edev)
 420 {
 421         struct ecore_hwfn *p_hwfn;
 422         uint8_t vport_id;
 423         int rc;
 424         int i;
 425
 426         vport_id = 0;
 427         for_each_hwfn(edev, i) {
 428                 p_hwfn = &edev->hwfns[i];
 429                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 430                                          vport_id);
 431                 if (rc != ECORE_SUCCESS) {
 432                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 433                         return rc;
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* Activate or deactivate vport via vport-update */
 441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 442 {
 443         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 444         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 445         struct ecore_sp_vport_update_params params;
 446         struct ecore_hwfn *p_hwfn;
 447         uint8_t i;
 448         int rc = -1;
 449
 450         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 451         params.vport_id = 0;
 452         params.update_vport_active_rx_flg = 1;
 453         params.update_vport_active_tx_flg = 1;
 454         params.vport_active_rx_flg = flg;
 455         params.vport_active_tx_flg = flg;
 456         for_each_hwfn(edev, i) {
 457                 p_hwfn = &edev->hwfns[i];
 458                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 459                 rc = ecore_sp_vport_update(p_hwfn, &params,
 460                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 461                 if (rc != ECORE_SUCCESS) {
 462                         DP_ERR(edev, "Failed to update vport\n");
 463                         break;
 464                 }
 465         }
 466         DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
 467         return rc;
 468 }
 469
 470 static void
 471 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 472                            uint16_t mtu, bool enable)
 473 {
 474         /* Enable LRO in split mode */
 475         sge_tpa_params->tpa_ipv4_en_flg = enable;
 476         sge_tpa_params->tpa_ipv6_en_flg = enable;
 477         sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
 478         sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
 479         /* set if tpa enable changes */
 480         sge_tpa_params->update_tpa_en_flg = 1;
 481         /* set if tpa parameters should be handled */
 482         sge_tpa_params->update_tpa_param_flg = enable;
 483
 484         sge_tpa_params->max_buffers_per_cqe = 20;
 485         /* Enable TPA in split mode. In this mode each TPA segment
 486          * starts on the new BD, so there is one BD per segment.
 487          */
 488         sge_tpa_params->tpa_pkt_split_flg = 1;
 489         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 490         sge_tpa_params->tpa_gro_consistent_flg = 0;
 491         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 492         sge_tpa_params->tpa_max_size = 0x7FFF;
 493         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 494         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 495 }
 496
 497 /* Enable/disable LRO via vport-update */
 498 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 499 {
 500         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 501         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 502         struct ecore_sp_vport_update_params params;
 503         struct ecore_sge_tpa_params tpa_params;
 504         struct ecore_hwfn *p_hwfn;
 505         int rc;
 506         int i;
 507
 508         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 509         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 510         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 511         params.vport_id = 0;
 512         params.sge_tpa_params = &tpa_params;
 513         for_each_hwfn(edev, i) {
 514                 p_hwfn = &edev->hwfns[i];
 515                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 516                 rc = ecore_sp_vport_update(p_hwfn, &params,
 517                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 518                 if (rc != ECORE_SUCCESS) {
 519                         DP_ERR(edev, "Failed to update LRO\n");
 520                         return -1;
 521                 }
 522         }
 523
 524         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 525
 526         return 0;
 527 }
 528
 529 /* Update MTU via vport-update without doing port restart.
 530  * The vport must be deactivated before calling this API.
 531  */
 532 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 533 {
 534         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 535         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 536         struct ecore_sp_vport_update_params params;
 537         struct ecore_hwfn *p_hwfn;
 538         int rc;
 539         int i;
 540
 541         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 542         params.vport_id = 0;
 543         params.mtu = mtu;
 544         params.vport_id = 0;
 545         for_each_hwfn(edev, i) {
 546                 p_hwfn = &edev->hwfns[i];
 547                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 548                 rc = ecore_sp_vport_update(p_hwfn, &params,
 549                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 550                 if (rc != ECORE_SUCCESS) {
 551                         DP_ERR(edev, "Failed to update MTU\n");
 552                         return -1;
 553                 }
 554         }
 555         DP_INFO(edev, "MTU updated to %u\n", mtu);
 556
 557         return 0;
 558 }
 559
 560 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 561 {
 562         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 563         ucast->is_rx_filter = true;
 564         ucast->is_tx_filter = true;
 565         /* ucast->assert_on_error = true; - For debug */
 566 }
 567
 568 static int
 569 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 570                              enum qed_filter_rx_mode_type type)
 571 {
 572         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 573         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 574         struct ecore_filter_accept_flags flags;
 575
 576         memset(&flags, 0, sizeof(flags));
 577
 578         flags.update_rx_mode_config = 1;
 579         flags.update_tx_mode_config = 1;
 580         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 581                 ECORE_ACCEPT_MCAST_MATCHED |
 582                 ECORE_ACCEPT_BCAST;
 583
 584         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 585                 ECORE_ACCEPT_MCAST_MATCHED |
 586                 ECORE_ACCEPT_BCAST;
 587
 588         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 589                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 590                 if (IS_VF(edev)) {
 591                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 592                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 593                 }
 594         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 595                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 596         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 597                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 598                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 599                         ECORE_ACCEPT_MCAST_UNMATCHED;
 600         }
 601
 602         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 603                         ECORE_SPQ_MODE_CB, NULL);
 604 }
 605 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
 606                                     uint8_t clss, bool mode, bool mask)
 607 {
 608         memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
 609         p_tunn->vxlan.b_update_mode = mode;
 610         p_tunn->vxlan.b_mode_enabled = mask;
 611         p_tunn->b_update_rx_cls = true;
 612         p_tunn->b_update_tx_cls = true;
 613         p_tunn->vxlan.tun_cls = clss;
 614 }
 615
 616 static int
 617 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 618                   bool add)
 619 {
 620         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 621         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 622         struct qede_ucast_entry *tmp = NULL;
 623         struct qede_ucast_entry *u;
 624         struct ether_addr *mac_addr;
 625
 626         mac_addr  = (struct ether_addr *)ucast->mac;
 627         if (add) {
 628                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 629                         if ((memcmp(mac_addr, &tmp->mac,
 630                                     ETHER_ADDR_LEN) == 0) &&
 631                              ucast->vni == tmp->vni &&
 632                              ucast->vlan == tmp->vlan) {
 633                                 DP_ERR(edev, "Unicast MAC is already added"
 634                                        " with vlan = %u, vni = %u\n",
 635                                        ucast->vlan,  ucast->vni);
 636                                         return -EEXIST;
 637                         }
 638                 }
 639                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 640                                RTE_CACHE_LINE_SIZE);
 641                 if (!u) {
 642                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 643                         return -ENOMEM;
 644                 }
 645                 ether_addr_copy(mac_addr, &u->mac);
 646                 u->vlan = ucast->vlan;
 647                 u->vni = ucast->vni;
 648                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 649                 qdev->num_uc_addr++;
 650         } else {
 651                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 652                         if ((memcmp(mac_addr, &tmp->mac,
 653                                     ETHER_ADDR_LEN) == 0) &&
 654                             ucast->vlan == tmp->vlan      &&
 655                             ucast->vni == tmp->vni)
 656                         break;
 657                 }
 658                 if (tmp == NULL) {
 659                         DP_INFO(edev, "Unicast MAC is not found\n");
 660                         return -EINVAL;
 661                 }
 662                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 663                 qdev->num_uc_addr--;
 664         }
 665
 666         return 0;
 667 }
 668
 669 static int
 670 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 671                   bool add)
 672 {
 673         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 674         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 675         struct ether_addr *mac_addr;
 676         struct qede_mcast_entry *tmp = NULL;
 677         struct qede_mcast_entry *m;
 678
 679         mac_addr  = (struct ether_addr *)mcast->mac;
 680         if (add) {
 681                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 682                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 683                                 DP_ERR(edev,
 684                                         "Multicast MAC is already added\n");
 685                                 return -EEXIST;
 686                         }
 687                 }
 688                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 689                         RTE_CACHE_LINE_SIZE);
 690                 if (!m) {
 691                         DP_ERR(edev,
 692                                 "Did not allocate memory for mcast\n");
 693                         return -ENOMEM;
 694                 }
 695                 ether_addr_copy(mac_addr, &m->mac);
 696                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 697                 qdev->num_mc_addr++;
 698         } else {
 699                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 700                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 701                                 break;
 702                 }
 703                 if (tmp == NULL) {
 704                         DP_INFO(edev, "Multicast mac is not found\n");
 705                         return -EINVAL;
 706                 }
 707                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 708                              qede_mcast_entry, list);
 709                 qdev->num_mc_addr--;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static enum _ecore_status_t
 716 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 717                  bool add)
 718 {
 719         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 720         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 721         enum _ecore_status_t rc;
 722         struct ecore_filter_mcast mcast;
 723         struct qede_mcast_entry *tmp;
 724         uint16_t j = 0;
 725
 726         /* Multicast */
 727         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 728                 if (add) {
 729                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 730                                 DP_ERR(edev,
 731                                        "Mcast filter table limit exceeded, "
 732                                        "Please enable mcast promisc mode\n");
 733                                 return -ECORE_INVAL;
 734                         }
 735                 }
 736                 rc = qede_mcast_filter(eth_dev, ucast, add);
 737                 if (rc == 0) {
 738                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 739                         memset(&mcast, 0, sizeof(mcast));
 740                         mcast.num_mc_addrs = qdev->num_mc_addr;
 741                         mcast.opcode = ECORE_FILTER_ADD;
 742                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 743                                 ether_addr_copy(&tmp->mac,
 744                                         (struct ether_addr *)&mcast.mac[j]);
 745                                 j++;
 746                         }
 747                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 748                                                     ECORE_SPQ_MODE_CB, NULL);
 749                 }
 750                 if (rc != ECORE_SUCCESS) {
 751                         DP_ERR(edev, "Failed to add multicast filter"
 752                                " rc = %d, op = %d\n", rc, add);
 753                 }
 754         } else { /* Unicast */
 755                 if (add) {
 756                         if (qdev->num_uc_addr >=
 757                             qdev->dev_info.num_mac_filters) {
 758                                 DP_ERR(edev,
 759                                        "Ucast filter table limit exceeded,"
 760                                        " Please enable promisc mode\n");
 761                                 return -ECORE_INVAL;
 762                         }
 763                 }
 764                 rc = qede_ucast_filter(eth_dev, ucast, add);
 765                 if (rc == 0)
 766                         rc = ecore_filter_ucast_cmd(edev, ucast,
 767                                                     ECORE_SPQ_MODE_CB, NULL);
 768                 if (rc != ECORE_SUCCESS) {
 769                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 770                                rc, add);
 771                 }
 772         }
 773
 774         return rc;
 775 }
 776
 777 static int
 778 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 779                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 780 {
 781         struct ecore_filter_ucast ucast;
 782         int re;
 783
 784         qede_set_ucast_cmn_params(&ucast);
 785         ucast.type = ECORE_FILTER_MAC;
 786         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 787         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 788         return re;
 789 }
 790
 791 static void
 792 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 793 {
 794         struct qede_dev *qdev = eth_dev->data->dev_private;
 795         struct ecore_dev *edev = &qdev->edev;
 796         struct ecore_filter_ucast ucast;
 797
 798         PMD_INIT_FUNC_TRACE(edev);
 799
 800         if (index >= qdev->dev_info.num_mac_filters) {
 801                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 802                        index, qdev->dev_info.num_mac_filters);
 803                 return;
 804         }
 805
 806         qede_set_ucast_cmn_params(&ucast);
 807         ucast.opcode = ECORE_FILTER_REMOVE;
 808         ucast.type = ECORE_FILTER_MAC;
 809
 810         /* Use the index maintained by rte */
 811         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 812                         (struct ether_addr *)&ucast.mac);
 813
 814         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 815 }
 816
 817 static void
 818 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 819 {
 820         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 821         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 822
 823         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 824                                                mac_addr->addr_bytes)) {
 825                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 826                 ether_addr_copy(&qdev->primary_mac,
 827                                 &eth_dev->data->mac_addrs[0]);
 828                 return;
 829         }
 830
 831         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 832 }
 833
 834 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 835 {
 836         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 837         struct ecore_sp_vport_update_params params;
 838         struct ecore_hwfn *p_hwfn;
 839         uint8_t i;
 840         int rc;
 841
 842         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 843         params.vport_id = 0;
 844         params.update_accept_any_vlan_flg = 1;
 845         params.accept_any_vlan = flg;
 846         for_each_hwfn(edev, i) {
 847                 p_hwfn = &edev->hwfns[i];
 848                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 849                 rc = ecore_sp_vport_update(p_hwfn, &params,
 850                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 851                 if (rc != ECORE_SUCCESS) {
 852                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 853                         return;
 854                 }
 855         }
 856
 857         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 858 }
 859
 860 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 861 {
 862         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 863         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 864         struct ecore_sp_vport_update_params params;
 865         struct ecore_hwfn *p_hwfn;
 866         uint8_t i;
 867         int rc;
 868
 869         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 870         params.vport_id = 0;
 871         params.update_inner_vlan_removal_flg = 1;
 872         params.inner_vlan_removal_flg = flg;
 873         for_each_hwfn(edev, i) {
 874                 p_hwfn = &edev->hwfns[i];
 875                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 876                 rc = ecore_sp_vport_update(p_hwfn, &params,
 877                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 878                 if (rc != ECORE_SUCCESS) {
 879                         DP_ERR(edev, "Failed to update vport\n");
 880                         return -1;
 881                 }
 882         }
 883
 884         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 885         return 0;
 886 }
 887
 888 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 889                                 uint16_t vlan_id, int on)
 890 {
 891         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 892         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 893         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 894         struct qede_vlan_entry *tmp = NULL;
 895         struct qede_vlan_entry *vlan;
 896         struct ecore_filter_ucast ucast;
 897         int rc;
 898
 899         if (on) {
 900                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 901                         DP_ERR(edev, "Reached max VLAN filter limit"
 902                                       " enabling accept_any_vlan\n");
 903                         qede_config_accept_any_vlan(qdev, true);
 904                         return 0;
 905                 }
 906
 907                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 908                         if (tmp->vid == vlan_id) {
 909                                 DP_ERR(edev, "VLAN %u already configured\n",
 910                                        vlan_id);
 911                                 return -EEXIST;
 912                         }
 913                 }
 914
 915                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 916                                   RTE_CACHE_LINE_SIZE);
 917
 918                 if (!vlan) {
 919                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 920                         return -ENOMEM;
 921                 }
 922
 923                 qede_set_ucast_cmn_params(&ucast);
 924                 ucast.opcode = ECORE_FILTER_ADD;
 925                 ucast.type = ECORE_FILTER_VLAN;
 926                 ucast.vlan = vlan_id;
 927                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 928                                             NULL);
 929                 if (rc != 0) {
 930                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 931                                rc);
 932                         rte_free(vlan);
 933                 } else {
 934                         vlan->vid = vlan_id;
 935                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 936                         qdev->configured_vlans++;
 937                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 938                                 vlan_id, qdev->configured_vlans);
 939                 }
 940         } else {
 941                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 942                         if (tmp->vid == vlan_id)
 943                                 break;
 944                 }
 945
 946                 if (!tmp) {
 947                         if (qdev->configured_vlans == 0) {
 948                                 DP_INFO(edev,
 949                                         "No VLAN filters configured yet\n");
 950                                 return 0;
 951                         }
 952
 953                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 954                         return -EINVAL;
 955                 }
 956
 957                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 958
 959                 qede_set_ucast_cmn_params(&ucast);
 960                 ucast.opcode = ECORE_FILTER_REMOVE;
 961                 ucast.type = ECORE_FILTER_VLAN;
 962                 ucast.vlan = vlan_id;
 963                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 964                                             NULL);
 965                 if (rc != 0) {
 966                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 967                                vlan_id, rc);
 968                 } else {
 969                         qdev->configured_vlans--;
 970                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 971                                 vlan_id, qdev->configured_vlans);
 972                 }
 973         }
 974
 975         return rc;
 976 }
 977
 978 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 979 {
 980         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 981         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 982         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 983
 984         if (mask & ETH_VLAN_STRIP_MASK) {
 985                 if (rxmode->hw_vlan_strip)
 986                         (void)qede_vlan_stripping(eth_dev, 1);
 987                 else
 988                         (void)qede_vlan_stripping(eth_dev, 0);
 989         }
 990
 991         if (mask & ETH_VLAN_FILTER_MASK) {
 992                 /* VLAN filtering kicks in when a VLAN is added */
 993                 if (rxmode->hw_vlan_filter) {
 994                         qede_vlan_filter_set(eth_dev, 0, 1);
 995                 } else {
 996                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 997                                 DP_ERR(edev,
 998                                   " Please remove existing VLAN filters"
 999                                   " before disabling VLAN filtering\n");
1000                                 /* Signal app that VLAN filtering is still
1001                                  * enabled
1002                                  */
1003                                 rxmode->hw_vlan_filter = true;
1004                         } else {
1005                                 qede_vlan_filter_set(eth_dev, 0, 0);
1006                         }
1007                 }
1008         }
1009
1010         if (mask & ETH_VLAN_EXTEND_MASK)
1011                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1012                         " and classification is based on outer tag only\n");
1013
1014         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1015                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1016 }
1017
1018 static void qede_prandom_bytes(uint32_t *buff)
1019 {
1020         uint8_t i;
1021
1022         srand((unsigned int)time(NULL));
1023         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1024                 buff[i] = rand();
1025 }
1026
1027 int qede_config_rss(struct rte_eth_dev *eth_dev)
1028 {
1029         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1030 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1031         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1032 #endif
1033         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1034         struct rte_eth_rss_reta_entry64 reta_conf[2];
1035         struct rte_eth_rss_conf rss_conf;
1036         uint32_t i, id, pos, q;
1037
1038         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1039         if (!rss_conf.rss_key) {
1040                 DP_INFO(edev, "Applying driver default key\n");
1041                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1042                 qede_prandom_bytes(&def_rss_key[0]);
1043                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1044         }
1045
1046         /* Configure RSS hash */
1047         if (qede_rss_hash_update(eth_dev, &rss_conf))
1048                 return -EINVAL;
1049
1050         /* Configure default RETA */
1051         memset(reta_conf, 0, sizeof(reta_conf));
1052         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1053                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1054
1055         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1056                 id = i / RTE_RETA_GROUP_SIZE;
1057                 pos = i % RTE_RETA_GROUP_SIZE;
1058                 q = i % QEDE_RSS_COUNT(qdev);
1059                 reta_conf[id].reta[pos] = q;
1060         }
1061         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1062                                  ECORE_RSS_IND_TABLE_SIZE))
1063                 return -EINVAL;
1064
1065         return 0;
1066 }
1067
1068 static void qede_fastpath_start(struct ecore_dev *edev)
1069 {
1070         struct ecore_hwfn *p_hwfn;
1071         int i;
1072
1073         for_each_hwfn(edev, i) {
1074                 p_hwfn = &edev->hwfns[i];
1075                 ecore_hw_start_fastpath(p_hwfn);
1076         }
1077 }
1078
1079 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1080 {
1081         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1082         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1083
1084         PMD_INIT_FUNC_TRACE(edev);
1085
1086         /* Update MTU only if it has changed */
1087         if (qdev->mtu != qdev->new_mtu) {
1088                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1089                         goto err;
1090                 qdev->mtu = qdev->new_mtu;
1091                 /* If MTU has changed then update TPA too */
1092                 if (qdev->enable_lro)
1093                         if (qede_enable_tpa(eth_dev, true))
1094                                 goto err;
1095         }
1096
1097         /* Start queues */
1098         if (qede_start_queues(eth_dev))
1099                 goto err;
1100
1101         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1102          * enabling RSS. Hence RSS configuration is deferred upto this point.
1103          * Also, we would like to retain similar behavior in PF case, so we
1104          * don't do PF/VF specific check here.
1105          */
1106         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1107                 if (qede_config_rss(eth_dev))
1108                         goto err;
1109
1110         /* Enable vport*/
1111         if (qede_activate_vport(eth_dev, true))
1112                 goto err;
1113
1114         /* Bring-up the link */
1115         qede_dev_set_link_state(eth_dev, true);
1116
1117         /* Start/resume traffic */
1118         qede_fastpath_start(edev);
1119
1120         DP_INFO(edev, "Device started\n");
1121
1122         return 0;
1123 err:
1124         DP_ERR(edev, "Device start fails\n");
1125         return -1; /* common error code is < 0 */
1126 }
1127
1128 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1129 {
1130         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1131         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1132
1133         PMD_INIT_FUNC_TRACE(edev);
1134
1135         /* Disable vport */
1136         if (qede_activate_vport(eth_dev, false))
1137                 return;
1138
1139         if (qdev->enable_lro)
1140                 qede_enable_tpa(eth_dev, false);
1141
1142         /* TODO: Do we need disable LRO or RSS */
1143         /* Stop queues */
1144         qede_stop_queues(eth_dev);
1145
1146         /* Disable traffic */
1147         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1148
1149         /* Bring the link down */
1150         qede_dev_set_link_state(eth_dev, false);
1151
1152         DP_INFO(edev, "Device is stopped\n");
1153 }
1154
1155 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1156 {
1157         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1158         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1159         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1160
1161         PMD_INIT_FUNC_TRACE(edev);
1162
1163         /* Check requirements for 100G mode */
1164         if (edev->num_hwfns > 1) {
1165                 if (eth_dev->data->nb_rx_queues < 2 ||
1166                                 eth_dev->data->nb_tx_queues < 2) {
1167                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1168                         return -EINVAL;
1169                 }
1170
1171                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1172                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1173                         DP_ERR(edev,
1174                                         "100G mode needs even no. of RX/TX queues\n");
1175                         return -EINVAL;
1176                 }
1177         }
1178
1179         /* Sanity checks and throw warnings */
1180         if (rxmode->enable_scatter)
1181                 eth_dev->data->scattered_rx = 1;
1182
1183         if (!rxmode->hw_strip_crc)
1184                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1185
1186         if (!rxmode->hw_ip_checksum)
1187                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1188                                 "in hw\n");
1189         if (rxmode->header_split)
1190                 DP_INFO(edev, "Header split enable is not supported\n");
1191         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1192                                 ETH_MQ_RX_RSS)) {
1193                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1194                 return -ENOTSUP;
1195         }
1196         /* Flow director mode check */
1197         if (qede_check_fdir_support(eth_dev))
1198                 return -ENOTSUP;
1199
1200         /* Deallocate resources if held previously. It is needed only if the
1201          * queue count has been changed from previous configuration. If its
1202          * going to change then it means RX/TX queue setup will be called
1203          * again and the fastpath pointers will be reinitialized there.
1204          */
1205         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1206             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1207                 qede_dealloc_fp_resc(eth_dev);
1208                 /* Proceed with updated queue count */
1209                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1210                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1211                 if (qede_alloc_fp_resc(qdev))
1212                         return -ENOMEM;
1213         }
1214
1215         /* VF's MTU has to be set using vport-start where as
1216          * PF's MTU can be updated via vport-update.
1217          */
1218         if (IS_VF(edev)) {
1219                 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1220                         return -1;
1221         } else {
1222                 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1223                         return -1;
1224         }
1225
1226         qdev->mtu = rxmode->max_rx_pkt_len;
1227         qdev->new_mtu = qdev->mtu;
1228
1229         /* Configure TPA parameters */
1230         if (rxmode->enable_lro) {
1231                 if (qede_enable_tpa(eth_dev, true))
1232                         return -EINVAL;
1233                 /* Enable scatter mode for LRO */
1234                 if (!rxmode->enable_scatter)
1235                         eth_dev->data->scattered_rx = 1;
1236         }
1237         qdev->enable_lro = rxmode->enable_lro;
1238
1239         /* Enable VLAN offloads by default */
1240         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1241                         ETH_VLAN_FILTER_MASK |
1242                         ETH_VLAN_EXTEND_MASK);
1243
1244         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1245                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1246
1247         return 0;
1248 }
1249
1250 /* Info about HW descriptor ring limitations */
1251 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1252         .nb_max = 0x8000, /* 32K */
1253         .nb_min = 128,
1254         .nb_align = 128 /* lowest common multiple */
1255 };
1256
1257 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1258         .nb_max = 0x8000, /* 32K */
1259         .nb_min = 256,
1260         .nb_align = 256,
1261         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1262         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1263 };
1264
1265 static void
1266 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1267                   struct rte_eth_dev_info *dev_info)
1268 {
1269         struct qede_dev *qdev = eth_dev->data->dev_private;
1270         struct ecore_dev *edev = &qdev->edev;
1271         struct qed_link_output link;
1272         uint32_t speed_cap = 0;
1273
1274         PMD_INIT_FUNC_TRACE(edev);
1275
1276         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1277         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1278         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1279         dev_info->rx_desc_lim = qede_rx_desc_lim;
1280         dev_info->tx_desc_lim = qede_tx_desc_lim;
1281
1282         if (IS_PF(edev))
1283                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1284                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1285         else
1286                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1287                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1288         dev_info->max_tx_queues = dev_info->max_rx_queues;
1289
1290         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1291         dev_info->max_vfs = 0;
1292         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1293         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1294         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1295
1296         dev_info->default_txconf = (struct rte_eth_txconf) {
1297                 .txq_flags = QEDE_TXQ_FLAGS,
1298         };
1299
1300         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1301                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1302                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1303                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1304                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1305                                      DEV_RX_OFFLOAD_TCP_LRO);
1306
1307         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1308                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1309                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1310                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1311                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1312                                      DEV_TX_OFFLOAD_TCP_TSO |
1313                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1314
1315         memset(&link, 0, sizeof(struct qed_link_output));
1316         qdev->ops->common->get_link(edev, &link);
1317         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1318                 speed_cap |= ETH_LINK_SPEED_1G;
1319         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1320                 speed_cap |= ETH_LINK_SPEED_10G;
1321         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1322                 speed_cap |= ETH_LINK_SPEED_25G;
1323         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1324                 speed_cap |= ETH_LINK_SPEED_40G;
1325         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1326                 speed_cap |= ETH_LINK_SPEED_50G;
1327         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1328                 speed_cap |= ETH_LINK_SPEED_100G;
1329         dev_info->speed_capa = speed_cap;
1330 }
1331
1332 /* return 0 means link status changed, -1 means not changed */
1333 static int
1334 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1335 {
1336         struct qede_dev *qdev = eth_dev->data->dev_private;
1337         struct ecore_dev *edev = &qdev->edev;
1338         uint16_t link_duplex;
1339         struct qed_link_output link;
1340         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1341
1342         memset(&link, 0, sizeof(struct qed_link_output));
1343         qdev->ops->common->get_link(edev, &link);
1344
1345         /* Link Speed */
1346         curr->link_speed = link.speed;
1347
1348         /* Link Mode */
1349         switch (link.duplex) {
1350         case QEDE_DUPLEX_HALF:
1351                 link_duplex = ETH_LINK_HALF_DUPLEX;
1352                 break;
1353         case QEDE_DUPLEX_FULL:
1354                 link_duplex = ETH_LINK_FULL_DUPLEX;
1355                 break;
1356         case QEDE_DUPLEX_UNKNOWN:
1357         default:
1358                 link_duplex = -1;
1359         }
1360         curr->link_duplex = link_duplex;
1361
1362         /* Link Status */
1363         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1364
1365         /* AN */
1366         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1367                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1368
1369         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1370                 curr->link_speed, curr->link_duplex,
1371                 curr->link_autoneg, curr->link_status);
1372
1373         /* return 0 means link status changed, -1 means not changed */
1374         return ((curr->link_status == link.link_up) ? -1 : 0);
1375 }
1376
1377 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1378 {
1379 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1380         struct qede_dev *qdev = eth_dev->data->dev_private;
1381         struct ecore_dev *edev = &qdev->edev;
1382
1383         PMD_INIT_FUNC_TRACE(edev);
1384 #endif
1385
1386         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1387
1388         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1389                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1390
1391         qed_configure_filter_rx_mode(eth_dev, type);
1392 }
1393
1394 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1395 {
1396 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1397         struct qede_dev *qdev = eth_dev->data->dev_private;
1398         struct ecore_dev *edev = &qdev->edev;
1399
1400         PMD_INIT_FUNC_TRACE(edev);
1401 #endif
1402
1403         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1404                 qed_configure_filter_rx_mode(eth_dev,
1405                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1406         else
1407                 qed_configure_filter_rx_mode(eth_dev,
1408                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1409 }
1410
1411 static void qede_poll_sp_sb_cb(void *param)
1412 {
1413         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1414         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1415         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1416         int rc;
1417
1418         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1419         qede_interrupt_action(&edev->hwfns[1]);
1420
1421         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1422                                qede_poll_sp_sb_cb,
1423                                (void *)eth_dev);
1424         if (rc != 0) {
1425                 DP_ERR(edev, "Unable to start periodic"
1426                              " timer rc %d\n", rc);
1427                 assert(false && "Unable to start periodic timer");
1428         }
1429 }
1430
1431 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1432 {
1433         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1434         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1435         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1436
1437         PMD_INIT_FUNC_TRACE(edev);
1438
1439         /* dev_stop() shall cleanup fp resources in hw but without releasing
1440          * dma memories and sw structures so that dev_start() can be called
1441          * by the app without reconfiguration. However, in dev_close() we
1442          * can release all the resources and device can be brought up newly
1443          */
1444         if (eth_dev->data->dev_started)
1445                 qede_dev_stop(eth_dev);
1446
1447         qede_stop_vport(edev);
1448         qede_fdir_dealloc_resc(eth_dev);
1449         qede_dealloc_fp_resc(eth_dev);
1450
1451         eth_dev->data->nb_rx_queues = 0;
1452         eth_dev->data->nb_tx_queues = 0;
1453
1454         qdev->ops->common->slowpath_stop(edev);
1455         qdev->ops->common->remove(edev);
1456         rte_intr_disable(&pci_dev->intr_handle);
1457         rte_intr_callback_unregister(&pci_dev->intr_handle,
1458                                      qede_interrupt_handler, (void *)eth_dev);
1459         if (edev->num_hwfns > 1)
1460                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1461 }
1462
1463 static void
1464 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1465 {
1466         struct qede_dev *qdev = eth_dev->data->dev_private;
1467         struct ecore_dev *edev = &qdev->edev;
1468         struct ecore_eth_stats stats;
1469         unsigned int i = 0, j = 0, qid;
1470         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1471         struct qede_tx_queue *txq;
1472
1473         ecore_get_vport_stats(edev, &stats);
1474
1475         /* RX Stats */
1476         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1477             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1478
1479         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1480             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1481
1482         eth_stats->ierrors = stats.common.rx_crc_errors +
1483             stats.common.rx_align_errors +
1484             stats.common.rx_carrier_errors +
1485             stats.common.rx_oversize_packets +
1486             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1487
1488         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1489
1490         eth_stats->imissed = stats.common.mftag_filter_discards +
1491             stats.common.mac_filter_discards +
1492             stats.common.no_buff_discards +
1493             stats.common.brb_truncates + stats.common.brb_discards;
1494
1495         /* TX stats */
1496         eth_stats->opackets = stats.common.tx_ucast_pkts +
1497             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1498
1499         eth_stats->obytes = stats.common.tx_ucast_bytes +
1500             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1501
1502         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1503
1504         /* Queue stats */
1505         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1506                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1507         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1508                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1509         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1510             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1511                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1512                        "Not all the queue stats will be displayed. Set"
1513                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1514                        " appropriately and retry.\n");
1515
1516         for_each_rss(qid) {
1517                 eth_stats->q_ipackets[i] =
1518                         *(uint64_t *)(
1519                                 ((char *)(qdev->fp_array[qid].rxq)) +
1520                                 offsetof(struct qede_rx_queue,
1521                                 rcv_pkts));
1522                 eth_stats->q_errors[i] =
1523                         *(uint64_t *)(
1524                                 ((char *)(qdev->fp_array[qid].rxq)) +
1525                                 offsetof(struct qede_rx_queue,
1526                                 rx_hw_errors)) +
1527                         *(uint64_t *)(
1528                                 ((char *)(qdev->fp_array[qid].rxq)) +
1529                                 offsetof(struct qede_rx_queue,
1530                                 rx_alloc_errors));
1531                 i++;
1532                 if (i == rxq_stat_cntrs)
1533                         break;
1534         }
1535
1536         for_each_tss(qid) {
1537                 txq = qdev->fp_array[qid].txq;
1538                 eth_stats->q_opackets[j] =
1539                         *((uint64_t *)(uintptr_t)
1540                                 (((uint64_t)(uintptr_t)(txq)) +
1541                                  offsetof(struct qede_tx_queue,
1542                                           xmit_pkts)));
1543                 j++;
1544                 if (j == txq_stat_cntrs)
1545                         break;
1546         }
1547 }
1548
1549 static unsigned
1550 qede_get_xstats_count(struct qede_dev *qdev) {
1551         if (ECORE_IS_BB(&qdev->edev))
1552                 return RTE_DIM(qede_xstats_strings) +
1553                        RTE_DIM(qede_bb_xstats_strings) +
1554                        (RTE_DIM(qede_rxq_xstats_strings) *
1555                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1556                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1557         else
1558                 return RTE_DIM(qede_xstats_strings) +
1559                        RTE_DIM(qede_ah_xstats_strings) +
1560                        (RTE_DIM(qede_rxq_xstats_strings) *
1561                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1562                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1563 }
1564
1565 static int
1566 qede_get_xstats_names(struct rte_eth_dev *dev,
1567                       struct rte_eth_xstat_name *xstats_names,
1568                       __rte_unused unsigned int limit)
1569 {
1570         struct qede_dev *qdev = dev->data->dev_private;
1571         struct ecore_dev *edev = &qdev->edev;
1572         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1573         unsigned int i, qid, stat_idx = 0;
1574         unsigned int rxq_stat_cntrs;
1575
1576         if (xstats_names != NULL) {
1577                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1578                         snprintf(xstats_names[stat_idx].name,
1579                                 sizeof(xstats_names[stat_idx].name),
1580                                 "%s",
1581                                 qede_xstats_strings[i].name);
1582                         stat_idx++;
1583                 }
1584
1585                 if (ECORE_IS_BB(edev)) {
1586                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1587                                 snprintf(xstats_names[stat_idx].name,
1588                                         sizeof(xstats_names[stat_idx].name),
1589                                         "%s",
1590                                         qede_bb_xstats_strings[i].name);
1591                                 stat_idx++;
1592                         }
1593                 } else {
1594                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1595                                 snprintf(xstats_names[stat_idx].name,
1596                                         sizeof(xstats_names[stat_idx].name),
1597                                         "%s",
1598                                         qede_ah_xstats_strings[i].name);
1599                                 stat_idx++;
1600                         }
1601                 }
1602
1603                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1604                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1605                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1606                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1607                                 snprintf(xstats_names[stat_idx].name,
1608                                         sizeof(xstats_names[stat_idx].name),
1609                                         "%.4s%d%s",
1610                                         qede_rxq_xstats_strings[i].name, qid,
1611                                         qede_rxq_xstats_strings[i].name + 4);
1612                                 stat_idx++;
1613                         }
1614                 }
1615         }
1616
1617         return stat_cnt;
1618 }
1619
1620 static int
1621 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1622                 unsigned int n)
1623 {
1624         struct qede_dev *qdev = dev->data->dev_private;
1625         struct ecore_dev *edev = &qdev->edev;
1626         struct ecore_eth_stats stats;
1627         const unsigned int num = qede_get_xstats_count(qdev);
1628         unsigned int i, qid, stat_idx = 0;
1629         unsigned int rxq_stat_cntrs;
1630
1631         if (n < num)
1632                 return num;
1633
1634         ecore_get_vport_stats(edev, &stats);
1635
1636         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1637                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1638                                              qede_xstats_strings[i].offset);
1639                 xstats[stat_idx].id = stat_idx;
1640                 stat_idx++;
1641         }
1642
1643         if (ECORE_IS_BB(edev)) {
1644                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1645                         xstats[stat_idx].value =
1646                                         *(uint64_t *)(((char *)&stats) +
1647                                         qede_bb_xstats_strings[i].offset);
1648                         xstats[stat_idx].id = stat_idx;
1649                         stat_idx++;
1650                 }
1651         } else {
1652                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1653                         xstats[stat_idx].value =
1654                                         *(uint64_t *)(((char *)&stats) +
1655                                         qede_ah_xstats_strings[i].offset);
1656                         xstats[stat_idx].id = stat_idx;
1657                         stat_idx++;
1658                 }
1659         }
1660
1661         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1662                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1663         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1664                 for_each_rss(qid) {
1665                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1666                                 xstats[stat_idx].value = *(uint64_t *)(
1667                                         ((char *)(qdev->fp_array[qid].rxq)) +
1668                                          qede_rxq_xstats_strings[i].offset);
1669                                 xstats[stat_idx].id = stat_idx;
1670                                 stat_idx++;
1671                         }
1672                 }
1673         }
1674
1675         return stat_idx;
1676 }
1677
1678 static void
1679 qede_reset_xstats(struct rte_eth_dev *dev)
1680 {
1681         struct qede_dev *qdev = dev->data->dev_private;
1682         struct ecore_dev *edev = &qdev->edev;
1683
1684         ecore_reset_vport_stats(edev);
1685 }
1686
1687 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1688 {
1689         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1690         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1691         struct qed_link_params link_params;
1692         int rc;
1693
1694         DP_INFO(edev, "setting link state %d\n", link_up);
1695         memset(&link_params, 0, sizeof(link_params));
1696         link_params.link_up = link_up;
1697         rc = qdev->ops->common->set_link(edev, &link_params);
1698         if (rc != ECORE_SUCCESS)
1699                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1700
1701         return rc;
1702 }
1703
1704 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1705 {
1706         return qede_dev_set_link_state(eth_dev, true);
1707 }
1708
1709 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1710 {
1711         return qede_dev_set_link_state(eth_dev, false);
1712 }
1713
1714 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1715 {
1716         struct qede_dev *qdev = eth_dev->data->dev_private;
1717         struct ecore_dev *edev = &qdev->edev;
1718
1719         ecore_reset_vport_stats(edev);
1720 }
1721
1722 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1723 {
1724         enum qed_filter_rx_mode_type type =
1725             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1726
1727         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1728                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1729
1730         qed_configure_filter_rx_mode(eth_dev, type);
1731 }
1732
1733 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1734 {
1735         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1736                 qed_configure_filter_rx_mode(eth_dev,
1737                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1738         else
1739                 qed_configure_filter_rx_mode(eth_dev,
1740                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1741 }
1742
1743 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1744                               struct rte_eth_fc_conf *fc_conf)
1745 {
1746         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1747         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1748         struct qed_link_output current_link;
1749         struct qed_link_params params;
1750
1751         memset(&current_link, 0, sizeof(current_link));
1752         qdev->ops->common->get_link(edev, &current_link);
1753
1754         memset(&params, 0, sizeof(params));
1755         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1756         if (fc_conf->autoneg) {
1757                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1758                         DP_ERR(edev, "Autoneg not supported\n");
1759                         return -EINVAL;
1760                 }
1761                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1762         }
1763
1764         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1765         if (fc_conf->mode == RTE_FC_FULL)
1766                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1767                                         QED_LINK_PAUSE_RX_ENABLE);
1768         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1769                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1770         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1771                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1772
1773         params.link_up = true;
1774         (void)qdev->ops->common->set_link(edev, &params);
1775
1776         return 0;
1777 }
1778
1779 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1780                               struct rte_eth_fc_conf *fc_conf)
1781 {
1782         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1783         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1784         struct qed_link_output current_link;
1785
1786         memset(&current_link, 0, sizeof(current_link));
1787         qdev->ops->common->get_link(edev, &current_link);
1788
1789         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1790                 fc_conf->autoneg = true;
1791
1792         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1793                                          QED_LINK_PAUSE_TX_ENABLE))
1794                 fc_conf->mode = RTE_FC_FULL;
1795         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1796                 fc_conf->mode = RTE_FC_RX_PAUSE;
1797         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1798                 fc_conf->mode = RTE_FC_TX_PAUSE;
1799         else
1800                 fc_conf->mode = RTE_FC_NONE;
1801
1802         return 0;
1803 }
1804
1805 static const uint32_t *
1806 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1807 {
1808         static const uint32_t ptypes[] = {
1809                 RTE_PTYPE_L3_IPV4,
1810                 RTE_PTYPE_L3_IPV6,
1811                 RTE_PTYPE_UNKNOWN
1812         };
1813
1814         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1815                 return ptypes;
1816
1817         return NULL;
1818 }
1819
1820 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1821 {
1822         *rss_caps = 0;
1823         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1824         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1825         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1826         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1827         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1828         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1829         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1830         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1831 }
1832
1833 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1834                          struct rte_eth_rss_conf *rss_conf)
1835 {
1836         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1837         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1838         struct ecore_sp_vport_update_params vport_update_params;
1839         struct ecore_rss_params rss_params;
1840         struct ecore_hwfn *p_hwfn;
1841         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1842         uint64_t hf = rss_conf->rss_hf;
1843         uint8_t len = rss_conf->rss_key_len;
1844         uint8_t idx;
1845         uint8_t i;
1846         int rc;
1847
1848         memset(&vport_update_params, 0, sizeof(vport_update_params));
1849         memset(&rss_params, 0, sizeof(rss_params));
1850
1851         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1852                 (unsigned long)hf, len, key);
1853
1854         if (hf != 0) {
1855                 /* Enabling RSS */
1856                 DP_INFO(edev, "Enabling rss\n");
1857
1858                 /* RSS caps */
1859                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1860                 rss_params.update_rss_capabilities = 1;
1861
1862                 /* RSS hash key */
1863                 if (key) {
1864                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1865                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1866                                 return -EINVAL;
1867                         }
1868                         DP_INFO(edev, "Applying user supplied hash key\n");
1869                         rss_params.update_rss_key = 1;
1870                         memcpy(&rss_params.rss_key, key, len);
1871                 }
1872                 rss_params.rss_enable = 1;
1873         }
1874
1875         rss_params.update_rss_config = 1;
1876         /* tbl_size has to be set with capabilities */
1877         rss_params.rss_table_size_log = 7;
1878         vport_update_params.vport_id = 0;
1879         /* pass the L2 handles instead of qids */
1880         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1881                 idx = qdev->rss_ind_table[i];
1882                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1883         }
1884         vport_update_params.rss_params = &rss_params;
1885
1886         for_each_hwfn(edev, i) {
1887                 p_hwfn = &edev->hwfns[i];
1888                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1889                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1890                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1891                 if (rc) {
1892                         DP_ERR(edev, "vport-update for RSS failed\n");
1893                         return rc;
1894                 }
1895         }
1896         qdev->rss_enable = rss_params.rss_enable;
1897
1898         /* Update local structure for hash query */
1899         qdev->rss_conf.rss_hf = hf;
1900         qdev->rss_conf.rss_key_len = len;
1901         if (qdev->rss_enable) {
1902                 if  (qdev->rss_conf.rss_key == NULL) {
1903                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1904                         if (qdev->rss_conf.rss_key == NULL) {
1905                                 DP_ERR(edev, "No memory to store RSS key\n");
1906                                 return -ENOMEM;
1907                         }
1908                 }
1909                 if (key && len) {
1910                         DP_INFO(edev, "Storing RSS key\n");
1911                         memcpy(qdev->rss_conf.rss_key, key, len);
1912                 }
1913         } else if (!qdev->rss_enable && len == 0) {
1914                 if (qdev->rss_conf.rss_key) {
1915                         free(qdev->rss_conf.rss_key);
1916                         qdev->rss_conf.rss_key = NULL;
1917                         DP_INFO(edev, "Free RSS key\n");
1918                 }
1919         }
1920
1921         return 0;
1922 }
1923
1924 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1925                            struct rte_eth_rss_conf *rss_conf)
1926 {
1927         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1928
1929         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1930         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1931
1932         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1933                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1934                        rss_conf->rss_key_len);
1935         return 0;
1936 }
1937
1938 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1939                                     struct ecore_rss_params *rss)
1940 {
1941         int i, fn;
1942         bool rss_mode = 1; /* enable */
1943         struct ecore_queue_cid *cid;
1944         struct ecore_rss_params *t_rss;
1945
1946         /* In regular scenario, we'd simply need to take input handlers.
1947          * But in CMT, we'd have to split the handlers according to the
1948          * engine they were configured on. We'd then have to understand
1949          * whether RSS is really required, since 2-queues on CMT doesn't
1950          * require RSS.
1951          */
1952
1953         /* CMT should be round-robin */
1954         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1955                 cid = rss->rss_ind_table[i];
1956
1957                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1958                         t_rss = &rss[0];
1959                 else
1960                         t_rss = &rss[1];
1961
1962                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
1963         }
1964
1965         t_rss = &rss[1];
1966         t_rss->update_rss_ind_table = 1;
1967         t_rss->rss_table_size_log = 7;
1968         t_rss->update_rss_config = 1;
1969
1970         /* Make sure RSS is actually required */
1971         for_each_hwfn(edev, fn) {
1972                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
1973                      i++) {
1974                         if (rss[fn].rss_ind_table[i] !=
1975                             rss[fn].rss_ind_table[0])
1976                                 break;
1977                 }
1978
1979                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
1980                         DP_INFO(edev,
1981                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1982                         rss_mode = 0;
1983                         goto out;
1984                 }
1985         }
1986
1987 out:
1988         t_rss->rss_enable = rss_mode;
1989
1990         return rss_mode;
1991 }
1992
1993 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1994                          struct rte_eth_rss_reta_entry64 *reta_conf,
1995                          uint16_t reta_size)
1996 {
1997         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1998         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1999         struct ecore_sp_vport_update_params vport_update_params;
2000         struct ecore_rss_params *params;
2001         struct ecore_hwfn *p_hwfn;
2002         uint16_t i, idx, shift;
2003         uint8_t entry;
2004         int rc = 0;
2005
2006         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2007                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2008                        reta_size);
2009                 return -EINVAL;
2010         }
2011
2012         memset(&vport_update_params, 0, sizeof(vport_update_params));
2013         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2014                              RTE_CACHE_LINE_SIZE);
2015         if (params == NULL) {
2016                 DP_ERR(edev, "failed to allocate memory\n");
2017                 return -ENOMEM;
2018         }
2019
2020         for (i = 0; i < reta_size; i++) {
2021                 idx = i / RTE_RETA_GROUP_SIZE;
2022                 shift = i % RTE_RETA_GROUP_SIZE;
2023                 if (reta_conf[idx].mask & (1ULL << shift)) {
2024                         entry = reta_conf[idx].reta[shift];
2025                         /* Pass rxq handles to ecore */
2026                         params->rss_ind_table[i] =
2027                                         qdev->fp_array[entry].rxq->handle;
2028                         /* Update the local copy for RETA query command */
2029                         qdev->rss_ind_table[i] = entry;
2030                 }
2031         }
2032
2033         params->update_rss_ind_table = 1;
2034         params->rss_table_size_log = 7;
2035         params->update_rss_config = 1;
2036
2037         /* Fix up RETA for CMT mode device */
2038         if (edev->num_hwfns > 1)
2039                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2040                                                             params);
2041         vport_update_params.vport_id = 0;
2042         /* Use the current value of rss_enable */
2043         params->rss_enable = qdev->rss_enable;
2044         vport_update_params.rss_params = params;
2045
2046         for_each_hwfn(edev, i) {
2047                 p_hwfn = &edev->hwfns[i];
2048                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2049                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2050                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2051                 if (rc) {
2052                         DP_ERR(edev, "vport-update for RSS failed\n");
2053                         goto out;
2054                 }
2055         }
2056
2057 out:
2058         rte_free(params);
2059         return rc;
2060 }
2061
2062 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2063                                struct rte_eth_rss_reta_entry64 *reta_conf,
2064                                uint16_t reta_size)
2065 {
2066         struct qede_dev *qdev = eth_dev->data->dev_private;
2067         struct ecore_dev *edev = &qdev->edev;
2068         uint16_t i, idx, shift;
2069         uint8_t entry;
2070
2071         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2072                 DP_ERR(edev, "reta_size %d is not supported\n",
2073                        reta_size);
2074                 return -EINVAL;
2075         }
2076
2077         for (i = 0; i < reta_size; i++) {
2078                 idx = i / RTE_RETA_GROUP_SIZE;
2079                 shift = i % RTE_RETA_GROUP_SIZE;
2080                 if (reta_conf[idx].mask & (1ULL << shift)) {
2081                         entry = qdev->rss_ind_table[i];
2082                         reta_conf[idx].reta[shift] = entry;
2083                 }
2084         }
2085
2086         return 0;
2087 }
2088
2089
2090
2091 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2092 {
2093         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2094         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2095         struct rte_eth_dev_info dev_info = {0};
2096         struct qede_fastpath *fp;
2097         uint32_t frame_size;
2098         uint16_t rx_buf_size;
2099         uint16_t bufsz;
2100         int i;
2101
2102         PMD_INIT_FUNC_TRACE(edev);
2103         qede_dev_info_get(dev, &dev_info);
2104         frame_size = mtu + QEDE_ETH_OVERHEAD;
2105         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2106                 DP_ERR(edev, "MTU %u out of range\n", mtu);
2107                 return -EINVAL;
2108         }
2109         if (!dev->data->scattered_rx &&
2110             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2111                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2112                         dev->data->min_rx_buf_size);
2113                 return -EINVAL;
2114         }
2115         /* Temporarily replace I/O functions with dummy ones. It cannot
2116          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2117          */
2118         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2119         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2120         qede_dev_stop(dev);
2121         rte_delay_ms(1000);
2122         qdev->mtu = mtu;
2123         /* Fix up RX buf size for all queues of the port */
2124         for_each_rss(i) {
2125                 fp = &qdev->fp_array[i];
2126                 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2127                         fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2128                 if (dev->data->scattered_rx)
2129                         rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2130                 else
2131                         rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2132                 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2133                 fp->rxq->rx_buf_size = rx_buf_size;
2134                 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2135         }
2136         qede_dev_start(dev);
2137         if (frame_size > ETHER_MAX_LEN)
2138                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2139         else
2140                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2141         /* update max frame size */
2142         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2143         /* Reassign back */
2144         dev->rx_pkt_burst = qede_recv_pkts;
2145         dev->tx_pkt_burst = qede_xmit_pkts;
2146
2147         return 0;
2148 }
2149
2150 static int
2151 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2152                        struct rte_eth_udp_tunnel *tunnel_udp,
2153                        bool add)
2154 {
2155         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2156         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2157         struct ecore_tunnel_info tunn; /* @DPDK */
2158         struct ecore_hwfn *p_hwfn;
2159         int rc, i;
2160
2161         PMD_INIT_FUNC_TRACE(edev);
2162
2163         memset(&tunn, 0, sizeof(tunn));
2164         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2165                 tunn.vxlan_port.b_update_port = true;
2166                 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
2167                                                   QEDE_VXLAN_DEF_PORT;
2168                 for_each_hwfn(edev, i) {
2169                         p_hwfn = &edev->hwfns[i];
2170                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2171                                                 ECORE_SPQ_MODE_CB, NULL);
2172                         if (rc != ECORE_SUCCESS) {
2173                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2174                                        tunn.vxlan_port.port);
2175                                 return rc;
2176                         }
2177                 }
2178         }
2179
2180         return 0;
2181 }
2182
2183 static int
2184 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2185                       struct rte_eth_udp_tunnel *tunnel_udp)
2186 {
2187         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2188 }
2189
2190 static int
2191 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2192                       struct rte_eth_udp_tunnel *tunnel_udp)
2193 {
2194         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2195 }
2196
2197 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2198                                        uint32_t *clss, char *str)
2199 {
2200         uint16_t j;
2201         *clss = MAX_ECORE_TUNN_CLSS;
2202
2203         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2204                 if (filter == qede_tunn_types[j].rte_filter_type) {
2205                         *type = qede_tunn_types[j].qede_type;
2206                         *clss = qede_tunn_types[j].qede_tunn_clss;
2207                         strcpy(str, qede_tunn_types[j].string);
2208                         return;
2209                 }
2210         }
2211 }
2212
2213 static int
2214 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2215                               const struct rte_eth_tunnel_filter_conf *conf,
2216                               uint32_t type)
2217 {
2218         /* Init commmon ucast params first */
2219         qede_set_ucast_cmn_params(ucast);
2220
2221         /* Copy out the required fields based on classification type */
2222         ucast->type = type;
2223
2224         switch (type) {
2225         case ECORE_FILTER_VNI:
2226                 ucast->vni = conf->tenant_id;
2227         break;
2228         case ECORE_FILTER_INNER_VLAN:
2229                 ucast->vlan = conf->inner_vlan;
2230         break;
2231         case ECORE_FILTER_MAC:
2232                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2233                        ETHER_ADDR_LEN);
2234         break;
2235         case ECORE_FILTER_INNER_MAC:
2236                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2237                        ETHER_ADDR_LEN);
2238         break;
2239         case ECORE_FILTER_MAC_VNI_PAIR:
2240                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2241                         ETHER_ADDR_LEN);
2242                 ucast->vni = conf->tenant_id;
2243         break;
2244         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2245                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2246                         ETHER_ADDR_LEN);
2247                 ucast->vni = conf->tenant_id;
2248         break;
2249         case ECORE_FILTER_INNER_PAIR:
2250                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2251                         ETHER_ADDR_LEN);
2252                 ucast->vlan = conf->inner_vlan;
2253         break;
2254         default:
2255                 return -EINVAL;
2256         }
2257
2258         return ECORE_SUCCESS;
2259 }
2260
2261 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2262                                   enum rte_filter_op filter_op,
2263                                   const struct rte_eth_tunnel_filter_conf *conf)
2264 {
2265         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2266         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2267         struct ecore_tunnel_info tunn;
2268         struct ecore_hwfn *p_hwfn;
2269         enum ecore_filter_ucast_type type;
2270         enum ecore_tunn_clss clss;
2271         struct ecore_filter_ucast ucast;
2272         char str[80];
2273         uint16_t filter_type;
2274         int rc, i;
2275
2276         PMD_INIT_FUNC_TRACE(edev);
2277
2278         filter_type = conf->filter_type | qdev->vxlan_filter_type;
2279         /* First determine if the given filter classification is supported */
2280         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2281         if (clss == MAX_ECORE_TUNN_CLSS) {
2282                 DP_ERR(edev, "Wrong filter type\n");
2283                 return -EINVAL;
2284         }
2285         /* Init tunnel ucast params */
2286         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2287         if (rc != ECORE_SUCCESS) {
2288                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2289                                 conf->filter_type);
2290                 return rc;
2291         }
2292         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2293                 str, filter_op, ucast.type);
2294         switch (filter_op) {
2295         case RTE_ETH_FILTER_ADD:
2296                 ucast.opcode = ECORE_FILTER_ADD;
2297
2298                 /* Skip MAC/VLAN if filter is based on VNI */
2299                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2300                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2301                         if (rc == 0) {
2302                                 /* Enable accept anyvlan */
2303                                 qede_config_accept_any_vlan(qdev, true);
2304                         }
2305                 } else {
2306                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2307                         if (rc == 0)
2308                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2309                                                     ECORE_SPQ_MODE_CB, NULL);
2310                 }
2311
2312                 if (rc != ECORE_SUCCESS)
2313                         return rc;
2314
2315                 qdev->vxlan_filter_type = filter_type;
2316
2317                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
2318                 qede_set_cmn_tunn_param(&tunn, clss, true, true);
2319                 for_each_hwfn(edev, i) {
2320                         p_hwfn = &edev->hwfns[i];
2321                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
2322                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
2323                         if (rc != ECORE_SUCCESS) {
2324                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
2325                                        tunn.vxlan.tun_cls);
2326                         }
2327                 }
2328                 qdev->num_tunn_filters++; /* Filter added successfully */
2329         break;
2330         case RTE_ETH_FILTER_DELETE:
2331                 ucast.opcode = ECORE_FILTER_REMOVE;
2332
2333                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2334                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2335                 } else {
2336                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2337                         if (rc == 0)
2338                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2339                                                     ECORE_SPQ_MODE_CB, NULL);
2340                 }
2341                 if (rc != ECORE_SUCCESS)
2342                         return rc;
2343
2344                 qdev->vxlan_filter_type = filter_type;
2345                 qdev->num_tunn_filters--;
2346
2347                 /* Disable VXLAN if VXLAN filters become 0 */
2348                 if (qdev->num_tunn_filters == 0) {
2349                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
2350
2351                         /* Use 0 as tunnel mode */
2352                         qede_set_cmn_tunn_param(&tunn, clss, false, true);
2353                         for_each_hwfn(edev, i) {
2354                                 p_hwfn = &edev->hwfns[i];
2355                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2356                                         ECORE_SPQ_MODE_CB, NULL);
2357                                 if (rc != ECORE_SUCCESS) {
2358                                         DP_ERR(edev,
2359                                                 "Failed to update tunn_clss %u\n",
2360                                                 tunn.vxlan.tun_cls);
2361                                         break;
2362                                 }
2363                         }
2364                 }
2365         break;
2366         default:
2367                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2368                 return -EINVAL;
2369         }
2370         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
2371
2372         return 0;
2373 }
2374
2375 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2376                          enum rte_filter_type filter_type,
2377                          enum rte_filter_op filter_op,
2378                          void *arg)
2379 {
2380         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2381         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2382         struct rte_eth_tunnel_filter_conf *filter_conf =
2383                         (struct rte_eth_tunnel_filter_conf *)arg;
2384
2385         switch (filter_type) {
2386         case RTE_ETH_FILTER_TUNNEL:
2387                 switch (filter_conf->tunnel_type) {
2388                 case RTE_TUNNEL_TYPE_VXLAN:
2389                         DP_INFO(edev,
2390                                 "Packet steering to the specified Rx queue"
2391                                 " is not supported with VXLAN tunneling");
2392                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2393                                                       filter_conf));
2394                 /* Place holders for future tunneling support */
2395                 case RTE_TUNNEL_TYPE_GENEVE:
2396                 case RTE_TUNNEL_TYPE_TEREDO:
2397                 case RTE_TUNNEL_TYPE_NVGRE:
2398                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2399                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2400                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2401                                 filter_conf->tunnel_type);
2402                         return -EINVAL;
2403                 case RTE_TUNNEL_TYPE_NONE:
2404                 default:
2405                         return 0;
2406                 }
2407                 break;
2408         case RTE_ETH_FILTER_FDIR:
2409                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2410         case RTE_ETH_FILTER_NTUPLE:
2411                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2412         case RTE_ETH_FILTER_MACVLAN:
2413         case RTE_ETH_FILTER_ETHERTYPE:
2414         case RTE_ETH_FILTER_FLEXIBLE:
2415         case RTE_ETH_FILTER_SYN:
2416         case RTE_ETH_FILTER_HASH:
2417         case RTE_ETH_FILTER_L2_TUNNEL:
2418         case RTE_ETH_FILTER_MAX:
2419         default:
2420                 DP_ERR(edev, "Unsupported filter type %d\n",
2421                         filter_type);
2422                 return -EINVAL;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static const struct eth_dev_ops qede_eth_dev_ops = {
2429         .dev_configure = qede_dev_configure,
2430         .dev_infos_get = qede_dev_info_get,
2431         .rx_queue_setup = qede_rx_queue_setup,
2432         .rx_queue_release = qede_rx_queue_release,
2433         .tx_queue_setup = qede_tx_queue_setup,
2434         .tx_queue_release = qede_tx_queue_release,
2435         .dev_start = qede_dev_start,
2436         .dev_set_link_up = qede_dev_set_link_up,
2437         .dev_set_link_down = qede_dev_set_link_down,
2438         .link_update = qede_link_update,
2439         .promiscuous_enable = qede_promiscuous_enable,
2440         .promiscuous_disable = qede_promiscuous_disable,
2441         .allmulticast_enable = qede_allmulticast_enable,
2442         .allmulticast_disable = qede_allmulticast_disable,
2443         .dev_stop = qede_dev_stop,
2444         .dev_close = qede_dev_close,
2445         .stats_get = qede_get_stats,
2446         .stats_reset = qede_reset_stats,
2447         .xstats_get = qede_get_xstats,
2448         .xstats_reset = qede_reset_xstats,
2449         .xstats_get_names = qede_get_xstats_names,
2450         .mac_addr_add = qede_mac_addr_add,
2451         .mac_addr_remove = qede_mac_addr_remove,
2452         .mac_addr_set = qede_mac_addr_set,
2453         .vlan_offload_set = qede_vlan_offload_set,
2454         .vlan_filter_set = qede_vlan_filter_set,
2455         .flow_ctrl_set = qede_flow_ctrl_set,
2456         .flow_ctrl_get = qede_flow_ctrl_get,
2457         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2458         .rss_hash_update = qede_rss_hash_update,
2459         .rss_hash_conf_get = qede_rss_hash_conf_get,
2460         .reta_update  = qede_rss_reta_update,
2461         .reta_query  = qede_rss_reta_query,
2462         .mtu_set = qede_set_mtu,
2463         .filter_ctrl = qede_dev_filter_ctrl,
2464         .udp_tunnel_port_add = qede_udp_dst_port_add,
2465         .udp_tunnel_port_del = qede_udp_dst_port_del,
2466 };
2467
2468 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2469         .dev_configure = qede_dev_configure,
2470         .dev_infos_get = qede_dev_info_get,
2471         .rx_queue_setup = qede_rx_queue_setup,
2472         .rx_queue_release = qede_rx_queue_release,
2473         .tx_queue_setup = qede_tx_queue_setup,
2474         .tx_queue_release = qede_tx_queue_release,
2475         .dev_start = qede_dev_start,
2476         .dev_set_link_up = qede_dev_set_link_up,
2477         .dev_set_link_down = qede_dev_set_link_down,
2478         .link_update = qede_link_update,
2479         .promiscuous_enable = qede_promiscuous_enable,
2480         .promiscuous_disable = qede_promiscuous_disable,
2481         .allmulticast_enable = qede_allmulticast_enable,
2482         .allmulticast_disable = qede_allmulticast_disable,
2483         .dev_stop = qede_dev_stop,
2484         .dev_close = qede_dev_close,
2485         .stats_get = qede_get_stats,
2486         .stats_reset = qede_reset_stats,
2487         .xstats_get = qede_get_xstats,
2488         .xstats_reset = qede_reset_xstats,
2489         .xstats_get_names = qede_get_xstats_names,
2490         .vlan_offload_set = qede_vlan_offload_set,
2491         .vlan_filter_set = qede_vlan_filter_set,
2492         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2493         .rss_hash_update = qede_rss_hash_update,
2494         .rss_hash_conf_get = qede_rss_hash_conf_get,
2495         .reta_update  = qede_rss_reta_update,
2496         .reta_query  = qede_rss_reta_query,
2497         .mtu_set = qede_set_mtu,
2498 };
2499
2500 static void qede_update_pf_params(struct ecore_dev *edev)
2501 {
2502         struct ecore_pf_params pf_params;
2503
2504         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2505         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2506         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2507         qed_ops->common->update_pf_params(edev, &pf_params);
2508 }
2509
2510 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2511 {
2512         struct rte_pci_device *pci_dev;
2513         struct rte_pci_addr pci_addr;
2514         struct qede_dev *adapter;
2515         struct ecore_dev *edev;
2516         struct qed_dev_eth_info dev_info;
2517         struct qed_slowpath_params params;
2518         static bool do_once = true;
2519         uint8_t bulletin_change;
2520         uint8_t vf_mac[ETHER_ADDR_LEN];
2521         uint8_t is_mac_forced;
2522         bool is_mac_exist;
2523         /* Fix up ecore debug level */
2524         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2525         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2526         int rc;
2527
2528         /* Extract key data structures */
2529         adapter = eth_dev->data->dev_private;
2530         edev = &adapter->edev;
2531         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2532         pci_addr = pci_dev->addr;
2533
2534         PMD_INIT_FUNC_TRACE(edev);
2535
2536         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2537                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2538                  eth_dev->data->port_id);
2539
2540         eth_dev->rx_pkt_burst = qede_recv_pkts;
2541         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2542         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2543
2544         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2545                 DP_ERR(edev, "Skipping device init from secondary process\n");
2546                 return 0;
2547         }
2548
2549         rte_eth_copy_pci_info(eth_dev, pci_dev);
2550
2551         /* @DPDK */
2552         edev->vendor_id = pci_dev->id.vendor_id;
2553         edev->device_id = pci_dev->id.device_id;
2554
2555         qed_ops = qed_get_eth_ops();
2556         if (!qed_ops) {
2557                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2558                 return -EINVAL;
2559         }
2560
2561         DP_INFO(edev, "Starting qede probe\n");
2562         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2563                                     dp_level, is_vf);
2564         if (rc != 0) {
2565                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2566                 return -ENODEV;
2567         }
2568         qede_update_pf_params(edev);
2569         rte_intr_callback_register(&pci_dev->intr_handle,
2570                                    qede_interrupt_handler, (void *)eth_dev);
2571         if (rte_intr_enable(&pci_dev->intr_handle)) {
2572                 DP_ERR(edev, "rte_intr_enable() failed\n");
2573                 return -ENODEV;
2574         }
2575
2576         /* Start the Slowpath-process */
2577         memset(&params, 0, sizeof(struct qed_slowpath_params));
2578         params.int_mode = ECORE_INT_MODE_MSIX;
2579         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2580         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2581         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2582         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2583         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2584                 QEDE_PMD_DRV_VER_STR_SIZE);
2585
2586         /* For CMT mode device do periodic polling for slowpath events.
2587          * This is required since uio device uses only one MSI-x
2588          * interrupt vector but we need one for each engine.
2589          */
2590         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2591                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2592                                        qede_poll_sp_sb_cb,
2593                                        (void *)eth_dev);
2594                 if (rc != 0) {
2595                         DP_ERR(edev, "Unable to start periodic"
2596                                      " timer rc %d\n", rc);
2597                         return -EINVAL;
2598                 }
2599         }
2600
2601         rc = qed_ops->common->slowpath_start(edev, &params);
2602         if (rc) {
2603                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2604                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2605                                      (void *)eth_dev);
2606                 return -ENODEV;
2607         }
2608
2609         rc = qed_ops->fill_dev_info(edev, &dev_info);
2610         if (rc) {
2611                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2612                 qed_ops->common->slowpath_stop(edev);
2613                 qed_ops->common->remove(edev);
2614                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2615                                      (void *)eth_dev);
2616                 return -ENODEV;
2617         }
2618
2619         qede_alloc_etherdev(adapter, &dev_info);
2620
2621         adapter->ops->common->set_name(edev, edev->name);
2622
2623         if (!is_vf)
2624                 adapter->dev_info.num_mac_filters =
2625                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2626                                             ECORE_MAC);
2627         else
2628                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2629                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2630
2631         /* Allocate memory for storing MAC addr */
2632         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2633                                         (ETHER_ADDR_LEN *
2634                                         adapter->dev_info.num_mac_filters),
2635                                         RTE_CACHE_LINE_SIZE);
2636
2637         if (eth_dev->data->mac_addrs == NULL) {
2638                 DP_ERR(edev, "Failed to allocate MAC address\n");
2639                 qed_ops->common->slowpath_stop(edev);
2640                 qed_ops->common->remove(edev);
2641                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2642                                      (void *)eth_dev);
2643                 return -ENOMEM;
2644         }
2645
2646         if (!is_vf) {
2647                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2648                                 hw_info.hw_mac_addr,
2649                                 &eth_dev->data->mac_addrs[0]);
2650                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2651                                 &adapter->primary_mac);
2652         } else {
2653                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2654                                        &bulletin_change);
2655                 if (bulletin_change) {
2656                         is_mac_exist =
2657                             ecore_vf_bulletin_get_forced_mac(
2658                                                 ECORE_LEADING_HWFN(edev),
2659                                                 vf_mac,
2660                                                 &is_mac_forced);
2661                         if (is_mac_exist && is_mac_forced) {
2662                                 DP_INFO(edev, "VF macaddr received from PF\n");
2663                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2664                                                 &eth_dev->data->mac_addrs[0]);
2665                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2666                                                 &adapter->primary_mac);
2667                         } else {
2668                                 DP_ERR(edev, "No VF macaddr assigned\n");
2669                         }
2670                 }
2671         }
2672
2673         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2674
2675         if (do_once) {
2676 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2677                 qede_print_adapter_info(adapter);
2678 #endif
2679                 do_once = false;
2680         }
2681
2682         adapter->num_tx_queues = 0;
2683         adapter->num_rx_queues = 0;
2684         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2685         SLIST_INIT(&adapter->vlan_list_head);
2686         SLIST_INIT(&adapter->uc_list_head);
2687         adapter->mtu = ETHER_MTU;
2688         adapter->new_mtu = ETHER_MTU;
2689         if (!is_vf)
2690                 if (qede_start_vport(adapter, adapter->mtu))
2691                         return -1;
2692
2693         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2694                 adapter->primary_mac.addr_bytes[0],
2695                 adapter->primary_mac.addr_bytes[1],
2696                 adapter->primary_mac.addr_bytes[2],
2697                 adapter->primary_mac.addr_bytes[3],
2698                 adapter->primary_mac.addr_bytes[4],
2699                 adapter->primary_mac.addr_bytes[5]);
2700
2701         DP_INFO(edev, "Device initialized\n");
2702
2703         return 0;
2704 }
2705
2706 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2707 {
2708         return qede_common_dev_init(eth_dev, 1);
2709 }
2710
2711 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2712 {
2713         return qede_common_dev_init(eth_dev, 0);
2714 }
2715
2716 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2717 {
2718 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2719         struct qede_dev *qdev = eth_dev->data->dev_private;
2720         struct ecore_dev *edev = &qdev->edev;
2721
2722         PMD_INIT_FUNC_TRACE(edev);
2723 #endif
2724
2725         /* only uninitialize in the primary process */
2726         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2727                 return 0;
2728
2729         /* safe to close dev here */
2730         qede_dev_close(eth_dev);
2731
2732         eth_dev->dev_ops = NULL;
2733         eth_dev->rx_pkt_burst = NULL;
2734         eth_dev->tx_pkt_burst = NULL;
2735
2736         if (eth_dev->data->mac_addrs)
2737                 rte_free(eth_dev->data->mac_addrs);
2738
2739         eth_dev->data->mac_addrs = NULL;
2740
2741         return 0;
2742 }
2743
2744 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2745 {
2746         return qede_dev_common_uninit(eth_dev);
2747 }
2748
2749 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2750 {
2751         return qede_dev_common_uninit(eth_dev);
2752 }
2753
2754 static const struct rte_pci_id pci_id_qedevf_map[] = {
2755 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2756         {
2757                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2758         },
2759         {
2760                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2761         },
2762         {
2763                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2764         },
2765         {.vendor_id = 0,}
2766 };
2767
2768 static const struct rte_pci_id pci_id_qede_map[] = {
2769 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2770         {
2771                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2772         },
2773         {
2774                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2775         },
2776         {
2777                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2778         },
2779         {
2780                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2781         },
2782         {
2783                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2784         },
2785         {
2786                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2787         },
2788         {
2789                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2790         },
2791         {
2792                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2793         },
2794         {
2795                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2796         },
2797         {
2798                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2799         },
2800         {.vendor_id = 0,}
2801 };
2802
2803 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2804         struct rte_pci_device *pci_dev)
2805 {
2806         return rte_eth_dev_pci_generic_probe(pci_dev,
2807                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2808 }
2809
2810 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2811 {
2812         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2813 }
2814
2815 static struct rte_pci_driver rte_qedevf_pmd = {
2816         .id_table = pci_id_qedevf_map,
2817         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2818         .probe = qedevf_eth_dev_pci_probe,
2819         .remove = qedevf_eth_dev_pci_remove,
2820 };
2821
2822 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2823         struct rte_pci_device *pci_dev)
2824 {
2825         return rte_eth_dev_pci_generic_probe(pci_dev,
2826                 sizeof(struct qede_dev), qede_eth_dev_init);
2827 }
2828
2829 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2830 {
2831         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2832 }
2833
2834 static struct rte_pci_driver rte_qede_pmd = {
2835         .id_table = pci_id_qede_map,
2836         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2837         .probe = qede_eth_dev_pci_probe,
2838         .remove = qede_eth_dev_pci_remove,
2839 };
2840
2841 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2842 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2843 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2844 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2845 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2846 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");