1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #include "qede_ethdev.h"
8 #include <rte_string_fns.h>
10 #include <rte_version.h>
11 #include <rte_kvargs.h>
14 int qede_logtype_init;
15 int qede_logtype_driver;
17 static const struct qed_eth_ops *qed_ops;
18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
21 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */
23 struct rte_qede_xstats_name_off {
24 char name[RTE_ETH_XSTATS_NAME_SIZE];
28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
30 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
31 {"rx_multicast_bytes",
32 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
33 {"rx_broadcast_bytes",
34 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
35 {"rx_unicast_packets",
36 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
37 {"rx_multicast_packets",
38 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
39 {"rx_broadcast_packets",
40 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
43 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
44 {"tx_multicast_bytes",
45 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
46 {"tx_broadcast_bytes",
47 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
48 {"tx_unicast_packets",
49 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
50 {"tx_multicast_packets",
51 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
52 {"tx_broadcast_packets",
53 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
55 {"rx_64_byte_packets",
56 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
57 {"rx_65_to_127_byte_packets",
58 offsetof(struct ecore_eth_stats_common,
59 rx_65_to_127_byte_packets)},
60 {"rx_128_to_255_byte_packets",
61 offsetof(struct ecore_eth_stats_common,
62 rx_128_to_255_byte_packets)},
63 {"rx_256_to_511_byte_packets",
64 offsetof(struct ecore_eth_stats_common,
65 rx_256_to_511_byte_packets)},
66 {"rx_512_to_1023_byte_packets",
67 offsetof(struct ecore_eth_stats_common,
68 rx_512_to_1023_byte_packets)},
69 {"rx_1024_to_1518_byte_packets",
70 offsetof(struct ecore_eth_stats_common,
71 rx_1024_to_1518_byte_packets)},
72 {"tx_64_byte_packets",
73 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
74 {"tx_65_to_127_byte_packets",
75 offsetof(struct ecore_eth_stats_common,
76 tx_65_to_127_byte_packets)},
77 {"tx_128_to_255_byte_packets",
78 offsetof(struct ecore_eth_stats_common,
79 tx_128_to_255_byte_packets)},
80 {"tx_256_to_511_byte_packets",
81 offsetof(struct ecore_eth_stats_common,
82 tx_256_to_511_byte_packets)},
83 {"tx_512_to_1023_byte_packets",
84 offsetof(struct ecore_eth_stats_common,
85 tx_512_to_1023_byte_packets)},
86 {"tx_1024_to_1518_byte_packets",
87 offsetof(struct ecore_eth_stats_common,
88 tx_1024_to_1518_byte_packets)},
90 {"rx_mac_crtl_frames",
91 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
92 {"tx_mac_control_frames",
93 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
95 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
97 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
98 {"rx_priority_flow_control_frames",
99 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
100 {"tx_priority_flow_control_frames",
101 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
104 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
106 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
107 {"rx_carrier_errors",
108 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
109 {"rx_oversize_packet_errors",
110 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
112 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
113 {"rx_undersize_packet_errors",
114 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
115 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
116 {"rx_host_buffer_not_available",
117 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
118 /* Number of packets discarded because they are bigger than MTU */
119 {"rx_packet_too_big_discards",
120 offsetof(struct ecore_eth_stats_common,
121 packet_too_big_discard)},
122 {"rx_ttl_zero_discards",
123 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
124 {"rx_multi_function_tag_filter_discards",
125 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
126 {"rx_mac_filter_discards",
127 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
128 {"rx_gft_filter_drop",
129 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
130 {"rx_hw_buffer_truncates",
131 offsetof(struct ecore_eth_stats_common, brb_truncates)},
132 {"rx_hw_buffer_discards",
133 offsetof(struct ecore_eth_stats_common, brb_discards)},
134 {"tx_error_drop_packets",
135 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
137 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
138 {"rx_mac_unicast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
140 {"rx_mac_multicast_packets",
141 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
142 {"rx_mac_broadcast_packets",
143 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
145 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
146 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
147 {"tx_mac_unicast_packets",
148 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
149 {"tx_mac_multicast_packets",
150 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
151 {"tx_mac_broadcast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
154 {"lro_coalesced_packets",
155 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
156 {"lro_coalesced_events",
157 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
159 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
160 {"lro_not_coalesced_packets",
161 offsetof(struct ecore_eth_stats_common,
162 tpa_not_coalesced_pkts)},
163 {"lro_coalesced_bytes",
164 offsetof(struct ecore_eth_stats_common,
165 tpa_coalesced_bytes)},
168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
169 {"rx_1519_to_1522_byte_packets",
170 offsetof(struct ecore_eth_stats, bb) +
171 offsetof(struct ecore_eth_stats_bb,
172 rx_1519_to_1522_byte_packets)},
173 {"rx_1519_to_2047_byte_packets",
174 offsetof(struct ecore_eth_stats, bb) +
175 offsetof(struct ecore_eth_stats_bb,
176 rx_1519_to_2047_byte_packets)},
177 {"rx_2048_to_4095_byte_packets",
178 offsetof(struct ecore_eth_stats, bb) +
179 offsetof(struct ecore_eth_stats_bb,
180 rx_2048_to_4095_byte_packets)},
181 {"rx_4096_to_9216_byte_packets",
182 offsetof(struct ecore_eth_stats, bb) +
183 offsetof(struct ecore_eth_stats_bb,
184 rx_4096_to_9216_byte_packets)},
185 {"rx_9217_to_16383_byte_packets",
186 offsetof(struct ecore_eth_stats, bb) +
187 offsetof(struct ecore_eth_stats_bb,
188 rx_9217_to_16383_byte_packets)},
190 {"tx_1519_to_2047_byte_packets",
191 offsetof(struct ecore_eth_stats, bb) +
192 offsetof(struct ecore_eth_stats_bb,
193 tx_1519_to_2047_byte_packets)},
194 {"tx_2048_to_4095_byte_packets",
195 offsetof(struct ecore_eth_stats, bb) +
196 offsetof(struct ecore_eth_stats_bb,
197 tx_2048_to_4095_byte_packets)},
198 {"tx_4096_to_9216_byte_packets",
199 offsetof(struct ecore_eth_stats, bb) +
200 offsetof(struct ecore_eth_stats_bb,
201 tx_4096_to_9216_byte_packets)},
202 {"tx_9217_to_16383_byte_packets",
203 offsetof(struct ecore_eth_stats, bb) +
204 offsetof(struct ecore_eth_stats_bb,
205 tx_9217_to_16383_byte_packets)},
207 {"tx_lpi_entry_count",
208 offsetof(struct ecore_eth_stats, bb) +
209 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
210 {"tx_total_collisions",
211 offsetof(struct ecore_eth_stats, bb) +
212 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
216 {"rx_1519_to_max_byte_packets",
217 offsetof(struct ecore_eth_stats, ah) +
218 offsetof(struct ecore_eth_stats_ah,
219 rx_1519_to_max_byte_packets)},
220 {"tx_1519_to_max_byte_packets",
221 offsetof(struct ecore_eth_stats, ah) +
222 offsetof(struct ecore_eth_stats_ah,
223 tx_1519_to_max_byte_packets)},
226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
228 offsetof(struct qede_rx_queue, rx_segs)},
230 offsetof(struct qede_rx_queue, rx_hw_errors)},
231 {"rx_q_allocation_errors",
232 offsetof(struct qede_rx_queue, rx_alloc_errors)}
235 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
237 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
241 qede_interrupt_handler_intx(void *param)
243 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
244 struct qede_dev *qdev = eth_dev->data->dev_private;
245 struct ecore_dev *edev = &qdev->edev;
248 /* Check if our device actually raised an interrupt */
249 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
251 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
253 if (rte_intr_ack(eth_dev->intr_handle))
254 DP_ERR(edev, "rte_intr_ack failed\n");
259 qede_interrupt_handler(void *param)
261 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
262 struct qede_dev *qdev = eth_dev->data->dev_private;
263 struct ecore_dev *edev = &qdev->edev;
265 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
266 if (rte_intr_ack(eth_dev->intr_handle))
267 DP_ERR(edev, "rte_intr_ack failed\n");
271 qede_assign_rxtx_handlers(struct rte_eth_dev *dev)
273 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
274 struct qede_dev *qdev = dev->data->dev_private;
275 struct ecore_dev *edev = &qdev->edev;
276 bool use_tx_offload = false;
278 if (ECORE_IS_CMT(edev)) {
279 dev->rx_pkt_burst = qede_recv_pkts_cmt;
280 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
284 if (dev->data->lro || dev->data->scattered_rx) {
285 DP_INFO(edev, "Assigning qede_recv_pkts\n");
286 dev->rx_pkt_burst = qede_recv_pkts;
288 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
289 dev->rx_pkt_burst = qede_recv_pkts_regular;
292 use_tx_offload = !!(tx_offloads &
293 (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
294 DEV_TX_OFFLOAD_TCP_TSO | /* tso */
295 DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
297 if (use_tx_offload) {
298 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
299 dev->tx_pkt_burst = qede_xmit_pkts;
301 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
302 dev->tx_pkt_burst = qede_xmit_pkts_regular;
307 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
309 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
313 static void qede_print_adapter_info(struct qede_dev *qdev)
315 struct ecore_dev *edev = &qdev->edev;
316 struct qed_dev_info *info = &qdev->dev_info.common;
317 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
319 DP_INFO(edev, "**************************************************\n");
320 DP_INFO(edev, " DPDK version\t\t\t: %s\n", rte_version());
321 DP_INFO(edev, " Chip details\t\t\t: %s %c%d\n",
322 ECORE_IS_BB(edev) ? "BB" : "AH",
323 'A' + edev->chip_rev,
324 (int)edev->chip_metal);
325 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
326 QEDE_PMD_DRV_VERSION);
327 DP_INFO(edev, " Driver version\t\t\t: %s\n", ver_str);
329 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
330 QEDE_PMD_BASE_VERSION);
331 DP_INFO(edev, " Base version\t\t\t: %s\n", ver_str);
334 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
335 QEDE_PMD_FW_VERSION);
337 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
338 info->fw_major, info->fw_minor,
339 info->fw_rev, info->fw_eng);
340 DP_INFO(edev, " Firmware version\t\t\t: %s\n", ver_str);
342 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
344 (info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
345 QED_MFW_VERSION_3_OFFSET,
346 (info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
347 QED_MFW_VERSION_2_OFFSET,
348 (info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
349 QED_MFW_VERSION_1_OFFSET,
350 (info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
351 QED_MFW_VERSION_0_OFFSET);
352 DP_INFO(edev, " Management Firmware version\t: %s\n", ver_str);
353 DP_INFO(edev, " Firmware file\t\t\t: %s\n", qede_fw_file);
354 DP_INFO(edev, "**************************************************\n");
357 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
359 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
360 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
361 unsigned int i = 0, j = 0, qid;
362 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
363 struct qede_tx_queue *txq;
365 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
367 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
368 RTE_ETHDEV_QUEUE_STAT_CNTRS);
369 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
370 RTE_ETHDEV_QUEUE_STAT_CNTRS);
372 for (qid = 0; qid < qdev->num_rx_queues; qid++) {
373 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
374 offsetof(struct qede_rx_queue, rcv_pkts), 0,
376 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
377 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
379 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
380 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
384 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
385 OSAL_MEMSET((((char *)
386 (qdev->fp_array[qid].rxq)) +
387 qede_rxq_xstats_strings[j].offset),
392 if (i == rxq_stat_cntrs)
398 for (qid = 0; qid < qdev->num_tx_queues; qid++) {
399 txq = qdev->fp_array[qid].txq;
401 OSAL_MEMSET((uint64_t *)(uintptr_t)
402 (((uint64_t)(uintptr_t)(txq)) +
403 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
407 if (i == txq_stat_cntrs)
413 qede_stop_vport(struct ecore_dev *edev)
415 struct ecore_hwfn *p_hwfn;
421 for_each_hwfn(edev, i) {
422 p_hwfn = &edev->hwfns[i];
423 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
425 if (rc != ECORE_SUCCESS) {
426 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
431 DP_INFO(edev, "vport stopped\n");
437 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
439 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
440 struct ecore_sp_vport_start_params params;
441 struct ecore_hwfn *p_hwfn;
445 if (qdev->vport_started)
446 qede_stop_vport(edev);
448 memset(¶ms, 0, sizeof(params));
451 /* @DPDK - Disable FW placement */
452 params.zero_placement_offset = 1;
453 for_each_hwfn(edev, i) {
454 p_hwfn = &edev->hwfns[i];
455 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
456 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
457 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
458 if (rc != ECORE_SUCCESS) {
459 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
463 ecore_reset_vport_stats(edev);
464 qdev->vport_started = true;
465 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
470 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
471 #define QEDE_VF_TX_SWITCHING "vf_tx_switching"
473 /* Activate or deactivate vport via vport-update */
474 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
476 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
477 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
478 struct ecore_sp_vport_update_params params;
479 struct ecore_hwfn *p_hwfn;
483 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
485 params.update_vport_active_rx_flg = 1;
486 params.update_vport_active_tx_flg = 1;
487 params.vport_active_rx_flg = flg;
488 params.vport_active_tx_flg = flg;
489 if ((qdev->enable_tx_switching == false) && (flg == true)) {
490 params.update_tx_switching_flg = 1;
491 params.tx_switching_flg = !flg;
493 for_each_hwfn(edev, i) {
494 p_hwfn = &edev->hwfns[i];
495 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
496 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
497 ECORE_SPQ_MODE_EBLOCK, NULL);
498 if (rc != ECORE_SUCCESS) {
499 DP_ERR(edev, "Failed to update vport\n");
503 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
509 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
510 uint16_t mtu, bool enable)
512 /* Enable LRO in split mode */
513 sge_tpa_params->tpa_ipv4_en_flg = enable;
514 sge_tpa_params->tpa_ipv6_en_flg = enable;
515 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
516 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
517 /* set if tpa enable changes */
518 sge_tpa_params->update_tpa_en_flg = 1;
519 /* set if tpa parameters should be handled */
520 sge_tpa_params->update_tpa_param_flg = enable;
522 sge_tpa_params->max_buffers_per_cqe = 20;
523 /* Enable TPA in split mode. In this mode each TPA segment
524 * starts on the new BD, so there is one BD per segment.
526 sge_tpa_params->tpa_pkt_split_flg = 1;
527 sge_tpa_params->tpa_hdr_data_split_flg = 0;
528 sge_tpa_params->tpa_gro_consistent_flg = 0;
529 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
530 sge_tpa_params->tpa_max_size = 0x7FFF;
531 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
532 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
535 /* Enable/disable LRO via vport-update */
536 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
538 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
539 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
540 struct ecore_sp_vport_update_params params;
541 struct ecore_sge_tpa_params tpa_params;
542 struct ecore_hwfn *p_hwfn;
546 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
547 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
548 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
550 params.sge_tpa_params = &tpa_params;
551 for_each_hwfn(edev, i) {
552 p_hwfn = &edev->hwfns[i];
553 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
554 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
555 ECORE_SPQ_MODE_EBLOCK, NULL);
556 if (rc != ECORE_SUCCESS) {
557 DP_ERR(edev, "Failed to update LRO\n");
561 qdev->enable_lro = flg;
562 eth_dev->data->lro = flg;
564 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
570 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
571 enum qed_filter_rx_mode_type type)
573 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
574 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
575 struct ecore_filter_accept_flags flags;
577 memset(&flags, 0, sizeof(flags));
579 flags.update_rx_mode_config = 1;
580 flags.update_tx_mode_config = 1;
581 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
582 ECORE_ACCEPT_MCAST_MATCHED |
585 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
586 ECORE_ACCEPT_MCAST_MATCHED |
589 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
590 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
592 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
593 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
595 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
596 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
597 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
598 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
599 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
600 ECORE_ACCEPT_MCAST_UNMATCHED;
603 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
604 ECORE_SPQ_MODE_CB, NULL);
608 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
611 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
612 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
613 struct qede_ucast_entry *tmp = NULL;
614 struct qede_ucast_entry *u;
615 struct rte_ether_addr *mac_addr;
617 mac_addr = (struct rte_ether_addr *)ucast->mac;
619 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
620 if ((memcmp(mac_addr, &tmp->mac,
621 RTE_ETHER_ADDR_LEN) == 0) &&
622 ucast->vni == tmp->vni &&
623 ucast->vlan == tmp->vlan) {
624 DP_INFO(edev, "Unicast MAC is already added"
625 " with vlan = %u, vni = %u\n",
626 ucast->vlan, ucast->vni);
630 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
631 RTE_CACHE_LINE_SIZE);
633 DP_ERR(edev, "Did not allocate memory for ucast\n");
636 rte_ether_addr_copy(mac_addr, &u->mac);
637 u->vlan = ucast->vlan;
639 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
642 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
643 if ((memcmp(mac_addr, &tmp->mac,
644 RTE_ETHER_ADDR_LEN) == 0) &&
645 ucast->vlan == tmp->vlan &&
646 ucast->vni == tmp->vni)
650 DP_INFO(edev, "Unicast MAC is not found\n");
653 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
661 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
662 struct rte_ether_addr *mc_addrs,
663 uint32_t mc_addrs_num)
665 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
666 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
667 struct ecore_filter_mcast mcast;
668 struct qede_mcast_entry *m = NULL;
672 for (i = 0; i < mc_addrs_num; i++) {
673 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
674 RTE_CACHE_LINE_SIZE);
676 DP_ERR(edev, "Did not allocate memory for mcast\n");
679 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
680 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
682 memset(&mcast, 0, sizeof(mcast));
683 mcast.num_mc_addrs = mc_addrs_num;
684 mcast.opcode = ECORE_FILTER_ADD;
685 for (i = 0; i < mc_addrs_num; i++)
686 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
688 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
689 if (rc != ECORE_SUCCESS) {
690 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
697 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
699 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
700 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
701 struct qede_mcast_entry *tmp = NULL;
702 struct ecore_filter_mcast mcast;
706 memset(&mcast, 0, sizeof(mcast));
707 mcast.num_mc_addrs = qdev->num_mc_addr;
708 mcast.opcode = ECORE_FILTER_REMOVE;
710 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
711 rte_ether_addr_copy(&tmp->mac,
712 (struct rte_ether_addr *)&mcast.mac[j]);
715 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
716 if (rc != ECORE_SUCCESS) {
717 DP_ERR(edev, "Failed to delete multicast filter\n");
721 while (!SLIST_EMPTY(&qdev->mc_list_head)) {
722 tmp = SLIST_FIRST(&qdev->mc_list_head);
723 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
725 SLIST_INIT(&qdev->mc_list_head);
731 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
734 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
735 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
736 enum _ecore_status_t rc = ECORE_INVAL;
738 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
739 DP_ERR(edev, "Ucast filter table limit exceeded,"
740 " Please enable promisc mode\n");
744 rc = qede_ucast_filter(eth_dev, ucast, add);
746 rc = ecore_filter_ucast_cmd(edev, ucast,
747 ECORE_SPQ_MODE_CB, NULL);
748 /* Indicate error only for add filter operation.
749 * Delete filter operations are not severe.
751 if ((rc != ECORE_SUCCESS) && add)
752 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
759 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
760 __rte_unused uint32_t index, __rte_unused uint32_t pool)
762 struct ecore_filter_ucast ucast;
765 if (!rte_is_valid_assigned_ether_addr(mac_addr))
768 qede_set_ucast_cmn_params(&ucast);
769 ucast.opcode = ECORE_FILTER_ADD;
770 ucast.type = ECORE_FILTER_MAC;
771 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
772 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
777 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
779 struct qede_dev *qdev = eth_dev->data->dev_private;
780 struct ecore_dev *edev = &qdev->edev;
781 struct ecore_filter_ucast ucast;
783 PMD_INIT_FUNC_TRACE(edev);
785 if (index >= qdev->dev_info.num_mac_filters) {
786 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
787 index, qdev->dev_info.num_mac_filters);
791 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
794 qede_set_ucast_cmn_params(&ucast);
795 ucast.opcode = ECORE_FILTER_REMOVE;
796 ucast.type = ECORE_FILTER_MAC;
798 /* Use the index maintained by rte */
799 rte_ether_addr_copy(ð_dev->data->mac_addrs[index],
800 (struct rte_ether_addr *)&ucast.mac);
802 qede_mac_int_ops(eth_dev, &ucast, false);
806 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
808 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
809 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
811 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
812 mac_addr->addr_bytes)) {
813 DP_ERR(edev, "Setting MAC address is not allowed\n");
817 qede_mac_addr_remove(eth_dev, 0);
819 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
822 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
824 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
825 struct ecore_sp_vport_update_params params;
826 struct ecore_hwfn *p_hwfn;
830 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
832 params.update_accept_any_vlan_flg = 1;
833 params.accept_any_vlan = flg;
834 for_each_hwfn(edev, i) {
835 p_hwfn = &edev->hwfns[i];
836 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
837 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
838 ECORE_SPQ_MODE_EBLOCK, NULL);
839 if (rc != ECORE_SUCCESS) {
840 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
845 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
848 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
850 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
851 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
852 struct ecore_sp_vport_update_params params;
853 struct ecore_hwfn *p_hwfn;
857 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
859 params.update_inner_vlan_removal_flg = 1;
860 params.inner_vlan_removal_flg = flg;
861 for_each_hwfn(edev, i) {
862 p_hwfn = &edev->hwfns[i];
863 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
864 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
865 ECORE_SPQ_MODE_EBLOCK, NULL);
866 if (rc != ECORE_SUCCESS) {
867 DP_ERR(edev, "Failed to update vport\n");
872 qdev->vlan_strip_flg = flg;
874 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
878 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
879 uint16_t vlan_id, int on)
881 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
882 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
883 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
884 struct qede_vlan_entry *tmp = NULL;
885 struct qede_vlan_entry *vlan;
886 struct ecore_filter_ucast ucast;
890 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
891 DP_ERR(edev, "Reached max VLAN filter limit"
892 " enabling accept_any_vlan\n");
893 qede_config_accept_any_vlan(qdev, true);
897 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
898 if (tmp->vid == vlan_id) {
899 DP_INFO(edev, "VLAN %u already configured\n",
905 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
906 RTE_CACHE_LINE_SIZE);
909 DP_ERR(edev, "Did not allocate memory for VLAN\n");
913 qede_set_ucast_cmn_params(&ucast);
914 ucast.opcode = ECORE_FILTER_ADD;
915 ucast.type = ECORE_FILTER_VLAN;
916 ucast.vlan = vlan_id;
917 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
920 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
925 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
926 qdev->configured_vlans++;
927 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
928 vlan_id, qdev->configured_vlans);
931 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
932 if (tmp->vid == vlan_id)
937 if (qdev->configured_vlans == 0) {
939 "No VLAN filters configured yet\n");
943 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
947 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
949 qede_set_ucast_cmn_params(&ucast);
950 ucast.opcode = ECORE_FILTER_REMOVE;
951 ucast.type = ECORE_FILTER_VLAN;
952 ucast.vlan = vlan_id;
953 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
956 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
959 qdev->configured_vlans--;
960 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
961 vlan_id, qdev->configured_vlans);
968 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
970 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
971 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
972 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
974 if (mask & ETH_VLAN_STRIP_MASK) {
975 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
976 (void)qede_vlan_stripping(eth_dev, 1);
978 (void)qede_vlan_stripping(eth_dev, 0);
981 if (mask & ETH_VLAN_FILTER_MASK) {
982 /* VLAN filtering kicks in when a VLAN is added */
983 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
984 qede_vlan_filter_set(eth_dev, 0, 1);
986 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
988 " Please remove existing VLAN filters"
989 " before disabling VLAN filtering\n");
990 /* Signal app that VLAN filtering is still
993 eth_dev->data->dev_conf.rxmode.offloads |=
994 DEV_RX_OFFLOAD_VLAN_FILTER;
996 qede_vlan_filter_set(eth_dev, 0, 0);
1001 if (mask & ETH_VLAN_EXTEND_MASK)
1002 DP_ERR(edev, "Extend VLAN not supported\n");
1004 qdev->vlan_offload_mask = mask;
1006 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1011 static void qede_prandom_bytes(uint32_t *buff)
1015 srand((unsigned int)time(NULL));
1016 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1020 int qede_config_rss(struct rte_eth_dev *eth_dev)
1022 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1023 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1024 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1025 struct rte_eth_rss_reta_entry64 reta_conf[2];
1026 struct rte_eth_rss_conf rss_conf;
1027 uint32_t i, id, pos, q;
1029 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1030 if (!rss_conf.rss_key) {
1031 DP_INFO(edev, "Applying driver default key\n");
1032 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1033 qede_prandom_bytes(&def_rss_key[0]);
1034 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1037 /* Configure RSS hash */
1038 if (qede_rss_hash_update(eth_dev, &rss_conf))
1041 /* Configure default RETA */
1042 memset(reta_conf, 0, sizeof(reta_conf));
1043 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1044 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1046 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1047 id = i / RTE_RETA_GROUP_SIZE;
1048 pos = i % RTE_RETA_GROUP_SIZE;
1049 q = i % QEDE_RSS_COUNT(eth_dev);
1050 reta_conf[id].reta[pos] = q;
1052 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1053 ECORE_RSS_IND_TABLE_SIZE))
1059 static void qede_fastpath_start(struct ecore_dev *edev)
1061 struct ecore_hwfn *p_hwfn;
1064 for_each_hwfn(edev, i) {
1065 p_hwfn = &edev->hwfns[i];
1066 ecore_hw_start_fastpath(p_hwfn);
1070 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1072 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1073 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1074 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1076 PMD_INIT_FUNC_TRACE(edev);
1078 /* Update MTU only if it has changed */
1079 if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1080 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1082 qdev->mtu = qdev->new_mtu;
1086 /* Configure TPA parameters */
1087 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1088 if (qede_enable_tpa(eth_dev, true))
1090 /* Enable scatter mode for LRO */
1091 if (!eth_dev->data->scattered_rx)
1092 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1096 if (qede_start_queues(eth_dev))
1100 qede_reset_queue_stats(qdev, true);
1102 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1103 * enabling RSS. Hence RSS configuration is deferred upto this point.
1104 * Also, we would like to retain similar behavior in PF case, so we
1105 * don't do PF/VF specific check here.
1107 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1108 if (qede_config_rss(eth_dev))
1112 if (qede_activate_vport(eth_dev, true))
1115 /* Update link status */
1116 qede_link_update(eth_dev, 0);
1118 /* Start/resume traffic */
1119 qede_fastpath_start(edev);
1121 qede_assign_rxtx_handlers(eth_dev);
1122 DP_INFO(edev, "Device started\n");
1126 DP_ERR(edev, "Device start fails\n");
1127 return -1; /* common error code is < 0 */
1130 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1132 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1133 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1135 PMD_INIT_FUNC_TRACE(edev);
1138 if (qede_activate_vport(eth_dev, false))
1141 if (qdev->enable_lro)
1142 qede_enable_tpa(eth_dev, false);
1145 qede_stop_queues(eth_dev);
1147 /* Disable traffic */
1148 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1150 DP_INFO(edev, "Device is stopped\n");
1153 static const char * const valid_args[] = {
1154 QEDE_NPAR_TX_SWITCHING,
1155 QEDE_VF_TX_SWITCHING,
1159 static int qede_args_check(const char *key, const char *val, void *opaque)
1163 struct rte_eth_dev *eth_dev = opaque;
1164 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1165 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1168 tmp = strtoul(val, NULL, 0);
1170 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1174 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1175 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1176 qdev->enable_tx_switching = !!tmp;
1177 DP_INFO(edev, "Disabling %s tx-switching\n",
1178 strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1185 static int qede_args(struct rte_eth_dev *eth_dev)
1187 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1188 struct rte_kvargs *kvlist;
1189 struct rte_devargs *devargs;
1193 devargs = pci_dev->device.devargs;
1195 return 0; /* return success */
1197 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1201 /* Process parameters. */
1202 for (i = 0; (valid_args[i] != NULL); ++i) {
1203 if (rte_kvargs_count(kvlist, valid_args[i])) {
1204 ret = rte_kvargs_process(kvlist, valid_args[i],
1205 qede_args_check, eth_dev);
1206 if (ret != ECORE_SUCCESS) {
1207 rte_kvargs_free(kvlist);
1212 rte_kvargs_free(kvlist);
1217 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1219 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1220 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1221 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1224 PMD_INIT_FUNC_TRACE(edev);
1226 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1227 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1229 /* We need to have min 1 RX queue.There is no min check in
1230 * rte_eth_dev_configure(), so we are checking it here.
1232 if (eth_dev->data->nb_rx_queues == 0) {
1233 DP_ERR(edev, "Minimum one RX queue is required\n");
1237 /* Enable Tx switching by default */
1238 qdev->enable_tx_switching = 1;
1240 /* Parse devargs and fix up rxmode */
1241 if (qede_args(eth_dev))
1242 DP_NOTICE(edev, false,
1243 "Invalid devargs supplied, requested change will not take effect\n");
1245 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1246 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1247 DP_ERR(edev, "Unsupported multi-queue mode\n");
1250 /* Flow director mode check */
1251 if (qede_check_fdir_support(eth_dev))
1254 qede_dealloc_fp_resc(eth_dev);
1255 qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1256 qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1258 if (qede_alloc_fp_resc(qdev))
1261 /* If jumbo enabled adjust MTU */
1262 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1263 eth_dev->data->mtu =
1264 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1265 RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1267 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1268 eth_dev->data->scattered_rx = 1;
1270 if (qede_start_vport(qdev, eth_dev->data->mtu))
1273 qdev->mtu = eth_dev->data->mtu;
1275 /* Enable VLAN offloads by default */
1276 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1277 ETH_VLAN_FILTER_MASK);
1281 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1282 QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1284 if (ECORE_IS_CMT(edev))
1285 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1286 qdev->num_rx_queues, qdev->num_tx_queues);
1292 /* Info about HW descriptor ring limitations */
1293 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1294 .nb_max = 0x8000, /* 32K */
1296 .nb_align = 128 /* lowest common multiple */
1299 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1300 .nb_max = 0x8000, /* 32K */
1303 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1304 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1308 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1309 struct rte_eth_dev_info *dev_info)
1311 struct qede_dev *qdev = eth_dev->data->dev_private;
1312 struct ecore_dev *edev = &qdev->edev;
1313 struct qed_link_output link;
1314 uint32_t speed_cap = 0;
1316 PMD_INIT_FUNC_TRACE(edev);
1318 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1319 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1320 dev_info->rx_desc_lim = qede_rx_desc_lim;
1321 dev_info->tx_desc_lim = qede_tx_desc_lim;
1324 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1325 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1327 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1328 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1329 /* Since CMT mode internally doubles the number of queues */
1330 if (ECORE_IS_CMT(edev))
1331 dev_info->max_rx_queues = dev_info->max_rx_queues / 2;
1333 dev_info->max_tx_queues = dev_info->max_rx_queues;
1335 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1336 dev_info->max_vfs = 0;
1337 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1338 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1339 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1340 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1341 DEV_RX_OFFLOAD_UDP_CKSUM |
1342 DEV_RX_OFFLOAD_TCP_CKSUM |
1343 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1344 DEV_RX_OFFLOAD_TCP_LRO |
1345 DEV_RX_OFFLOAD_KEEP_CRC |
1346 DEV_RX_OFFLOAD_SCATTER |
1347 DEV_RX_OFFLOAD_JUMBO_FRAME |
1348 DEV_RX_OFFLOAD_VLAN_FILTER |
1349 DEV_RX_OFFLOAD_VLAN_STRIP |
1350 DEV_RX_OFFLOAD_RSS_HASH);
1351 dev_info->rx_queue_offload_capa = 0;
1353 /* TX offloads are on a per-packet basis, so it is applicable
1354 * to both at port and queue levels.
1356 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1357 DEV_TX_OFFLOAD_IPV4_CKSUM |
1358 DEV_TX_OFFLOAD_UDP_CKSUM |
1359 DEV_TX_OFFLOAD_TCP_CKSUM |
1360 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1361 DEV_TX_OFFLOAD_MULTI_SEGS |
1362 DEV_TX_OFFLOAD_TCP_TSO |
1363 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1364 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1365 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1367 dev_info->default_txconf = (struct rte_eth_txconf) {
1368 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1371 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1372 /* Packets are always dropped if no descriptors are available */
1377 memset(&link, 0, sizeof(struct qed_link_output));
1378 qdev->ops->common->get_link(edev, &link);
1379 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1380 speed_cap |= ETH_LINK_SPEED_1G;
1381 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1382 speed_cap |= ETH_LINK_SPEED_10G;
1383 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1384 speed_cap |= ETH_LINK_SPEED_25G;
1385 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1386 speed_cap |= ETH_LINK_SPEED_40G;
1387 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1388 speed_cap |= ETH_LINK_SPEED_50G;
1389 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1390 speed_cap |= ETH_LINK_SPEED_100G;
1391 dev_info->speed_capa = speed_cap;
1396 /* return 0 means link status changed, -1 means not changed */
1398 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1400 struct qede_dev *qdev = eth_dev->data->dev_private;
1401 struct ecore_dev *edev = &qdev->edev;
1402 struct qed_link_output q_link;
1403 struct rte_eth_link link;
1404 uint16_t link_duplex;
1406 memset(&q_link, 0, sizeof(q_link));
1407 memset(&link, 0, sizeof(link));
1409 qdev->ops->common->get_link(edev, &q_link);
1412 link.link_speed = q_link.speed;
1415 switch (q_link.duplex) {
1416 case QEDE_DUPLEX_HALF:
1417 link_duplex = ETH_LINK_HALF_DUPLEX;
1419 case QEDE_DUPLEX_FULL:
1420 link_duplex = ETH_LINK_FULL_DUPLEX;
1422 case QEDE_DUPLEX_UNKNOWN:
1426 link.link_duplex = link_duplex;
1429 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1432 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1433 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1435 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1436 link.link_speed, link.link_duplex,
1437 link.link_autoneg, link.link_status);
1439 return rte_eth_linkstatus_set(eth_dev, &link);
1442 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1444 struct qede_dev *qdev = eth_dev->data->dev_private;
1445 struct ecore_dev *edev = &qdev->edev;
1446 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1447 enum _ecore_status_t ecore_status;
1449 PMD_INIT_FUNC_TRACE(edev);
1451 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1452 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1454 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1456 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1459 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1461 struct qede_dev *qdev = eth_dev->data->dev_private;
1462 struct ecore_dev *edev = &qdev->edev;
1463 enum _ecore_status_t ecore_status;
1465 PMD_INIT_FUNC_TRACE(edev);
1467 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1468 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1469 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1471 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1472 QED_FILTER_RX_MODE_TYPE_REGULAR);
1474 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1477 static void qede_poll_sp_sb_cb(void *param)
1479 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1480 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1481 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1484 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1485 qede_interrupt_action(&edev->hwfns[1]);
1487 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1491 DP_ERR(edev, "Unable to start periodic"
1492 " timer rc %d\n", rc);
1496 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1498 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1499 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1500 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1502 PMD_INIT_FUNC_TRACE(edev);
1504 /* dev_stop() shall cleanup fp resources in hw but without releasing
1505 * dma memories and sw structures so that dev_start() can be called
1506 * by the app without reconfiguration. However, in dev_close() we
1507 * can release all the resources and device can be brought up newly
1509 if (eth_dev->data->dev_started)
1510 qede_dev_stop(eth_dev);
1512 qede_stop_vport(edev);
1513 qdev->vport_started = false;
1514 qede_fdir_dealloc_resc(eth_dev);
1515 qede_dealloc_fp_resc(eth_dev);
1517 eth_dev->data->nb_rx_queues = 0;
1518 eth_dev->data->nb_tx_queues = 0;
1520 /* Bring the link down */
1521 qede_dev_set_link_state(eth_dev, false);
1522 qdev->ops->common->slowpath_stop(edev);
1523 qdev->ops->common->remove(edev);
1524 rte_intr_disable(&pci_dev->intr_handle);
1526 switch (pci_dev->intr_handle.type) {
1527 case RTE_INTR_HANDLE_UIO_INTX:
1528 case RTE_INTR_HANDLE_VFIO_LEGACY:
1529 rte_intr_callback_unregister(&pci_dev->intr_handle,
1530 qede_interrupt_handler_intx,
1534 rte_intr_callback_unregister(&pci_dev->intr_handle,
1535 qede_interrupt_handler,
1539 if (ECORE_IS_CMT(edev))
1540 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1544 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1546 struct qede_dev *qdev = eth_dev->data->dev_private;
1547 struct ecore_dev *edev = &qdev->edev;
1548 struct ecore_eth_stats stats;
1549 unsigned int i = 0, j = 0, qid, idx, hw_fn;
1550 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1551 struct qede_tx_queue *txq;
1553 ecore_get_vport_stats(edev, &stats);
1556 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1557 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1559 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1560 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1562 eth_stats->ierrors = stats.common.rx_crc_errors +
1563 stats.common.rx_align_errors +
1564 stats.common.rx_carrier_errors +
1565 stats.common.rx_oversize_packets +
1566 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1568 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1570 eth_stats->imissed = stats.common.mftag_filter_discards +
1571 stats.common.mac_filter_discards +
1572 stats.common.no_buff_discards +
1573 stats.common.brb_truncates + stats.common.brb_discards;
1576 eth_stats->opackets = stats.common.tx_ucast_pkts +
1577 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1579 eth_stats->obytes = stats.common.tx_ucast_bytes +
1580 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1582 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1585 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1586 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1587 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1588 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1589 if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1590 txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1591 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1592 "Not all the queue stats will be displayed. Set"
1593 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1594 " appropriately and retry.\n");
1596 for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1597 eth_stats->q_ipackets[i] = 0;
1598 eth_stats->q_errors[i] = 0;
1600 for_each_hwfn(edev, hw_fn) {
1601 idx = qid * edev->num_hwfns + hw_fn;
1603 eth_stats->q_ipackets[i] +=
1605 (((char *)(qdev->fp_array[idx].rxq)) +
1606 offsetof(struct qede_rx_queue,
1608 eth_stats->q_errors[i] +=
1610 (((char *)(qdev->fp_array[idx].rxq)) +
1611 offsetof(struct qede_rx_queue,
1614 (((char *)(qdev->fp_array[idx].rxq)) +
1615 offsetof(struct qede_rx_queue,
1620 if (i == rxq_stat_cntrs)
1624 for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1625 eth_stats->q_opackets[j] = 0;
1627 for_each_hwfn(edev, hw_fn) {
1628 idx = qid * edev->num_hwfns + hw_fn;
1630 txq = qdev->fp_array[idx].txq;
1631 eth_stats->q_opackets[j] +=
1632 *((uint64_t *)(uintptr_t)
1633 (((uint64_t)(uintptr_t)(txq)) +
1634 offsetof(struct qede_tx_queue,
1639 if (j == txq_stat_cntrs)
1647 qede_get_xstats_count(struct qede_dev *qdev) {
1648 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1650 if (ECORE_IS_BB(&qdev->edev))
1651 return RTE_DIM(qede_xstats_strings) +
1652 RTE_DIM(qede_bb_xstats_strings) +
1653 (RTE_DIM(qede_rxq_xstats_strings) *
1654 QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1656 return RTE_DIM(qede_xstats_strings) +
1657 RTE_DIM(qede_ah_xstats_strings) +
1658 (RTE_DIM(qede_rxq_xstats_strings) *
1659 QEDE_RSS_COUNT(dev));
1663 qede_get_xstats_names(struct rte_eth_dev *dev,
1664 struct rte_eth_xstat_name *xstats_names,
1665 __rte_unused unsigned int limit)
1667 struct qede_dev *qdev = dev->data->dev_private;
1668 struct ecore_dev *edev = &qdev->edev;
1669 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1670 unsigned int i, qid, hw_fn, stat_idx = 0;
1672 if (xstats_names == NULL)
1675 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1676 strlcpy(xstats_names[stat_idx].name,
1677 qede_xstats_strings[i].name,
1678 sizeof(xstats_names[stat_idx].name));
1682 if (ECORE_IS_BB(edev)) {
1683 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1684 strlcpy(xstats_names[stat_idx].name,
1685 qede_bb_xstats_strings[i].name,
1686 sizeof(xstats_names[stat_idx].name));
1690 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1691 strlcpy(xstats_names[stat_idx].name,
1692 qede_ah_xstats_strings[i].name,
1693 sizeof(xstats_names[stat_idx].name));
1698 for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1699 for_each_hwfn(edev, hw_fn) {
1700 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1701 snprintf(xstats_names[stat_idx].name,
1702 RTE_ETH_XSTATS_NAME_SIZE,
1704 qede_rxq_xstats_strings[i].name,
1706 qede_rxq_xstats_strings[i].name + 4);
1716 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1719 struct qede_dev *qdev = dev->data->dev_private;
1720 struct ecore_dev *edev = &qdev->edev;
1721 struct ecore_eth_stats stats;
1722 const unsigned int num = qede_get_xstats_count(qdev);
1723 unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1728 ecore_get_vport_stats(edev, &stats);
1730 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1731 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1732 qede_xstats_strings[i].offset);
1733 xstats[stat_idx].id = stat_idx;
1737 if (ECORE_IS_BB(edev)) {
1738 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1739 xstats[stat_idx].value =
1740 *(uint64_t *)(((char *)&stats) +
1741 qede_bb_xstats_strings[i].offset);
1742 xstats[stat_idx].id = stat_idx;
1746 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1747 xstats[stat_idx].value =
1748 *(uint64_t *)(((char *)&stats) +
1749 qede_ah_xstats_strings[i].offset);
1750 xstats[stat_idx].id = stat_idx;
1755 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1756 for_each_hwfn(edev, hw_fn) {
1757 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1758 fpidx = qid * edev->num_hwfns + hw_fn;
1759 xstats[stat_idx].value = *(uint64_t *)
1760 (((char *)(qdev->fp_array[fpidx].rxq)) +
1761 qede_rxq_xstats_strings[i].offset);
1762 xstats[stat_idx].id = stat_idx;
1773 qede_reset_xstats(struct rte_eth_dev *dev)
1775 struct qede_dev *qdev = dev->data->dev_private;
1776 struct ecore_dev *edev = &qdev->edev;
1778 ecore_reset_vport_stats(edev);
1779 qede_reset_queue_stats(qdev, true);
1784 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1786 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1787 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1788 struct qed_link_params link_params;
1791 DP_INFO(edev, "setting link state %d\n", link_up);
1792 memset(&link_params, 0, sizeof(link_params));
1793 link_params.link_up = link_up;
1794 rc = qdev->ops->common->set_link(edev, &link_params);
1795 if (rc != ECORE_SUCCESS)
1796 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1801 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1803 return qede_dev_set_link_state(eth_dev, true);
1806 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1808 return qede_dev_set_link_state(eth_dev, false);
1811 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1813 struct qede_dev *qdev = eth_dev->data->dev_private;
1814 struct ecore_dev *edev = &qdev->edev;
1816 ecore_reset_vport_stats(edev);
1817 qede_reset_queue_stats(qdev, false);
1822 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1824 enum qed_filter_rx_mode_type type =
1825 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1826 enum _ecore_status_t ecore_status;
1828 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1829 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1831 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1833 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1836 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1838 enum _ecore_status_t ecore_status;
1840 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1841 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1842 QED_FILTER_RX_MODE_TYPE_PROMISC);
1844 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1845 QED_FILTER_RX_MODE_TYPE_REGULAR);
1847 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1851 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1852 struct rte_ether_addr *mc_addrs,
1853 uint32_t mc_addrs_num)
1855 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1856 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1859 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1860 DP_ERR(edev, "Reached max multicast filters limit,"
1861 "Please enable multicast promisc mode\n");
1865 for (i = 0; i < mc_addrs_num; i++) {
1866 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1867 DP_ERR(edev, "Not a valid multicast MAC\n");
1872 /* Flush all existing entries */
1873 if (qede_del_mcast_filters(eth_dev))
1876 /* Set new mcast list */
1877 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1880 /* Update MTU via vport-update without doing port restart.
1881 * The vport must be deactivated before calling this API.
1883 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1885 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1886 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1887 struct ecore_hwfn *p_hwfn;
1892 struct ecore_sp_vport_update_params params;
1894 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1895 params.vport_id = 0;
1897 params.vport_id = 0;
1898 for_each_hwfn(edev, i) {
1899 p_hwfn = &edev->hwfns[i];
1900 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1901 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1902 ECORE_SPQ_MODE_EBLOCK, NULL);
1903 if (rc != ECORE_SUCCESS)
1907 for_each_hwfn(edev, i) {
1908 p_hwfn = &edev->hwfns[i];
1909 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1910 if (rc == ECORE_INVAL) {
1911 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1912 /* Recreate vport */
1913 rc = qede_start_vport(qdev, mtu);
1914 if (rc != ECORE_SUCCESS)
1917 /* Restore config lost due to vport stop */
1918 if (eth_dev->data->promiscuous)
1919 qede_promiscuous_enable(eth_dev);
1921 qede_promiscuous_disable(eth_dev);
1923 if (eth_dev->data->all_multicast)
1924 qede_allmulticast_enable(eth_dev);
1926 qede_allmulticast_disable(eth_dev);
1928 qede_vlan_offload_set(eth_dev,
1929 qdev->vlan_offload_mask);
1930 } else if (rc != ECORE_SUCCESS) {
1935 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1940 DP_ERR(edev, "Failed to update MTU\n");
1944 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1945 struct rte_eth_fc_conf *fc_conf)
1947 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1948 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1949 struct qed_link_output current_link;
1950 struct qed_link_params params;
1952 memset(¤t_link, 0, sizeof(current_link));
1953 qdev->ops->common->get_link(edev, ¤t_link);
1955 memset(¶ms, 0, sizeof(params));
1956 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1957 if (fc_conf->autoneg) {
1958 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1959 DP_ERR(edev, "Autoneg not supported\n");
1962 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1965 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1966 if (fc_conf->mode == RTE_FC_FULL)
1967 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1968 QED_LINK_PAUSE_RX_ENABLE);
1969 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1970 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1971 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1972 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1974 params.link_up = true;
1975 (void)qdev->ops->common->set_link(edev, ¶ms);
1980 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1981 struct rte_eth_fc_conf *fc_conf)
1983 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1984 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1985 struct qed_link_output current_link;
1987 memset(¤t_link, 0, sizeof(current_link));
1988 qdev->ops->common->get_link(edev, ¤t_link);
1990 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1991 fc_conf->autoneg = true;
1993 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1994 QED_LINK_PAUSE_TX_ENABLE))
1995 fc_conf->mode = RTE_FC_FULL;
1996 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1997 fc_conf->mode = RTE_FC_RX_PAUSE;
1998 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1999 fc_conf->mode = RTE_FC_TX_PAUSE;
2001 fc_conf->mode = RTE_FC_NONE;
2006 static const uint32_t *
2007 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2009 static const uint32_t ptypes[] = {
2011 RTE_PTYPE_L2_ETHER_VLAN,
2016 RTE_PTYPE_TUNNEL_VXLAN,
2018 RTE_PTYPE_TUNNEL_GENEVE,
2019 RTE_PTYPE_TUNNEL_GRE,
2021 RTE_PTYPE_INNER_L2_ETHER,
2022 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2023 RTE_PTYPE_INNER_L3_IPV4,
2024 RTE_PTYPE_INNER_L3_IPV6,
2025 RTE_PTYPE_INNER_L4_TCP,
2026 RTE_PTYPE_INNER_L4_UDP,
2027 RTE_PTYPE_INNER_L4_FRAG,
2031 if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2032 eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2033 eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2039 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2042 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2043 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2044 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2045 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2046 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2047 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2048 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2049 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2052 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2053 struct rte_eth_rss_conf *rss_conf)
2055 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2056 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2057 struct ecore_sp_vport_update_params vport_update_params;
2058 struct ecore_rss_params rss_params;
2059 struct ecore_hwfn *p_hwfn;
2060 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2061 uint64_t hf = rss_conf->rss_hf;
2062 uint8_t len = rss_conf->rss_key_len;
2063 uint8_t idx, i, j, fpidx;
2066 memset(&vport_update_params, 0, sizeof(vport_update_params));
2067 memset(&rss_params, 0, sizeof(rss_params));
2069 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2070 (unsigned long)hf, len, key);
2074 DP_INFO(edev, "Enabling rss\n");
2077 qede_init_rss_caps(&rss_params.rss_caps, hf);
2078 rss_params.update_rss_capabilities = 1;
2082 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2083 DP_ERR(edev, "RSS key length exceeds limit\n");
2086 DP_INFO(edev, "Applying user supplied hash key\n");
2087 rss_params.update_rss_key = 1;
2088 memcpy(&rss_params.rss_key, key, len);
2090 rss_params.rss_enable = 1;
2093 rss_params.update_rss_config = 1;
2094 /* tbl_size has to be set with capabilities */
2095 rss_params.rss_table_size_log = 7;
2096 vport_update_params.vport_id = 0;
2098 for_each_hwfn(edev, i) {
2099 /* pass the L2 handles instead of qids */
2100 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2101 idx = j % QEDE_RSS_COUNT(eth_dev);
2102 fpidx = idx * edev->num_hwfns + i;
2103 rss_params.rss_ind_table[j] =
2104 qdev->fp_array[fpidx].rxq->handle;
2107 vport_update_params.rss_params = &rss_params;
2109 p_hwfn = &edev->hwfns[i];
2110 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2111 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2112 ECORE_SPQ_MODE_EBLOCK, NULL);
2114 DP_ERR(edev, "vport-update for RSS failed\n");
2118 qdev->rss_enable = rss_params.rss_enable;
2120 /* Update local structure for hash query */
2121 qdev->rss_conf.rss_hf = hf;
2122 qdev->rss_conf.rss_key_len = len;
2123 if (qdev->rss_enable) {
2124 if (qdev->rss_conf.rss_key == NULL) {
2125 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2126 if (qdev->rss_conf.rss_key == NULL) {
2127 DP_ERR(edev, "No memory to store RSS key\n");
2132 DP_INFO(edev, "Storing RSS key\n");
2133 memcpy(qdev->rss_conf.rss_key, key, len);
2135 } else if (!qdev->rss_enable && len == 0) {
2136 if (qdev->rss_conf.rss_key) {
2137 free(qdev->rss_conf.rss_key);
2138 qdev->rss_conf.rss_key = NULL;
2139 DP_INFO(edev, "Free RSS key\n");
2146 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2147 struct rte_eth_rss_conf *rss_conf)
2149 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2151 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2152 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2154 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2155 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2156 rss_conf->rss_key_len);
2160 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2161 struct rte_eth_rss_reta_entry64 *reta_conf,
2164 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2165 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2166 struct ecore_sp_vport_update_params vport_update_params;
2167 struct ecore_rss_params *params;
2168 uint16_t i, j, idx, fid, shift;
2169 struct ecore_hwfn *p_hwfn;
2173 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2174 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2179 memset(&vport_update_params, 0, sizeof(vport_update_params));
2180 params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2181 if (params == NULL) {
2182 DP_ERR(edev, "failed to allocate memory\n");
2186 params->update_rss_ind_table = 1;
2187 params->rss_table_size_log = 7;
2188 params->update_rss_config = 1;
2190 vport_update_params.vport_id = 0;
2191 /* Use the current value of rss_enable */
2192 params->rss_enable = qdev->rss_enable;
2193 vport_update_params.rss_params = params;
2195 for_each_hwfn(edev, i) {
2196 for (j = 0; j < reta_size; j++) {
2197 idx = j / RTE_RETA_GROUP_SIZE;
2198 shift = j % RTE_RETA_GROUP_SIZE;
2199 if (reta_conf[idx].mask & (1ULL << shift)) {
2200 entry = reta_conf[idx].reta[shift];
2201 fid = entry * edev->num_hwfns + i;
2202 /* Pass rxq handles to ecore */
2203 params->rss_ind_table[j] =
2204 qdev->fp_array[fid].rxq->handle;
2205 /* Update the local copy for RETA query cmd */
2206 qdev->rss_ind_table[j] = entry;
2210 p_hwfn = &edev->hwfns[i];
2211 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2212 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2213 ECORE_SPQ_MODE_EBLOCK, NULL);
2215 DP_ERR(edev, "vport-update for RSS failed\n");
2225 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2226 struct rte_eth_rss_reta_entry64 *reta_conf,
2229 struct qede_dev *qdev = eth_dev->data->dev_private;
2230 struct ecore_dev *edev = &qdev->edev;
2231 uint16_t i, idx, shift;
2234 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2235 DP_ERR(edev, "reta_size %d is not supported\n",
2240 for (i = 0; i < reta_size; i++) {
2241 idx = i / RTE_RETA_GROUP_SIZE;
2242 shift = i % RTE_RETA_GROUP_SIZE;
2243 if (reta_conf[idx].mask & (1ULL << shift)) {
2244 entry = qdev->rss_ind_table[i];
2245 reta_conf[idx].reta[shift] = entry;
2254 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2256 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2257 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2258 struct rte_eth_dev_info dev_info = {0};
2259 struct qede_fastpath *fp;
2260 uint32_t max_rx_pkt_len;
2261 uint32_t frame_size;
2263 bool restart = false;
2266 PMD_INIT_FUNC_TRACE(edev);
2267 rc = qede_dev_info_get(dev, &dev_info);
2269 DP_ERR(edev, "Error during getting ethernet device info\n");
2272 max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2273 frame_size = max_rx_pkt_len;
2274 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2275 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2276 mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2280 if (!dev->data->scattered_rx &&
2281 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2282 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2283 dev->data->min_rx_buf_size);
2286 /* Temporarily replace I/O functions with dummy ones. It cannot
2287 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2289 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2290 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2291 if (dev->data->dev_started) {
2292 dev->data->dev_started = 0;
2297 qdev->new_mtu = mtu;
2299 /* Fix up RX buf size for all queues of the port */
2300 for (i = 0; i < qdev->num_rx_queues; i++) {
2301 fp = &qdev->fp_array[i];
2302 if (fp->rxq != NULL) {
2303 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2304 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2305 /* cache align the mbuf size to simplfy rx_buf_size
2308 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2309 rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2313 fp->rxq->rx_buf_size = rc;
2316 if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2317 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2319 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2321 if (!dev->data->dev_started && restart) {
2322 qede_dev_start(dev);
2323 dev->data->dev_started = 1;
2326 /* update max frame size */
2327 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2330 qede_assign_rxtx_handlers(dev);
2331 if (ECORE_IS_CMT(edev)) {
2332 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2333 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2335 dev->rx_pkt_burst = qede_recv_pkts;
2336 dev->tx_pkt_burst = qede_xmit_pkts;
2342 qede_dev_reset(struct rte_eth_dev *dev)
2346 ret = qede_eth_dev_uninit(dev);
2350 return qede_eth_dev_init(dev);
2353 static const struct eth_dev_ops qede_eth_dev_ops = {
2354 .dev_configure = qede_dev_configure,
2355 .dev_infos_get = qede_dev_info_get,
2356 .rx_queue_setup = qede_rx_queue_setup,
2357 .rx_queue_release = qede_rx_queue_release,
2358 .rx_descriptor_status = qede_rx_descriptor_status,
2359 .tx_queue_setup = qede_tx_queue_setup,
2360 .tx_queue_release = qede_tx_queue_release,
2361 .dev_start = qede_dev_start,
2362 .dev_reset = qede_dev_reset,
2363 .dev_set_link_up = qede_dev_set_link_up,
2364 .dev_set_link_down = qede_dev_set_link_down,
2365 .link_update = qede_link_update,
2366 .promiscuous_enable = qede_promiscuous_enable,
2367 .promiscuous_disable = qede_promiscuous_disable,
2368 .allmulticast_enable = qede_allmulticast_enable,
2369 .allmulticast_disable = qede_allmulticast_disable,
2370 .set_mc_addr_list = qede_set_mc_addr_list,
2371 .dev_stop = qede_dev_stop,
2372 .dev_close = qede_dev_close,
2373 .stats_get = qede_get_stats,
2374 .stats_reset = qede_reset_stats,
2375 .xstats_get = qede_get_xstats,
2376 .xstats_reset = qede_reset_xstats,
2377 .xstats_get_names = qede_get_xstats_names,
2378 .mac_addr_add = qede_mac_addr_add,
2379 .mac_addr_remove = qede_mac_addr_remove,
2380 .mac_addr_set = qede_mac_addr_set,
2381 .vlan_offload_set = qede_vlan_offload_set,
2382 .vlan_filter_set = qede_vlan_filter_set,
2383 .flow_ctrl_set = qede_flow_ctrl_set,
2384 .flow_ctrl_get = qede_flow_ctrl_get,
2385 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2386 .rss_hash_update = qede_rss_hash_update,
2387 .rss_hash_conf_get = qede_rss_hash_conf_get,
2388 .reta_update = qede_rss_reta_update,
2389 .reta_query = qede_rss_reta_query,
2390 .mtu_set = qede_set_mtu,
2391 .filter_ctrl = qede_dev_filter_ctrl,
2392 .udp_tunnel_port_add = qede_udp_dst_port_add,
2393 .udp_tunnel_port_del = qede_udp_dst_port_del,
2396 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2397 .dev_configure = qede_dev_configure,
2398 .dev_infos_get = qede_dev_info_get,
2399 .rx_queue_setup = qede_rx_queue_setup,
2400 .rx_queue_release = qede_rx_queue_release,
2401 .rx_descriptor_status = qede_rx_descriptor_status,
2402 .tx_queue_setup = qede_tx_queue_setup,
2403 .tx_queue_release = qede_tx_queue_release,
2404 .dev_start = qede_dev_start,
2405 .dev_reset = qede_dev_reset,
2406 .dev_set_link_up = qede_dev_set_link_up,
2407 .dev_set_link_down = qede_dev_set_link_down,
2408 .link_update = qede_link_update,
2409 .promiscuous_enable = qede_promiscuous_enable,
2410 .promiscuous_disable = qede_promiscuous_disable,
2411 .allmulticast_enable = qede_allmulticast_enable,
2412 .allmulticast_disable = qede_allmulticast_disable,
2413 .set_mc_addr_list = qede_set_mc_addr_list,
2414 .dev_stop = qede_dev_stop,
2415 .dev_close = qede_dev_close,
2416 .stats_get = qede_get_stats,
2417 .stats_reset = qede_reset_stats,
2418 .xstats_get = qede_get_xstats,
2419 .xstats_reset = qede_reset_xstats,
2420 .xstats_get_names = qede_get_xstats_names,
2421 .vlan_offload_set = qede_vlan_offload_set,
2422 .vlan_filter_set = qede_vlan_filter_set,
2423 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2424 .rss_hash_update = qede_rss_hash_update,
2425 .rss_hash_conf_get = qede_rss_hash_conf_get,
2426 .reta_update = qede_rss_reta_update,
2427 .reta_query = qede_rss_reta_query,
2428 .mtu_set = qede_set_mtu,
2429 .udp_tunnel_port_add = qede_udp_dst_port_add,
2430 .udp_tunnel_port_del = qede_udp_dst_port_del,
2431 .mac_addr_add = qede_mac_addr_add,
2432 .mac_addr_remove = qede_mac_addr_remove,
2433 .mac_addr_set = qede_mac_addr_set,
2436 static void qede_update_pf_params(struct ecore_dev *edev)
2438 struct ecore_pf_params pf_params;
2440 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2441 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2442 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2443 qed_ops->common->update_pf_params(edev, &pf_params);
2446 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2448 struct rte_pci_device *pci_dev;
2449 struct rte_pci_addr pci_addr;
2450 struct qede_dev *adapter;
2451 struct ecore_dev *edev;
2452 struct qed_dev_eth_info dev_info;
2453 struct qed_slowpath_params params;
2454 static bool do_once = true;
2455 uint8_t bulletin_change;
2456 uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2457 uint8_t is_mac_forced;
2459 /* Fix up ecore debug level */
2460 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2461 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2465 /* Extract key data structures */
2466 adapter = eth_dev->data->dev_private;
2467 adapter->ethdev = eth_dev;
2468 edev = &adapter->edev;
2469 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2470 pci_addr = pci_dev->addr;
2472 PMD_INIT_FUNC_TRACE(edev);
2474 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2475 pci_addr.bus, pci_addr.devid, pci_addr.function,
2476 eth_dev->data->port_id);
2478 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2479 DP_ERR(edev, "Skipping device init from secondary process\n");
2483 rte_eth_copy_pci_info(eth_dev, pci_dev);
2486 edev->vendor_id = pci_dev->id.vendor_id;
2487 edev->device_id = pci_dev->id.device_id;
2489 qed_ops = qed_get_eth_ops();
2491 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2496 DP_INFO(edev, "Starting qede probe\n");
2497 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2500 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2504 qede_update_pf_params(edev);
2506 switch (pci_dev->intr_handle.type) {
2507 case RTE_INTR_HANDLE_UIO_INTX:
2508 case RTE_INTR_HANDLE_VFIO_LEGACY:
2509 int_mode = ECORE_INT_MODE_INTA;
2510 rte_intr_callback_register(&pci_dev->intr_handle,
2511 qede_interrupt_handler_intx,
2515 int_mode = ECORE_INT_MODE_MSIX;
2516 rte_intr_callback_register(&pci_dev->intr_handle,
2517 qede_interrupt_handler,
2521 if (rte_intr_enable(&pci_dev->intr_handle)) {
2522 DP_ERR(edev, "rte_intr_enable() failed\n");
2527 /* Start the Slowpath-process */
2528 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2530 params.int_mode = int_mode;
2531 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2532 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2533 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2534 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2535 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2536 QEDE_PMD_DRV_VER_STR_SIZE);
2538 qede_assign_rxtx_handlers(eth_dev);
2539 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2541 /* For CMT mode device do periodic polling for slowpath events.
2542 * This is required since uio device uses only one MSI-x
2543 * interrupt vector but we need one for each engine.
2545 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2546 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2550 DP_ERR(edev, "Unable to start periodic"
2551 " timer rc %d\n", rc);
2557 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2559 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2560 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2566 rc = qed_ops->fill_dev_info(edev, &dev_info);
2568 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2569 qed_ops->common->slowpath_stop(edev);
2570 qed_ops->common->remove(edev);
2571 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2577 qede_alloc_etherdev(adapter, &dev_info);
2580 qede_print_adapter_info(adapter);
2584 adapter->ops->common->set_name(edev, edev->name);
2587 adapter->dev_info.num_mac_filters =
2588 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2591 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2592 (uint32_t *)&adapter->dev_info.num_mac_filters);
2594 /* Allocate memory for storing MAC addr */
2595 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2596 (RTE_ETHER_ADDR_LEN *
2597 adapter->dev_info.num_mac_filters),
2598 RTE_CACHE_LINE_SIZE);
2600 if (eth_dev->data->mac_addrs == NULL) {
2601 DP_ERR(edev, "Failed to allocate MAC address\n");
2602 qed_ops->common->slowpath_stop(edev);
2603 qed_ops->common->remove(edev);
2604 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2610 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2611 hw_info.hw_mac_addr,
2612 ð_dev->data->mac_addrs[0]);
2613 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2614 &adapter->primary_mac);
2616 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2618 if (bulletin_change) {
2620 ecore_vf_bulletin_get_forced_mac(
2621 ECORE_LEADING_HWFN(edev),
2625 DP_INFO(edev, "VF macaddr received from PF\n");
2626 rte_ether_addr_copy(
2627 (struct rte_ether_addr *)&vf_mac,
2628 ð_dev->data->mac_addrs[0]);
2629 rte_ether_addr_copy(
2630 ð_dev->data->mac_addrs[0],
2631 &adapter->primary_mac);
2633 DP_ERR(edev, "No VF macaddr assigned\n");
2638 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2640 /* Bring-up the link */
2641 qede_dev_set_link_state(eth_dev, true);
2643 adapter->num_tx_queues = 0;
2644 adapter->num_rx_queues = 0;
2645 SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2646 SLIST_INIT(&adapter->vlan_list_head);
2647 SLIST_INIT(&adapter->uc_list_head);
2648 SLIST_INIT(&adapter->mc_list_head);
2649 adapter->mtu = RTE_ETHER_MTU;
2650 adapter->vport_started = false;
2652 /* VF tunnel offloads is enabled by default in PF driver */
2653 adapter->vxlan.num_filters = 0;
2654 adapter->geneve.num_filters = 0;
2655 adapter->ipgre.num_filters = 0;
2657 adapter->vxlan.enable = true;
2658 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2659 ETH_TUNNEL_FILTER_IVLAN;
2660 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2661 adapter->geneve.enable = true;
2662 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2663 ETH_TUNNEL_FILTER_IVLAN;
2664 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2665 adapter->ipgre.enable = true;
2666 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2667 ETH_TUNNEL_FILTER_IVLAN;
2669 adapter->vxlan.enable = false;
2670 adapter->geneve.enable = false;
2671 adapter->ipgre.enable = false;
2674 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2675 adapter->primary_mac.addr_bytes[0],
2676 adapter->primary_mac.addr_bytes[1],
2677 adapter->primary_mac.addr_bytes[2],
2678 adapter->primary_mac.addr_bytes[3],
2679 adapter->primary_mac.addr_bytes[4],
2680 adapter->primary_mac.addr_bytes[5]);
2682 DP_INFO(edev, "Device initialized\n");
2688 qede_print_adapter_info(adapter);
2694 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2696 return qede_common_dev_init(eth_dev, 1);
2699 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2701 return qede_common_dev_init(eth_dev, 0);
2704 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2706 struct qede_dev *qdev = eth_dev->data->dev_private;
2707 struct ecore_dev *edev = &qdev->edev;
2709 PMD_INIT_FUNC_TRACE(edev);
2711 /* only uninitialize in the primary process */
2712 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2715 /* safe to close dev here */
2716 qede_dev_close(eth_dev);
2718 eth_dev->dev_ops = NULL;
2719 eth_dev->rx_pkt_burst = NULL;
2720 eth_dev->tx_pkt_burst = NULL;
2725 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2727 return qede_dev_common_uninit(eth_dev);
2730 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2732 return qede_dev_common_uninit(eth_dev);
2735 static const struct rte_pci_id pci_id_qedevf_map[] = {
2736 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2738 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2741 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2744 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2749 static const struct rte_pci_id pci_id_qede_map[] = {
2750 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2752 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2755 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2758 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2761 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2764 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2767 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2770 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2773 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2776 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2779 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2784 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2785 struct rte_pci_device *pci_dev)
2787 return rte_eth_dev_pci_generic_probe(pci_dev,
2788 sizeof(struct qede_dev), qedevf_eth_dev_init);
2791 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2793 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2796 static struct rte_pci_driver rte_qedevf_pmd = {
2797 .id_table = pci_id_qedevf_map,
2798 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2799 .probe = qedevf_eth_dev_pci_probe,
2800 .remove = qedevf_eth_dev_pci_remove,
2803 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2804 struct rte_pci_device *pci_dev)
2806 return rte_eth_dev_pci_generic_probe(pci_dev,
2807 sizeof(struct qede_dev), qede_eth_dev_init);
2810 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2812 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2815 static struct rte_pci_driver rte_qede_pmd = {
2816 .id_table = pci_id_qede_map,
2817 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2818 .probe = qede_eth_dev_pci_probe,
2819 .remove = qede_eth_dev_pci_remove,
2822 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2823 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2824 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2825 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2826 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2827 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2829 RTE_INIT(qede_init_log)
2831 qede_logtype_init = rte_log_register("pmd.net.qede.init");
2832 if (qede_logtype_init >= 0)
2833 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2834 qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2835 if (qede_logtype_driver >= 0)
2836 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);