drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 236 {
 237         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 238 }
 239
 240 static void
 241 qede_interrupt_handler_intx(void *param)
 242 {
 243         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 244         struct qede_dev *qdev = eth_dev->data->dev_private;
 245         struct ecore_dev *edev = &qdev->edev;
 246         u64 status;
 247
 248         /* Check if our device actually raised an interrupt */
 249         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 250         if (status & 0x1) {
 251                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 252
 253                 if (rte_intr_ack(eth_dev->intr_handle))
 254                         DP_ERR(edev, "rte_intr_ack failed\n");
 255         }
 256 }
 257
 258 static void
 259 qede_interrupt_handler(void *param)
 260 {
 261         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 262         struct qede_dev *qdev = eth_dev->data->dev_private;
 263         struct ecore_dev *edev = &qdev->edev;
 264
 265         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 266         if (rte_intr_ack(eth_dev->intr_handle))
 267                 DP_ERR(edev, "rte_intr_ack failed\n");
 268 }
 269
 270 static void
 271 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 272 {
 273         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 274         qdev->ops = qed_ops;
 275 }
 276
 277 static void qede_print_adapter_info(struct qede_dev *qdev)
 278 {
 279         struct ecore_dev *edev = &qdev->edev;
 280         struct qed_dev_info *info = &qdev->dev_info.common;
 281         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 282
 283         DP_INFO(edev, "**************************************************\n");
 284         DP_INFO(edev, " DPDK version\t\t\t: %s\n", rte_version());
 285         DP_INFO(edev, " Chip details\t\t\t: %s %c%d\n",
 286                   ECORE_IS_BB(edev) ? "BB" : "AH",
 287                   'A' + edev->chip_rev,
 288                   (int)edev->chip_metal);
 289         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 290                  QEDE_PMD_DRV_VERSION);
 291         DP_INFO(edev, " Driver version\t\t\t: %s\n", ver_str);
 292
 293         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 294                  QEDE_PMD_BASE_VERSION);
 295         DP_INFO(edev, " Base version\t\t\t: %s\n", ver_str);
 296
 297         if (!IS_VF(edev))
 298                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 299                          QEDE_PMD_FW_VERSION);
 300         else
 301                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 302                          info->fw_major, info->fw_minor,
 303                          info->fw_rev, info->fw_eng);
 304         DP_INFO(edev, " Firmware version\t\t\t: %s\n", ver_str);
 305
 306         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 307                  "%d.%d.%d.%d",
 308                  (info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
 309                  QED_MFW_VERSION_3_OFFSET,
 310                  (info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
 311                  QED_MFW_VERSION_2_OFFSET,
 312                  (info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
 313                  QED_MFW_VERSION_1_OFFSET,
 314                  (info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
 315                  QED_MFW_VERSION_0_OFFSET);
 316         DP_INFO(edev, " Management Firmware version\t: %s\n", ver_str);
 317         DP_INFO(edev, " Firmware file\t\t\t: %s\n", qede_fw_file);
 318         DP_INFO(edev, "**************************************************\n");
 319 }
 320
 321 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 322 {
 323         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 324         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 325         unsigned int i = 0, j = 0, qid;
 326         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 327         struct qede_tx_queue *txq;
 328
 329         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 330
 331         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 332                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 333         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 334                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 335
 336         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 337                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 338                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 339                             sizeof(uint64_t));
 340                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 341                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 342                             sizeof(uint64_t));
 343                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 344                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 345                             sizeof(uint64_t));
 346
 347                 if (xstats)
 348                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 349                                 OSAL_MEMSET((((char *)
 350                                               (qdev->fp_array[qid].rxq)) +
 351                                              qede_rxq_xstats_strings[j].offset),
 352                                             0,
 353                                             sizeof(uint64_t));
 354
 355                 i++;
 356                 if (i == rxq_stat_cntrs)
 357                         break;
 358         }
 359
 360         i = 0;
 361
 362         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 363                 txq = qdev->fp_array[qid].txq;
 364
 365                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 366                                 (((uint64_t)(uintptr_t)(txq)) +
 367                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 368                             sizeof(uint64_t));
 369
 370                 i++;
 371                 if (i == txq_stat_cntrs)
 372                         break;
 373         }
 374 }
 375
 376 static int
 377 qede_stop_vport(struct ecore_dev *edev)
 378 {
 379         struct ecore_hwfn *p_hwfn;
 380         uint8_t vport_id;
 381         int rc;
 382         int i;
 383
 384         vport_id = 0;
 385         for_each_hwfn(edev, i) {
 386                 p_hwfn = &edev->hwfns[i];
 387                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 388                                          vport_id);
 389                 if (rc != ECORE_SUCCESS) {
 390                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 391                         return rc;
 392                 }
 393         }
 394
 395         DP_INFO(edev, "vport stopped\n");
 396
 397         return 0;
 398 }
 399
 400 static int
 401 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 402 {
 403         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 404         struct ecore_sp_vport_start_params params;
 405         struct ecore_hwfn *p_hwfn;
 406         int rc;
 407         int i;
 408
 409         if (qdev->vport_started)
 410                 qede_stop_vport(edev);
 411
 412         memset(&params, 0, sizeof(params));
 413         params.vport_id = 0;
 414         params.mtu = mtu;
 415         /* @DPDK - Disable FW placement */
 416         params.zero_placement_offset = 1;
 417         for_each_hwfn(edev, i) {
 418                 p_hwfn = &edev->hwfns[i];
 419                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 420                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 421                 rc = ecore_sp_vport_start(p_hwfn, &params);
 422                 if (rc != ECORE_SUCCESS) {
 423                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 424                         return rc;
 425                 }
 426         }
 427         ecore_reset_vport_stats(edev);
 428         qdev->vport_started = true;
 429         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 430
 431         return 0;
 432 }
 433
 434 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 435 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 436
 437 /* Activate or deactivate vport via vport-update */
 438 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 439 {
 440         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 441         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 442         struct ecore_sp_vport_update_params params;
 443         struct ecore_hwfn *p_hwfn;
 444         uint8_t i;
 445         int rc = -1;
 446
 447         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 448         params.vport_id = 0;
 449         params.update_vport_active_rx_flg = 1;
 450         params.update_vport_active_tx_flg = 1;
 451         params.vport_active_rx_flg = flg;
 452         params.vport_active_tx_flg = flg;
 453         if (~qdev->enable_tx_switching & flg) {
 454                 params.update_tx_switching_flg = 1;
 455                 params.tx_switching_flg = !flg;
 456         }
 457         for_each_hwfn(edev, i) {
 458                 p_hwfn = &edev->hwfns[i];
 459                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 460                 rc = ecore_sp_vport_update(p_hwfn, &params,
 461                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 462                 if (rc != ECORE_SUCCESS) {
 463                         DP_ERR(edev, "Failed to update vport\n");
 464                         break;
 465                 }
 466         }
 467         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 468
 469         return rc;
 470 }
 471
 472 static void
 473 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 474                            uint16_t mtu, bool enable)
 475 {
 476         /* Enable LRO in split mode */
 477         sge_tpa_params->tpa_ipv4_en_flg = enable;
 478         sge_tpa_params->tpa_ipv6_en_flg = enable;
 479         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 480         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 481         /* set if tpa enable changes */
 482         sge_tpa_params->update_tpa_en_flg = 1;
 483         /* set if tpa parameters should be handled */
 484         sge_tpa_params->update_tpa_param_flg = enable;
 485
 486         sge_tpa_params->max_buffers_per_cqe = 20;
 487         /* Enable TPA in split mode. In this mode each TPA segment
 488          * starts on the new BD, so there is one BD per segment.
 489          */
 490         sge_tpa_params->tpa_pkt_split_flg = 1;
 491         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 492         sge_tpa_params->tpa_gro_consistent_flg = 0;
 493         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 494         sge_tpa_params->tpa_max_size = 0x7FFF;
 495         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 496         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 497 }
 498
 499 /* Enable/disable LRO via vport-update */
 500 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 501 {
 502         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 503         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 504         struct ecore_sp_vport_update_params params;
 505         struct ecore_sge_tpa_params tpa_params;
 506         struct ecore_hwfn *p_hwfn;
 507         int rc;
 508         int i;
 509
 510         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 511         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 512         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 513         params.vport_id = 0;
 514         params.sge_tpa_params = &tpa_params;
 515         for_each_hwfn(edev, i) {
 516                 p_hwfn = &edev->hwfns[i];
 517                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 518                 rc = ecore_sp_vport_update(p_hwfn, &params,
 519                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 520                 if (rc != ECORE_SUCCESS) {
 521                         DP_ERR(edev, "Failed to update LRO\n");
 522                         return -1;
 523                 }
 524         }
 525         qdev->enable_lro = flg;
 526         eth_dev->data->lro = flg;
 527
 528         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 529
 530         return 0;
 531 }
 532
 533 static int
 534 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 535                              enum qed_filter_rx_mode_type type)
 536 {
 537         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 538         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 539         struct ecore_filter_accept_flags flags;
 540
 541         memset(&flags, 0, sizeof(flags));
 542
 543         flags.update_rx_mode_config = 1;
 544         flags.update_tx_mode_config = 1;
 545         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 546                 ECORE_ACCEPT_MCAST_MATCHED |
 547                 ECORE_ACCEPT_BCAST;
 548
 549         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 550                 ECORE_ACCEPT_MCAST_MATCHED |
 551                 ECORE_ACCEPT_BCAST;
 552
 553         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 554                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 555                 if (IS_VF(edev)) {
 556                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 557                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 558                 }
 559         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 560                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 561         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 562                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 563                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 564                         ECORE_ACCEPT_MCAST_UNMATCHED;
 565         }
 566
 567         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 568                         ECORE_SPQ_MODE_CB, NULL);
 569 }
 570
 571 int
 572 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 573                   bool add)
 574 {
 575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 577         struct qede_ucast_entry *tmp = NULL;
 578         struct qede_ucast_entry *u;
 579         struct rte_ether_addr *mac_addr;
 580
 581         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 582         if (add) {
 583                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 584                         if ((memcmp(mac_addr, &tmp->mac,
 585                                     RTE_ETHER_ADDR_LEN) == 0) &&
 586                              ucast->vni == tmp->vni &&
 587                              ucast->vlan == tmp->vlan) {
 588                                 DP_INFO(edev, "Unicast MAC is already added"
 589                                         " with vlan = %u, vni = %u\n",
 590                                         ucast->vlan,  ucast->vni);
 591                                         return 0;
 592                         }
 593                 }
 594                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 595                                RTE_CACHE_LINE_SIZE);
 596                 if (!u) {
 597                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 598                         return -ENOMEM;
 599                 }
 600                 rte_ether_addr_copy(mac_addr, &u->mac);
 601                 u->vlan = ucast->vlan;
 602                 u->vni = ucast->vni;
 603                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 604                 qdev->num_uc_addr++;
 605         } else {
 606                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 607                         if ((memcmp(mac_addr, &tmp->mac,
 608                                     RTE_ETHER_ADDR_LEN) == 0) &&
 609                             ucast->vlan == tmp->vlan      &&
 610                             ucast->vni == tmp->vni)
 611                         break;
 612                 }
 613                 if (tmp == NULL) {
 614                         DP_INFO(edev, "Unicast MAC is not found\n");
 615                         return -EINVAL;
 616                 }
 617                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 618                 qdev->num_uc_addr--;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int
 625 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 626                 struct rte_ether_addr *mc_addrs,
 627                 uint32_t mc_addrs_num)
 628 {
 629         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 630         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 631         struct ecore_filter_mcast mcast;
 632         struct qede_mcast_entry *m = NULL;
 633         uint8_t i;
 634         int rc;
 635
 636         for (i = 0; i < mc_addrs_num; i++) {
 637                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 638                                RTE_CACHE_LINE_SIZE);
 639                 if (!m) {
 640                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 641                         return -ENOMEM;
 642                 }
 643                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 644                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 645         }
 646         memset(&mcast, 0, sizeof(mcast));
 647         mcast.num_mc_addrs = mc_addrs_num;
 648         mcast.opcode = ECORE_FILTER_ADD;
 649         for (i = 0; i < mc_addrs_num; i++)
 650                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 651                                                         &mcast.mac[i]);
 652         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 653         if (rc != ECORE_SUCCESS) {
 654                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 655                 return -1;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 662 {
 663         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 664         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 665         struct qede_mcast_entry *tmp = NULL;
 666         struct ecore_filter_mcast mcast;
 667         int j;
 668         int rc;
 669
 670         memset(&mcast, 0, sizeof(mcast));
 671         mcast.num_mc_addrs = qdev->num_mc_addr;
 672         mcast.opcode = ECORE_FILTER_REMOVE;
 673         j = 0;
 674         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 675                 rte_ether_addr_copy(&tmp->mac,
 676                                 (struct rte_ether_addr *)&mcast.mac[j]);
 677                 j++;
 678         }
 679         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 680         if (rc != ECORE_SUCCESS) {
 681                 DP_ERR(edev, "Failed to delete multicast filter\n");
 682                 return -1;
 683         }
 684         /* Init the list */
 685         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 686                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 687                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 688         }
 689         SLIST_INIT(&qdev->mc_list_head);
 690
 691         return 0;
 692 }
 693
 694 enum _ecore_status_t
 695 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 696                  bool add)
 697 {
 698         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 699         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 700         enum _ecore_status_t rc = ECORE_INVAL;
 701
 702         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 703                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 704                               " Please enable promisc mode\n");
 705                         return ECORE_INVAL;
 706         }
 707
 708         rc = qede_ucast_filter(eth_dev, ucast, add);
 709         if (rc == 0)
 710                 rc = ecore_filter_ucast_cmd(edev, ucast,
 711                                             ECORE_SPQ_MODE_CB, NULL);
 712         /* Indicate error only for add filter operation.
 713          * Delete filter operations are not severe.
 714          */
 715         if ((rc != ECORE_SUCCESS) && add)
 716                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 717                        rc, add);
 718
 719         return rc;
 720 }
 721
 722 static int
 723 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 724                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 725 {
 726         struct ecore_filter_ucast ucast;
 727         int re;
 728
 729         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 730                 return -EINVAL;
 731
 732         qede_set_ucast_cmn_params(&ucast);
 733         ucast.opcode = ECORE_FILTER_ADD;
 734         ucast.type = ECORE_FILTER_MAC;
 735         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 736         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 737         return re;
 738 }
 739
 740 static void
 741 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 742 {
 743         struct qede_dev *qdev = eth_dev->data->dev_private;
 744         struct ecore_dev *edev = &qdev->edev;
 745         struct ecore_filter_ucast ucast;
 746
 747         PMD_INIT_FUNC_TRACE(edev);
 748
 749         if (index >= qdev->dev_info.num_mac_filters) {
 750                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 751                        index, qdev->dev_info.num_mac_filters);
 752                 return;
 753         }
 754
 755         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 756                 return;
 757
 758         qede_set_ucast_cmn_params(&ucast);
 759         ucast.opcode = ECORE_FILTER_REMOVE;
 760         ucast.type = ECORE_FILTER_MAC;
 761
 762         /* Use the index maintained by rte */
 763         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 764                         (struct rte_ether_addr *)&ucast.mac);
 765
 766         qede_mac_int_ops(eth_dev, &ucast, false);
 767 }
 768
 769 static int
 770 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 771 {
 772         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 773         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 774
 775         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 776                                                mac_addr->addr_bytes)) {
 777                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 778                 return -EPERM;
 779         }
 780
 781         qede_mac_addr_remove(eth_dev, 0);
 782
 783         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 784 }
 785
 786 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 787 {
 788         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 789         struct ecore_sp_vport_update_params params;
 790         struct ecore_hwfn *p_hwfn;
 791         uint8_t i;
 792         int rc;
 793
 794         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 795         params.vport_id = 0;
 796         params.update_accept_any_vlan_flg = 1;
 797         params.accept_any_vlan = flg;
 798         for_each_hwfn(edev, i) {
 799                 p_hwfn = &edev->hwfns[i];
 800                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 801                 rc = ecore_sp_vport_update(p_hwfn, &params,
 802                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 803                 if (rc != ECORE_SUCCESS) {
 804                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 805                         return;
 806                 }
 807         }
 808
 809         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 810 }
 811
 812 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 813 {
 814         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 815         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 816         struct ecore_sp_vport_update_params params;
 817         struct ecore_hwfn *p_hwfn;
 818         uint8_t i;
 819         int rc;
 820
 821         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 822         params.vport_id = 0;
 823         params.update_inner_vlan_removal_flg = 1;
 824         params.inner_vlan_removal_flg = flg;
 825         for_each_hwfn(edev, i) {
 826                 p_hwfn = &edev->hwfns[i];
 827                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 828                 rc = ecore_sp_vport_update(p_hwfn, &params,
 829                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 830                 if (rc != ECORE_SUCCESS) {
 831                         DP_ERR(edev, "Failed to update vport\n");
 832                         return -1;
 833                 }
 834         }
 835
 836         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 837         return 0;
 838 }
 839
 840 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 841                                 uint16_t vlan_id, int on)
 842 {
 843         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 844         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 845         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 846         struct qede_vlan_entry *tmp = NULL;
 847         struct qede_vlan_entry *vlan;
 848         struct ecore_filter_ucast ucast;
 849         int rc;
 850
 851         if (on) {
 852                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 853                         DP_ERR(edev, "Reached max VLAN filter limit"
 854                                       " enabling accept_any_vlan\n");
 855                         qede_config_accept_any_vlan(qdev, true);
 856                         return 0;
 857                 }
 858
 859                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 860                         if (tmp->vid == vlan_id) {
 861                                 DP_INFO(edev, "VLAN %u already configured\n",
 862                                         vlan_id);
 863                                 return 0;
 864                         }
 865                 }
 866
 867                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 868                                   RTE_CACHE_LINE_SIZE);
 869
 870                 if (!vlan) {
 871                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 872                         return -ENOMEM;
 873                 }
 874
 875                 qede_set_ucast_cmn_params(&ucast);
 876                 ucast.opcode = ECORE_FILTER_ADD;
 877                 ucast.type = ECORE_FILTER_VLAN;
 878                 ucast.vlan = vlan_id;
 879                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 880                                             NULL);
 881                 if (rc != 0) {
 882                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 883                                rc);
 884                         rte_free(vlan);
 885                 } else {
 886                         vlan->vid = vlan_id;
 887                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 888                         qdev->configured_vlans++;
 889                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 890                                 vlan_id, qdev->configured_vlans);
 891                 }
 892         } else {
 893                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 894                         if (tmp->vid == vlan_id)
 895                                 break;
 896                 }
 897
 898                 if (!tmp) {
 899                         if (qdev->configured_vlans == 0) {
 900                                 DP_INFO(edev,
 901                                         "No VLAN filters configured yet\n");
 902                                 return 0;
 903                         }
 904
 905                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 906                         return -EINVAL;
 907                 }
 908
 909                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 910
 911                 qede_set_ucast_cmn_params(&ucast);
 912                 ucast.opcode = ECORE_FILTER_REMOVE;
 913                 ucast.type = ECORE_FILTER_VLAN;
 914                 ucast.vlan = vlan_id;
 915                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 916                                             NULL);
 917                 if (rc != 0) {
 918                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 919                                vlan_id, rc);
 920                 } else {
 921                         qdev->configured_vlans--;
 922                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 923                                 vlan_id, qdev->configured_vlans);
 924                 }
 925         }
 926
 927         return rc;
 928 }
 929
 930 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 931 {
 932         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 933         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 934         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 935
 936         if (mask & ETH_VLAN_STRIP_MASK) {
 937                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 938                         (void)qede_vlan_stripping(eth_dev, 1);
 939                 else
 940                         (void)qede_vlan_stripping(eth_dev, 0);
 941         }
 942
 943         if (mask & ETH_VLAN_FILTER_MASK) {
 944                 /* VLAN filtering kicks in when a VLAN is added */
 945                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 946                         qede_vlan_filter_set(eth_dev, 0, 1);
 947                 } else {
 948                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 949                                 DP_ERR(edev,
 950                                   " Please remove existing VLAN filters"
 951                                   " before disabling VLAN filtering\n");
 952                                 /* Signal app that VLAN filtering is still
 953                                  * enabled
 954                                  */
 955                                 eth_dev->data->dev_conf.rxmode.offloads |=
 956                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 957                         } else {
 958                                 qede_vlan_filter_set(eth_dev, 0, 0);
 959                         }
 960                 }
 961         }
 962
 963         if (mask & ETH_VLAN_EXTEND_MASK)
 964                 DP_ERR(edev, "Extend VLAN not supported\n");
 965
 966         qdev->vlan_offload_mask = mask;
 967
 968         DP_INFO(edev, "VLAN offload mask %d\n", mask);
 969
 970         return 0;
 971 }
 972
 973 static void qede_prandom_bytes(uint32_t *buff)
 974 {
 975         uint8_t i;
 976
 977         srand((unsigned int)time(NULL));
 978         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 979                 buff[i] = rand();
 980 }
 981
 982 int qede_config_rss(struct rte_eth_dev *eth_dev)
 983 {
 984         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 985         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 986         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 987         struct rte_eth_rss_reta_entry64 reta_conf[2];
 988         struct rte_eth_rss_conf rss_conf;
 989         uint32_t i, id, pos, q;
 990
 991         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 992         if (!rss_conf.rss_key) {
 993                 DP_INFO(edev, "Applying driver default key\n");
 994                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 995                 qede_prandom_bytes(&def_rss_key[0]);
 996                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 997         }
 998
 999         /* Configure RSS hash */
1000         if (qede_rss_hash_update(eth_dev, &rss_conf))
1001                 return -EINVAL;
1002
1003         /* Configure default RETA */
1004         memset(reta_conf, 0, sizeof(reta_conf));
1005         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1006                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1007
1008         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1009                 id = i / RTE_RETA_GROUP_SIZE;
1010                 pos = i % RTE_RETA_GROUP_SIZE;
1011                 q = i % QEDE_RSS_COUNT(eth_dev);
1012                 reta_conf[id].reta[pos] = q;
1013         }
1014         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1015                                  ECORE_RSS_IND_TABLE_SIZE))
1016                 return -EINVAL;
1017
1018         return 0;
1019 }
1020
1021 static void qede_fastpath_start(struct ecore_dev *edev)
1022 {
1023         struct ecore_hwfn *p_hwfn;
1024         int i;
1025
1026         for_each_hwfn(edev, i) {
1027                 p_hwfn = &edev->hwfns[i];
1028                 ecore_hw_start_fastpath(p_hwfn);
1029         }
1030 }
1031
1032 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1033 {
1034         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1035         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1036         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1037
1038         PMD_INIT_FUNC_TRACE(edev);
1039
1040         /* Update MTU only if it has changed */
1041         if (eth_dev->data->mtu != qdev->mtu) {
1042                 if (qede_update_mtu(eth_dev, qdev->mtu))
1043                         goto err;
1044         }
1045
1046         /* Configure TPA parameters */
1047         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1048                 if (qede_enable_tpa(eth_dev, true))
1049                         return -EINVAL;
1050                 /* Enable scatter mode for LRO */
1051                 if (!eth_dev->data->scattered_rx)
1052                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1053         }
1054
1055         /* Start queues */
1056         if (qede_start_queues(eth_dev))
1057                 goto err;
1058
1059         if (IS_PF(edev))
1060                 qede_reset_queue_stats(qdev, true);
1061
1062         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1063          * enabling RSS. Hence RSS configuration is deferred upto this point.
1064          * Also, we would like to retain similar behavior in PF case, so we
1065          * don't do PF/VF specific check here.
1066          */
1067         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1068                 if (qede_config_rss(eth_dev))
1069                         goto err;
1070
1071         /* Enable vport*/
1072         if (qede_activate_vport(eth_dev, true))
1073                 goto err;
1074
1075         /* Update link status */
1076         qede_link_update(eth_dev, 0);
1077
1078         /* Start/resume traffic */
1079         qede_fastpath_start(edev);
1080
1081         DP_INFO(edev, "Device started\n");
1082
1083         return 0;
1084 err:
1085         DP_ERR(edev, "Device start fails\n");
1086         return -1; /* common error code is < 0 */
1087 }
1088
1089 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1090 {
1091         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1092         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1093
1094         PMD_INIT_FUNC_TRACE(edev);
1095
1096         /* Disable vport */
1097         if (qede_activate_vport(eth_dev, false))
1098                 return;
1099
1100         if (qdev->enable_lro)
1101                 qede_enable_tpa(eth_dev, false);
1102
1103         /* Stop queues */
1104         qede_stop_queues(eth_dev);
1105
1106         /* Disable traffic */
1107         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1108
1109         DP_INFO(edev, "Device is stopped\n");
1110 }
1111
1112 static const char * const valid_args[] = {
1113         QEDE_NPAR_TX_SWITCHING,
1114         QEDE_VF_TX_SWITCHING,
1115         NULL,
1116 };
1117
1118 static int qede_args_check(const char *key, const char *val, void *opaque)
1119 {
1120         unsigned long tmp;
1121         int ret = 0;
1122         struct rte_eth_dev *eth_dev = opaque;
1123         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1124         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1125
1126         errno = 0;
1127         tmp = strtoul(val, NULL, 0);
1128         if (errno) {
1129                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1130                 return errno;
1131         }
1132
1133         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1134             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1135                 qdev->enable_tx_switching = !!tmp;
1136                 DP_INFO(edev, "Disabling %s tx-switching\n",
1137                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1138                         "VF" : "NPAR");
1139         }
1140
1141         return ret;
1142 }
1143
1144 static int qede_args(struct rte_eth_dev *eth_dev)
1145 {
1146         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1147         struct rte_kvargs *kvlist;
1148         struct rte_devargs *devargs;
1149         int ret;
1150         int i;
1151
1152         devargs = pci_dev->device.devargs;
1153         if (!devargs)
1154                 return 0; /* return success */
1155
1156         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1157         if (kvlist == NULL)
1158                 return -EINVAL;
1159
1160          /* Process parameters. */
1161         for (i = 0; (valid_args[i] != NULL); ++i) {
1162                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1163                         ret = rte_kvargs_process(kvlist, valid_args[i],
1164                                                  qede_args_check, eth_dev);
1165                         if (ret != ECORE_SUCCESS) {
1166                                 rte_kvargs_free(kvlist);
1167                                 return ret;
1168                         }
1169                 }
1170         }
1171         rte_kvargs_free(kvlist);
1172
1173         return 0;
1174 }
1175
1176 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1177 {
1178         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1179         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1180         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1181         int ret;
1182
1183         PMD_INIT_FUNC_TRACE(edev);
1184
1185         /* We need to have min 1 RX queue.There is no min check in
1186          * rte_eth_dev_configure(), so we are checking it here.
1187          */
1188         if (eth_dev->data->nb_rx_queues == 0) {
1189                 DP_ERR(edev, "Minimum one RX queue is required\n");
1190                 return -EINVAL;
1191         }
1192
1193         /* Enable Tx switching by default */
1194         qdev->enable_tx_switching = 1;
1195
1196         /* Parse devargs and fix up rxmode */
1197         if (qede_args(eth_dev))
1198                 DP_NOTICE(edev, false,
1199                           "Invalid devargs supplied, requested change will not take effect\n");
1200
1201         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1202               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1203                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1204                 return -ENOTSUP;
1205         }
1206         /* Flow director mode check */
1207         if (qede_check_fdir_support(eth_dev))
1208                 return -ENOTSUP;
1209
1210         qede_dealloc_fp_resc(eth_dev);
1211         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1212         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1213
1214         if (qede_alloc_fp_resc(qdev))
1215                 return -ENOMEM;
1216
1217         /* If jumbo enabled adjust MTU */
1218         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1219                 eth_dev->data->mtu =
1220                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1221                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1222
1223         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1224                 eth_dev->data->scattered_rx = 1;
1225
1226         if (qede_start_vport(qdev, eth_dev->data->mtu))
1227                 return -1;
1228
1229         qdev->mtu = eth_dev->data->mtu;
1230
1231         /* Enable VLAN offloads by default */
1232         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1233                                              ETH_VLAN_FILTER_MASK);
1234         if (ret)
1235                 return ret;
1236
1237         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1238                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1239
1240         if (ECORE_IS_CMT(edev))
1241                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1242                         qdev->num_rx_queues, qdev->num_tx_queues);
1243
1244
1245         return 0;
1246 }
1247
1248 /* Info about HW descriptor ring limitations */
1249 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1250         .nb_max = 0x8000, /* 32K */
1251         .nb_min = 128,
1252         .nb_align = 128 /* lowest common multiple */
1253 };
1254
1255 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1256         .nb_max = 0x8000, /* 32K */
1257         .nb_min = 256,
1258         .nb_align = 256,
1259         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1260         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1261 };
1262
1263 static int
1264 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1265                   struct rte_eth_dev_info *dev_info)
1266 {
1267         struct qede_dev *qdev = eth_dev->data->dev_private;
1268         struct ecore_dev *edev = &qdev->edev;
1269         struct qed_link_output link;
1270         uint32_t speed_cap = 0;
1271
1272         PMD_INIT_FUNC_TRACE(edev);
1273
1274         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1275         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1276         dev_info->rx_desc_lim = qede_rx_desc_lim;
1277         dev_info->tx_desc_lim = qede_tx_desc_lim;
1278
1279         if (IS_PF(edev))
1280                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1281                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1282         else
1283                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1284                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1285         /* Since CMT mode internally doubles the number of queues */
1286         if (ECORE_IS_CMT(edev))
1287                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1288
1289         dev_info->max_tx_queues = dev_info->max_rx_queues;
1290
1291         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1292         dev_info->max_vfs = 0;
1293         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1294         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1295         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1296         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1297                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1298                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1299                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1300                                      DEV_RX_OFFLOAD_TCP_LRO     |
1301                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1302                                      DEV_RX_OFFLOAD_SCATTER     |
1303                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1304                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1305                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1306         dev_info->rx_queue_offload_capa = 0;
1307
1308         /* TX offloads are on a per-packet basis, so it is applicable
1309          * to both at port and queue levels.
1310          */
1311         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1312                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1313                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1314                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1315                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1316                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1317                                      DEV_TX_OFFLOAD_TCP_TSO     |
1318                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1319                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1320         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1321
1322         dev_info->default_txconf = (struct rte_eth_txconf) {
1323                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1324         };
1325
1326         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1327                 /* Packets are always dropped if no descriptors are available */
1328                 .rx_drop_en = 1,
1329                 .offloads = 0,
1330         };
1331
1332         memset(&link, 0, sizeof(struct qed_link_output));
1333         qdev->ops->common->get_link(edev, &link);
1334         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1335                 speed_cap |= ETH_LINK_SPEED_1G;
1336         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1337                 speed_cap |= ETH_LINK_SPEED_10G;
1338         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1339                 speed_cap |= ETH_LINK_SPEED_25G;
1340         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1341                 speed_cap |= ETH_LINK_SPEED_40G;
1342         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1343                 speed_cap |= ETH_LINK_SPEED_50G;
1344         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1345                 speed_cap |= ETH_LINK_SPEED_100G;
1346         dev_info->speed_capa = speed_cap;
1347
1348         return 0;
1349 }
1350
1351 /* return 0 means link status changed, -1 means not changed */
1352 int
1353 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1354 {
1355         struct qede_dev *qdev = eth_dev->data->dev_private;
1356         struct ecore_dev *edev = &qdev->edev;
1357         struct qed_link_output q_link;
1358         struct rte_eth_link link;
1359         uint16_t link_duplex;
1360
1361         memset(&q_link, 0, sizeof(q_link));
1362         memset(&link, 0, sizeof(link));
1363
1364         qdev->ops->common->get_link(edev, &q_link);
1365
1366         /* Link Speed */
1367         link.link_speed = q_link.speed;
1368
1369         /* Link Mode */
1370         switch (q_link.duplex) {
1371         case QEDE_DUPLEX_HALF:
1372                 link_duplex = ETH_LINK_HALF_DUPLEX;
1373                 break;
1374         case QEDE_DUPLEX_FULL:
1375                 link_duplex = ETH_LINK_FULL_DUPLEX;
1376                 break;
1377         case QEDE_DUPLEX_UNKNOWN:
1378         default:
1379                 link_duplex = -1;
1380         }
1381         link.link_duplex = link_duplex;
1382
1383         /* Link Status */
1384         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1385
1386         /* AN */
1387         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1388                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1389
1390         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1391                 link.link_speed, link.link_duplex,
1392                 link.link_autoneg, link.link_status);
1393
1394         return rte_eth_linkstatus_set(eth_dev, &link);
1395 }
1396
1397 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1398 {
1399         struct qede_dev *qdev = eth_dev->data->dev_private;
1400         struct ecore_dev *edev = &qdev->edev;
1401         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1402         enum _ecore_status_t ecore_status;
1403
1404         PMD_INIT_FUNC_TRACE(edev);
1405
1406         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1407                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1408
1409         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1410
1411         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1412 }
1413
1414 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1415 {
1416         struct qede_dev *qdev = eth_dev->data->dev_private;
1417         struct ecore_dev *edev = &qdev->edev;
1418         enum _ecore_status_t ecore_status;
1419
1420         PMD_INIT_FUNC_TRACE(edev);
1421
1422         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1423                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1424                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1425         else
1426                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1427                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1428
1429         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1430 }
1431
1432 static void qede_poll_sp_sb_cb(void *param)
1433 {
1434         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1435         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1436         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1437         int rc;
1438
1439         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1440         qede_interrupt_action(&edev->hwfns[1]);
1441
1442         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1443                                qede_poll_sp_sb_cb,
1444                                (void *)eth_dev);
1445         if (rc != 0) {
1446                 DP_ERR(edev, "Unable to start periodic"
1447                              " timer rc %d\n", rc);
1448         }
1449 }
1450
1451 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1452 {
1453         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1454         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1455         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1456
1457         PMD_INIT_FUNC_TRACE(edev);
1458
1459         /* dev_stop() shall cleanup fp resources in hw but without releasing
1460          * dma memories and sw structures so that dev_start() can be called
1461          * by the app without reconfiguration. However, in dev_close() we
1462          * can release all the resources and device can be brought up newly
1463          */
1464         if (eth_dev->data->dev_started)
1465                 qede_dev_stop(eth_dev);
1466
1467         qede_stop_vport(edev);
1468         qdev->vport_started = false;
1469         qede_fdir_dealloc_resc(eth_dev);
1470         qede_dealloc_fp_resc(eth_dev);
1471
1472         eth_dev->data->nb_rx_queues = 0;
1473         eth_dev->data->nb_tx_queues = 0;
1474
1475         /* Bring the link down */
1476         qede_dev_set_link_state(eth_dev, false);
1477         qdev->ops->common->slowpath_stop(edev);
1478         qdev->ops->common->remove(edev);
1479         rte_intr_disable(&pci_dev->intr_handle);
1480
1481         switch (pci_dev->intr_handle.type) {
1482         case RTE_INTR_HANDLE_UIO_INTX:
1483         case RTE_INTR_HANDLE_VFIO_LEGACY:
1484                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1485                                              qede_interrupt_handler_intx,
1486                                              (void *)eth_dev);
1487                 break;
1488         default:
1489                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1490                                            qede_interrupt_handler,
1491                                            (void *)eth_dev);
1492         }
1493
1494         if (ECORE_IS_CMT(edev))
1495                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1496 }
1497
1498 static int
1499 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1500 {
1501         struct qede_dev *qdev = eth_dev->data->dev_private;
1502         struct ecore_dev *edev = &qdev->edev;
1503         struct ecore_eth_stats stats;
1504         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1505         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1506         struct qede_tx_queue *txq;
1507
1508         ecore_get_vport_stats(edev, &stats);
1509
1510         /* RX Stats */
1511         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1512             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1513
1514         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1515             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1516
1517         eth_stats->ierrors = stats.common.rx_crc_errors +
1518             stats.common.rx_align_errors +
1519             stats.common.rx_carrier_errors +
1520             stats.common.rx_oversize_packets +
1521             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1522
1523         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1524
1525         eth_stats->imissed = stats.common.mftag_filter_discards +
1526             stats.common.mac_filter_discards +
1527             stats.common.no_buff_discards +
1528             stats.common.brb_truncates + stats.common.brb_discards;
1529
1530         /* TX stats */
1531         eth_stats->opackets = stats.common.tx_ucast_pkts +
1532             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1533
1534         eth_stats->obytes = stats.common.tx_ucast_bytes +
1535             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1536
1537         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1538
1539         /* Queue stats */
1540         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1541                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1542         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1543                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1544         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1545             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1546                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1547                        "Not all the queue stats will be displayed. Set"
1548                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1549                        " appropriately and retry.\n");
1550
1551         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1552                 eth_stats->q_ipackets[i] = 0;
1553                 eth_stats->q_errors[i] = 0;
1554
1555                 for_each_hwfn(edev, hw_fn) {
1556                         idx = qid * edev->num_hwfns + hw_fn;
1557
1558                         eth_stats->q_ipackets[i] +=
1559                                 *(uint64_t *)
1560                                         (((char *)(qdev->fp_array[idx].rxq)) +
1561                                          offsetof(struct qede_rx_queue,
1562                                          rcv_pkts));
1563                         eth_stats->q_errors[i] +=
1564                                 *(uint64_t *)
1565                                         (((char *)(qdev->fp_array[idx].rxq)) +
1566                                          offsetof(struct qede_rx_queue,
1567                                          rx_hw_errors)) +
1568                                 *(uint64_t *)
1569                                         (((char *)(qdev->fp_array[idx].rxq)) +
1570                                          offsetof(struct qede_rx_queue,
1571                                          rx_alloc_errors));
1572                 }
1573
1574                 i++;
1575                 if (i == rxq_stat_cntrs)
1576                         break;
1577         }
1578
1579         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1580                 eth_stats->q_opackets[j] = 0;
1581
1582                 for_each_hwfn(edev, hw_fn) {
1583                         idx = qid * edev->num_hwfns + hw_fn;
1584
1585                         txq = qdev->fp_array[idx].txq;
1586                         eth_stats->q_opackets[j] +=
1587                                 *((uint64_t *)(uintptr_t)
1588                                         (((uint64_t)(uintptr_t)(txq)) +
1589                                          offsetof(struct qede_tx_queue,
1590                                                   xmit_pkts)));
1591                 }
1592
1593                 j++;
1594                 if (j == txq_stat_cntrs)
1595                         break;
1596         }
1597
1598         return 0;
1599 }
1600
1601 static unsigned
1602 qede_get_xstats_count(struct qede_dev *qdev) {
1603         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1604
1605         if (ECORE_IS_BB(&qdev->edev))
1606                 return RTE_DIM(qede_xstats_strings) +
1607                        RTE_DIM(qede_bb_xstats_strings) +
1608                        (RTE_DIM(qede_rxq_xstats_strings) *
1609                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1610         else
1611                 return RTE_DIM(qede_xstats_strings) +
1612                        RTE_DIM(qede_ah_xstats_strings) +
1613                        (RTE_DIM(qede_rxq_xstats_strings) *
1614                         QEDE_RSS_COUNT(dev));
1615 }
1616
1617 static int
1618 qede_get_xstats_names(struct rte_eth_dev *dev,
1619                       struct rte_eth_xstat_name *xstats_names,
1620                       __rte_unused unsigned int limit)
1621 {
1622         struct qede_dev *qdev = dev->data->dev_private;
1623         struct ecore_dev *edev = &qdev->edev;
1624         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1625         unsigned int i, qid, hw_fn, stat_idx = 0;
1626
1627         if (xstats_names == NULL)
1628                 return stat_cnt;
1629
1630         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1631                 strlcpy(xstats_names[stat_idx].name,
1632                         qede_xstats_strings[i].name,
1633                         sizeof(xstats_names[stat_idx].name));
1634                 stat_idx++;
1635         }
1636
1637         if (ECORE_IS_BB(edev)) {
1638                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1639                         strlcpy(xstats_names[stat_idx].name,
1640                                 qede_bb_xstats_strings[i].name,
1641                                 sizeof(xstats_names[stat_idx].name));
1642                         stat_idx++;
1643                 }
1644         } else {
1645                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1646                         strlcpy(xstats_names[stat_idx].name,
1647                                 qede_ah_xstats_strings[i].name,
1648                                 sizeof(xstats_names[stat_idx].name));
1649                         stat_idx++;
1650                 }
1651         }
1652
1653         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1654                 for_each_hwfn(edev, hw_fn) {
1655                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1656                                 snprintf(xstats_names[stat_idx].name,
1657                                          RTE_ETH_XSTATS_NAME_SIZE,
1658                                          "%.4s%d.%d%s",
1659                                          qede_rxq_xstats_strings[i].name,
1660                                          hw_fn, qid,
1661                                          qede_rxq_xstats_strings[i].name + 4);
1662                                 stat_idx++;
1663                         }
1664                 }
1665         }
1666
1667         return stat_cnt;
1668 }
1669
1670 static int
1671 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1672                 unsigned int n)
1673 {
1674         struct qede_dev *qdev = dev->data->dev_private;
1675         struct ecore_dev *edev = &qdev->edev;
1676         struct ecore_eth_stats stats;
1677         const unsigned int num = qede_get_xstats_count(qdev);
1678         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1679
1680         if (n < num)
1681                 return num;
1682
1683         ecore_get_vport_stats(edev, &stats);
1684
1685         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1686                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1687                                              qede_xstats_strings[i].offset);
1688                 xstats[stat_idx].id = stat_idx;
1689                 stat_idx++;
1690         }
1691
1692         if (ECORE_IS_BB(edev)) {
1693                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1694                         xstats[stat_idx].value =
1695                                         *(uint64_t *)(((char *)&stats) +
1696                                         qede_bb_xstats_strings[i].offset);
1697                         xstats[stat_idx].id = stat_idx;
1698                         stat_idx++;
1699                 }
1700         } else {
1701                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1702                         xstats[stat_idx].value =
1703                                         *(uint64_t *)(((char *)&stats) +
1704                                         qede_ah_xstats_strings[i].offset);
1705                         xstats[stat_idx].id = stat_idx;
1706                         stat_idx++;
1707                 }
1708         }
1709
1710         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1711                 for_each_hwfn(edev, hw_fn) {
1712                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1713                                 fpidx = qid * edev->num_hwfns + hw_fn;
1714                                 xstats[stat_idx].value = *(uint64_t *)
1715                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1716                                          qede_rxq_xstats_strings[i].offset);
1717                                 xstats[stat_idx].id = stat_idx;
1718                                 stat_idx++;
1719                         }
1720
1721                 }
1722         }
1723
1724         return stat_idx;
1725 }
1726
1727 static int
1728 qede_reset_xstats(struct rte_eth_dev *dev)
1729 {
1730         struct qede_dev *qdev = dev->data->dev_private;
1731         struct ecore_dev *edev = &qdev->edev;
1732
1733         ecore_reset_vport_stats(edev);
1734         qede_reset_queue_stats(qdev, true);
1735
1736         return 0;
1737 }
1738
1739 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1740 {
1741         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1742         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1743         struct qed_link_params link_params;
1744         int rc;
1745
1746         DP_INFO(edev, "setting link state %d\n", link_up);
1747         memset(&link_params, 0, sizeof(link_params));
1748         link_params.link_up = link_up;
1749         rc = qdev->ops->common->set_link(edev, &link_params);
1750         if (rc != ECORE_SUCCESS)
1751                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1752
1753         return rc;
1754 }
1755
1756 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1757 {
1758         return qede_dev_set_link_state(eth_dev, true);
1759 }
1760
1761 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1762 {
1763         return qede_dev_set_link_state(eth_dev, false);
1764 }
1765
1766 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1767 {
1768         struct qede_dev *qdev = eth_dev->data->dev_private;
1769         struct ecore_dev *edev = &qdev->edev;
1770
1771         ecore_reset_vport_stats(edev);
1772         qede_reset_queue_stats(qdev, false);
1773
1774         return 0;
1775 }
1776
1777 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1778 {
1779         enum qed_filter_rx_mode_type type =
1780             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1781         enum _ecore_status_t ecore_status;
1782
1783         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1784                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1785
1786         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1787
1788         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1789 }
1790
1791 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1792 {
1793         enum _ecore_status_t ecore_status;
1794
1795         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1796                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1797                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1798         else
1799                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1800                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1801
1802         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1803 }
1804
1805 static int
1806 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1807                 struct rte_ether_addr *mc_addrs,
1808                 uint32_t mc_addrs_num)
1809 {
1810         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1811         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1812         uint8_t i;
1813
1814         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1815                 DP_ERR(edev, "Reached max multicast filters limit,"
1816                              "Please enable multicast promisc mode\n");
1817                 return -ENOSPC;
1818         }
1819
1820         for (i = 0; i < mc_addrs_num; i++) {
1821                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1822                         DP_ERR(edev, "Not a valid multicast MAC\n");
1823                         return -EINVAL;
1824                 }
1825         }
1826
1827         /* Flush all existing entries */
1828         if (qede_del_mcast_filters(eth_dev))
1829                 return -1;
1830
1831         /* Set new mcast list */
1832         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1833 }
1834
1835 /* Update MTU via vport-update without doing port restart.
1836  * The vport must be deactivated before calling this API.
1837  */
1838 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1839 {
1840         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1841         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1842         struct ecore_hwfn *p_hwfn;
1843         int rc;
1844         int i;
1845
1846         if (IS_PF(edev)) {
1847                 struct ecore_sp_vport_update_params params;
1848
1849                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1850                 params.vport_id = 0;
1851                 params.mtu = mtu;
1852                 params.vport_id = 0;
1853                 for_each_hwfn(edev, i) {
1854                         p_hwfn = &edev->hwfns[i];
1855                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1856                         rc = ecore_sp_vport_update(p_hwfn, &params,
1857                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1858                         if (rc != ECORE_SUCCESS)
1859                                 goto err;
1860                 }
1861         } else {
1862                 for_each_hwfn(edev, i) {
1863                         p_hwfn = &edev->hwfns[i];
1864                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1865                         if (rc == ECORE_INVAL) {
1866                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1867                                 /* Recreate vport */
1868                                 rc = qede_start_vport(qdev, mtu);
1869                                 if (rc != ECORE_SUCCESS)
1870                                         goto err;
1871
1872                                 /* Restore config lost due to vport stop */
1873                                 if (eth_dev->data->promiscuous)
1874                                         qede_promiscuous_enable(eth_dev);
1875                                 else
1876                                         qede_promiscuous_disable(eth_dev);
1877
1878                                 if (eth_dev->data->all_multicast)
1879                                         qede_allmulticast_enable(eth_dev);
1880                                 else
1881                                         qede_allmulticast_disable(eth_dev);
1882
1883                                 qede_vlan_offload_set(eth_dev,
1884                                                       qdev->vlan_offload_mask);
1885                         } else if (rc != ECORE_SUCCESS) {
1886                                 goto err;
1887                         }
1888                 }
1889         }
1890         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1891
1892         return 0;
1893
1894 err:
1895         DP_ERR(edev, "Failed to update MTU\n");
1896         return -1;
1897 }
1898
1899 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1900                               struct rte_eth_fc_conf *fc_conf)
1901 {
1902         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1903         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1904         struct qed_link_output current_link;
1905         struct qed_link_params params;
1906
1907         memset(&current_link, 0, sizeof(current_link));
1908         qdev->ops->common->get_link(edev, &current_link);
1909
1910         memset(&params, 0, sizeof(params));
1911         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1912         if (fc_conf->autoneg) {
1913                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1914                         DP_ERR(edev, "Autoneg not supported\n");
1915                         return -EINVAL;
1916                 }
1917                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1918         }
1919
1920         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1921         if (fc_conf->mode == RTE_FC_FULL)
1922                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1923                                         QED_LINK_PAUSE_RX_ENABLE);
1924         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1925                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1926         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1927                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1928
1929         params.link_up = true;
1930         (void)qdev->ops->common->set_link(edev, &params);
1931
1932         return 0;
1933 }
1934
1935 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1936                               struct rte_eth_fc_conf *fc_conf)
1937 {
1938         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1939         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1940         struct qed_link_output current_link;
1941
1942         memset(&current_link, 0, sizeof(current_link));
1943         qdev->ops->common->get_link(edev, &current_link);
1944
1945         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1946                 fc_conf->autoneg = true;
1947
1948         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1949                                          QED_LINK_PAUSE_TX_ENABLE))
1950                 fc_conf->mode = RTE_FC_FULL;
1951         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1952                 fc_conf->mode = RTE_FC_RX_PAUSE;
1953         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1954                 fc_conf->mode = RTE_FC_TX_PAUSE;
1955         else
1956                 fc_conf->mode = RTE_FC_NONE;
1957
1958         return 0;
1959 }
1960
1961 static const uint32_t *
1962 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1963 {
1964         static const uint32_t ptypes[] = {
1965                 RTE_PTYPE_L2_ETHER,
1966                 RTE_PTYPE_L2_ETHER_VLAN,
1967                 RTE_PTYPE_L3_IPV4,
1968                 RTE_PTYPE_L3_IPV6,
1969                 RTE_PTYPE_L4_TCP,
1970                 RTE_PTYPE_L4_UDP,
1971                 RTE_PTYPE_TUNNEL_VXLAN,
1972                 RTE_PTYPE_L4_FRAG,
1973                 RTE_PTYPE_TUNNEL_GENEVE,
1974                 RTE_PTYPE_TUNNEL_GRE,
1975                 /* Inner */
1976                 RTE_PTYPE_INNER_L2_ETHER,
1977                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1978                 RTE_PTYPE_INNER_L3_IPV4,
1979                 RTE_PTYPE_INNER_L3_IPV6,
1980                 RTE_PTYPE_INNER_L4_TCP,
1981                 RTE_PTYPE_INNER_L4_UDP,
1982                 RTE_PTYPE_INNER_L4_FRAG,
1983                 RTE_PTYPE_UNKNOWN
1984         };
1985
1986         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
1987             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
1988                 return ptypes;
1989
1990         return NULL;
1991 }
1992
1993 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1994 {
1995         *rss_caps = 0;
1996         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1997         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1998         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1999         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2000         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2001         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2002         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2003         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2004 }
2005
2006 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2007                          struct rte_eth_rss_conf *rss_conf)
2008 {
2009         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2010         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2011         struct ecore_sp_vport_update_params vport_update_params;
2012         struct ecore_rss_params rss_params;
2013         struct ecore_hwfn *p_hwfn;
2014         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2015         uint64_t hf = rss_conf->rss_hf;
2016         uint8_t len = rss_conf->rss_key_len;
2017         uint8_t idx, i, j, fpidx;
2018         int rc;
2019
2020         memset(&vport_update_params, 0, sizeof(vport_update_params));
2021         memset(&rss_params, 0, sizeof(rss_params));
2022
2023         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2024                 (unsigned long)hf, len, key);
2025
2026         if (hf != 0) {
2027                 /* Enabling RSS */
2028                 DP_INFO(edev, "Enabling rss\n");
2029
2030                 /* RSS caps */
2031                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2032                 rss_params.update_rss_capabilities = 1;
2033
2034                 /* RSS hash key */
2035                 if (key) {
2036                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2037                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2038                                 return -EINVAL;
2039                         }
2040                         DP_INFO(edev, "Applying user supplied hash key\n");
2041                         rss_params.update_rss_key = 1;
2042                         memcpy(&rss_params.rss_key, key, len);
2043                 }
2044                 rss_params.rss_enable = 1;
2045         }
2046
2047         rss_params.update_rss_config = 1;
2048         /* tbl_size has to be set with capabilities */
2049         rss_params.rss_table_size_log = 7;
2050         vport_update_params.vport_id = 0;
2051
2052         for_each_hwfn(edev, i) {
2053                 /* pass the L2 handles instead of qids */
2054                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2055                         idx = j % QEDE_RSS_COUNT(eth_dev);
2056                         fpidx = idx * edev->num_hwfns + i;
2057                         rss_params.rss_ind_table[j] =
2058                                 qdev->fp_array[fpidx].rxq->handle;
2059                 }
2060
2061                 vport_update_params.rss_params = &rss_params;
2062
2063                 p_hwfn = &edev->hwfns[i];
2064                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2065                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2066                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2067                 if (rc) {
2068                         DP_ERR(edev, "vport-update for RSS failed\n");
2069                         return rc;
2070                 }
2071         }
2072         qdev->rss_enable = rss_params.rss_enable;
2073
2074         /* Update local structure for hash query */
2075         qdev->rss_conf.rss_hf = hf;
2076         qdev->rss_conf.rss_key_len = len;
2077         if (qdev->rss_enable) {
2078                 if  (qdev->rss_conf.rss_key == NULL) {
2079                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2080                         if (qdev->rss_conf.rss_key == NULL) {
2081                                 DP_ERR(edev, "No memory to store RSS key\n");
2082                                 return -ENOMEM;
2083                         }
2084                 }
2085                 if (key && len) {
2086                         DP_INFO(edev, "Storing RSS key\n");
2087                         memcpy(qdev->rss_conf.rss_key, key, len);
2088                 }
2089         } else if (!qdev->rss_enable && len == 0) {
2090                 if (qdev->rss_conf.rss_key) {
2091                         free(qdev->rss_conf.rss_key);
2092                         qdev->rss_conf.rss_key = NULL;
2093                         DP_INFO(edev, "Free RSS key\n");
2094                 }
2095         }
2096
2097         return 0;
2098 }
2099
2100 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2101                            struct rte_eth_rss_conf *rss_conf)
2102 {
2103         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2104
2105         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2106         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2107
2108         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2109                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2110                        rss_conf->rss_key_len);
2111         return 0;
2112 }
2113
2114 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2115                          struct rte_eth_rss_reta_entry64 *reta_conf,
2116                          uint16_t reta_size)
2117 {
2118         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2119         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2120         struct ecore_sp_vport_update_params vport_update_params;
2121         struct ecore_rss_params *params;
2122         uint16_t i, j, idx, fid, shift;
2123         struct ecore_hwfn *p_hwfn;
2124         uint8_t entry;
2125         int rc = 0;
2126
2127         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2128                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2129                        reta_size);
2130                 return -EINVAL;
2131         }
2132
2133         memset(&vport_update_params, 0, sizeof(vport_update_params));
2134         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2135         if (params == NULL) {
2136                 DP_ERR(edev, "failed to allocate memory\n");
2137                 return -ENOMEM;
2138         }
2139
2140         params->update_rss_ind_table = 1;
2141         params->rss_table_size_log = 7;
2142         params->update_rss_config = 1;
2143
2144         vport_update_params.vport_id = 0;
2145         /* Use the current value of rss_enable */
2146         params->rss_enable = qdev->rss_enable;
2147         vport_update_params.rss_params = params;
2148
2149         for_each_hwfn(edev, i) {
2150                 for (j = 0; j < reta_size; j++) {
2151                         idx = j / RTE_RETA_GROUP_SIZE;
2152                         shift = j % RTE_RETA_GROUP_SIZE;
2153                         if (reta_conf[idx].mask & (1ULL << shift)) {
2154                                 entry = reta_conf[idx].reta[shift];
2155                                 fid = entry * edev->num_hwfns + i;
2156                                 /* Pass rxq handles to ecore */
2157                                 params->rss_ind_table[j] =
2158                                                 qdev->fp_array[fid].rxq->handle;
2159                                 /* Update the local copy for RETA query cmd */
2160                                 qdev->rss_ind_table[j] = entry;
2161                         }
2162                 }
2163
2164                 p_hwfn = &edev->hwfns[i];
2165                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2166                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2167                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2168                 if (rc) {
2169                         DP_ERR(edev, "vport-update for RSS failed\n");
2170                         goto out;
2171                 }
2172         }
2173
2174 out:
2175         rte_free(params);
2176         return rc;
2177 }
2178
2179 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2180                                struct rte_eth_rss_reta_entry64 *reta_conf,
2181                                uint16_t reta_size)
2182 {
2183         struct qede_dev *qdev = eth_dev->data->dev_private;
2184         struct ecore_dev *edev = &qdev->edev;
2185         uint16_t i, idx, shift;
2186         uint8_t entry;
2187
2188         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2189                 DP_ERR(edev, "reta_size %d is not supported\n",
2190                        reta_size);
2191                 return -EINVAL;
2192         }
2193
2194         for (i = 0; i < reta_size; i++) {
2195                 idx = i / RTE_RETA_GROUP_SIZE;
2196                 shift = i % RTE_RETA_GROUP_SIZE;
2197                 if (reta_conf[idx].mask & (1ULL << shift)) {
2198                         entry = qdev->rss_ind_table[i];
2199                         reta_conf[idx].reta[shift] = entry;
2200                 }
2201         }
2202
2203         return 0;
2204 }
2205
2206
2207
2208 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2209 {
2210         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2211         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2212         struct rte_eth_dev_info dev_info = {0};
2213         struct qede_fastpath *fp;
2214         uint32_t max_rx_pkt_len;
2215         uint32_t frame_size;
2216         uint16_t bufsz;
2217         bool restart = false;
2218         int i, rc;
2219
2220         PMD_INIT_FUNC_TRACE(edev);
2221         rc = qede_dev_info_get(dev, &dev_info);
2222         if (rc != 0) {
2223                 DP_ERR(edev, "Error during getting ethernet device info\n");
2224                 return rc;
2225         }
2226         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2227         frame_size = max_rx_pkt_len;
2228         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2229                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2230                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2231                        QEDE_ETH_OVERHEAD);
2232                 return -EINVAL;
2233         }
2234         if (!dev->data->scattered_rx &&
2235             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2236                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2237                         dev->data->min_rx_buf_size);
2238                 return -EINVAL;
2239         }
2240         /* Temporarily replace I/O functions with dummy ones. It cannot
2241          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2242          */
2243         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2244         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2245         if (dev->data->dev_started) {
2246                 dev->data->dev_started = 0;
2247                 qede_dev_stop(dev);
2248                 restart = true;
2249         }
2250         rte_delay_ms(1000);
2251         qdev->mtu = mtu;
2252
2253         /* Fix up RX buf size for all queues of the port */
2254         for (i = 0; i < qdev->num_rx_queues; i++) {
2255                 fp = &qdev->fp_array[i];
2256                 if (fp->rxq != NULL) {
2257                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2258                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2259                         /* cache align the mbuf size to simplfy rx_buf_size
2260                          * calculation
2261                          */
2262                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2263                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2264                         if (rc < 0)
2265                                 return rc;
2266
2267                         fp->rxq->rx_buf_size = rc;
2268                 }
2269         }
2270         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2271                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2272         else
2273                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2274
2275         if (!dev->data->dev_started && restart) {
2276                 qede_dev_start(dev);
2277                 dev->data->dev_started = 1;
2278         }
2279
2280         /* update max frame size */
2281         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2282         /* Reassign back */
2283         if (ECORE_IS_CMT(edev)) {
2284                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2285                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2286         } else {
2287                 dev->rx_pkt_burst = qede_recv_pkts;
2288                 dev->tx_pkt_burst = qede_xmit_pkts;
2289         }
2290         return 0;
2291 }
2292
2293 static int
2294 qede_dev_reset(struct rte_eth_dev *dev)
2295 {
2296         int ret;
2297
2298         ret = qede_eth_dev_uninit(dev);
2299         if (ret)
2300                 return ret;
2301
2302         return qede_eth_dev_init(dev);
2303 }
2304
2305 static const struct eth_dev_ops qede_eth_dev_ops = {
2306         .dev_configure = qede_dev_configure,
2307         .dev_infos_get = qede_dev_info_get,
2308         .rx_queue_setup = qede_rx_queue_setup,
2309         .rx_queue_release = qede_rx_queue_release,
2310         .rx_descriptor_status = qede_rx_descriptor_status,
2311         .tx_queue_setup = qede_tx_queue_setup,
2312         .tx_queue_release = qede_tx_queue_release,
2313         .dev_start = qede_dev_start,
2314         .dev_reset = qede_dev_reset,
2315         .dev_set_link_up = qede_dev_set_link_up,
2316         .dev_set_link_down = qede_dev_set_link_down,
2317         .link_update = qede_link_update,
2318         .promiscuous_enable = qede_promiscuous_enable,
2319         .promiscuous_disable = qede_promiscuous_disable,
2320         .allmulticast_enable = qede_allmulticast_enable,
2321         .allmulticast_disable = qede_allmulticast_disable,
2322         .set_mc_addr_list = qede_set_mc_addr_list,
2323         .dev_stop = qede_dev_stop,
2324         .dev_close = qede_dev_close,
2325         .stats_get = qede_get_stats,
2326         .stats_reset = qede_reset_stats,
2327         .xstats_get = qede_get_xstats,
2328         .xstats_reset = qede_reset_xstats,
2329         .xstats_get_names = qede_get_xstats_names,
2330         .mac_addr_add = qede_mac_addr_add,
2331         .mac_addr_remove = qede_mac_addr_remove,
2332         .mac_addr_set = qede_mac_addr_set,
2333         .vlan_offload_set = qede_vlan_offload_set,
2334         .vlan_filter_set = qede_vlan_filter_set,
2335         .flow_ctrl_set = qede_flow_ctrl_set,
2336         .flow_ctrl_get = qede_flow_ctrl_get,
2337         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2338         .rss_hash_update = qede_rss_hash_update,
2339         .rss_hash_conf_get = qede_rss_hash_conf_get,
2340         .reta_update  = qede_rss_reta_update,
2341         .reta_query  = qede_rss_reta_query,
2342         .mtu_set = qede_set_mtu,
2343         .filter_ctrl = qede_dev_filter_ctrl,
2344         .udp_tunnel_port_add = qede_udp_dst_port_add,
2345         .udp_tunnel_port_del = qede_udp_dst_port_del,
2346 };
2347
2348 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2349         .dev_configure = qede_dev_configure,
2350         .dev_infos_get = qede_dev_info_get,
2351         .rx_queue_setup = qede_rx_queue_setup,
2352         .rx_queue_release = qede_rx_queue_release,
2353         .rx_descriptor_status = qede_rx_descriptor_status,
2354         .tx_queue_setup = qede_tx_queue_setup,
2355         .tx_queue_release = qede_tx_queue_release,
2356         .dev_start = qede_dev_start,
2357         .dev_reset = qede_dev_reset,
2358         .dev_set_link_up = qede_dev_set_link_up,
2359         .dev_set_link_down = qede_dev_set_link_down,
2360         .link_update = qede_link_update,
2361         .promiscuous_enable = qede_promiscuous_enable,
2362         .promiscuous_disable = qede_promiscuous_disable,
2363         .allmulticast_enable = qede_allmulticast_enable,
2364         .allmulticast_disable = qede_allmulticast_disable,
2365         .set_mc_addr_list = qede_set_mc_addr_list,
2366         .dev_stop = qede_dev_stop,
2367         .dev_close = qede_dev_close,
2368         .stats_get = qede_get_stats,
2369         .stats_reset = qede_reset_stats,
2370         .xstats_get = qede_get_xstats,
2371         .xstats_reset = qede_reset_xstats,
2372         .xstats_get_names = qede_get_xstats_names,
2373         .vlan_offload_set = qede_vlan_offload_set,
2374         .vlan_filter_set = qede_vlan_filter_set,
2375         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2376         .rss_hash_update = qede_rss_hash_update,
2377         .rss_hash_conf_get = qede_rss_hash_conf_get,
2378         .reta_update  = qede_rss_reta_update,
2379         .reta_query  = qede_rss_reta_query,
2380         .mtu_set = qede_set_mtu,
2381         .udp_tunnel_port_add = qede_udp_dst_port_add,
2382         .udp_tunnel_port_del = qede_udp_dst_port_del,
2383         .mac_addr_add = qede_mac_addr_add,
2384         .mac_addr_remove = qede_mac_addr_remove,
2385         .mac_addr_set = qede_mac_addr_set,
2386 };
2387
2388 static void qede_update_pf_params(struct ecore_dev *edev)
2389 {
2390         struct ecore_pf_params pf_params;
2391
2392         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2393         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2394         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2395         qed_ops->common->update_pf_params(edev, &pf_params);
2396 }
2397
2398 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2399 {
2400         struct rte_pci_device *pci_dev;
2401         struct rte_pci_addr pci_addr;
2402         struct qede_dev *adapter;
2403         struct ecore_dev *edev;
2404         struct qed_dev_eth_info dev_info;
2405         struct qed_slowpath_params params;
2406         static bool do_once = true;
2407         uint8_t bulletin_change;
2408         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2409         uint8_t is_mac_forced;
2410         bool is_mac_exist;
2411         /* Fix up ecore debug level */
2412         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2413         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2414         uint32_t int_mode;
2415         int rc;
2416
2417         /* Extract key data structures */
2418         adapter = eth_dev->data->dev_private;
2419         adapter->ethdev = eth_dev;
2420         edev = &adapter->edev;
2421         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2422         pci_addr = pci_dev->addr;
2423
2424         PMD_INIT_FUNC_TRACE(edev);
2425
2426         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2427                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2428                  eth_dev->data->port_id);
2429
2430         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2431                 DP_ERR(edev, "Skipping device init from secondary process\n");
2432                 return 0;
2433         }
2434
2435         rte_eth_copy_pci_info(eth_dev, pci_dev);
2436
2437         /* @DPDK */
2438         edev->vendor_id = pci_dev->id.vendor_id;
2439         edev->device_id = pci_dev->id.device_id;
2440
2441         qed_ops = qed_get_eth_ops();
2442         if (!qed_ops) {
2443                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2444                 rc = -EINVAL;
2445                 goto err;
2446         }
2447
2448         DP_INFO(edev, "Starting qede probe\n");
2449         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2450                                     dp_level, is_vf);
2451         if (rc != 0) {
2452                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2453                 rc = -ENODEV;
2454                 goto err;
2455         }
2456         qede_update_pf_params(edev);
2457
2458         switch (pci_dev->intr_handle.type) {
2459         case RTE_INTR_HANDLE_UIO_INTX:
2460         case RTE_INTR_HANDLE_VFIO_LEGACY:
2461                 int_mode = ECORE_INT_MODE_INTA;
2462                 rte_intr_callback_register(&pci_dev->intr_handle,
2463                                            qede_interrupt_handler_intx,
2464                                            (void *)eth_dev);
2465                 break;
2466         default:
2467                 int_mode = ECORE_INT_MODE_MSIX;
2468                 rte_intr_callback_register(&pci_dev->intr_handle,
2469                                            qede_interrupt_handler,
2470                                            (void *)eth_dev);
2471         }
2472
2473         if (rte_intr_enable(&pci_dev->intr_handle)) {
2474                 DP_ERR(edev, "rte_intr_enable() failed\n");
2475                 rc = -ENODEV;
2476                 goto err;
2477         }
2478
2479         /* Start the Slowpath-process */
2480         memset(&params, 0, sizeof(struct qed_slowpath_params));
2481
2482         params.int_mode = int_mode;
2483         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2484         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2485         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2486         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2487         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2488                 QEDE_PMD_DRV_VER_STR_SIZE);
2489
2490         if (ECORE_IS_CMT(edev)) {
2491                 eth_dev->rx_pkt_burst = qede_recv_pkts_cmt;
2492                 eth_dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2493         } else {
2494                 eth_dev->rx_pkt_burst = qede_recv_pkts;
2495                 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2496         }
2497
2498         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2499
2500         /* For CMT mode device do periodic polling for slowpath events.
2501          * This is required since uio device uses only one MSI-x
2502          * interrupt vector but we need one for each engine.
2503          */
2504         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2505                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2506                                        qede_poll_sp_sb_cb,
2507                                        (void *)eth_dev);
2508                 if (rc != 0) {
2509                         DP_ERR(edev, "Unable to start periodic"
2510                                      " timer rc %d\n", rc);
2511                         rc = -EINVAL;
2512                         goto err;
2513                 }
2514         }
2515
2516         rc = qed_ops->common->slowpath_start(edev, &params);
2517         if (rc) {
2518                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2519                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2520                                      (void *)eth_dev);
2521                 rc = -ENODEV;
2522                 goto err;
2523         }
2524
2525         rc = qed_ops->fill_dev_info(edev, &dev_info);
2526         if (rc) {
2527                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2528                 qed_ops->common->slowpath_stop(edev);
2529                 qed_ops->common->remove(edev);
2530                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2531                                      (void *)eth_dev);
2532                 rc = -ENODEV;
2533                 goto err;
2534         }
2535
2536         qede_alloc_etherdev(adapter, &dev_info);
2537
2538         if (do_once) {
2539                 qede_print_adapter_info(adapter);
2540                 do_once = false;
2541         }
2542
2543         adapter->ops->common->set_name(edev, edev->name);
2544
2545         if (!is_vf)
2546                 adapter->dev_info.num_mac_filters =
2547                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2548                                             ECORE_MAC);
2549         else
2550                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2551                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2552
2553         /* Allocate memory for storing MAC addr */
2554         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2555                                         (RTE_ETHER_ADDR_LEN *
2556                                         adapter->dev_info.num_mac_filters),
2557                                         RTE_CACHE_LINE_SIZE);
2558
2559         if (eth_dev->data->mac_addrs == NULL) {
2560                 DP_ERR(edev, "Failed to allocate MAC address\n");
2561                 qed_ops->common->slowpath_stop(edev);
2562                 qed_ops->common->remove(edev);
2563                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2564                                      (void *)eth_dev);
2565                 return -ENOMEM;
2566         }
2567
2568         if (!is_vf) {
2569                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2570                                 hw_info.hw_mac_addr,
2571                                 &eth_dev->data->mac_addrs[0]);
2572                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2573                                 &adapter->primary_mac);
2574         } else {
2575                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2576                                        &bulletin_change);
2577                 if (bulletin_change) {
2578                         is_mac_exist =
2579                             ecore_vf_bulletin_get_forced_mac(
2580                                                 ECORE_LEADING_HWFN(edev),
2581                                                 vf_mac,
2582                                                 &is_mac_forced);
2583                         if (is_mac_exist) {
2584                                 DP_INFO(edev, "VF macaddr received from PF\n");
2585                                 rte_ether_addr_copy(
2586                                         (struct rte_ether_addr *)&vf_mac,
2587                                         &eth_dev->data->mac_addrs[0]);
2588                                 rte_ether_addr_copy(
2589                                         &eth_dev->data->mac_addrs[0],
2590                                         &adapter->primary_mac);
2591                         } else {
2592                                 DP_ERR(edev, "No VF macaddr assigned\n");
2593                         }
2594                 }
2595         }
2596
2597         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2598
2599         /* Bring-up the link */
2600         qede_dev_set_link_state(eth_dev, true);
2601
2602         adapter->num_tx_queues = 0;
2603         adapter->num_rx_queues = 0;
2604         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2605         SLIST_INIT(&adapter->vlan_list_head);
2606         SLIST_INIT(&adapter->uc_list_head);
2607         SLIST_INIT(&adapter->mc_list_head);
2608         adapter->mtu = RTE_ETHER_MTU;
2609         adapter->vport_started = false;
2610
2611         /* VF tunnel offloads is enabled by default in PF driver */
2612         adapter->vxlan.num_filters = 0;
2613         adapter->geneve.num_filters = 0;
2614         adapter->ipgre.num_filters = 0;
2615         if (is_vf) {
2616                 adapter->vxlan.enable = true;
2617                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2618                                              ETH_TUNNEL_FILTER_IVLAN;
2619                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2620                 adapter->geneve.enable = true;
2621                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2622                                               ETH_TUNNEL_FILTER_IVLAN;
2623                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2624                 adapter->ipgre.enable = true;
2625                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2626                                              ETH_TUNNEL_FILTER_IVLAN;
2627         } else {
2628                 adapter->vxlan.enable = false;
2629                 adapter->geneve.enable = false;
2630                 adapter->ipgre.enable = false;
2631         }
2632
2633         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2634                 adapter->primary_mac.addr_bytes[0],
2635                 adapter->primary_mac.addr_bytes[1],
2636                 adapter->primary_mac.addr_bytes[2],
2637                 adapter->primary_mac.addr_bytes[3],
2638                 adapter->primary_mac.addr_bytes[4],
2639                 adapter->primary_mac.addr_bytes[5]);
2640
2641         DP_INFO(edev, "Device initialized\n");
2642
2643         return 0;
2644
2645 err:
2646         if (do_once) {
2647                 qede_print_adapter_info(adapter);
2648                 do_once = false;
2649         }
2650         return rc;
2651 }
2652
2653 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2654 {
2655         return qede_common_dev_init(eth_dev, 1);
2656 }
2657
2658 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2659 {
2660         return qede_common_dev_init(eth_dev, 0);
2661 }
2662
2663 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2664 {
2665         struct qede_dev *qdev = eth_dev->data->dev_private;
2666         struct ecore_dev *edev = &qdev->edev;
2667
2668         PMD_INIT_FUNC_TRACE(edev);
2669
2670         /* only uninitialize in the primary process */
2671         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2672                 return 0;
2673
2674         /* safe to close dev here */
2675         qede_dev_close(eth_dev);
2676
2677         eth_dev->dev_ops = NULL;
2678         eth_dev->rx_pkt_burst = NULL;
2679         eth_dev->tx_pkt_burst = NULL;
2680
2681         return 0;
2682 }
2683
2684 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2685 {
2686         return qede_dev_common_uninit(eth_dev);
2687 }
2688
2689 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2690 {
2691         return qede_dev_common_uninit(eth_dev);
2692 }
2693
2694 static const struct rte_pci_id pci_id_qedevf_map[] = {
2695 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2696         {
2697                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2698         },
2699         {
2700                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2701         },
2702         {
2703                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2704         },
2705         {.vendor_id = 0,}
2706 };
2707
2708 static const struct rte_pci_id pci_id_qede_map[] = {
2709 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2710         {
2711                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2712         },
2713         {
2714                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2715         },
2716         {
2717                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2718         },
2719         {
2720                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2721         },
2722         {
2723                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2724         },
2725         {
2726                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2727         },
2728         {
2729                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2730         },
2731         {
2732                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2733         },
2734         {
2735                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2736         },
2737         {
2738                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2739         },
2740         {.vendor_id = 0,}
2741 };
2742
2743 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2744         struct rte_pci_device *pci_dev)
2745 {
2746         return rte_eth_dev_pci_generic_probe(pci_dev,
2747                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2748 }
2749
2750 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2751 {
2752         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2753 }
2754
2755 static struct rte_pci_driver rte_qedevf_pmd = {
2756         .id_table = pci_id_qedevf_map,
2757         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2758         .probe = qedevf_eth_dev_pci_probe,
2759         .remove = qedevf_eth_dev_pci_remove,
2760 };
2761
2762 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2763         struct rte_pci_device *pci_dev)
2764 {
2765         return rte_eth_dev_pci_generic_probe(pci_dev,
2766                 sizeof(struct qede_dev), qede_eth_dev_init);
2767 }
2768
2769 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2770 {
2771         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2772 }
2773
2774 static struct rte_pci_driver rte_qede_pmd = {
2775         .id_table = pci_id_qede_map,
2776         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2777         .probe = qede_eth_dev_pci_probe,
2778         .remove = qede_eth_dev_pci_remove,
2779 };
2780
2781 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2782 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2783 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2784 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2785 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2786 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2787
2788 RTE_INIT(qede_init_log)
2789 {
2790         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2791         if (qede_logtype_init >= 0)
2792                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2793         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2794         if (qede_logtype_driver >= 0)
2795                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2796 }