2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
12 #include <rte_kvargs.h>
15 int qede_logtype_init;
16 int qede_logtype_driver;
18 static const struct qed_eth_ops *qed_ops;
19 static int64_t timer_period = 1;
21 /* VXLAN tunnel classification mapping */
22 const struct _qede_udp_tunn_types {
23 uint16_t rte_filter_type;
24 enum ecore_filter_ucast_type qede_type;
25 enum ecore_tunn_clss qede_tunn_clss;
27 } qede_tunn_types[] = {
29 ETH_TUNNEL_FILTER_OMAC,
31 ECORE_TUNN_CLSS_MAC_VLAN,
35 ETH_TUNNEL_FILTER_TENID,
37 ECORE_TUNN_CLSS_MAC_VNI,
41 ETH_TUNNEL_FILTER_IMAC,
42 ECORE_FILTER_INNER_MAC,
43 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
47 ETH_TUNNEL_FILTER_IVLAN,
48 ECORE_FILTER_INNER_VLAN,
49 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
53 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
54 ECORE_FILTER_MAC_VNI_PAIR,
55 ECORE_TUNN_CLSS_MAC_VNI,
59 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
62 "outer-mac and inner-mac"
65 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
68 "outer-mac and inner-vlan"
71 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
72 ECORE_FILTER_INNER_MAC_VNI_PAIR,
73 ECORE_TUNN_CLSS_INNER_MAC_VNI,
77 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
83 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
84 ECORE_FILTER_INNER_PAIR,
85 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
86 "inner-mac and inner-vlan",
89 ETH_TUNNEL_FILTER_OIP,
95 ETH_TUNNEL_FILTER_IIP,
101 RTE_TUNNEL_FILTER_IMAC_IVLAN,
107 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
113 RTE_TUNNEL_FILTER_IMAC_TENID,
119 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
126 struct rte_qede_xstats_name_off {
127 char name[RTE_ETH_XSTATS_NAME_SIZE];
131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
133 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
134 {"rx_multicast_bytes",
135 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
136 {"rx_broadcast_bytes",
137 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
138 {"rx_unicast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
140 {"rx_multicast_packets",
141 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
142 {"rx_broadcast_packets",
143 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
146 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
147 {"tx_multicast_bytes",
148 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
149 {"tx_broadcast_bytes",
150 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
151 {"tx_unicast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
153 {"tx_multicast_packets",
154 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
155 {"tx_broadcast_packets",
156 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
158 {"rx_64_byte_packets",
159 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
160 {"rx_65_to_127_byte_packets",
161 offsetof(struct ecore_eth_stats_common,
162 rx_65_to_127_byte_packets)},
163 {"rx_128_to_255_byte_packets",
164 offsetof(struct ecore_eth_stats_common,
165 rx_128_to_255_byte_packets)},
166 {"rx_256_to_511_byte_packets",
167 offsetof(struct ecore_eth_stats_common,
168 rx_256_to_511_byte_packets)},
169 {"rx_512_to_1023_byte_packets",
170 offsetof(struct ecore_eth_stats_common,
171 rx_512_to_1023_byte_packets)},
172 {"rx_1024_to_1518_byte_packets",
173 offsetof(struct ecore_eth_stats_common,
174 rx_1024_to_1518_byte_packets)},
175 {"tx_64_byte_packets",
176 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
177 {"tx_65_to_127_byte_packets",
178 offsetof(struct ecore_eth_stats_common,
179 tx_65_to_127_byte_packets)},
180 {"tx_128_to_255_byte_packets",
181 offsetof(struct ecore_eth_stats_common,
182 tx_128_to_255_byte_packets)},
183 {"tx_256_to_511_byte_packets",
184 offsetof(struct ecore_eth_stats_common,
185 tx_256_to_511_byte_packets)},
186 {"tx_512_to_1023_byte_packets",
187 offsetof(struct ecore_eth_stats_common,
188 tx_512_to_1023_byte_packets)},
189 {"tx_1024_to_1518_byte_packets",
190 offsetof(struct ecore_eth_stats_common,
191 tx_1024_to_1518_byte_packets)},
193 {"rx_mac_crtl_frames",
194 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
195 {"tx_mac_control_frames",
196 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
198 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
200 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
201 {"rx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
203 {"tx_priority_flow_control_frames",
204 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
207 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
209 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
210 {"rx_carrier_errors",
211 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
212 {"rx_oversize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
215 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
216 {"rx_undersize_packet_errors",
217 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
218 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
219 {"rx_host_buffer_not_available",
220 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
221 /* Number of packets discarded because they are bigger than MTU */
222 {"rx_packet_too_big_discards",
223 offsetof(struct ecore_eth_stats_common,
224 packet_too_big_discard)},
225 {"rx_ttl_zero_discards",
226 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
227 {"rx_multi_function_tag_filter_discards",
228 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
229 {"rx_mac_filter_discards",
230 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
231 {"rx_hw_buffer_truncates",
232 offsetof(struct ecore_eth_stats_common, brb_truncates)},
233 {"rx_hw_buffer_discards",
234 offsetof(struct ecore_eth_stats_common, brb_discards)},
235 {"tx_error_drop_packets",
236 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
239 {"rx_mac_unicast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
241 {"rx_mac_multicast_packets",
242 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
243 {"rx_mac_broadcast_packets",
244 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
246 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
248 {"tx_mac_unicast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
250 {"tx_mac_multicast_packets",
251 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
252 {"tx_mac_broadcast_packets",
253 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
255 {"lro_coalesced_packets",
256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
257 {"lro_coalesced_events",
258 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
260 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
261 {"lro_not_coalesced_packets",
262 offsetof(struct ecore_eth_stats_common,
263 tpa_not_coalesced_pkts)},
264 {"lro_coalesced_bytes",
265 offsetof(struct ecore_eth_stats_common,
266 tpa_coalesced_bytes)},
269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
270 {"rx_1519_to_1522_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_1522_byte_packets)},
274 {"rx_1519_to_2047_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_1519_to_2047_byte_packets)},
278 {"rx_2048_to_4095_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_2048_to_4095_byte_packets)},
282 {"rx_4096_to_9216_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_4096_to_9216_byte_packets)},
286 {"rx_9217_to_16383_byte_packets",
287 offsetof(struct ecore_eth_stats, bb) +
288 offsetof(struct ecore_eth_stats_bb,
289 rx_9217_to_16383_byte_packets)},
291 {"tx_1519_to_2047_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_1519_to_2047_byte_packets)},
295 {"tx_2048_to_4095_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_2048_to_4095_byte_packets)},
299 {"tx_4096_to_9216_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_4096_to_9216_byte_packets)},
303 {"tx_9217_to_16383_byte_packets",
304 offsetof(struct ecore_eth_stats, bb) +
305 offsetof(struct ecore_eth_stats_bb,
306 tx_9217_to_16383_byte_packets)},
308 {"tx_lpi_entry_count",
309 offsetof(struct ecore_eth_stats, bb) +
310 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
311 {"tx_total_collisions",
312 offsetof(struct ecore_eth_stats, bb) +
313 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
317 {"rx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 rx_1519_to_max_byte_packets)},
321 {"tx_1519_to_max_byte_packets",
322 offsetof(struct ecore_eth_stats, ah) +
323 offsetof(struct ecore_eth_stats_ah,
324 tx_1519_to_max_byte_packets)},
327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
329 offsetof(struct qede_rx_queue, rx_segs)},
331 offsetof(struct qede_rx_queue, rx_hw_errors)},
332 {"rx_q_allocation_errors",
333 offsetof(struct qede_rx_queue, rx_alloc_errors)}
336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
338 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
342 qede_interrupt_handler(void *param)
344 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
345 struct qede_dev *qdev = eth_dev->data->dev_private;
346 struct ecore_dev *edev = &qdev->edev;
348 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
349 if (rte_intr_enable(eth_dev->intr_handle))
350 DP_ERR(edev, "rte_intr_enable failed\n");
354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
356 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
360 static void qede_print_adapter_info(struct qede_dev *qdev)
362 struct ecore_dev *edev = &qdev->edev;
363 struct qed_dev_info *info = &qdev->dev_info.common;
364 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
365 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
367 DP_INFO(edev, "*********************************\n");
368 DP_INFO(edev, " DPDK version:%s\n", rte_version());
369 DP_INFO(edev, " Chip details : %s %c%d\n",
370 ECORE_IS_BB(edev) ? "BB" : "AH",
371 'A' + edev->chip_rev,
372 (int)edev->chip_metal);
373 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
374 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
375 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
376 ver_str, QEDE_PMD_VERSION);
377 DP_INFO(edev, " Driver version : %s\n", drv_ver);
378 DP_INFO(edev, " Firmware version : %s\n", ver_str);
380 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
382 (info->mfw_rev >> 24) & 0xff,
383 (info->mfw_rev >> 16) & 0xff,
384 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
385 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
386 DP_INFO(edev, " Firmware file : %s\n", fw_file);
387 DP_INFO(edev, "*********************************\n");
390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
393 unsigned int i = 0, j = 0, qid;
394 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
395 struct qede_tx_queue *txq;
397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
400 RTE_ETHDEV_QUEUE_STAT_CNTRS);
401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
402 RTE_ETHDEV_QUEUE_STAT_CNTRS);
405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
406 offsetof(struct qede_rx_queue, rcv_pkts), 0,
408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
409 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
417 OSAL_MEMSET((((char *)
418 (qdev->fp_array[qid].rxq)) +
419 qede_rxq_xstats_strings[j].offset),
424 if (i == rxq_stat_cntrs)
431 txq = qdev->fp_array[qid].txq;
433 OSAL_MEMSET((uint64_t *)(uintptr_t)
434 (((uint64_t)(uintptr_t)(txq)) +
435 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
439 if (i == txq_stat_cntrs)
445 qede_stop_vport(struct ecore_dev *edev)
447 struct ecore_hwfn *p_hwfn;
453 for_each_hwfn(edev, i) {
454 p_hwfn = &edev->hwfns[i];
455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
457 if (rc != ECORE_SUCCESS) {
458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
463 DP_INFO(edev, "vport stopped\n");
469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
472 struct ecore_sp_vport_start_params params;
473 struct ecore_hwfn *p_hwfn;
477 if (qdev->vport_started)
478 qede_stop_vport(edev);
480 memset(¶ms, 0, sizeof(params));
483 /* @DPDK - Disable FW placement */
484 params.zero_placement_offset = 1;
485 for_each_hwfn(edev, i) {
486 p_hwfn = &edev->hwfns[i];
487 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
488 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
489 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
490 if (rc != ECORE_SUCCESS) {
491 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
495 ecore_reset_vport_stats(edev);
496 qdev->vport_started = true;
497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
502 /* Activate or deactivate vport via vport-update */
503 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
505 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
506 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
507 struct ecore_sp_vport_update_params params;
508 struct ecore_hwfn *p_hwfn;
512 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
514 params.update_vport_active_rx_flg = 1;
515 params.update_vport_active_tx_flg = 1;
516 params.vport_active_rx_flg = flg;
517 params.vport_active_tx_flg = flg;
518 if (!qdev->enable_tx_switching) {
520 params.update_tx_switching_flg = 1;
521 params.tx_switching_flg = !flg;
522 DP_INFO(edev, "VF tx-switching is disabled\n");
525 for_each_hwfn(edev, i) {
526 p_hwfn = &edev->hwfns[i];
527 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
528 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
529 ECORE_SPQ_MODE_EBLOCK, NULL);
530 if (rc != ECORE_SUCCESS) {
531 DP_ERR(edev, "Failed to update vport\n");
535 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
542 uint16_t mtu, bool enable)
544 /* Enable LRO in split mode */
545 sge_tpa_params->tpa_ipv4_en_flg = enable;
546 sge_tpa_params->tpa_ipv6_en_flg = enable;
547 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
548 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
549 /* set if tpa enable changes */
550 sge_tpa_params->update_tpa_en_flg = 1;
551 /* set if tpa parameters should be handled */
552 sge_tpa_params->update_tpa_param_flg = enable;
554 sge_tpa_params->max_buffers_per_cqe = 20;
555 /* Enable TPA in split mode. In this mode each TPA segment
556 * starts on the new BD, so there is one BD per segment.
558 sge_tpa_params->tpa_pkt_split_flg = 1;
559 sge_tpa_params->tpa_hdr_data_split_flg = 0;
560 sge_tpa_params->tpa_gro_consistent_flg = 0;
561 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
562 sge_tpa_params->tpa_max_size = 0x7FFF;
563 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
564 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
567 /* Enable/disable LRO via vport-update */
568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
570 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
571 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
572 struct ecore_sp_vport_update_params params;
573 struct ecore_sge_tpa_params tpa_params;
574 struct ecore_hwfn *p_hwfn;
578 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
579 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
580 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
582 params.sge_tpa_params = &tpa_params;
583 for_each_hwfn(edev, i) {
584 p_hwfn = &edev->hwfns[i];
585 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
586 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
587 ECORE_SPQ_MODE_EBLOCK, NULL);
588 if (rc != ECORE_SUCCESS) {
589 DP_ERR(edev, "Failed to update LRO\n");
593 qdev->enable_lro = flg;
594 eth_dev->data->lro = flg;
596 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
601 /* Update MTU via vport-update without doing port restart.
602 * The vport must be deactivated before calling this API.
604 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
606 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
607 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
608 struct ecore_sp_vport_update_params params;
609 struct ecore_hwfn *p_hwfn;
613 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
617 for_each_hwfn(edev, i) {
618 p_hwfn = &edev->hwfns[i];
619 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
620 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
621 ECORE_SPQ_MODE_EBLOCK, NULL);
622 if (rc != ECORE_SUCCESS) {
623 DP_ERR(edev, "Failed to update MTU\n");
627 DP_INFO(edev, "MTU updated to %u\n", mtu);
632 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
634 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
635 ucast->is_rx_filter = true;
636 ucast->is_tx_filter = true;
637 /* ucast->assert_on_error = true; - For debug */
641 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
642 enum qed_filter_rx_mode_type type)
644 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
645 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
646 struct ecore_filter_accept_flags flags;
648 memset(&flags, 0, sizeof(flags));
650 flags.update_rx_mode_config = 1;
651 flags.update_tx_mode_config = 1;
652 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
653 ECORE_ACCEPT_MCAST_MATCHED |
656 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
657 ECORE_ACCEPT_MCAST_MATCHED |
660 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
661 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
663 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
664 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
666 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
667 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
668 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
669 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
670 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
671 ECORE_ACCEPT_MCAST_UNMATCHED;
674 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
675 ECORE_SPQ_MODE_CB, NULL);
679 qede_tunnel_update(struct qede_dev *qdev,
680 struct ecore_tunnel_info *tunn_info)
682 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
683 enum _ecore_status_t rc = ECORE_INVAL;
684 struct ecore_hwfn *p_hwfn;
685 struct ecore_ptt *p_ptt;
688 for_each_hwfn(edev, i) {
689 p_hwfn = &edev->hwfns[i];
691 p_ptt = ecore_ptt_acquire(p_hwfn);
693 DP_ERR(p_hwfn, "Can't acquire PTT\n");
700 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
701 tunn_info, ECORE_SPQ_MODE_CB, NULL);
703 ecore_ptt_release(p_hwfn, p_ptt);
705 if (rc != ECORE_SUCCESS)
713 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
716 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
717 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
718 enum _ecore_status_t rc = ECORE_INVAL;
719 struct ecore_tunnel_info tunn;
721 if (qdev->vxlan.enable == enable)
722 return ECORE_SUCCESS;
724 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
725 tunn.vxlan.b_update_mode = true;
726 tunn.vxlan.b_mode_enabled = enable;
727 tunn.b_update_rx_cls = true;
728 tunn.b_update_tx_cls = true;
729 tunn.vxlan.tun_cls = clss;
731 tunn.vxlan_port.b_update_port = true;
732 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
734 rc = qede_tunnel_update(qdev, &tunn);
735 if (rc == ECORE_SUCCESS) {
736 qdev->vxlan.enable = enable;
737 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
738 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
739 enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
741 DP_ERR(edev, "Failed to update tunn_clss %u\n",
749 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
752 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
753 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
754 enum _ecore_status_t rc = ECORE_INVAL;
755 struct ecore_tunnel_info tunn;
757 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
758 tunn.l2_geneve.b_update_mode = true;
759 tunn.l2_geneve.b_mode_enabled = enable;
760 tunn.ip_geneve.b_update_mode = true;
761 tunn.ip_geneve.b_mode_enabled = enable;
762 tunn.l2_geneve.tun_cls = clss;
763 tunn.ip_geneve.tun_cls = clss;
764 tunn.b_update_rx_cls = true;
765 tunn.b_update_tx_cls = true;
767 tunn.geneve_port.b_update_port = true;
768 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
770 rc = qede_tunnel_update(qdev, &tunn);
771 if (rc == ECORE_SUCCESS) {
772 qdev->geneve.enable = enable;
773 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
774 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
775 enable ? "enabled" : "disabled", qdev->geneve.udp_port);
777 DP_ERR(edev, "Failed to update tunn_clss %u\n",
785 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
786 enum rte_eth_tunnel_type tunn_type, bool enable)
791 case RTE_TUNNEL_TYPE_VXLAN:
792 rc = qede_vxlan_enable(eth_dev, clss, enable);
794 case RTE_TUNNEL_TYPE_GENEVE:
795 rc = qede_geneve_enable(eth_dev, clss, enable);
806 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
809 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
810 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
811 struct qede_ucast_entry *tmp = NULL;
812 struct qede_ucast_entry *u;
813 struct ether_addr *mac_addr;
815 mac_addr = (struct ether_addr *)ucast->mac;
817 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
818 if ((memcmp(mac_addr, &tmp->mac,
819 ETHER_ADDR_LEN) == 0) &&
820 ucast->vni == tmp->vni &&
821 ucast->vlan == tmp->vlan) {
822 DP_ERR(edev, "Unicast MAC is already added"
823 " with vlan = %u, vni = %u\n",
824 ucast->vlan, ucast->vni);
828 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
829 RTE_CACHE_LINE_SIZE);
831 DP_ERR(edev, "Did not allocate memory for ucast\n");
834 ether_addr_copy(mac_addr, &u->mac);
835 u->vlan = ucast->vlan;
837 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
840 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
841 if ((memcmp(mac_addr, &tmp->mac,
842 ETHER_ADDR_LEN) == 0) &&
843 ucast->vlan == tmp->vlan &&
844 ucast->vni == tmp->vni)
848 DP_INFO(edev, "Unicast MAC is not found\n");
851 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
859 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
862 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
863 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
864 struct ether_addr *mac_addr;
865 struct qede_mcast_entry *tmp = NULL;
866 struct qede_mcast_entry *m;
868 mac_addr = (struct ether_addr *)mcast->mac;
870 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
871 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
873 "Multicast MAC is already added\n");
877 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
878 RTE_CACHE_LINE_SIZE);
881 "Did not allocate memory for mcast\n");
884 ether_addr_copy(mac_addr, &m->mac);
885 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
888 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
889 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
893 DP_INFO(edev, "Multicast mac is not found\n");
896 SLIST_REMOVE(&qdev->mc_list_head, tmp,
897 qede_mcast_entry, list);
904 static enum _ecore_status_t
905 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
908 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
909 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
910 enum _ecore_status_t rc;
911 struct ecore_filter_mcast mcast;
912 struct qede_mcast_entry *tmp;
916 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
918 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
920 "Mcast filter table limit exceeded, "
921 "Please enable mcast promisc mode\n");
925 rc = qede_mcast_filter(eth_dev, ucast, add);
927 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
928 memset(&mcast, 0, sizeof(mcast));
929 mcast.num_mc_addrs = qdev->num_mc_addr;
930 mcast.opcode = ECORE_FILTER_ADD;
931 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
932 ether_addr_copy(&tmp->mac,
933 (struct ether_addr *)&mcast.mac[j]);
936 rc = ecore_filter_mcast_cmd(edev, &mcast,
937 ECORE_SPQ_MODE_CB, NULL);
939 if (rc != ECORE_SUCCESS) {
940 DP_ERR(edev, "Failed to add multicast filter"
941 " rc = %d, op = %d\n", rc, add);
943 } else { /* Unicast */
945 if (qdev->num_uc_addr >=
946 qdev->dev_info.num_mac_filters) {
948 "Ucast filter table limit exceeded,"
949 " Please enable promisc mode\n");
953 rc = qede_ucast_filter(eth_dev, ucast, add);
955 rc = ecore_filter_ucast_cmd(edev, ucast,
956 ECORE_SPQ_MODE_CB, NULL);
957 if (rc != ECORE_SUCCESS) {
958 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
967 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
968 __rte_unused uint32_t index, __rte_unused uint32_t pool)
970 struct ecore_filter_ucast ucast;
973 qede_set_ucast_cmn_params(&ucast);
974 ucast.type = ECORE_FILTER_MAC;
975 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
976 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
981 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
983 struct qede_dev *qdev = eth_dev->data->dev_private;
984 struct ecore_dev *edev = &qdev->edev;
985 struct ecore_filter_ucast ucast;
987 PMD_INIT_FUNC_TRACE(edev);
989 if (index >= qdev->dev_info.num_mac_filters) {
990 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
991 index, qdev->dev_info.num_mac_filters);
995 qede_set_ucast_cmn_params(&ucast);
996 ucast.opcode = ECORE_FILTER_REMOVE;
997 ucast.type = ECORE_FILTER_MAC;
999 /* Use the index maintained by rte */
1000 ether_addr_copy(ð_dev->data->mac_addrs[index],
1001 (struct ether_addr *)&ucast.mac);
1003 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
1007 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1009 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1010 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1012 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1013 mac_addr->addr_bytes)) {
1014 DP_ERR(edev, "Setting MAC address is not allowed\n");
1015 ether_addr_copy(&qdev->primary_mac,
1016 ð_dev->data->mac_addrs[0]);
1020 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1023 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1025 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1026 struct ecore_sp_vport_update_params params;
1027 struct ecore_hwfn *p_hwfn;
1031 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1032 params.vport_id = 0;
1033 params.update_accept_any_vlan_flg = 1;
1034 params.accept_any_vlan = flg;
1035 for_each_hwfn(edev, i) {
1036 p_hwfn = &edev->hwfns[i];
1037 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1038 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1039 ECORE_SPQ_MODE_EBLOCK, NULL);
1040 if (rc != ECORE_SUCCESS) {
1041 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1046 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1049 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1051 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1052 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1053 struct ecore_sp_vport_update_params params;
1054 struct ecore_hwfn *p_hwfn;
1058 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1059 params.vport_id = 0;
1060 params.update_inner_vlan_removal_flg = 1;
1061 params.inner_vlan_removal_flg = flg;
1062 for_each_hwfn(edev, i) {
1063 p_hwfn = &edev->hwfns[i];
1064 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1065 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1066 ECORE_SPQ_MODE_EBLOCK, NULL);
1067 if (rc != ECORE_SUCCESS) {
1068 DP_ERR(edev, "Failed to update vport\n");
1073 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1077 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1078 uint16_t vlan_id, int on)
1080 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1081 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1082 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1083 struct qede_vlan_entry *tmp = NULL;
1084 struct qede_vlan_entry *vlan;
1085 struct ecore_filter_ucast ucast;
1089 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1090 DP_ERR(edev, "Reached max VLAN filter limit"
1091 " enabling accept_any_vlan\n");
1092 qede_config_accept_any_vlan(qdev, true);
1096 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1097 if (tmp->vid == vlan_id) {
1098 DP_ERR(edev, "VLAN %u already configured\n",
1104 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1105 RTE_CACHE_LINE_SIZE);
1108 DP_ERR(edev, "Did not allocate memory for VLAN\n");
1112 qede_set_ucast_cmn_params(&ucast);
1113 ucast.opcode = ECORE_FILTER_ADD;
1114 ucast.type = ECORE_FILTER_VLAN;
1115 ucast.vlan = vlan_id;
1116 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1119 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1123 vlan->vid = vlan_id;
1124 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1125 qdev->configured_vlans++;
1126 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1127 vlan_id, qdev->configured_vlans);
1130 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1131 if (tmp->vid == vlan_id)
1136 if (qdev->configured_vlans == 0) {
1138 "No VLAN filters configured yet\n");
1142 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1146 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1148 qede_set_ucast_cmn_params(&ucast);
1149 ucast.opcode = ECORE_FILTER_REMOVE;
1150 ucast.type = ECORE_FILTER_VLAN;
1151 ucast.vlan = vlan_id;
1152 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1155 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1158 qdev->configured_vlans--;
1159 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1160 vlan_id, qdev->configured_vlans);
1167 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1169 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1170 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1171 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1173 if (mask & ETH_VLAN_STRIP_MASK) {
1174 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1175 (void)qede_vlan_stripping(eth_dev, 1);
1177 (void)qede_vlan_stripping(eth_dev, 0);
1180 if (mask & ETH_VLAN_FILTER_MASK) {
1181 /* VLAN filtering kicks in when a VLAN is added */
1182 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1183 qede_vlan_filter_set(eth_dev, 0, 1);
1185 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1187 " Please remove existing VLAN filters"
1188 " before disabling VLAN filtering\n");
1189 /* Signal app that VLAN filtering is still
1192 eth_dev->data->dev_conf.rxmode.offloads |=
1193 DEV_RX_OFFLOAD_VLAN_FILTER;
1195 qede_vlan_filter_set(eth_dev, 0, 0);
1200 if (mask & ETH_VLAN_EXTEND_MASK)
1201 DP_ERR(edev, "Extend VLAN not supported\n");
1203 qdev->vlan_offload_mask = mask;
1205 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1210 static void qede_prandom_bytes(uint32_t *buff)
1214 srand((unsigned int)time(NULL));
1215 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1219 int qede_config_rss(struct rte_eth_dev *eth_dev)
1221 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1222 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1223 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1224 struct rte_eth_rss_reta_entry64 reta_conf[2];
1225 struct rte_eth_rss_conf rss_conf;
1226 uint32_t i, id, pos, q;
1228 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1229 if (!rss_conf.rss_key) {
1230 DP_INFO(edev, "Applying driver default key\n");
1231 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1232 qede_prandom_bytes(&def_rss_key[0]);
1233 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1236 /* Configure RSS hash */
1237 if (qede_rss_hash_update(eth_dev, &rss_conf))
1240 /* Configure default RETA */
1241 memset(reta_conf, 0, sizeof(reta_conf));
1242 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1243 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1245 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1246 id = i / RTE_RETA_GROUP_SIZE;
1247 pos = i % RTE_RETA_GROUP_SIZE;
1248 q = i % QEDE_RSS_COUNT(qdev);
1249 reta_conf[id].reta[pos] = q;
1251 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1252 ECORE_RSS_IND_TABLE_SIZE))
1258 static void qede_fastpath_start(struct ecore_dev *edev)
1260 struct ecore_hwfn *p_hwfn;
1263 for_each_hwfn(edev, i) {
1264 p_hwfn = &edev->hwfns[i];
1265 ecore_hw_start_fastpath(p_hwfn);
1269 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1271 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1272 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1273 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1275 PMD_INIT_FUNC_TRACE(edev);
1277 /* Configure TPA parameters */
1278 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1279 if (qede_enable_tpa(eth_dev, true))
1281 /* Enable scatter mode for LRO */
1282 if (!eth_dev->data->scattered_rx)
1283 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1287 if (qede_start_queues(eth_dev))
1291 qede_reset_queue_stats(qdev, true);
1293 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1294 * enabling RSS. Hence RSS configuration is deferred upto this point.
1295 * Also, we would like to retain similar behavior in PF case, so we
1296 * don't do PF/VF specific check here.
1298 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1299 if (qede_config_rss(eth_dev))
1303 if (qede_activate_vport(eth_dev, true))
1306 /* Update link status */
1307 qede_link_update(eth_dev, 0);
1309 /* Start/resume traffic */
1310 qede_fastpath_start(edev);
1312 DP_INFO(edev, "Device started\n");
1316 DP_ERR(edev, "Device start fails\n");
1317 return -1; /* common error code is < 0 */
1320 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1322 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1323 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1325 PMD_INIT_FUNC_TRACE(edev);
1328 if (qede_activate_vport(eth_dev, false))
1331 if (qdev->enable_lro)
1332 qede_enable_tpa(eth_dev, false);
1335 qede_stop_queues(eth_dev);
1337 /* Disable traffic */
1338 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1340 DP_INFO(edev, "Device is stopped\n");
1343 #define QEDE_TX_SWITCHING "vf_txswitch"
1345 const char *valid_args[] = {
1350 static int qede_args_check(const char *key, const char *val, void *opaque)
1354 struct rte_eth_dev *eth_dev = opaque;
1355 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1356 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1359 tmp = strtoul(val, NULL, 0);
1361 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1365 if (strcmp(QEDE_TX_SWITCHING, key) == 0)
1366 qdev->enable_tx_switching = !!tmp;
1371 static int qede_args(struct rte_eth_dev *eth_dev)
1373 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1374 struct rte_kvargs *kvlist;
1375 struct rte_devargs *devargs;
1379 devargs = pci_dev->device.devargs;
1381 return 0; /* return success */
1383 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1387 /* Process parameters. */
1388 for (i = 0; (valid_args[i] != NULL); ++i) {
1389 if (rte_kvargs_count(kvlist, valid_args[i])) {
1390 ret = rte_kvargs_process(kvlist, valid_args[i],
1391 qede_args_check, eth_dev);
1392 if (ret != ECORE_SUCCESS) {
1393 rte_kvargs_free(kvlist);
1398 rte_kvargs_free(kvlist);
1403 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1405 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1406 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1407 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1410 PMD_INIT_FUNC_TRACE(edev);
1412 /* Check requirements for 100G mode */
1413 if (ECORE_IS_CMT(edev)) {
1414 if (eth_dev->data->nb_rx_queues < 2 ||
1415 eth_dev->data->nb_tx_queues < 2) {
1416 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1420 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1421 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1423 "100G mode needs even no. of RX/TX queues\n");
1428 /* We need to have min 1 RX queue.There is no min check in
1429 * rte_eth_dev_configure(), so we are checking it here.
1431 if (eth_dev->data->nb_rx_queues == 0) {
1432 DP_ERR(edev, "Minimum one RX queue is required\n");
1436 /* Enable Tx switching by default */
1437 qdev->enable_tx_switching = 1;
1439 /* Parse devargs and fix up rxmode */
1440 if (qede_args(eth_dev))
1443 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1444 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1445 DP_ERR(edev, "Unsupported multi-queue mode\n");
1448 /* Flow director mode check */
1449 if (qede_check_fdir_support(eth_dev))
1452 qede_dealloc_fp_resc(eth_dev);
1453 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1454 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1455 if (qede_alloc_fp_resc(qdev))
1458 /* If jumbo enabled adjust MTU */
1459 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1460 eth_dev->data->mtu =
1461 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1462 ETHER_HDR_LEN - ETHER_CRC_LEN;
1464 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1465 eth_dev->data->scattered_rx = 1;
1467 if (qede_start_vport(qdev, eth_dev->data->mtu))
1470 qdev->mtu = eth_dev->data->mtu;
1472 /* Enable VLAN offloads by default */
1473 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1474 ETH_VLAN_FILTER_MASK |
1475 ETH_VLAN_EXTEND_MASK);
1479 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1480 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1485 /* Info about HW descriptor ring limitations */
1486 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1487 .nb_max = 0x8000, /* 32K */
1489 .nb_align = 128 /* lowest common multiple */
1492 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1493 .nb_max = 0x8000, /* 32K */
1496 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1497 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1501 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1502 struct rte_eth_dev_info *dev_info)
1504 struct qede_dev *qdev = eth_dev->data->dev_private;
1505 struct ecore_dev *edev = &qdev->edev;
1506 struct qed_link_output link;
1507 uint32_t speed_cap = 0;
1509 PMD_INIT_FUNC_TRACE(edev);
1511 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1512 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1513 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1514 dev_info->rx_desc_lim = qede_rx_desc_lim;
1515 dev_info->tx_desc_lim = qede_tx_desc_lim;
1518 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1519 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1521 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1522 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1523 dev_info->max_tx_queues = dev_info->max_rx_queues;
1525 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1526 dev_info->max_vfs = 0;
1527 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1528 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1529 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1530 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1531 DEV_RX_OFFLOAD_UDP_CKSUM |
1532 DEV_RX_OFFLOAD_TCP_CKSUM |
1533 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1534 DEV_RX_OFFLOAD_TCP_LRO |
1535 DEV_RX_OFFLOAD_CRC_STRIP |
1536 DEV_RX_OFFLOAD_SCATTER |
1537 DEV_RX_OFFLOAD_JUMBO_FRAME |
1538 DEV_RX_OFFLOAD_VLAN_FILTER |
1539 DEV_RX_OFFLOAD_VLAN_STRIP);
1540 dev_info->rx_queue_offload_capa = 0;
1542 /* TX offloads are on a per-packet basis, so it is applicable
1543 * to both at port and queue levels.
1545 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1546 DEV_TX_OFFLOAD_IPV4_CKSUM |
1547 DEV_TX_OFFLOAD_UDP_CKSUM |
1548 DEV_TX_OFFLOAD_TCP_CKSUM |
1549 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1550 DEV_TX_OFFLOAD_QINQ_INSERT |
1551 DEV_TX_OFFLOAD_MULTI_SEGS |
1552 DEV_TX_OFFLOAD_TCP_TSO |
1553 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1554 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1555 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1557 dev_info->default_txconf = (struct rte_eth_txconf) {
1558 .txq_flags = DEV_TX_OFFLOAD_MULTI_SEGS,
1561 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1562 /* Packets are always dropped if no descriptors are available */
1564 /* The below RX offloads are always enabled */
1565 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP |
1566 DEV_RX_OFFLOAD_IPV4_CKSUM |
1567 DEV_RX_OFFLOAD_TCP_CKSUM |
1568 DEV_RX_OFFLOAD_UDP_CKSUM),
1571 memset(&link, 0, sizeof(struct qed_link_output));
1572 qdev->ops->common->get_link(edev, &link);
1573 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1574 speed_cap |= ETH_LINK_SPEED_1G;
1575 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1576 speed_cap |= ETH_LINK_SPEED_10G;
1577 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1578 speed_cap |= ETH_LINK_SPEED_25G;
1579 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1580 speed_cap |= ETH_LINK_SPEED_40G;
1581 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1582 speed_cap |= ETH_LINK_SPEED_50G;
1583 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1584 speed_cap |= ETH_LINK_SPEED_100G;
1585 dev_info->speed_capa = speed_cap;
1588 /* return 0 means link status changed, -1 means not changed */
1590 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1592 struct qede_dev *qdev = eth_dev->data->dev_private;
1593 struct ecore_dev *edev = &qdev->edev;
1594 uint16_t link_duplex;
1595 struct qed_link_output link;
1596 struct rte_eth_link *curr = ð_dev->data->dev_link;
1598 memset(&link, 0, sizeof(struct qed_link_output));
1599 qdev->ops->common->get_link(edev, &link);
1602 curr->link_speed = link.speed;
1605 switch (link.duplex) {
1606 case QEDE_DUPLEX_HALF:
1607 link_duplex = ETH_LINK_HALF_DUPLEX;
1609 case QEDE_DUPLEX_FULL:
1610 link_duplex = ETH_LINK_FULL_DUPLEX;
1612 case QEDE_DUPLEX_UNKNOWN:
1616 curr->link_duplex = link_duplex;
1619 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1622 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1623 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1625 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1626 curr->link_speed, curr->link_duplex,
1627 curr->link_autoneg, curr->link_status);
1629 /* return 0 means link status changed, -1 means not changed */
1630 return ((curr->link_status == link.link_up) ? -1 : 0);
1633 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1635 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1636 struct qede_dev *qdev = eth_dev->data->dev_private;
1637 struct ecore_dev *edev = &qdev->edev;
1639 PMD_INIT_FUNC_TRACE(edev);
1642 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1644 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1645 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1647 qed_configure_filter_rx_mode(eth_dev, type);
1650 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1652 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1653 struct qede_dev *qdev = eth_dev->data->dev_private;
1654 struct ecore_dev *edev = &qdev->edev;
1656 PMD_INIT_FUNC_TRACE(edev);
1659 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1660 qed_configure_filter_rx_mode(eth_dev,
1661 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1663 qed_configure_filter_rx_mode(eth_dev,
1664 QED_FILTER_RX_MODE_TYPE_REGULAR);
1667 static void qede_poll_sp_sb_cb(void *param)
1669 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1670 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1671 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1674 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1675 qede_interrupt_action(&edev->hwfns[1]);
1677 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1681 DP_ERR(edev, "Unable to start periodic"
1682 " timer rc %d\n", rc);
1683 assert(false && "Unable to start periodic timer");
1687 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1689 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1690 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1691 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1693 PMD_INIT_FUNC_TRACE(edev);
1695 /* dev_stop() shall cleanup fp resources in hw but without releasing
1696 * dma memories and sw structures so that dev_start() can be called
1697 * by the app without reconfiguration. However, in dev_close() we
1698 * can release all the resources and device can be brought up newly
1700 if (eth_dev->data->dev_started)
1701 qede_dev_stop(eth_dev);
1703 qede_stop_vport(edev);
1704 qdev->vport_started = false;
1705 qede_fdir_dealloc_resc(eth_dev);
1706 qede_dealloc_fp_resc(eth_dev);
1708 eth_dev->data->nb_rx_queues = 0;
1709 eth_dev->data->nb_tx_queues = 0;
1711 /* Bring the link down */
1712 qede_dev_set_link_state(eth_dev, false);
1713 qdev->ops->common->slowpath_stop(edev);
1714 qdev->ops->common->remove(edev);
1715 rte_intr_disable(&pci_dev->intr_handle);
1716 rte_intr_callback_unregister(&pci_dev->intr_handle,
1717 qede_interrupt_handler, (void *)eth_dev);
1718 if (ECORE_IS_CMT(edev))
1719 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1723 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1725 struct qede_dev *qdev = eth_dev->data->dev_private;
1726 struct ecore_dev *edev = &qdev->edev;
1727 struct ecore_eth_stats stats;
1728 unsigned int i = 0, j = 0, qid;
1729 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1730 struct qede_tx_queue *txq;
1732 ecore_get_vport_stats(edev, &stats);
1735 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1736 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1738 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1739 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1741 eth_stats->ierrors = stats.common.rx_crc_errors +
1742 stats.common.rx_align_errors +
1743 stats.common.rx_carrier_errors +
1744 stats.common.rx_oversize_packets +
1745 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1747 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1749 eth_stats->imissed = stats.common.mftag_filter_discards +
1750 stats.common.mac_filter_discards +
1751 stats.common.no_buff_discards +
1752 stats.common.brb_truncates + stats.common.brb_discards;
1755 eth_stats->opackets = stats.common.tx_ucast_pkts +
1756 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1758 eth_stats->obytes = stats.common.tx_ucast_bytes +
1759 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1761 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1764 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1765 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1766 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1767 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1768 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1769 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1770 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1771 "Not all the queue stats will be displayed. Set"
1772 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1773 " appropriately and retry.\n");
1776 eth_stats->q_ipackets[i] =
1778 ((char *)(qdev->fp_array[qid].rxq)) +
1779 offsetof(struct qede_rx_queue,
1781 eth_stats->q_errors[i] =
1783 ((char *)(qdev->fp_array[qid].rxq)) +
1784 offsetof(struct qede_rx_queue,
1787 ((char *)(qdev->fp_array[qid].rxq)) +
1788 offsetof(struct qede_rx_queue,
1791 if (i == rxq_stat_cntrs)
1796 txq = qdev->fp_array[qid].txq;
1797 eth_stats->q_opackets[j] =
1798 *((uint64_t *)(uintptr_t)
1799 (((uint64_t)(uintptr_t)(txq)) +
1800 offsetof(struct qede_tx_queue,
1803 if (j == txq_stat_cntrs)
1811 qede_get_xstats_count(struct qede_dev *qdev) {
1812 if (ECORE_IS_BB(&qdev->edev))
1813 return RTE_DIM(qede_xstats_strings) +
1814 RTE_DIM(qede_bb_xstats_strings) +
1815 (RTE_DIM(qede_rxq_xstats_strings) *
1816 RTE_MIN(QEDE_RSS_COUNT(qdev),
1817 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1819 return RTE_DIM(qede_xstats_strings) +
1820 RTE_DIM(qede_ah_xstats_strings) +
1821 (RTE_DIM(qede_rxq_xstats_strings) *
1822 RTE_MIN(QEDE_RSS_COUNT(qdev),
1823 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1827 qede_get_xstats_names(struct rte_eth_dev *dev,
1828 struct rte_eth_xstat_name *xstats_names,
1829 __rte_unused unsigned int limit)
1831 struct qede_dev *qdev = dev->data->dev_private;
1832 struct ecore_dev *edev = &qdev->edev;
1833 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1834 unsigned int i, qid, stat_idx = 0;
1835 unsigned int rxq_stat_cntrs;
1837 if (xstats_names != NULL) {
1838 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1839 snprintf(xstats_names[stat_idx].name,
1840 sizeof(xstats_names[stat_idx].name),
1842 qede_xstats_strings[i].name);
1846 if (ECORE_IS_BB(edev)) {
1847 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1848 snprintf(xstats_names[stat_idx].name,
1849 sizeof(xstats_names[stat_idx].name),
1851 qede_bb_xstats_strings[i].name);
1855 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1856 snprintf(xstats_names[stat_idx].name,
1857 sizeof(xstats_names[stat_idx].name),
1859 qede_ah_xstats_strings[i].name);
1864 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1865 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1866 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1867 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1868 snprintf(xstats_names[stat_idx].name,
1869 sizeof(xstats_names[stat_idx].name),
1871 qede_rxq_xstats_strings[i].name, qid,
1872 qede_rxq_xstats_strings[i].name + 4);
1882 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1885 struct qede_dev *qdev = dev->data->dev_private;
1886 struct ecore_dev *edev = &qdev->edev;
1887 struct ecore_eth_stats stats;
1888 const unsigned int num = qede_get_xstats_count(qdev);
1889 unsigned int i, qid, stat_idx = 0;
1890 unsigned int rxq_stat_cntrs;
1895 ecore_get_vport_stats(edev, &stats);
1897 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1898 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1899 qede_xstats_strings[i].offset);
1900 xstats[stat_idx].id = stat_idx;
1904 if (ECORE_IS_BB(edev)) {
1905 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1906 xstats[stat_idx].value =
1907 *(uint64_t *)(((char *)&stats) +
1908 qede_bb_xstats_strings[i].offset);
1909 xstats[stat_idx].id = stat_idx;
1913 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1914 xstats[stat_idx].value =
1915 *(uint64_t *)(((char *)&stats) +
1916 qede_ah_xstats_strings[i].offset);
1917 xstats[stat_idx].id = stat_idx;
1922 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1923 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1924 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1926 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1927 xstats[stat_idx].value = *(uint64_t *)(
1928 ((char *)(qdev->fp_array[qid].rxq)) +
1929 qede_rxq_xstats_strings[i].offset);
1930 xstats[stat_idx].id = stat_idx;
1940 qede_reset_xstats(struct rte_eth_dev *dev)
1942 struct qede_dev *qdev = dev->data->dev_private;
1943 struct ecore_dev *edev = &qdev->edev;
1945 ecore_reset_vport_stats(edev);
1946 qede_reset_queue_stats(qdev, true);
1949 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1951 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1952 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1953 struct qed_link_params link_params;
1956 DP_INFO(edev, "setting link state %d\n", link_up);
1957 memset(&link_params, 0, sizeof(link_params));
1958 link_params.link_up = link_up;
1959 rc = qdev->ops->common->set_link(edev, &link_params);
1960 if (rc != ECORE_SUCCESS)
1961 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1966 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1968 return qede_dev_set_link_state(eth_dev, true);
1971 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1973 return qede_dev_set_link_state(eth_dev, false);
1976 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1978 struct qede_dev *qdev = eth_dev->data->dev_private;
1979 struct ecore_dev *edev = &qdev->edev;
1981 ecore_reset_vport_stats(edev);
1982 qede_reset_queue_stats(qdev, false);
1985 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1987 enum qed_filter_rx_mode_type type =
1988 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1990 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1991 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1993 qed_configure_filter_rx_mode(eth_dev, type);
1996 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1998 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1999 qed_configure_filter_rx_mode(eth_dev,
2000 QED_FILTER_RX_MODE_TYPE_PROMISC);
2002 qed_configure_filter_rx_mode(eth_dev,
2003 QED_FILTER_RX_MODE_TYPE_REGULAR);
2006 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2007 struct rte_eth_fc_conf *fc_conf)
2009 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2010 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2011 struct qed_link_output current_link;
2012 struct qed_link_params params;
2014 memset(¤t_link, 0, sizeof(current_link));
2015 qdev->ops->common->get_link(edev, ¤t_link);
2017 memset(¶ms, 0, sizeof(params));
2018 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2019 if (fc_conf->autoneg) {
2020 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2021 DP_ERR(edev, "Autoneg not supported\n");
2024 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2027 /* Pause is assumed to be supported (SUPPORTED_Pause) */
2028 if (fc_conf->mode == RTE_FC_FULL)
2029 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2030 QED_LINK_PAUSE_RX_ENABLE);
2031 if (fc_conf->mode == RTE_FC_TX_PAUSE)
2032 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2033 if (fc_conf->mode == RTE_FC_RX_PAUSE)
2034 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2036 params.link_up = true;
2037 (void)qdev->ops->common->set_link(edev, ¶ms);
2042 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2043 struct rte_eth_fc_conf *fc_conf)
2045 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2046 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2047 struct qed_link_output current_link;
2049 memset(¤t_link, 0, sizeof(current_link));
2050 qdev->ops->common->get_link(edev, ¤t_link);
2052 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2053 fc_conf->autoneg = true;
2055 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2056 QED_LINK_PAUSE_TX_ENABLE))
2057 fc_conf->mode = RTE_FC_FULL;
2058 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2059 fc_conf->mode = RTE_FC_RX_PAUSE;
2060 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2061 fc_conf->mode = RTE_FC_TX_PAUSE;
2063 fc_conf->mode = RTE_FC_NONE;
2068 static const uint32_t *
2069 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2071 static const uint32_t ptypes[] = {
2073 RTE_PTYPE_L2_ETHER_VLAN,
2078 RTE_PTYPE_TUNNEL_VXLAN,
2080 RTE_PTYPE_TUNNEL_GENEVE,
2082 RTE_PTYPE_INNER_L2_ETHER,
2083 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2084 RTE_PTYPE_INNER_L3_IPV4,
2085 RTE_PTYPE_INNER_L3_IPV6,
2086 RTE_PTYPE_INNER_L4_TCP,
2087 RTE_PTYPE_INNER_L4_UDP,
2088 RTE_PTYPE_INNER_L4_FRAG,
2092 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2098 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2101 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2102 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2103 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2104 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2105 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2106 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2107 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2108 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2111 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2112 struct rte_eth_rss_conf *rss_conf)
2114 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2115 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2116 struct ecore_sp_vport_update_params vport_update_params;
2117 struct ecore_rss_params rss_params;
2118 struct ecore_hwfn *p_hwfn;
2119 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2120 uint64_t hf = rss_conf->rss_hf;
2121 uint8_t len = rss_conf->rss_key_len;
2126 memset(&vport_update_params, 0, sizeof(vport_update_params));
2127 memset(&rss_params, 0, sizeof(rss_params));
2129 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2130 (unsigned long)hf, len, key);
2134 DP_INFO(edev, "Enabling rss\n");
2137 qede_init_rss_caps(&rss_params.rss_caps, hf);
2138 rss_params.update_rss_capabilities = 1;
2142 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2143 DP_ERR(edev, "RSS key length exceeds limit\n");
2146 DP_INFO(edev, "Applying user supplied hash key\n");
2147 rss_params.update_rss_key = 1;
2148 memcpy(&rss_params.rss_key, key, len);
2150 rss_params.rss_enable = 1;
2153 rss_params.update_rss_config = 1;
2154 /* tbl_size has to be set with capabilities */
2155 rss_params.rss_table_size_log = 7;
2156 vport_update_params.vport_id = 0;
2157 /* pass the L2 handles instead of qids */
2158 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2159 idx = qdev->rss_ind_table[i];
2160 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2162 vport_update_params.rss_params = &rss_params;
2164 for_each_hwfn(edev, i) {
2165 p_hwfn = &edev->hwfns[i];
2166 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2167 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2168 ECORE_SPQ_MODE_EBLOCK, NULL);
2170 DP_ERR(edev, "vport-update for RSS failed\n");
2174 qdev->rss_enable = rss_params.rss_enable;
2176 /* Update local structure for hash query */
2177 qdev->rss_conf.rss_hf = hf;
2178 qdev->rss_conf.rss_key_len = len;
2179 if (qdev->rss_enable) {
2180 if (qdev->rss_conf.rss_key == NULL) {
2181 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2182 if (qdev->rss_conf.rss_key == NULL) {
2183 DP_ERR(edev, "No memory to store RSS key\n");
2188 DP_INFO(edev, "Storing RSS key\n");
2189 memcpy(qdev->rss_conf.rss_key, key, len);
2191 } else if (!qdev->rss_enable && len == 0) {
2192 if (qdev->rss_conf.rss_key) {
2193 free(qdev->rss_conf.rss_key);
2194 qdev->rss_conf.rss_key = NULL;
2195 DP_INFO(edev, "Free RSS key\n");
2202 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2203 struct rte_eth_rss_conf *rss_conf)
2205 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2207 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2208 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2210 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2211 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2212 rss_conf->rss_key_len);
2216 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2217 struct ecore_rss_params *rss)
2220 bool rss_mode = 1; /* enable */
2221 struct ecore_queue_cid *cid;
2222 struct ecore_rss_params *t_rss;
2224 /* In regular scenario, we'd simply need to take input handlers.
2225 * But in CMT, we'd have to split the handlers according to the
2226 * engine they were configured on. We'd then have to understand
2227 * whether RSS is really required, since 2-queues on CMT doesn't
2231 /* CMT should be round-robin */
2232 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2233 cid = rss->rss_ind_table[i];
2235 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2240 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2244 t_rss->update_rss_ind_table = 1;
2245 t_rss->rss_table_size_log = 7;
2246 t_rss->update_rss_config = 1;
2248 /* Make sure RSS is actually required */
2249 for_each_hwfn(edev, fn) {
2250 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2252 if (rss[fn].rss_ind_table[i] !=
2253 rss[fn].rss_ind_table[0])
2257 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2259 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2266 t_rss->rss_enable = rss_mode;
2271 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2272 struct rte_eth_rss_reta_entry64 *reta_conf,
2275 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2276 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2277 struct ecore_sp_vport_update_params vport_update_params;
2278 struct ecore_rss_params *params;
2279 struct ecore_hwfn *p_hwfn;
2280 uint16_t i, idx, shift;
2284 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2285 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2290 memset(&vport_update_params, 0, sizeof(vport_update_params));
2291 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2292 RTE_CACHE_LINE_SIZE);
2293 if (params == NULL) {
2294 DP_ERR(edev, "failed to allocate memory\n");
2298 for (i = 0; i < reta_size; i++) {
2299 idx = i / RTE_RETA_GROUP_SIZE;
2300 shift = i % RTE_RETA_GROUP_SIZE;
2301 if (reta_conf[idx].mask & (1ULL << shift)) {
2302 entry = reta_conf[idx].reta[shift];
2303 /* Pass rxq handles to ecore */
2304 params->rss_ind_table[i] =
2305 qdev->fp_array[entry].rxq->handle;
2306 /* Update the local copy for RETA query command */
2307 qdev->rss_ind_table[i] = entry;
2311 params->update_rss_ind_table = 1;
2312 params->rss_table_size_log = 7;
2313 params->update_rss_config = 1;
2315 /* Fix up RETA for CMT mode device */
2316 if (ECORE_IS_CMT(edev))
2317 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2319 vport_update_params.vport_id = 0;
2320 /* Use the current value of rss_enable */
2321 params->rss_enable = qdev->rss_enable;
2322 vport_update_params.rss_params = params;
2324 for_each_hwfn(edev, i) {
2325 p_hwfn = &edev->hwfns[i];
2326 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2327 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2328 ECORE_SPQ_MODE_EBLOCK, NULL);
2330 DP_ERR(edev, "vport-update for RSS failed\n");
2340 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2341 struct rte_eth_rss_reta_entry64 *reta_conf,
2344 struct qede_dev *qdev = eth_dev->data->dev_private;
2345 struct ecore_dev *edev = &qdev->edev;
2346 uint16_t i, idx, shift;
2349 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2350 DP_ERR(edev, "reta_size %d is not supported\n",
2355 for (i = 0; i < reta_size; i++) {
2356 idx = i / RTE_RETA_GROUP_SIZE;
2357 shift = i % RTE_RETA_GROUP_SIZE;
2358 if (reta_conf[idx].mask & (1ULL << shift)) {
2359 entry = qdev->rss_ind_table[i];
2360 reta_conf[idx].reta[shift] = entry;
2369 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2371 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2372 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2373 struct rte_eth_dev_info dev_info = {0};
2374 struct qede_fastpath *fp;
2375 uint32_t max_rx_pkt_len;
2376 uint32_t frame_size;
2377 uint16_t rx_buf_size;
2379 bool restart = false;
2382 PMD_INIT_FUNC_TRACE(edev);
2383 qede_dev_info_get(dev, &dev_info);
2384 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2385 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2386 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2387 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2388 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2389 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2392 if (!dev->data->scattered_rx &&
2393 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2394 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2395 dev->data->min_rx_buf_size);
2398 /* Temporarily replace I/O functions with dummy ones. It cannot
2399 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2401 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2402 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2403 if (dev->data->dev_started) {
2404 dev->data->dev_started = 0;
2409 qede_start_vport(qdev, mtu); /* Recreate vport */
2412 /* Fix up RX buf size for all queues of the port */
2414 fp = &qdev->fp_array[i];
2415 if (fp->rxq != NULL) {
2416 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2417 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2418 if (dev->data->scattered_rx)
2419 rx_buf_size = bufsz + ETHER_HDR_LEN +
2420 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2422 rx_buf_size = frame_size;
2423 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2424 fp->rxq->rx_buf_size = rx_buf_size;
2425 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2428 if (max_rx_pkt_len > ETHER_MAX_LEN)
2429 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2431 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2433 /* Restore config lost due to vport stop */
2434 qede_mac_addr_set(dev, &qdev->primary_mac);
2435 if (dev->data->promiscuous)
2436 qede_promiscuous_enable(dev);
2438 qede_promiscuous_disable(dev);
2440 if (dev->data->all_multicast)
2441 qede_allmulticast_enable(dev);
2443 qede_allmulticast_disable(dev);
2445 qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2447 if (!dev->data->dev_started && restart) {
2448 qede_dev_start(dev);
2449 dev->data->dev_started = 1;
2452 /* update max frame size */
2453 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2455 dev->rx_pkt_burst = qede_recv_pkts;
2456 dev->tx_pkt_burst = qede_xmit_pkts;
2462 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2463 struct rte_eth_udp_tunnel *tunnel_udp)
2465 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2466 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2467 struct ecore_tunnel_info tunn; /* @DPDK */
2471 PMD_INIT_FUNC_TRACE(edev);
2473 memset(&tunn, 0, sizeof(tunn));
2475 switch (tunnel_udp->prot_type) {
2476 case RTE_TUNNEL_TYPE_VXLAN:
2477 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2478 DP_ERR(edev, "UDP port %u doesn't exist\n",
2479 tunnel_udp->udp_port);
2484 tunn.vxlan_port.b_update_port = true;
2485 tunn.vxlan_port.port = udp_port;
2487 rc = qede_tunnel_update(qdev, &tunn);
2488 if (rc != ECORE_SUCCESS) {
2489 DP_ERR(edev, "Unable to config UDP port %u\n",
2490 tunn.vxlan_port.port);
2494 qdev->vxlan.udp_port = udp_port;
2495 /* If the request is to delete UDP port and if the number of
2496 * VXLAN filters have reached 0 then VxLAN offload can be be
2499 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2500 return qede_vxlan_enable(eth_dev,
2501 ECORE_TUNN_CLSS_MAC_VLAN, false);
2505 case RTE_TUNNEL_TYPE_GENEVE:
2506 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2507 DP_ERR(edev, "UDP port %u doesn't exist\n",
2508 tunnel_udp->udp_port);
2514 tunn.geneve_port.b_update_port = true;
2515 tunn.geneve_port.port = udp_port;
2517 rc = qede_tunnel_update(qdev, &tunn);
2518 if (rc != ECORE_SUCCESS) {
2519 DP_ERR(edev, "Unable to config UDP port %u\n",
2520 tunn.vxlan_port.port);
2524 qdev->vxlan.udp_port = udp_port;
2525 /* If the request is to delete UDP port and if the number of
2526 * GENEVE filters have reached 0 then GENEVE offload can be be
2529 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2530 return qede_geneve_enable(eth_dev,
2531 ECORE_TUNN_CLSS_MAC_VLAN, false);
2543 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2544 struct rte_eth_udp_tunnel *tunnel_udp)
2546 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2547 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2548 struct ecore_tunnel_info tunn; /* @DPDK */
2552 PMD_INIT_FUNC_TRACE(edev);
2554 memset(&tunn, 0, sizeof(tunn));
2556 switch (tunnel_udp->prot_type) {
2557 case RTE_TUNNEL_TYPE_VXLAN:
2558 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2560 "UDP port %u for VXLAN was already configured\n",
2561 tunnel_udp->udp_port);
2562 return ECORE_SUCCESS;
2565 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2566 * it was not enabled while adding VXLAN filter before UDP port
2569 if (!qdev->vxlan.enable) {
2570 rc = qede_vxlan_enable(eth_dev,
2571 ECORE_TUNN_CLSS_MAC_VLAN, true);
2572 if (rc != ECORE_SUCCESS) {
2573 DP_ERR(edev, "Failed to enable VXLAN "
2574 "prior to updating UDP port\n");
2578 udp_port = tunnel_udp->udp_port;
2580 tunn.vxlan_port.b_update_port = true;
2581 tunn.vxlan_port.port = udp_port;
2583 rc = qede_tunnel_update(qdev, &tunn);
2584 if (rc != ECORE_SUCCESS) {
2585 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2590 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2592 qdev->vxlan.udp_port = udp_port;
2595 case RTE_TUNNEL_TYPE_GENEVE:
2596 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2598 "UDP port %u for GENEVE was already configured\n",
2599 tunnel_udp->udp_port);
2600 return ECORE_SUCCESS;
2603 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2604 * it was not enabled while adding GENEVE filter before UDP port
2607 if (!qdev->geneve.enable) {
2608 rc = qede_geneve_enable(eth_dev,
2609 ECORE_TUNN_CLSS_MAC_VLAN, true);
2610 if (rc != ECORE_SUCCESS) {
2611 DP_ERR(edev, "Failed to enable GENEVE "
2612 "prior to updating UDP port\n");
2616 udp_port = tunnel_udp->udp_port;
2618 tunn.geneve_port.b_update_port = true;
2619 tunn.geneve_port.port = udp_port;
2621 rc = qede_tunnel_update(qdev, &tunn);
2622 if (rc != ECORE_SUCCESS) {
2623 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2628 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2630 qdev->geneve.udp_port = udp_port;
2640 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2641 uint32_t *clss, char *str)
2644 *clss = MAX_ECORE_TUNN_CLSS;
2646 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2647 if (filter == qede_tunn_types[j].rte_filter_type) {
2648 *type = qede_tunn_types[j].qede_type;
2649 *clss = qede_tunn_types[j].qede_tunn_clss;
2650 strcpy(str, qede_tunn_types[j].string);
2657 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2658 const struct rte_eth_tunnel_filter_conf *conf,
2661 /* Init commmon ucast params first */
2662 qede_set_ucast_cmn_params(ucast);
2664 /* Copy out the required fields based on classification type */
2668 case ECORE_FILTER_VNI:
2669 ucast->vni = conf->tenant_id;
2671 case ECORE_FILTER_INNER_VLAN:
2672 ucast->vlan = conf->inner_vlan;
2674 case ECORE_FILTER_MAC:
2675 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2678 case ECORE_FILTER_INNER_MAC:
2679 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2682 case ECORE_FILTER_MAC_VNI_PAIR:
2683 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2685 ucast->vni = conf->tenant_id;
2687 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2688 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2690 ucast->vni = conf->tenant_id;
2692 case ECORE_FILTER_INNER_PAIR:
2693 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2695 ucast->vlan = conf->inner_vlan;
2701 return ECORE_SUCCESS;
2705 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2706 const struct rte_eth_tunnel_filter_conf *conf,
2707 __attribute__((unused)) enum rte_filter_op filter_op,
2708 enum ecore_tunn_clss *clss,
2711 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2712 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2713 struct ecore_filter_ucast ucast = {0};
2714 enum ecore_filter_ucast_type type;
2715 uint16_t filter_type = 0;
2719 filter_type = conf->filter_type;
2720 /* Determine if the given filter classification is supported */
2721 qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2722 if (*clss == MAX_ECORE_TUNN_CLSS) {
2723 DP_ERR(edev, "Unsupported filter type\n");
2726 /* Init tunnel ucast params */
2727 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2728 if (rc != ECORE_SUCCESS) {
2729 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2733 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2734 str, filter_op, ucast.type);
2736 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2738 /* Skip MAC/VLAN if filter is based on VNI */
2739 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2740 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2741 if ((rc == 0) && add) {
2742 /* Enable accept anyvlan */
2743 qede_config_accept_any_vlan(qdev, true);
2746 rc = qede_ucast_filter(eth_dev, &ucast, add);
2748 rc = ecore_filter_ucast_cmd(edev, &ucast,
2749 ECORE_SPQ_MODE_CB, NULL);
2756 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2757 enum rte_filter_op filter_op,
2758 const struct rte_eth_tunnel_filter_conf *conf)
2760 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2761 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2762 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2766 PMD_INIT_FUNC_TRACE(edev);
2768 switch (filter_op) {
2769 case RTE_ETH_FILTER_ADD:
2772 case RTE_ETH_FILTER_DELETE:
2776 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2781 return qede_tunn_enable(eth_dev,
2782 ECORE_TUNN_CLSS_MAC_VLAN,
2783 conf->tunnel_type, add);
2785 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2786 if (rc != ECORE_SUCCESS)
2790 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2791 qdev->vxlan.num_filters++;
2792 qdev->vxlan.filter_type = conf->filter_type;
2793 } else { /* GENEVE */
2794 qdev->geneve.num_filters++;
2795 qdev->geneve.filter_type = conf->filter_type;
2798 if (!qdev->vxlan.enable || !qdev->geneve.enable)
2799 return qede_tunn_enable(eth_dev, clss,
2803 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2804 qdev->vxlan.num_filters--;
2806 qdev->geneve.num_filters--;
2808 /* Disable VXLAN if VXLAN filters become 0 */
2809 if ((qdev->vxlan.num_filters == 0) ||
2810 (qdev->geneve.num_filters == 0))
2811 return qede_tunn_enable(eth_dev, clss,
2819 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2820 enum rte_filter_type filter_type,
2821 enum rte_filter_op filter_op,
2824 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2825 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2826 struct rte_eth_tunnel_filter_conf *filter_conf =
2827 (struct rte_eth_tunnel_filter_conf *)arg;
2829 switch (filter_type) {
2830 case RTE_ETH_FILTER_TUNNEL:
2831 switch (filter_conf->tunnel_type) {
2832 case RTE_TUNNEL_TYPE_VXLAN:
2833 case RTE_TUNNEL_TYPE_GENEVE:
2835 "Packet steering to the specified Rx queue"
2836 " is not supported with UDP tunneling");
2837 return(qede_tunn_filter_config(eth_dev, filter_op,
2839 /* Place holders for future tunneling support */
2840 case RTE_TUNNEL_TYPE_TEREDO:
2841 case RTE_TUNNEL_TYPE_NVGRE:
2842 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2843 case RTE_L2_TUNNEL_TYPE_E_TAG:
2844 DP_ERR(edev, "Unsupported tunnel type %d\n",
2845 filter_conf->tunnel_type);
2847 case RTE_TUNNEL_TYPE_NONE:
2852 case RTE_ETH_FILTER_FDIR:
2853 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2854 case RTE_ETH_FILTER_NTUPLE:
2855 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2856 case RTE_ETH_FILTER_MACVLAN:
2857 case RTE_ETH_FILTER_ETHERTYPE:
2858 case RTE_ETH_FILTER_FLEXIBLE:
2859 case RTE_ETH_FILTER_SYN:
2860 case RTE_ETH_FILTER_HASH:
2861 case RTE_ETH_FILTER_L2_TUNNEL:
2862 case RTE_ETH_FILTER_MAX:
2864 DP_ERR(edev, "Unsupported filter type %d\n",
2872 static const struct eth_dev_ops qede_eth_dev_ops = {
2873 .dev_configure = qede_dev_configure,
2874 .dev_infos_get = qede_dev_info_get,
2875 .rx_queue_setup = qede_rx_queue_setup,
2876 .rx_queue_release = qede_rx_queue_release,
2877 .tx_queue_setup = qede_tx_queue_setup,
2878 .tx_queue_release = qede_tx_queue_release,
2879 .dev_start = qede_dev_start,
2880 .dev_set_link_up = qede_dev_set_link_up,
2881 .dev_set_link_down = qede_dev_set_link_down,
2882 .link_update = qede_link_update,
2883 .promiscuous_enable = qede_promiscuous_enable,
2884 .promiscuous_disable = qede_promiscuous_disable,
2885 .allmulticast_enable = qede_allmulticast_enable,
2886 .allmulticast_disable = qede_allmulticast_disable,
2887 .dev_stop = qede_dev_stop,
2888 .dev_close = qede_dev_close,
2889 .stats_get = qede_get_stats,
2890 .stats_reset = qede_reset_stats,
2891 .xstats_get = qede_get_xstats,
2892 .xstats_reset = qede_reset_xstats,
2893 .xstats_get_names = qede_get_xstats_names,
2894 .mac_addr_add = qede_mac_addr_add,
2895 .mac_addr_remove = qede_mac_addr_remove,
2896 .mac_addr_set = qede_mac_addr_set,
2897 .vlan_offload_set = qede_vlan_offload_set,
2898 .vlan_filter_set = qede_vlan_filter_set,
2899 .flow_ctrl_set = qede_flow_ctrl_set,
2900 .flow_ctrl_get = qede_flow_ctrl_get,
2901 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2902 .rss_hash_update = qede_rss_hash_update,
2903 .rss_hash_conf_get = qede_rss_hash_conf_get,
2904 .reta_update = qede_rss_reta_update,
2905 .reta_query = qede_rss_reta_query,
2906 .mtu_set = qede_set_mtu,
2907 .filter_ctrl = qede_dev_filter_ctrl,
2908 .udp_tunnel_port_add = qede_udp_dst_port_add,
2909 .udp_tunnel_port_del = qede_udp_dst_port_del,
2912 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2913 .dev_configure = qede_dev_configure,
2914 .dev_infos_get = qede_dev_info_get,
2915 .rx_queue_setup = qede_rx_queue_setup,
2916 .rx_queue_release = qede_rx_queue_release,
2917 .tx_queue_setup = qede_tx_queue_setup,
2918 .tx_queue_release = qede_tx_queue_release,
2919 .dev_start = qede_dev_start,
2920 .dev_set_link_up = qede_dev_set_link_up,
2921 .dev_set_link_down = qede_dev_set_link_down,
2922 .link_update = qede_link_update,
2923 .promiscuous_enable = qede_promiscuous_enable,
2924 .promiscuous_disable = qede_promiscuous_disable,
2925 .allmulticast_enable = qede_allmulticast_enable,
2926 .allmulticast_disable = qede_allmulticast_disable,
2927 .dev_stop = qede_dev_stop,
2928 .dev_close = qede_dev_close,
2929 .stats_get = qede_get_stats,
2930 .stats_reset = qede_reset_stats,
2931 .xstats_get = qede_get_xstats,
2932 .xstats_reset = qede_reset_xstats,
2933 .xstats_get_names = qede_get_xstats_names,
2934 .vlan_offload_set = qede_vlan_offload_set,
2935 .vlan_filter_set = qede_vlan_filter_set,
2936 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2937 .rss_hash_update = qede_rss_hash_update,
2938 .rss_hash_conf_get = qede_rss_hash_conf_get,
2939 .reta_update = qede_rss_reta_update,
2940 .reta_query = qede_rss_reta_query,
2941 .mtu_set = qede_set_mtu,
2942 .udp_tunnel_port_add = qede_udp_dst_port_add,
2943 .udp_tunnel_port_del = qede_udp_dst_port_del,
2946 static void qede_update_pf_params(struct ecore_dev *edev)
2948 struct ecore_pf_params pf_params;
2950 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2951 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2952 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2953 qed_ops->common->update_pf_params(edev, &pf_params);
2956 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2958 struct rte_pci_device *pci_dev;
2959 struct rte_pci_addr pci_addr;
2960 struct qede_dev *adapter;
2961 struct ecore_dev *edev;
2962 struct qed_dev_eth_info dev_info;
2963 struct qed_slowpath_params params;
2964 static bool do_once = true;
2965 uint8_t bulletin_change;
2966 uint8_t vf_mac[ETHER_ADDR_LEN];
2967 uint8_t is_mac_forced;
2969 /* Fix up ecore debug level */
2970 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2971 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2974 /* Extract key data structures */
2975 adapter = eth_dev->data->dev_private;
2976 adapter->ethdev = eth_dev;
2977 edev = &adapter->edev;
2978 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2979 pci_addr = pci_dev->addr;
2981 PMD_INIT_FUNC_TRACE(edev);
2983 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2984 pci_addr.bus, pci_addr.devid, pci_addr.function,
2985 eth_dev->data->port_id);
2987 eth_dev->rx_pkt_burst = qede_recv_pkts;
2988 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2989 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2991 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2992 DP_ERR(edev, "Skipping device init from secondary process\n");
2996 rte_eth_copy_pci_info(eth_dev, pci_dev);
2999 edev->vendor_id = pci_dev->id.vendor_id;
3000 edev->device_id = pci_dev->id.device_id;
3002 qed_ops = qed_get_eth_ops();
3004 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3008 DP_INFO(edev, "Starting qede probe\n");
3009 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3012 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3015 qede_update_pf_params(edev);
3016 rte_intr_callback_register(&pci_dev->intr_handle,
3017 qede_interrupt_handler, (void *)eth_dev);
3018 if (rte_intr_enable(&pci_dev->intr_handle)) {
3019 DP_ERR(edev, "rte_intr_enable() failed\n");
3023 /* Start the Slowpath-process */
3024 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
3025 params.int_mode = ECORE_INT_MODE_MSIX;
3026 params.drv_major = QEDE_PMD_VERSION_MAJOR;
3027 params.drv_minor = QEDE_PMD_VERSION_MINOR;
3028 params.drv_rev = QEDE_PMD_VERSION_REVISION;
3029 params.drv_eng = QEDE_PMD_VERSION_PATCH;
3030 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3031 QEDE_PMD_DRV_VER_STR_SIZE);
3033 /* For CMT mode device do periodic polling for slowpath events.
3034 * This is required since uio device uses only one MSI-x
3035 * interrupt vector but we need one for each engine.
3037 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3038 rc = rte_eal_alarm_set(timer_period * US_PER_S,
3042 DP_ERR(edev, "Unable to start periodic"
3043 " timer rc %d\n", rc);
3048 rc = qed_ops->common->slowpath_start(edev, ¶ms);
3050 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3051 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3056 rc = qed_ops->fill_dev_info(edev, &dev_info);
3058 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3059 qed_ops->common->slowpath_stop(edev);
3060 qed_ops->common->remove(edev);
3061 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3066 qede_alloc_etherdev(adapter, &dev_info);
3068 adapter->ops->common->set_name(edev, edev->name);
3071 adapter->dev_info.num_mac_filters =
3072 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3075 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3076 (uint32_t *)&adapter->dev_info.num_mac_filters);
3078 /* Allocate memory for storing MAC addr */
3079 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3081 adapter->dev_info.num_mac_filters),
3082 RTE_CACHE_LINE_SIZE);
3084 if (eth_dev->data->mac_addrs == NULL) {
3085 DP_ERR(edev, "Failed to allocate MAC address\n");
3086 qed_ops->common->slowpath_stop(edev);
3087 qed_ops->common->remove(edev);
3088 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3094 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3095 hw_info.hw_mac_addr,
3096 ð_dev->data->mac_addrs[0]);
3097 ether_addr_copy(ð_dev->data->mac_addrs[0],
3098 &adapter->primary_mac);
3100 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3102 if (bulletin_change) {
3104 ecore_vf_bulletin_get_forced_mac(
3105 ECORE_LEADING_HWFN(edev),
3108 if (is_mac_exist && is_mac_forced) {
3109 DP_INFO(edev, "VF macaddr received from PF\n");
3110 ether_addr_copy((struct ether_addr *)&vf_mac,
3111 ð_dev->data->mac_addrs[0]);
3112 ether_addr_copy(ð_dev->data->mac_addrs[0],
3113 &adapter->primary_mac);
3115 DP_ERR(edev, "No VF macaddr assigned\n");
3120 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3123 qede_print_adapter_info(adapter);
3127 /* Bring-up the link */
3128 qede_dev_set_link_state(eth_dev, true);
3130 adapter->num_tx_queues = 0;
3131 adapter->num_rx_queues = 0;
3132 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3133 SLIST_INIT(&adapter->vlan_list_head);
3134 SLIST_INIT(&adapter->uc_list_head);
3135 adapter->mtu = ETHER_MTU;
3136 adapter->vport_started = false;
3138 /* VF tunnel offloads is enabled by default in PF driver */
3139 adapter->vxlan.num_filters = 0;
3140 adapter->geneve.num_filters = 0;
3142 adapter->vxlan.enable = true;
3143 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3144 ETH_TUNNEL_FILTER_IVLAN;
3145 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3146 adapter->geneve.enable = true;
3148 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3149 ETH_TUNNEL_FILTER_IVLAN;
3150 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3152 adapter->vxlan.enable = false;
3153 adapter->geneve.enable = false;
3156 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3157 adapter->primary_mac.addr_bytes[0],
3158 adapter->primary_mac.addr_bytes[1],
3159 adapter->primary_mac.addr_bytes[2],
3160 adapter->primary_mac.addr_bytes[3],
3161 adapter->primary_mac.addr_bytes[4],
3162 adapter->primary_mac.addr_bytes[5]);
3164 DP_INFO(edev, "Device initialized\n");
3169 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3171 return qede_common_dev_init(eth_dev, 1);
3174 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3176 return qede_common_dev_init(eth_dev, 0);
3179 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3181 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3182 struct qede_dev *qdev = eth_dev->data->dev_private;
3183 struct ecore_dev *edev = &qdev->edev;
3185 PMD_INIT_FUNC_TRACE(edev);
3188 /* only uninitialize in the primary process */
3189 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3192 /* safe to close dev here */
3193 qede_dev_close(eth_dev);
3195 eth_dev->dev_ops = NULL;
3196 eth_dev->rx_pkt_burst = NULL;
3197 eth_dev->tx_pkt_burst = NULL;
3199 if (eth_dev->data->mac_addrs)
3200 rte_free(eth_dev->data->mac_addrs);
3202 eth_dev->data->mac_addrs = NULL;
3207 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3209 return qede_dev_common_uninit(eth_dev);
3212 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3214 return qede_dev_common_uninit(eth_dev);
3217 static const struct rte_pci_id pci_id_qedevf_map[] = {
3218 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3220 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3223 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3226 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3231 static const struct rte_pci_id pci_id_qede_map[] = {
3232 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3234 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3237 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3240 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3243 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3246 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3249 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3252 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3255 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3258 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3261 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3266 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3267 struct rte_pci_device *pci_dev)
3269 return rte_eth_dev_pci_generic_probe(pci_dev,
3270 sizeof(struct qede_dev), qedevf_eth_dev_init);
3273 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3275 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3278 static struct rte_pci_driver rte_qedevf_pmd = {
3279 .id_table = pci_id_qedevf_map,
3280 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3281 .probe = qedevf_eth_dev_pci_probe,
3282 .remove = qedevf_eth_dev_pci_remove,
3285 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3286 struct rte_pci_device *pci_dev)
3288 return rte_eth_dev_pci_generic_probe(pci_dev,
3289 sizeof(struct qede_dev), qede_eth_dev_init);
3292 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3294 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3297 static struct rte_pci_driver rte_qede_pmd = {
3298 .id_table = pci_id_qede_map,
3299 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3300 .probe = qede_eth_dev_pci_probe,
3301 .remove = qede_eth_dev_pci_remove,
3304 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3305 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3306 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3307 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3308 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3309 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3311 RTE_INIT(qede_init_log);
3315 qede_logtype_init = rte_log_register("pmd.net.qede.init");
3316 if (qede_logtype_init >= 0)
3317 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3318 qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3319 if (qede_logtype_driver >= 0)
3320 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);