drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(eth_dev->intr_handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 302 static void qede_print_adapter_info(struct qede_dev *qdev)
 303 {
 304         struct ecore_dev *edev = &qdev->edev;
 305         struct qed_dev_info *info = &qdev->dev_info.common;
 306         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 307         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 308
 309         DP_INFO(edev, "*********************************\n");
 310         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 311         DP_INFO(edev, " Chip details : %s%d\n",
 312                   ECORE_IS_BB(edev) ? "BB" : "AH",
 313                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 314         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 315                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 316         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 317                  ver_str, QEDE_PMD_VERSION);
 318         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 319         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 320
 321         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 322                  "%d.%d.%d.%d",
 323                 (info->mfw_rev >> 24) & 0xff,
 324                 (info->mfw_rev >> 16) & 0xff,
 325                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 326         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 327         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 328         DP_INFO(edev, "*********************************\n");
 329 }
 330 #endif
 331
 332 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 333 {
 334         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 335         ucast->is_rx_filter = true;
 336         ucast->is_tx_filter = true;
 337         /* ucast->assert_on_error = true; - For debug */
 338 }
 339
 340 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
 341                                     uint8_t clss, bool mode, bool mask)
 342 {
 343         memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
 344         p_tunn->vxlan.b_update_mode = mode;
 345         p_tunn->vxlan.b_mode_enabled = mask;
 346         p_tunn->b_update_rx_cls = true;
 347         p_tunn->b_update_tx_cls = true;
 348         p_tunn->vxlan.tun_cls = clss;
 349 }
 350
 351 static int
 352 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 353                   bool add)
 354 {
 355         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 356         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 357         struct qede_ucast_entry *tmp = NULL;
 358         struct qede_ucast_entry *u;
 359         struct ether_addr *mac_addr;
 360
 361         mac_addr  = (struct ether_addr *)ucast->mac;
 362         if (add) {
 363                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 364                         if ((memcmp(mac_addr, &tmp->mac,
 365                                     ETHER_ADDR_LEN) == 0) &&
 366                              ucast->vlan == tmp->vlan) {
 367                                 DP_ERR(edev, "Unicast MAC is already added"
 368                                        " with vlan = %u, vni = %u\n",
 369                                        ucast->vlan,  ucast->vni);
 370                                         return -EEXIST;
 371                         }
 372                 }
 373                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 374                                RTE_CACHE_LINE_SIZE);
 375                 if (!u) {
 376                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 377                         return -ENOMEM;
 378                 }
 379                 ether_addr_copy(mac_addr, &u->mac);
 380                 u->vlan = ucast->vlan;
 381                 u->vni = ucast->vni;
 382                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 383                 qdev->num_uc_addr++;
 384         } else {
 385                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 386                         if ((memcmp(mac_addr, &tmp->mac,
 387                                     ETHER_ADDR_LEN) == 0) &&
 388                             ucast->vlan == tmp->vlan      &&
 389                             ucast->vni == tmp->vni)
 390                         break;
 391                 }
 392                 if (tmp == NULL) {
 393                         DP_INFO(edev, "Unicast MAC is not found\n");
 394                         return -EINVAL;
 395                 }
 396                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 397                 qdev->num_uc_addr--;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int
 404 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 405                   bool add)
 406 {
 407         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 408         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 409         struct ether_addr *mac_addr;
 410         struct qede_mcast_entry *tmp = NULL;
 411         struct qede_mcast_entry *m;
 412
 413         mac_addr  = (struct ether_addr *)mcast->mac;
 414         if (add) {
 415                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 416                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 417                                 DP_ERR(edev,
 418                                         "Multicast MAC is already added\n");
 419                                 return -EEXIST;
 420                         }
 421                 }
 422                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 423                         RTE_CACHE_LINE_SIZE);
 424                 if (!m) {
 425                         DP_ERR(edev,
 426                                 "Did not allocate memory for mcast\n");
 427                         return -ENOMEM;
 428                 }
 429                 ether_addr_copy(mac_addr, &m->mac);
 430                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 431                 qdev->num_mc_addr++;
 432         } else {
 433                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 434                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 435                                 break;
 436                 }
 437                 if (tmp == NULL) {
 438                         DP_INFO(edev, "Multicast mac is not found\n");
 439                         return -EINVAL;
 440                 }
 441                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 442                              qede_mcast_entry, list);
 443                 qdev->num_mc_addr--;
 444         }
 445
 446         return 0;
 447 }
 448
 449 static enum _ecore_status_t
 450 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 451                  bool add)
 452 {
 453         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 454         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 455         enum _ecore_status_t rc;
 456         struct ecore_filter_mcast mcast;
 457         struct qede_mcast_entry *tmp;
 458         uint16_t j = 0;
 459
 460         /* Multicast */
 461         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 462                 if (add) {
 463                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 464                                 DP_ERR(edev,
 465                                        "Mcast filter table limit exceeded, "
 466                                        "Please enable mcast promisc mode\n");
 467                                 return -ECORE_INVAL;
 468                         }
 469                 }
 470                 rc = qede_mcast_filter(eth_dev, ucast, add);
 471                 if (rc == 0) {
 472                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 473                         memset(&mcast, 0, sizeof(mcast));
 474                         mcast.num_mc_addrs = qdev->num_mc_addr;
 475                         mcast.opcode = ECORE_FILTER_ADD;
 476                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 477                                 ether_addr_copy(&tmp->mac,
 478                                         (struct ether_addr *)&mcast.mac[j]);
 479                                 j++;
 480                         }
 481                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 482                                                     ECORE_SPQ_MODE_CB, NULL);
 483                 }
 484                 if (rc != ECORE_SUCCESS) {
 485                         DP_ERR(edev, "Failed to add multicast filter"
 486                                " rc = %d, op = %d\n", rc, add);
 487                 }
 488         } else { /* Unicast */
 489                 if (add) {
 490                         if (qdev->num_uc_addr >=
 491                             qdev->dev_info.num_mac_filters) {
 492                                 DP_ERR(edev,
 493                                        "Ucast filter table limit exceeded,"
 494                                        " Please enable promisc mode\n");
 495                                 return -ECORE_INVAL;
 496                         }
 497                 }
 498                 rc = qede_ucast_filter(eth_dev, ucast, add);
 499                 if (rc == 0)
 500                         rc = ecore_filter_ucast_cmd(edev, ucast,
 501                                                     ECORE_SPQ_MODE_CB, NULL);
 502                 if (rc != ECORE_SUCCESS) {
 503                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 504                                rc, add);
 505                 }
 506         }
 507
 508         return rc;
 509 }
 510
 511 static void
 512 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 513                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 514 {
 515         struct ecore_filter_ucast ucast;
 516
 517         qede_set_ucast_cmn_params(&ucast);
 518         ucast.type = ECORE_FILTER_MAC;
 519         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 520         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 521 }
 522
 523 static void
 524 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 525 {
 526         struct qede_dev *qdev = eth_dev->data->dev_private;
 527         struct ecore_dev *edev = &qdev->edev;
 528         struct ecore_filter_ucast ucast;
 529
 530         PMD_INIT_FUNC_TRACE(edev);
 531
 532         if (index >= qdev->dev_info.num_mac_filters) {
 533                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 534                        index, qdev->dev_info.num_mac_filters);
 535                 return;
 536         }
 537
 538         qede_set_ucast_cmn_params(&ucast);
 539         ucast.opcode = ECORE_FILTER_REMOVE;
 540         ucast.type = ECORE_FILTER_MAC;
 541
 542         /* Use the index maintained by rte */
 543         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 544                         (struct ether_addr *)&ucast.mac);
 545
 546         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 547 }
 548
 549 static void
 550 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 551 {
 552         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 553         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 554
 555         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 556                                                mac_addr->addr_bytes)) {
 557                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 558                 ether_addr_copy(&qdev->primary_mac,
 559                                 &eth_dev->data->mac_addrs[0]);
 560                 return;
 561         }
 562
 563         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 564 }
 565
 566 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 567 {
 568         struct ecore_dev *edev = &qdev->edev;
 569         struct qed_update_vport_params params = {
 570                 .vport_id = 0,
 571                 .accept_any_vlan = action,
 572                 .update_accept_any_vlan_flg = 1,
 573         };
 574         int rc;
 575
 576         /* Proceed only if action actually needs to be performed */
 577         if (qdev->accept_any_vlan == action)
 578                 return;
 579
 580         rc = qdev->ops->vport_update(edev, &params);
 581         if (rc) {
 582                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 583                        action ? "enable" : "disable");
 584         } else {
 585                 DP_INFO(edev, "%s accept-any-vlan\n",
 586                         action ? "enabled" : "disabled");
 587                 qdev->accept_any_vlan = action;
 588         }
 589 }
 590
 591 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 592 {
 593         struct qed_update_vport_params vport_update_params;
 594         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 595         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 596         int rc;
 597
 598         memset(&vport_update_params, 0, sizeof(vport_update_params));
 599         vport_update_params.vport_id = 0;
 600         vport_update_params.update_inner_vlan_removal_flg = 1;
 601         vport_update_params.inner_vlan_removal_flg = set_stripping;
 602         rc = qdev->ops->vport_update(edev, &vport_update_params);
 603         if (rc) {
 604                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 605                 return rc;
 606         }
 607         qdev->vlan_strip_flg = set_stripping;
 608
 609         return 0;
 610 }
 611
 612 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 613                                 uint16_t vlan_id, int on)
 614 {
 615         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 616         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 617         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 618         struct qede_vlan_entry *tmp = NULL;
 619         struct qede_vlan_entry *vlan;
 620         struct ecore_filter_ucast ucast;
 621         int rc;
 622
 623         if (on) {
 624                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 625                         DP_ERR(edev, "Reached max VLAN filter limit"
 626                                       " enabling accept_any_vlan\n");
 627                         qede_config_accept_any_vlan(qdev, true);
 628                         return 0;
 629                 }
 630
 631                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 632                         if (tmp->vid == vlan_id) {
 633                                 DP_ERR(edev, "VLAN %u already configured\n",
 634                                        vlan_id);
 635                                 return -EEXIST;
 636                         }
 637                 }
 638
 639                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 640                                   RTE_CACHE_LINE_SIZE);
 641
 642                 if (!vlan) {
 643                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 644                         return -ENOMEM;
 645                 }
 646
 647                 qede_set_ucast_cmn_params(&ucast);
 648                 ucast.opcode = ECORE_FILTER_ADD;
 649                 ucast.type = ECORE_FILTER_VLAN;
 650                 ucast.vlan = vlan_id;
 651                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 652                                             NULL);
 653                 if (rc != 0) {
 654                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 655                                rc);
 656                         rte_free(vlan);
 657                 } else {
 658                         vlan->vid = vlan_id;
 659                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 660                         qdev->configured_vlans++;
 661                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 662                                 vlan_id, qdev->configured_vlans);
 663                 }
 664         } else {
 665                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 666                         if (tmp->vid == vlan_id)
 667                                 break;
 668                 }
 669
 670                 if (!tmp) {
 671                         if (qdev->configured_vlans == 0) {
 672                                 DP_INFO(edev,
 673                                         "No VLAN filters configured yet\n");
 674                                 return 0;
 675                         }
 676
 677                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 678                         return -EINVAL;
 679                 }
 680
 681                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 682
 683                 qede_set_ucast_cmn_params(&ucast);
 684                 ucast.opcode = ECORE_FILTER_REMOVE;
 685                 ucast.type = ECORE_FILTER_VLAN;
 686                 ucast.vlan = vlan_id;
 687                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 688                                             NULL);
 689                 if (rc != 0) {
 690                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 691                                vlan_id, rc);
 692                 } else {
 693                         qdev->configured_vlans--;
 694                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 695                                 vlan_id, qdev->configured_vlans);
 696                 }
 697         }
 698
 699         return rc;
 700 }
 701
 702 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 703 {
 704         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 705         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 706         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 707
 708         if (mask & ETH_VLAN_STRIP_MASK) {
 709                 if (rxmode->hw_vlan_strip)
 710                         (void)qede_vlan_stripping(eth_dev, 1);
 711                 else
 712                         (void)qede_vlan_stripping(eth_dev, 0);
 713         }
 714
 715         if (mask & ETH_VLAN_FILTER_MASK) {
 716                 /* VLAN filtering kicks in when a VLAN is added */
 717                 if (rxmode->hw_vlan_filter) {
 718                         qede_vlan_filter_set(eth_dev, 0, 1);
 719                 } else {
 720                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 721                                 DP_ERR(edev,
 722                                   " Please remove existing VLAN filters"
 723                                   " before disabling VLAN filtering\n");
 724                                 /* Signal app that VLAN filtering is still
 725                                  * enabled
 726                                  */
 727                                 rxmode->hw_vlan_filter = true;
 728                         } else {
 729                                 qede_vlan_filter_set(eth_dev, 0, 0);
 730                         }
 731                 }
 732         }
 733
 734         if (mask & ETH_VLAN_EXTEND_MASK)
 735                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 736                         " and classification is based on outer tag only\n");
 737
 738         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 739                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 740 }
 741
 742 static int qede_init_vport(struct qede_dev *qdev)
 743 {
 744         struct ecore_dev *edev = &qdev->edev;
 745         struct qed_start_vport_params start = {0};
 746         int rc;
 747
 748         start.remove_inner_vlan = 1;
 749         start.enable_lro = qdev->enable_lro;
 750         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 751         start.vport_id = 0;
 752         start.drop_ttl0 = false;
 753         start.clear_stats = 1;
 754         start.handle_ptp_pkts = 0;
 755
 756         rc = qdev->ops->vport_start(edev, &start);
 757         if (rc) {
 758                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 759                 return rc;
 760         }
 761
 762         DP_INFO(edev,
 763                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 764                 start.vport_id, ETHER_MTU);
 765
 766         return 0;
 767 }
 768
 769 static void qede_prandom_bytes(uint32_t *buff)
 770 {
 771         uint8_t i;
 772
 773         srand((unsigned int)time(NULL));
 774         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 775                 buff[i] = rand();
 776 }
 777
 778 int qede_config_rss(struct rte_eth_dev *eth_dev)
 779 {
 780         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 781 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 782         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 783 #endif
 784         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 785         struct rte_eth_rss_reta_entry64 reta_conf[2];
 786         struct rte_eth_rss_conf rss_conf;
 787         uint32_t i, id, pos, q;
 788
 789         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 790         if (!rss_conf.rss_key) {
 791                 DP_INFO(edev, "Applying driver default key\n");
 792                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 793                 qede_prandom_bytes(&def_rss_key[0]);
 794                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 795         }
 796
 797         /* Configure RSS hash */
 798         if (qede_rss_hash_update(eth_dev, &rss_conf))
 799                 return -EINVAL;
 800
 801         /* Configure default RETA */
 802         memset(reta_conf, 0, sizeof(reta_conf));
 803         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 804                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 805
 806         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 807                 id = i / RTE_RETA_GROUP_SIZE;
 808                 pos = i % RTE_RETA_GROUP_SIZE;
 809                 q = i % QEDE_RSS_COUNT(qdev);
 810                 reta_conf[id].reta[pos] = q;
 811         }
 812         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 813                                  ECORE_RSS_IND_TABLE_SIZE))
 814                 return -EINVAL;
 815
 816         return 0;
 817 }
 818
 819 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 820 {
 821         struct qede_dev *qdev = eth_dev->data->dev_private;
 822         struct ecore_dev *edev = &qdev->edev;
 823         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 824         int rc;
 825
 826         PMD_INIT_FUNC_TRACE(edev);
 827
 828         /* Check requirements for 100G mode */
 829         if (edev->num_hwfns > 1) {
 830                 if (eth_dev->data->nb_rx_queues < 2 ||
 831                     eth_dev->data->nb_tx_queues < 2) {
 832                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
 833                         return -EINVAL;
 834                 }
 835
 836                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 837                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 838                         DP_ERR(edev,
 839                                   "100G mode needs even no. of RX/TX queues\n");
 840                         return -EINVAL;
 841                 }
 842         }
 843
 844         /* Sanity checks and throw warnings */
 845         if (rxmode->enable_scatter == 1)
 846                 eth_dev->data->scattered_rx = 1;
 847
 848         if (!rxmode->hw_strip_crc)
 849                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 850
 851         if (!rxmode->hw_ip_checksum)
 852                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 853                               "in hw\n");
 854
 855         if (rxmode->enable_lro) {
 856                 qdev->enable_lro = true;
 857                 /* Enable scatter mode for LRO */
 858                 if (!rxmode->enable_scatter)
 859                         eth_dev->data->scattered_rx = 1;
 860         }
 861
 862         /* Check for the port restart case */
 863         if (qdev->state != QEDE_DEV_INIT) {
 864                 rc = qdev->ops->vport_stop(edev, 0);
 865                 if (rc != 0)
 866                         return rc;
 867                 qede_dealloc_fp_resc(eth_dev);
 868         }
 869
 870         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 871         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 872         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 873
 874         /* Fastpath status block should be initialized before sending
 875          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 876          */
 877         rc = qede_alloc_fp_resc(qdev);
 878         if (rc != 0)
 879                 return rc;
 880
 881         /* Issue VPORT-START with default config values to allow
 882          * other port configurations early on.
 883          */
 884         rc = qede_init_vport(qdev);
 885         if (rc != 0)
 886                 return rc;
 887
 888         if (!(rxmode->mq_mode == ETH_MQ_RX_RSS ||
 889             rxmode->mq_mode == ETH_MQ_RX_NONE)) {
 890                 DP_ERR(edev, "Unsupported RSS mode\n");
 891                 qdev->ops->vport_stop(edev, 0);
 892                 qede_dealloc_fp_resc(eth_dev);
 893                 return -EINVAL;
 894         }
 895
 896         /* Flow director mode check */
 897         rc = qede_check_fdir_support(eth_dev);
 898         if (rc) {
 899                 qdev->ops->vport_stop(edev, 0);
 900                 qede_dealloc_fp_resc(eth_dev);
 901                 return -EINVAL;
 902         }
 903         SLIST_INIT(&qdev->fdir_info.fdir_list_head);
 904
 905         SLIST_INIT(&qdev->vlan_list_head);
 906
 907         /* Enable VLAN offloads by default */
 908         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 909                                        ETH_VLAN_FILTER_MASK |
 910                                        ETH_VLAN_EXTEND_MASK);
 911
 912         qdev->state = QEDE_DEV_CONFIG;
 913
 914         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 915                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 916                 qdev->num_tc);
 917
 918         return 0;
 919 }
 920
 921 /* Info about HW descriptor ring limitations */
 922 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 923         .nb_max = NUM_RX_BDS_MAX,
 924         .nb_min = 128,
 925         .nb_align = 128 /* lowest common multiple */
 926 };
 927
 928 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 929         .nb_max = NUM_TX_BDS_MAX,
 930         .nb_min = 256,
 931         .nb_align = 256,
 932         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
 933         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
 934 };
 935
 936 static void
 937 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 938                   struct rte_eth_dev_info *dev_info)
 939 {
 940         struct qede_dev *qdev = eth_dev->data->dev_private;
 941         struct ecore_dev *edev = &qdev->edev;
 942         struct qed_link_output link;
 943         uint32_t speed_cap = 0;
 944
 945         PMD_INIT_FUNC_TRACE(edev);
 946
 947         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 948         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
 949         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 950         dev_info->rx_desc_lim = qede_rx_desc_lim;
 951         dev_info->tx_desc_lim = qede_tx_desc_lim;
 952
 953         if (IS_PF(edev))
 954                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 955                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
 956         else
 957                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 958                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
 959         dev_info->max_tx_queues = dev_info->max_rx_queues;
 960
 961         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
 962         dev_info->max_vfs = 0;
 963         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 964         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 965         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 966
 967         dev_info->default_txconf = (struct rte_eth_txconf) {
 968                 .txq_flags = QEDE_TXQ_FLAGS,
 969         };
 970
 971         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
 972                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
 973                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
 974                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
 975                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 976                                      DEV_RX_OFFLOAD_TCP_LRO);
 977
 978         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 979                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
 980                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
 981                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
 982                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 983                                      DEV_TX_OFFLOAD_TCP_TSO |
 984                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
 985
 986         memset(&link, 0, sizeof(struct qed_link_output));
 987         qdev->ops->common->get_link(edev, &link);
 988         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 989                 speed_cap |= ETH_LINK_SPEED_1G;
 990         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 991                 speed_cap |= ETH_LINK_SPEED_10G;
 992         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 993                 speed_cap |= ETH_LINK_SPEED_25G;
 994         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 995                 speed_cap |= ETH_LINK_SPEED_40G;
 996         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 997                 speed_cap |= ETH_LINK_SPEED_50G;
 998         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 999                 speed_cap |= ETH_LINK_SPEED_100G;
1000         dev_info->speed_capa = speed_cap;
1001 }
1002
1003 /* return 0 means link status changed, -1 means not changed */
1004 static int
1005 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1006 {
1007         struct qede_dev *qdev = eth_dev->data->dev_private;
1008         struct ecore_dev *edev = &qdev->edev;
1009         uint16_t link_duplex;
1010         struct qed_link_output link;
1011         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1012
1013         memset(&link, 0, sizeof(struct qed_link_output));
1014         qdev->ops->common->get_link(edev, &link);
1015
1016         /* Link Speed */
1017         curr->link_speed = link.speed;
1018
1019         /* Link Mode */
1020         switch (link.duplex) {
1021         case QEDE_DUPLEX_HALF:
1022                 link_duplex = ETH_LINK_HALF_DUPLEX;
1023                 break;
1024         case QEDE_DUPLEX_FULL:
1025                 link_duplex = ETH_LINK_FULL_DUPLEX;
1026                 break;
1027         case QEDE_DUPLEX_UNKNOWN:
1028         default:
1029                 link_duplex = -1;
1030         }
1031         curr->link_duplex = link_duplex;
1032
1033         /* Link Status */
1034         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1035
1036         /* AN */
1037         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1038                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1039
1040         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1041                 curr->link_speed, curr->link_duplex,
1042                 curr->link_autoneg, curr->link_status);
1043
1044         /* return 0 means link status changed, -1 means not changed */
1045         return ((curr->link_status == link.link_up) ? -1 : 0);
1046 }
1047
1048 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1049 {
1050 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1051         struct qede_dev *qdev = eth_dev->data->dev_private;
1052         struct ecore_dev *edev = &qdev->edev;
1053
1054         PMD_INIT_FUNC_TRACE(edev);
1055 #endif
1056
1057         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1058
1059         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1060                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1061
1062         qed_configure_filter_rx_mode(eth_dev, type);
1063 }
1064
1065 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1066 {
1067 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1068         struct qede_dev *qdev = eth_dev->data->dev_private;
1069         struct ecore_dev *edev = &qdev->edev;
1070
1071         PMD_INIT_FUNC_TRACE(edev);
1072 #endif
1073
1074         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1075                 qed_configure_filter_rx_mode(eth_dev,
1076                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1077         else
1078                 qed_configure_filter_rx_mode(eth_dev,
1079                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1080 }
1081
1082 static void qede_poll_sp_sb_cb(void *param)
1083 {
1084         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1085         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1086         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1087         int rc;
1088
1089         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1090         qede_interrupt_action(&edev->hwfns[1]);
1091
1092         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1093                                qede_poll_sp_sb_cb,
1094                                (void *)eth_dev);
1095         if (rc != 0) {
1096                 DP_ERR(edev, "Unable to start periodic"
1097                              " timer rc %d\n", rc);
1098                 assert(false && "Unable to start periodic timer");
1099         }
1100 }
1101
1102 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1103 {
1104         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1105         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1106         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1107         int rc;
1108
1109         PMD_INIT_FUNC_TRACE(edev);
1110
1111         qede_fdir_dealloc_resc(eth_dev);
1112
1113         /* dev_stop() shall cleanup fp resources in hw but without releasing
1114          * dma memories and sw structures so that dev_start() can be called
1115          * by the app without reconfiguration. However, in dev_close() we
1116          * can release all the resources and device can be brought up newly
1117          */
1118         if (qdev->state != QEDE_DEV_STOP)
1119                 qede_dev_stop(eth_dev);
1120         else
1121                 DP_INFO(edev, "Device is already stopped\n");
1122
1123         rc = qdev->ops->vport_stop(edev, 0);
1124         if (rc != 0)
1125                 DP_ERR(edev, "Failed to stop VPORT\n");
1126
1127         qede_dealloc_fp_resc(eth_dev);
1128
1129         qdev->ops->common->slowpath_stop(edev);
1130
1131         qdev->ops->common->remove(edev);
1132
1133         rte_intr_disable(&pci_dev->intr_handle);
1134
1135         rte_intr_callback_unregister(&pci_dev->intr_handle,
1136                                      qede_interrupt_handler, (void *)eth_dev);
1137
1138         if (edev->num_hwfns > 1)
1139                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1140
1141         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1142 }
1143
1144 static void
1145 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1146 {
1147         struct qede_dev *qdev = eth_dev->data->dev_private;
1148         struct ecore_dev *edev = &qdev->edev;
1149         struct ecore_eth_stats stats;
1150         unsigned int i = 0, j = 0, qid;
1151         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1152         struct qede_tx_queue *txq;
1153
1154         qdev->ops->get_vport_stats(edev, &stats);
1155
1156         /* RX Stats */
1157         eth_stats->ipackets = stats.rx_ucast_pkts +
1158             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1159
1160         eth_stats->ibytes = stats.rx_ucast_bytes +
1161             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1162
1163         eth_stats->ierrors = stats.rx_crc_errors +
1164             stats.rx_align_errors +
1165             stats.rx_carrier_errors +
1166             stats.rx_oversize_packets +
1167             stats.rx_jabbers + stats.rx_undersize_packets;
1168
1169         eth_stats->rx_nombuf = stats.no_buff_discards;
1170
1171         eth_stats->imissed = stats.mftag_filter_discards +
1172             stats.mac_filter_discards +
1173             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1174
1175         /* TX stats */
1176         eth_stats->opackets = stats.tx_ucast_pkts +
1177             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1178
1179         eth_stats->obytes = stats.tx_ucast_bytes +
1180             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1181
1182         eth_stats->oerrors = stats.tx_err_drop_pkts;
1183
1184         /* Queue stats */
1185         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1186                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1187         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1188                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1189         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1190             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1191                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1192                        "Not all the queue stats will be displayed. Set"
1193                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1194                        " appropriately and retry.\n");
1195
1196         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1197                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1198                         eth_stats->q_ipackets[i] =
1199                                 *(uint64_t *)(
1200                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1201                                         offsetof(struct qede_rx_queue,
1202                                         rcv_pkts));
1203                         eth_stats->q_errors[i] =
1204                                 *(uint64_t *)(
1205                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1206                                         offsetof(struct qede_rx_queue,
1207                                         rx_hw_errors)) +
1208                                 *(uint64_t *)(
1209                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1210                                         offsetof(struct qede_rx_queue,
1211                                         rx_alloc_errors));
1212                         i++;
1213                 }
1214                 if (i == rxq_stat_cntrs)
1215                         break;
1216         }
1217
1218         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1219                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1220                         txq = qdev->fp_array[(qid)].txqs[0];
1221                         eth_stats->q_opackets[j] =
1222                                 *((uint64_t *)(uintptr_t)
1223                                         (((uint64_t)(uintptr_t)(txq)) +
1224                                          offsetof(struct qede_tx_queue,
1225                                                   xmit_pkts)));
1226                         j++;
1227                 }
1228                 if (j == txq_stat_cntrs)
1229                         break;
1230         }
1231 }
1232
1233 static unsigned
1234 qede_get_xstats_count(struct qede_dev *qdev) {
1235         return RTE_DIM(qede_xstats_strings) +
1236                 (RTE_DIM(qede_rxq_xstats_strings) *
1237                  RTE_MIN(QEDE_RSS_COUNT(qdev),
1238                          RTE_ETHDEV_QUEUE_STAT_CNTRS));
1239 }
1240
1241 static int
1242 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1243                       struct rte_eth_xstat_name *xstats_names,
1244                       __rte_unused unsigned int limit)
1245 {
1246         struct qede_dev *qdev = dev->data->dev_private;
1247         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1248         unsigned int i, qid, stat_idx = 0;
1249         unsigned int rxq_stat_cntrs;
1250
1251         if (xstats_names != NULL) {
1252                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1253                         snprintf(xstats_names[stat_idx].name,
1254                                 sizeof(xstats_names[stat_idx].name),
1255                                 "%s",
1256                                 qede_xstats_strings[i].name);
1257                         stat_idx++;
1258                 }
1259
1260                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1261                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1262                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1263                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1264                                 snprintf(xstats_names[stat_idx].name,
1265                                         sizeof(xstats_names[stat_idx].name),
1266                                         "%.4s%d%s",
1267                                         qede_rxq_xstats_strings[i].name, qid,
1268                                         qede_rxq_xstats_strings[i].name + 4);
1269                                 stat_idx++;
1270                         }
1271                 }
1272         }
1273
1274         return stat_cnt;
1275 }
1276
1277 static int
1278 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1279                 unsigned int n)
1280 {
1281         struct qede_dev *qdev = dev->data->dev_private;
1282         struct ecore_dev *edev = &qdev->edev;
1283         struct ecore_eth_stats stats;
1284         const unsigned int num = qede_get_xstats_count(qdev);
1285         unsigned int i, qid, stat_idx = 0;
1286         unsigned int rxq_stat_cntrs;
1287
1288         if (n < num)
1289                 return num;
1290
1291         qdev->ops->get_vport_stats(edev, &stats);
1292
1293         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1294                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1295                                              qede_xstats_strings[i].offset);
1296                 xstats[stat_idx].id = stat_idx;
1297                 stat_idx++;
1298         }
1299
1300         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1301                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1302         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1303                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1304                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1305                                 xstats[stat_idx].value = *(uint64_t *)(
1306                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1307                                          qede_rxq_xstats_strings[i].offset);
1308                                 xstats[stat_idx].id = stat_idx;
1309                                 stat_idx++;
1310                         }
1311                 }
1312         }
1313
1314         return stat_idx;
1315 }
1316
1317 static void
1318 qede_reset_xstats(struct rte_eth_dev *dev)
1319 {
1320         struct qede_dev *qdev = dev->data->dev_private;
1321         struct ecore_dev *edev = &qdev->edev;
1322
1323         ecore_reset_vport_stats(edev);
1324 }
1325
1326 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1327 {
1328         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1329         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1330         struct qed_link_params link_params;
1331         int rc;
1332
1333         DP_INFO(edev, "setting link state %d\n", link_up);
1334         memset(&link_params, 0, sizeof(link_params));
1335         link_params.link_up = link_up;
1336         rc = qdev->ops->common->set_link(edev, &link_params);
1337         if (rc != ECORE_SUCCESS)
1338                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1339
1340         return rc;
1341 }
1342
1343 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1344 {
1345         return qede_dev_set_link_state(eth_dev, true);
1346 }
1347
1348 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1349 {
1350         return qede_dev_set_link_state(eth_dev, false);
1351 }
1352
1353 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1354 {
1355         struct qede_dev *qdev = eth_dev->data->dev_private;
1356         struct ecore_dev *edev = &qdev->edev;
1357
1358         ecore_reset_vport_stats(edev);
1359 }
1360
1361 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1362 {
1363         enum qed_filter_rx_mode_type type =
1364             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1365
1366         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1367                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1368
1369         qed_configure_filter_rx_mode(eth_dev, type);
1370 }
1371
1372 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1373 {
1374         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1375                 qed_configure_filter_rx_mode(eth_dev,
1376                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1377         else
1378                 qed_configure_filter_rx_mode(eth_dev,
1379                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1380 }
1381
1382 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1383                               struct rte_eth_fc_conf *fc_conf)
1384 {
1385         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1386         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1387         struct qed_link_output current_link;
1388         struct qed_link_params params;
1389
1390         memset(&current_link, 0, sizeof(current_link));
1391         qdev->ops->common->get_link(edev, &current_link);
1392
1393         memset(&params, 0, sizeof(params));
1394         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1395         if (fc_conf->autoneg) {
1396                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1397                         DP_ERR(edev, "Autoneg not supported\n");
1398                         return -EINVAL;
1399                 }
1400                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1401         }
1402
1403         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1404         if (fc_conf->mode == RTE_FC_FULL)
1405                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1406                                         QED_LINK_PAUSE_RX_ENABLE);
1407         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1408                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1409         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1410                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1411
1412         params.link_up = true;
1413         (void)qdev->ops->common->set_link(edev, &params);
1414
1415         return 0;
1416 }
1417
1418 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1419                               struct rte_eth_fc_conf *fc_conf)
1420 {
1421         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1422         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1423         struct qed_link_output current_link;
1424
1425         memset(&current_link, 0, sizeof(current_link));
1426         qdev->ops->common->get_link(edev, &current_link);
1427
1428         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1429                 fc_conf->autoneg = true;
1430
1431         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1432                                          QED_LINK_PAUSE_TX_ENABLE))
1433                 fc_conf->mode = RTE_FC_FULL;
1434         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1435                 fc_conf->mode = RTE_FC_RX_PAUSE;
1436         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1437                 fc_conf->mode = RTE_FC_TX_PAUSE;
1438         else
1439                 fc_conf->mode = RTE_FC_NONE;
1440
1441         return 0;
1442 }
1443
1444 static const uint32_t *
1445 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1446 {
1447         static const uint32_t ptypes[] = {
1448                 RTE_PTYPE_L3_IPV4,
1449                 RTE_PTYPE_L3_IPV6,
1450                 RTE_PTYPE_UNKNOWN
1451         };
1452
1453         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1454                 return ptypes;
1455
1456         return NULL;
1457 }
1458
1459 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1460 {
1461         *rss_caps = 0;
1462         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1463         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1464         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1465         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1466         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1467         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1468         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1469         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1470 }
1471
1472 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1473                          struct rte_eth_rss_conf *rss_conf)
1474 {
1475         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1476         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1477         struct ecore_sp_vport_update_params vport_update_params;
1478         struct ecore_rss_params rss_params;
1479         struct ecore_hwfn *p_hwfn;
1480         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1481         uint64_t hf = rss_conf->rss_hf;
1482         uint8_t len = rss_conf->rss_key_len;
1483         uint8_t idx;
1484         uint8_t i;
1485         int rc;
1486
1487         memset(&vport_update_params, 0, sizeof(vport_update_params));
1488         memset(&rss_params, 0, sizeof(rss_params));
1489
1490         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1491                 (unsigned long)hf, len, key);
1492
1493         if (hf != 0) {
1494                 /* Enabling RSS */
1495                 DP_INFO(edev, "Enabling rss\n");
1496
1497                 /* RSS caps */
1498                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1499                 rss_params.update_rss_capabilities = 1;
1500
1501                 /* RSS hash key */
1502                 if (key) {
1503                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1504                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1505                                 return -EINVAL;
1506                         }
1507                         DP_INFO(edev, "Applying user supplied hash key\n");
1508                         rss_params.update_rss_key = 1;
1509                         memcpy(&rss_params.rss_key, key, len);
1510                 }
1511                 rss_params.rss_enable = 1;
1512         }
1513
1514         rss_params.update_rss_config = 1;
1515         /* tbl_size has to be set with capabilities */
1516         rss_params.rss_table_size_log = 7;
1517         vport_update_params.vport_id = 0;
1518         /* pass the L2 handles instead of qids */
1519         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1520                 idx = qdev->rss_ind_table[i];
1521                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1522         }
1523         vport_update_params.rss_params = &rss_params;
1524
1525         for_each_hwfn(edev, i) {
1526                 p_hwfn = &edev->hwfns[i];
1527                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1528                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1529                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1530                 if (rc) {
1531                         DP_ERR(edev, "vport-update for RSS failed\n");
1532                         return rc;
1533                 }
1534         }
1535         qdev->rss_enable = rss_params.rss_enable;
1536
1537         /* Update local structure for hash query */
1538         qdev->rss_conf.rss_hf = hf;
1539         qdev->rss_conf.rss_key_len = len;
1540         if (qdev->rss_enable) {
1541                 if  (qdev->rss_conf.rss_key == NULL) {
1542                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1543                         if (qdev->rss_conf.rss_key == NULL) {
1544                                 DP_ERR(edev, "No memory to store RSS key\n");
1545                                 return -ENOMEM;
1546                         }
1547                 }
1548                 if (key && len) {
1549                         DP_INFO(edev, "Storing RSS key\n");
1550                         memcpy(qdev->rss_conf.rss_key, key, len);
1551                 }
1552         } else if (!qdev->rss_enable && len == 0) {
1553                 if (qdev->rss_conf.rss_key) {
1554                         free(qdev->rss_conf.rss_key);
1555                         qdev->rss_conf.rss_key = NULL;
1556                         DP_INFO(edev, "Free RSS key\n");
1557                 }
1558         }
1559
1560         return 0;
1561 }
1562
1563 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1564                            struct rte_eth_rss_conf *rss_conf)
1565 {
1566         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1567
1568         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1569         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1570
1571         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1572                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1573                        rss_conf->rss_key_len);
1574         return 0;
1575 }
1576
1577 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1578                          struct rte_eth_rss_reta_entry64 *reta_conf,
1579                          uint16_t reta_size)
1580 {
1581         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1582         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1583         struct ecore_sp_vport_update_params vport_update_params;
1584         struct ecore_rss_params params;
1585         struct ecore_hwfn *p_hwfn;
1586         uint16_t i, idx, shift;
1587         uint8_t entry;
1588         int rc;
1589
1590         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1591                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1592                        reta_size);
1593                 return -EINVAL;
1594         }
1595
1596         memset(&vport_update_params, 0, sizeof(vport_update_params));
1597         memset(&params, 0, sizeof(params));
1598
1599         for (i = 0; i < reta_size; i++) {
1600                 idx = i / RTE_RETA_GROUP_SIZE;
1601                 shift = i % RTE_RETA_GROUP_SIZE;
1602                 if (reta_conf[idx].mask & (1ULL << shift)) {
1603                         entry = reta_conf[idx].reta[shift];
1604                         /* Pass rxq handles to ecore */
1605                         params.rss_ind_table[i] =
1606                                         qdev->fp_array[entry].rxq->handle;
1607                         /* Update the local copy for RETA query command */
1608                         qdev->rss_ind_table[i] = entry;
1609                 }
1610         }
1611
1612         /* Fix up RETA for CMT mode device */
1613         if (edev->num_hwfns > 1)
1614                 qdev->rss_enable = qed_update_rss_parm_cmt(edev,
1615                                         params.rss_ind_table[0]);
1616         params.update_rss_ind_table = 1;
1617         params.rss_table_size_log = 7;
1618         params.update_rss_config = 1;
1619         vport_update_params.vport_id = 0;
1620         /* Use the current value of rss_enable */
1621         params.rss_enable = qdev->rss_enable;
1622         vport_update_params.rss_params = &params;
1623
1624         for_each_hwfn(edev, i) {
1625                 p_hwfn = &edev->hwfns[i];
1626                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1627                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1628                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1629                 if (rc) {
1630                         DP_ERR(edev, "vport-update for RSS failed\n");
1631                         return rc;
1632                 }
1633         }
1634
1635         return 0;
1636 }
1637
1638 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1639                                struct rte_eth_rss_reta_entry64 *reta_conf,
1640                                uint16_t reta_size)
1641 {
1642         struct qede_dev *qdev = eth_dev->data->dev_private;
1643         struct ecore_dev *edev = &qdev->edev;
1644         uint16_t i, idx, shift;
1645         uint8_t entry;
1646
1647         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1648                 DP_ERR(edev, "reta_size %d is not supported\n",
1649                        reta_size);
1650                 return -EINVAL;
1651         }
1652
1653         for (i = 0; i < reta_size; i++) {
1654                 idx = i / RTE_RETA_GROUP_SIZE;
1655                 shift = i % RTE_RETA_GROUP_SIZE;
1656                 if (reta_conf[idx].mask & (1ULL << shift)) {
1657                         entry = qdev->rss_ind_table[i];
1658                         reta_conf[idx].reta[shift] = entry;
1659                 }
1660         }
1661
1662         return 0;
1663 }
1664
1665 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1666 {
1667         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1668         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1669         struct rte_eth_dev_info dev_info = {0};
1670         struct qede_fastpath *fp;
1671         uint32_t frame_size;
1672         uint16_t rx_buf_size;
1673         uint16_t bufsz;
1674         int i;
1675
1676         PMD_INIT_FUNC_TRACE(edev);
1677         qede_dev_info_get(dev, &dev_info);
1678         frame_size = mtu + QEDE_ETH_OVERHEAD;
1679         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1680                 DP_ERR(edev, "MTU %u out of range\n", mtu);
1681                 return -EINVAL;
1682         }
1683         if (!dev->data->scattered_rx &&
1684             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1685                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
1686                         dev->data->min_rx_buf_size);
1687                 return -EINVAL;
1688         }
1689         /* Temporarily replace I/O functions with dummy ones. It cannot
1690          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1691          */
1692         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
1693         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
1694         qede_dev_stop(dev);
1695         rte_delay_ms(1000);
1696         qdev->mtu = mtu;
1697         /* Fix up RX buf size for all queues of the port */
1698         for_each_queue(i) {
1699                 fp = &qdev->fp_array[i];
1700                 if (fp->type & QEDE_FASTPATH_RX) {
1701                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
1702                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1703                         if (dev->data->scattered_rx)
1704                                 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
1705                         else
1706                                 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
1707                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
1708                         fp->rxq->rx_buf_size = rx_buf_size;
1709                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
1710                 }
1711         }
1712         qede_dev_start(dev);
1713         if (frame_size > ETHER_MAX_LEN)
1714                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1715         else
1716                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1717         /* update max frame size */
1718         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1719         /* Reassign back */
1720         dev->rx_pkt_burst = qede_recv_pkts;
1721         dev->tx_pkt_burst = qede_xmit_pkts;
1722
1723         return 0;
1724 }
1725
1726 static int
1727 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1728                        struct rte_eth_udp_tunnel *tunnel_udp,
1729                        bool add)
1730 {
1731         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1732         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1733         struct ecore_tunnel_info tunn; /* @DPDK */
1734         struct ecore_hwfn *p_hwfn;
1735         int rc, i;
1736
1737         PMD_INIT_FUNC_TRACE(edev);
1738
1739         memset(&tunn, 0, sizeof(tunn));
1740         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1741                 tunn.vxlan_port.b_update_port = true;
1742                 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
1743                                                   QEDE_VXLAN_DEF_PORT;
1744                 for_each_hwfn(edev, i) {
1745                         p_hwfn = &edev->hwfns[i];
1746                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1747                                                 ECORE_SPQ_MODE_CB, NULL);
1748                         if (rc != ECORE_SUCCESS) {
1749                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1750                                        tunn.vxlan_port.port);
1751                                 return rc;
1752                         }
1753                 }
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int
1760 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1761                       struct rte_eth_udp_tunnel *tunnel_udp)
1762 {
1763         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1764 }
1765
1766 static int
1767 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1768                       struct rte_eth_udp_tunnel *tunnel_udp)
1769 {
1770         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1771 }
1772
1773 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1774                                        uint32_t *clss, char *str)
1775 {
1776         uint16_t j;
1777         *clss = MAX_ECORE_TUNN_CLSS;
1778
1779         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1780                 if (filter == qede_tunn_types[j].rte_filter_type) {
1781                         *type = qede_tunn_types[j].qede_type;
1782                         *clss = qede_tunn_types[j].qede_tunn_clss;
1783                         strcpy(str, qede_tunn_types[j].string);
1784                         return;
1785                 }
1786         }
1787 }
1788
1789 static int
1790 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1791                               const struct rte_eth_tunnel_filter_conf *conf,
1792                               uint32_t type)
1793 {
1794         /* Init commmon ucast params first */
1795         qede_set_ucast_cmn_params(ucast);
1796
1797         /* Copy out the required fields based on classification type */
1798         ucast->type = type;
1799
1800         switch (type) {
1801         case ECORE_FILTER_VNI:
1802                 ucast->vni = conf->tenant_id;
1803         break;
1804         case ECORE_FILTER_INNER_VLAN:
1805                 ucast->vlan = conf->inner_vlan;
1806         break;
1807         case ECORE_FILTER_MAC:
1808                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1809                        ETHER_ADDR_LEN);
1810         break;
1811         case ECORE_FILTER_INNER_MAC:
1812                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1813                        ETHER_ADDR_LEN);
1814         break;
1815         case ECORE_FILTER_MAC_VNI_PAIR:
1816                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1817                         ETHER_ADDR_LEN);
1818                 ucast->vni = conf->tenant_id;
1819         break;
1820         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1821                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1822                         ETHER_ADDR_LEN);
1823                 ucast->vni = conf->tenant_id;
1824         break;
1825         case ECORE_FILTER_INNER_PAIR:
1826                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1827                         ETHER_ADDR_LEN);
1828                 ucast->vlan = conf->inner_vlan;
1829         break;
1830         default:
1831                 return -EINVAL;
1832         }
1833
1834         return ECORE_SUCCESS;
1835 }
1836
1837 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1838                                   enum rte_filter_op filter_op,
1839                                   const struct rte_eth_tunnel_filter_conf *conf)
1840 {
1841         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1842         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1843         struct ecore_tunnel_info tunn;
1844         struct ecore_hwfn *p_hwfn;
1845         enum ecore_filter_ucast_type type;
1846         enum ecore_tunn_clss clss;
1847         struct ecore_filter_ucast ucast;
1848         char str[80];
1849         uint16_t filter_type;
1850         int rc, i;
1851
1852         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1853         /* First determine if the given filter classification is supported */
1854         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1855         if (clss == MAX_ECORE_TUNN_CLSS) {
1856                 DP_ERR(edev, "Wrong filter type\n");
1857                 return -EINVAL;
1858         }
1859         /* Init tunnel ucast params */
1860         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1861         if (rc != ECORE_SUCCESS) {
1862                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1863                                 conf->filter_type);
1864                 return rc;
1865         }
1866         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1867                 str, filter_op, ucast.type);
1868         switch (filter_op) {
1869         case RTE_ETH_FILTER_ADD:
1870                 ucast.opcode = ECORE_FILTER_ADD;
1871
1872                 /* Skip MAC/VLAN if filter is based on VNI */
1873                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1874                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1875                         if (rc == 0) {
1876                                 /* Enable accept anyvlan */
1877                                 qede_config_accept_any_vlan(qdev, true);
1878                         }
1879                 } else {
1880                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1881                         if (rc == 0)
1882                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1883                                                     ECORE_SPQ_MODE_CB, NULL);
1884                 }
1885
1886                 if (rc != ECORE_SUCCESS)
1887                         return rc;
1888
1889                 qdev->vxlan_filter_type = filter_type;
1890
1891                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1892                 qede_set_cmn_tunn_param(&tunn, clss, true, true);
1893                 for_each_hwfn(edev, i) {
1894                         p_hwfn = &edev->hwfns[i];
1895                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1896                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
1897                         if (rc != ECORE_SUCCESS) {
1898                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1899                                        tunn.vxlan.tun_cls);
1900                         }
1901                 }
1902                 qdev->num_tunn_filters++; /* Filter added successfully */
1903         break;
1904         case RTE_ETH_FILTER_DELETE:
1905                 ucast.opcode = ECORE_FILTER_REMOVE;
1906
1907                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1908                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1909                 } else {
1910                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1911                         if (rc == 0)
1912                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1913                                                     ECORE_SPQ_MODE_CB, NULL);
1914                 }
1915                 if (rc != ECORE_SUCCESS)
1916                         return rc;
1917
1918                 qdev->vxlan_filter_type = filter_type;
1919                 qdev->num_tunn_filters--;
1920
1921                 /* Disable VXLAN if VXLAN filters become 0 */
1922                 if (qdev->num_tunn_filters == 0) {
1923                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1924
1925                         /* Use 0 as tunnel mode */
1926                         qede_set_cmn_tunn_param(&tunn, clss, false, true);
1927                         for_each_hwfn(edev, i) {
1928                                 p_hwfn = &edev->hwfns[i];
1929                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1930                                         ECORE_SPQ_MODE_CB, NULL);
1931                                 if (rc != ECORE_SUCCESS) {
1932                                         DP_ERR(edev,
1933                                                 "Failed to update tunn_clss %u\n",
1934                                                 tunn.vxlan.tun_cls);
1935                                         break;
1936                                 }
1937                         }
1938                 }
1939         break;
1940         default:
1941                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1942                 return -EINVAL;
1943         }
1944         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1945
1946         return 0;
1947 }
1948
1949 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1950                          enum rte_filter_type filter_type,
1951                          enum rte_filter_op filter_op,
1952                          void *arg)
1953 {
1954         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1955         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1956         struct rte_eth_tunnel_filter_conf *filter_conf =
1957                         (struct rte_eth_tunnel_filter_conf *)arg;
1958
1959         switch (filter_type) {
1960         case RTE_ETH_FILTER_TUNNEL:
1961                 switch (filter_conf->tunnel_type) {
1962                 case RTE_TUNNEL_TYPE_VXLAN:
1963                         DP_INFO(edev,
1964                                 "Packet steering to the specified Rx queue"
1965                                 " is not supported with VXLAN tunneling");
1966                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
1967                                                       filter_conf));
1968                 /* Place holders for future tunneling support */
1969                 case RTE_TUNNEL_TYPE_GENEVE:
1970                 case RTE_TUNNEL_TYPE_TEREDO:
1971                 case RTE_TUNNEL_TYPE_NVGRE:
1972                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1973                 case RTE_L2_TUNNEL_TYPE_E_TAG:
1974                         DP_ERR(edev, "Unsupported tunnel type %d\n",
1975                                 filter_conf->tunnel_type);
1976                         return -EINVAL;
1977                 case RTE_TUNNEL_TYPE_NONE:
1978                 default:
1979                         return 0;
1980                 }
1981                 break;
1982         case RTE_ETH_FILTER_FDIR:
1983                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
1984         case RTE_ETH_FILTER_NTUPLE:
1985                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
1986         case RTE_ETH_FILTER_MACVLAN:
1987         case RTE_ETH_FILTER_ETHERTYPE:
1988         case RTE_ETH_FILTER_FLEXIBLE:
1989         case RTE_ETH_FILTER_SYN:
1990         case RTE_ETH_FILTER_HASH:
1991         case RTE_ETH_FILTER_L2_TUNNEL:
1992         case RTE_ETH_FILTER_MAX:
1993         default:
1994                 DP_ERR(edev, "Unsupported filter type %d\n",
1995                         filter_type);
1996                 return -EINVAL;
1997         }
1998
1999         return 0;
2000 }
2001
2002 static const struct eth_dev_ops qede_eth_dev_ops = {
2003         .dev_configure = qede_dev_configure,
2004         .dev_infos_get = qede_dev_info_get,
2005         .rx_queue_setup = qede_rx_queue_setup,
2006         .rx_queue_release = qede_rx_queue_release,
2007         .tx_queue_setup = qede_tx_queue_setup,
2008         .tx_queue_release = qede_tx_queue_release,
2009         .dev_start = qede_dev_start,
2010         .dev_set_link_up = qede_dev_set_link_up,
2011         .dev_set_link_down = qede_dev_set_link_down,
2012         .link_update = qede_link_update,
2013         .promiscuous_enable = qede_promiscuous_enable,
2014         .promiscuous_disable = qede_promiscuous_disable,
2015         .allmulticast_enable = qede_allmulticast_enable,
2016         .allmulticast_disable = qede_allmulticast_disable,
2017         .dev_stop = qede_dev_stop,
2018         .dev_close = qede_dev_close,
2019         .stats_get = qede_get_stats,
2020         .stats_reset = qede_reset_stats,
2021         .xstats_get = qede_get_xstats,
2022         .xstats_reset = qede_reset_xstats,
2023         .xstats_get_names = qede_get_xstats_names,
2024         .mac_addr_add = qede_mac_addr_add,
2025         .mac_addr_remove = qede_mac_addr_remove,
2026         .mac_addr_set = qede_mac_addr_set,
2027         .vlan_offload_set = qede_vlan_offload_set,
2028         .vlan_filter_set = qede_vlan_filter_set,
2029         .flow_ctrl_set = qede_flow_ctrl_set,
2030         .flow_ctrl_get = qede_flow_ctrl_get,
2031         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2032         .rss_hash_update = qede_rss_hash_update,
2033         .rss_hash_conf_get = qede_rss_hash_conf_get,
2034         .reta_update  = qede_rss_reta_update,
2035         .reta_query  = qede_rss_reta_query,
2036         .mtu_set = qede_set_mtu,
2037         .filter_ctrl = qede_dev_filter_ctrl,
2038         .udp_tunnel_port_add = qede_udp_dst_port_add,
2039         .udp_tunnel_port_del = qede_udp_dst_port_del,
2040 };
2041
2042 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2043         .dev_configure = qede_dev_configure,
2044         .dev_infos_get = qede_dev_info_get,
2045         .rx_queue_setup = qede_rx_queue_setup,
2046         .rx_queue_release = qede_rx_queue_release,
2047         .tx_queue_setup = qede_tx_queue_setup,
2048         .tx_queue_release = qede_tx_queue_release,
2049         .dev_start = qede_dev_start,
2050         .dev_set_link_up = qede_dev_set_link_up,
2051         .dev_set_link_down = qede_dev_set_link_down,
2052         .link_update = qede_link_update,
2053         .promiscuous_enable = qede_promiscuous_enable,
2054         .promiscuous_disable = qede_promiscuous_disable,
2055         .allmulticast_enable = qede_allmulticast_enable,
2056         .allmulticast_disable = qede_allmulticast_disable,
2057         .dev_stop = qede_dev_stop,
2058         .dev_close = qede_dev_close,
2059         .stats_get = qede_get_stats,
2060         .stats_reset = qede_reset_stats,
2061         .xstats_get = qede_get_xstats,
2062         .xstats_reset = qede_reset_xstats,
2063         .xstats_get_names = qede_get_xstats_names,
2064         .vlan_offload_set = qede_vlan_offload_set,
2065         .vlan_filter_set = qede_vlan_filter_set,
2066         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2067         .rss_hash_update = qede_rss_hash_update,
2068         .rss_hash_conf_get = qede_rss_hash_conf_get,
2069         .reta_update  = qede_rss_reta_update,
2070         .reta_query  = qede_rss_reta_query,
2071         .mtu_set = qede_set_mtu,
2072 };
2073
2074 static void qede_update_pf_params(struct ecore_dev *edev)
2075 {
2076         struct ecore_pf_params pf_params;
2077
2078         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2079         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2080         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2081         qed_ops->common->update_pf_params(edev, &pf_params);
2082 }
2083
2084 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2085 {
2086         struct rte_pci_device *pci_dev;
2087         struct rte_pci_addr pci_addr;
2088         struct qede_dev *adapter;
2089         struct ecore_dev *edev;
2090         struct qed_dev_eth_info dev_info;
2091         struct qed_slowpath_params params;
2092         static bool do_once = true;
2093         uint8_t bulletin_change;
2094         uint8_t vf_mac[ETHER_ADDR_LEN];
2095         uint8_t is_mac_forced;
2096         bool is_mac_exist;
2097         /* Fix up ecore debug level */
2098         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2099         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2100         int rc;
2101
2102         /* Extract key data structures */
2103         adapter = eth_dev->data->dev_private;
2104         edev = &adapter->edev;
2105         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2106         pci_addr = pci_dev->addr;
2107
2108         PMD_INIT_FUNC_TRACE(edev);
2109
2110         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2111                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2112                  eth_dev->data->port_id);
2113
2114         eth_dev->rx_pkt_burst = qede_recv_pkts;
2115         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2116         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2117
2118         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2119                 DP_NOTICE(edev, false,
2120                           "Skipping device init from secondary process\n");
2121                 return 0;
2122         }
2123
2124         rte_eth_copy_pci_info(eth_dev, pci_dev);
2125
2126         /* @DPDK */
2127         edev->vendor_id = pci_dev->id.vendor_id;
2128         edev->device_id = pci_dev->id.device_id;
2129
2130         qed_ops = qed_get_eth_ops();
2131         if (!qed_ops) {
2132                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2133                 return -EINVAL;
2134         }
2135
2136         DP_INFO(edev, "Starting qede probe\n");
2137
2138         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
2139                                     dp_module, dp_level, is_vf);
2140
2141         if (rc != 0) {
2142                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2143                 return -ENODEV;
2144         }
2145
2146         qede_update_pf_params(edev);
2147
2148         rte_intr_callback_register(&pci_dev->intr_handle,
2149                                    qede_interrupt_handler, (void *)eth_dev);
2150
2151         if (rte_intr_enable(&pci_dev->intr_handle)) {
2152                 DP_ERR(edev, "rte_intr_enable() failed\n");
2153                 return -ENODEV;
2154         }
2155
2156         /* Start the Slowpath-process */
2157         memset(&params, 0, sizeof(struct qed_slowpath_params));
2158         params.int_mode = ECORE_INT_MODE_MSIX;
2159         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2160         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2161         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2162         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2163         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2164                 QEDE_PMD_DRV_VER_STR_SIZE);
2165
2166         /* For CMT mode device do periodic polling for slowpath events.
2167          * This is required since uio device uses only one MSI-x
2168          * interrupt vector but we need one for each engine.
2169          */
2170         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2171                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2172                                        qede_poll_sp_sb_cb,
2173                                        (void *)eth_dev);
2174                 if (rc != 0) {
2175                         DP_ERR(edev, "Unable to start periodic"
2176                                      " timer rc %d\n", rc);
2177                         return -EINVAL;
2178                 }
2179         }
2180
2181         rc = qed_ops->common->slowpath_start(edev, &params);
2182         if (rc) {
2183                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2184                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2185                                      (void *)eth_dev);
2186                 return -ENODEV;
2187         }
2188
2189         rc = qed_ops->fill_dev_info(edev, &dev_info);
2190         if (rc) {
2191                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2192                 qed_ops->common->slowpath_stop(edev);
2193                 qed_ops->common->remove(edev);
2194                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2195                                      (void *)eth_dev);
2196                 return -ENODEV;
2197         }
2198
2199         qede_alloc_etherdev(adapter, &dev_info);
2200
2201         adapter->ops->common->set_name(edev, edev->name);
2202
2203         if (!is_vf)
2204                 adapter->dev_info.num_mac_filters =
2205                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2206                                             ECORE_MAC);
2207         else
2208                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2209                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2210
2211         /* Allocate memory for storing MAC addr */
2212         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2213                                         (ETHER_ADDR_LEN *
2214                                         adapter->dev_info.num_mac_filters),
2215                                         RTE_CACHE_LINE_SIZE);
2216
2217         if (eth_dev->data->mac_addrs == NULL) {
2218                 DP_ERR(edev, "Failed to allocate MAC address\n");
2219                 qed_ops->common->slowpath_stop(edev);
2220                 qed_ops->common->remove(edev);
2221                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2222                                      (void *)eth_dev);
2223                 return -ENOMEM;
2224         }
2225
2226         if (!is_vf) {
2227                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2228                                 hw_info.hw_mac_addr,
2229                                 &eth_dev->data->mac_addrs[0]);
2230                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2231                                 &adapter->primary_mac);
2232         } else {
2233                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2234                                        &bulletin_change);
2235                 if (bulletin_change) {
2236                         is_mac_exist =
2237                             ecore_vf_bulletin_get_forced_mac(
2238                                                 ECORE_LEADING_HWFN(edev),
2239                                                 vf_mac,
2240                                                 &is_mac_forced);
2241                         if (is_mac_exist && is_mac_forced) {
2242                                 DP_INFO(edev, "VF macaddr received from PF\n");
2243                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2244                                                 &eth_dev->data->mac_addrs[0]);
2245                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2246                                                 &adapter->primary_mac);
2247                         } else {
2248                                 DP_NOTICE(edev, false,
2249                                           "No VF macaddr assigned\n");
2250                         }
2251                 }
2252         }
2253
2254         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2255
2256         if (do_once) {
2257 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2258                 qede_print_adapter_info(adapter);
2259 #endif
2260                 do_once = false;
2261         }
2262
2263         adapter->state = QEDE_DEV_INIT;
2264
2265         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2266                   adapter->primary_mac.addr_bytes[0],
2267                   adapter->primary_mac.addr_bytes[1],
2268                   adapter->primary_mac.addr_bytes[2],
2269                   adapter->primary_mac.addr_bytes[3],
2270                   adapter->primary_mac.addr_bytes[4],
2271                   adapter->primary_mac.addr_bytes[5]);
2272
2273         return rc;
2274 }
2275
2276 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2277 {
2278         return qede_common_dev_init(eth_dev, 1);
2279 }
2280
2281 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2282 {
2283         return qede_common_dev_init(eth_dev, 0);
2284 }
2285
2286 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2287 {
2288         /* only uninitialize in the primary process */
2289         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2290                 return 0;
2291
2292         /* safe to close dev here */
2293         qede_dev_close(eth_dev);
2294
2295         eth_dev->dev_ops = NULL;
2296         eth_dev->rx_pkt_burst = NULL;
2297         eth_dev->tx_pkt_burst = NULL;
2298
2299         if (eth_dev->data->mac_addrs)
2300                 rte_free(eth_dev->data->mac_addrs);
2301
2302         eth_dev->data->mac_addrs = NULL;
2303
2304         return 0;
2305 }
2306
2307 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2308 {
2309         return qede_dev_common_uninit(eth_dev);
2310 }
2311
2312 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2313 {
2314         return qede_dev_common_uninit(eth_dev);
2315 }
2316
2317 static const struct rte_pci_id pci_id_qedevf_map[] = {
2318 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2319         {
2320                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2321         },
2322         {
2323                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2324         },
2325         {
2326                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2327         },
2328         {.vendor_id = 0,}
2329 };
2330
2331 static const struct rte_pci_id pci_id_qede_map[] = {
2332 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2333         {
2334                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2335         },
2336         {
2337                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2338         },
2339         {
2340                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2341         },
2342         {
2343                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2344         },
2345         {
2346                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2347         },
2348         {
2349                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2350         },
2351         {
2352                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2353         },
2354         {
2355                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2356         },
2357         {
2358                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2359         },
2360         {
2361                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2362         },
2363         {.vendor_id = 0,}
2364 };
2365
2366 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2367         struct rte_pci_device *pci_dev)
2368 {
2369         return rte_eth_dev_pci_generic_probe(pci_dev,
2370                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2371 }
2372
2373 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2374 {
2375         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2376 }
2377
2378 static struct rte_pci_driver rte_qedevf_pmd = {
2379         .id_table = pci_id_qedevf_map,
2380         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2381         .probe = qedevf_eth_dev_pci_probe,
2382         .remove = qedevf_eth_dev_pci_remove,
2383 };
2384
2385 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2386         struct rte_pci_device *pci_dev)
2387 {
2388         return rte_eth_dev_pci_generic_probe(pci_dev,
2389                 sizeof(struct qede_dev), qede_eth_dev_init);
2390 }
2391
2392 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2393 {
2394         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2395 }
2396
2397 static struct rte_pci_driver rte_qede_pmd = {
2398         .id_table = pci_id_qede_map,
2399         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2400         .probe = qede_eth_dev_pci_probe,
2401         .remove = qede_eth_dev_pci_remove,
2402 };
2403
2404 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2405 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2406 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2407 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2408 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2409 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");