drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 static const struct qed_eth_ops *qed_ops;
  14 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  15 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  16
  17 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  18
  19 struct rte_qede_xstats_name_off {
  20         char name[RTE_ETH_XSTATS_NAME_SIZE];
  21         uint64_t offset;
  22 };
  23
  24 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  25         {"rx_unicast_bytes",
  26                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  27         {"rx_multicast_bytes",
  28                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  29         {"rx_broadcast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  31         {"rx_unicast_packets",
  32                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  33         {"rx_multicast_packets",
  34                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  35         {"rx_broadcast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  37
  38         {"tx_unicast_bytes",
  39                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  40         {"tx_multicast_bytes",
  41                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  42         {"tx_broadcast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  44         {"tx_unicast_packets",
  45                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  46         {"tx_multicast_packets",
  47                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  48         {"tx_broadcast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  50
  51         {"rx_64_byte_packets",
  52                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  53         {"rx_65_to_127_byte_packets",
  54                 offsetof(struct ecore_eth_stats_common,
  55                          rx_65_to_127_byte_packets)},
  56         {"rx_128_to_255_byte_packets",
  57                 offsetof(struct ecore_eth_stats_common,
  58                          rx_128_to_255_byte_packets)},
  59         {"rx_256_to_511_byte_packets",
  60                 offsetof(struct ecore_eth_stats_common,
  61                          rx_256_to_511_byte_packets)},
  62         {"rx_512_to_1023_byte_packets",
  63                 offsetof(struct ecore_eth_stats_common,
  64                          rx_512_to_1023_byte_packets)},
  65         {"rx_1024_to_1518_byte_packets",
  66                 offsetof(struct ecore_eth_stats_common,
  67                          rx_1024_to_1518_byte_packets)},
  68         {"tx_64_byte_packets",
  69                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  70         {"tx_65_to_127_byte_packets",
  71                 offsetof(struct ecore_eth_stats_common,
  72                          tx_65_to_127_byte_packets)},
  73         {"tx_128_to_255_byte_packets",
  74                 offsetof(struct ecore_eth_stats_common,
  75                          tx_128_to_255_byte_packets)},
  76         {"tx_256_to_511_byte_packets",
  77                 offsetof(struct ecore_eth_stats_common,
  78                          tx_256_to_511_byte_packets)},
  79         {"tx_512_to_1023_byte_packets",
  80                 offsetof(struct ecore_eth_stats_common,
  81                          tx_512_to_1023_byte_packets)},
  82         {"tx_1024_to_1518_byte_packets",
  83                 offsetof(struct ecore_eth_stats_common,
  84                          tx_1024_to_1518_byte_packets)},
  85
  86         {"rx_mac_crtl_frames",
  87                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  88         {"tx_mac_control_frames",
  89                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  90         {"rx_pause_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  92         {"tx_pause_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  94         {"rx_priority_flow_control_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
  96         {"tx_priority_flow_control_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
  98
  99         {"rx_crc_errors",
 100                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 101         {"rx_align_errors",
 102                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 103         {"rx_carrier_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 105         {"rx_oversize_packet_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 107         {"rx_jabber_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 109         {"rx_undersize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 111         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 112         {"rx_host_buffer_not_available",
 113                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 114         /* Number of packets discarded because they are bigger than MTU */
 115         {"rx_packet_too_big_discards",
 116                 offsetof(struct ecore_eth_stats_common,
 117                          packet_too_big_discard)},
 118         {"rx_ttl_zero_discards",
 119                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 120         {"rx_multi_function_tag_filter_discards",
 121                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 122         {"rx_mac_filter_discards",
 123                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 124         {"rx_gft_filter_drop",
 125                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 126         {"rx_hw_buffer_truncates",
 127                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 128         {"rx_hw_buffer_discards",
 129                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 130         {"tx_error_drop_packets",
 131                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 132
 133         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 134         {"rx_mac_unicast_packets",
 135                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 136         {"rx_mac_multicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 138         {"rx_mac_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 140         {"rx_mac_frames_ok",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 142         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 143         {"tx_mac_unicast_packets",
 144                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 145         {"tx_mac_multicast_packets",
 146                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 147         {"tx_mac_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 149
 150         {"lro_coalesced_packets",
 151                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 152         {"lro_coalesced_events",
 153                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 154         {"lro_aborts_num",
 155                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 156         {"lro_not_coalesced_packets",
 157                 offsetof(struct ecore_eth_stats_common,
 158                          tpa_not_coalesced_pkts)},
 159         {"lro_coalesced_bytes",
 160                 offsetof(struct ecore_eth_stats_common,
 161                          tpa_coalesced_bytes)},
 162 };
 163
 164 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 165         {"rx_1519_to_1522_byte_packets",
 166                 offsetof(struct ecore_eth_stats, bb) +
 167                 offsetof(struct ecore_eth_stats_bb,
 168                          rx_1519_to_1522_byte_packets)},
 169         {"rx_1519_to_2047_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_2047_byte_packets)},
 173         {"rx_2048_to_4095_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_2048_to_4095_byte_packets)},
 177         {"rx_4096_to_9216_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_4096_to_9216_byte_packets)},
 181         {"rx_9217_to_16383_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_9217_to_16383_byte_packets)},
 185
 186         {"tx_1519_to_2047_byte_packets",
 187                 offsetof(struct ecore_eth_stats, bb) +
 188                 offsetof(struct ecore_eth_stats_bb,
 189                          tx_1519_to_2047_byte_packets)},
 190         {"tx_2048_to_4095_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_2048_to_4095_byte_packets)},
 194         {"tx_4096_to_9216_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_4096_to_9216_byte_packets)},
 198         {"tx_9217_to_16383_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_9217_to_16383_byte_packets)},
 202
 203         {"tx_lpi_entry_count",
 204                 offsetof(struct ecore_eth_stats, bb) +
 205                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 206         {"tx_total_collisions",
 207                 offsetof(struct ecore_eth_stats, bb) +
 208                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 209 };
 210
 211 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 212         {"rx_1519_to_max_byte_packets",
 213                 offsetof(struct ecore_eth_stats, ah) +
 214                 offsetof(struct ecore_eth_stats_ah,
 215                          rx_1519_to_max_byte_packets)},
 216         {"tx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          tx_1519_to_max_byte_packets)},
 220 };
 221
 222 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 223         {"rx_q_segments",
 224                 offsetof(struct qede_rx_queue, rx_segs)},
 225         {"rx_q_hw_errors",
 226                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 227         {"rx_q_allocation_errors",
 228                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 229 };
 230
 231 /* Get FW version string based on fw_size */
 232 static int
 233 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
 234 {
 235         struct qede_dev *qdev = dev->data->dev_private;
 236         struct ecore_dev *edev = &qdev->edev;
 237         struct qed_dev_info *info = &qdev->dev_info.common;
 238         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 239         size_t size;
 240
 241         if (fw_ver == NULL)
 242                 return 0;
 243
 244         if (IS_PF(edev))
 245                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 246                          QEDE_PMD_FW_VERSION);
 247         else
 248                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 249                          info->fw_major, info->fw_minor,
 250                          info->fw_rev, info->fw_eng);
 251         size = strlen(ver_str);
 252         if (size + 1 <= fw_size) /* Add 1 byte for "\0" */
 253                 strlcpy(fw_ver, ver_str, fw_size);
 254         else
 255                 return (size + 1);
 256
 257         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 258                  " MFW: %d.%d.%d.%d",
 259                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
 260                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
 261                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
 262                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
 263         size = strlen(ver_str);
 264         if (size + 1 <= fw_size)
 265                 strlcpy(fw_ver, ver_str, fw_size);
 266
 267         if (fw_size <= 32)
 268                 goto out;
 269
 270         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 271                  " MBI: %d.%d.%d",
 272                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
 273                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
 274                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
 275         size = strlen(ver_str);
 276         if (size + 1 <= fw_size)
 277                 strlcpy(fw_ver, ver_str, fw_size);
 278
 279 out:
 280         return 0;
 281 }
 282
 283 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 284 {
 285         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 286 }
 287
 288 static void
 289 qede_interrupt_handler_intx(void *param)
 290 {
 291         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 292         struct qede_dev *qdev = eth_dev->data->dev_private;
 293         struct ecore_dev *edev = &qdev->edev;
 294         u64 status;
 295
 296         /* Check if our device actually raised an interrupt */
 297         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 298         if (status & 0x1) {
 299                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 300
 301                 if (rte_intr_ack(eth_dev->intr_handle))
 302                         DP_ERR(edev, "rte_intr_ack failed\n");
 303         }
 304 }
 305
 306 static void
 307 qede_interrupt_handler(void *param)
 308 {
 309         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 310         struct qede_dev *qdev = eth_dev->data->dev_private;
 311         struct ecore_dev *edev = &qdev->edev;
 312
 313         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 314         if (rte_intr_ack(eth_dev->intr_handle))
 315                 DP_ERR(edev, "rte_intr_ack failed\n");
 316 }
 317
 318 static void
 319 qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy)
 320 {
 321         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
 322         struct qede_dev *qdev = dev->data->dev_private;
 323         struct ecore_dev *edev = &qdev->edev;
 324         bool use_tx_offload = false;
 325
 326         if (is_dummy) {
 327                 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
 328                 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
 329                 return;
 330         }
 331
 332         if (ECORE_IS_CMT(edev)) {
 333                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
 334                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
 335                 return;
 336         }
 337
 338         if (dev->data->lro || dev->data->scattered_rx) {
 339                 DP_INFO(edev, "Assigning qede_recv_pkts\n");
 340                 dev->rx_pkt_burst = qede_recv_pkts;
 341         } else {
 342                 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
 343                 dev->rx_pkt_burst = qede_recv_pkts_regular;
 344         }
 345
 346         use_tx_offload = !!(tx_offloads &
 347                             (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
 348                              DEV_TX_OFFLOAD_TCP_TSO | /* tso */
 349                              DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
 350
 351         if (use_tx_offload) {
 352                 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
 353                 dev->tx_pkt_burst = qede_xmit_pkts;
 354         } else {
 355                 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
 356                 dev->tx_pkt_burst = qede_xmit_pkts_regular;
 357         }
 358 }
 359
 360 static void
 361 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 362 {
 363         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 364         qdev->ops = qed_ops;
 365 }
 366
 367 static void qede_print_adapter_info(struct rte_eth_dev *dev)
 368 {
 369         struct qede_dev *qdev = dev->data->dev_private;
 370         struct ecore_dev *edev = &qdev->edev;
 371         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 372
 373         DP_INFO(edev, "**************************************************\n");
 374         DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
 375         DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
 376                   ECORE_IS_BB(edev) ? "BB" : "AH",
 377                   'A' + edev->chip_rev,
 378                   (int)edev->chip_metal);
 379         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 380                  QEDE_PMD_DRV_VERSION);
 381         DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
 382         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 383                  QEDE_PMD_BASE_VERSION);
 384         DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
 385         qede_fw_version_get(dev, ver_str, sizeof(ver_str));
 386         DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
 387         DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
 388         DP_INFO(edev, "**************************************************\n");
 389 }
 390
 391 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 392 {
 393         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 394         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 395         unsigned int i = 0, j = 0, qid;
 396         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 397         struct qede_tx_queue *txq;
 398
 399         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 400
 401         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 404                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 405
 406         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 407                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 408                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 409                             sizeof(uint64_t));
 410                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 411                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 412                             sizeof(uint64_t));
 413                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 414                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 415                             sizeof(uint64_t));
 416
 417                 if (xstats)
 418                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 419                                 OSAL_MEMSET((((char *)
 420                                               (qdev->fp_array[qid].rxq)) +
 421                                              qede_rxq_xstats_strings[j].offset),
 422                                             0,
 423                                             sizeof(uint64_t));
 424
 425                 i++;
 426                 if (i == rxq_stat_cntrs)
 427                         break;
 428         }
 429
 430         i = 0;
 431
 432         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 433                 txq = qdev->fp_array[qid].txq;
 434
 435                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 436                                 (((uint64_t)(uintptr_t)(txq)) +
 437                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 438                             sizeof(uint64_t));
 439
 440                 i++;
 441                 if (i == txq_stat_cntrs)
 442                         break;
 443         }
 444 }
 445
 446 static int
 447 qede_stop_vport(struct ecore_dev *edev)
 448 {
 449         struct ecore_hwfn *p_hwfn;
 450         uint8_t vport_id;
 451         int rc;
 452         int i;
 453
 454         vport_id = 0;
 455         for_each_hwfn(edev, i) {
 456                 p_hwfn = &edev->hwfns[i];
 457                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 458                                          vport_id);
 459                 if (rc != ECORE_SUCCESS) {
 460                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 461                         return rc;
 462                 }
 463         }
 464
 465         DP_INFO(edev, "vport stopped\n");
 466
 467         return 0;
 468 }
 469
 470 static int
 471 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 472 {
 473         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 474         struct ecore_sp_vport_start_params params;
 475         struct ecore_hwfn *p_hwfn;
 476         int rc;
 477         int i;
 478
 479         if (qdev->vport_started)
 480                 qede_stop_vport(edev);
 481
 482         memset(&params, 0, sizeof(params));
 483         params.vport_id = 0;
 484         params.mtu = mtu;
 485         /* @DPDK - Disable FW placement */
 486         params.zero_placement_offset = 1;
 487         for_each_hwfn(edev, i) {
 488                 p_hwfn = &edev->hwfns[i];
 489                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 490                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 491                 rc = ecore_sp_vport_start(p_hwfn, &params);
 492                 if (rc != ECORE_SUCCESS) {
 493                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 494                         return rc;
 495                 }
 496         }
 497         ecore_reset_vport_stats(edev);
 498         qdev->vport_started = true;
 499         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 500
 501         return 0;
 502 }
 503
 504 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 505 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 506
 507 /* Activate or deactivate vport via vport-update */
 508 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 509 {
 510         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 511         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 512         struct ecore_sp_vport_update_params params;
 513         struct ecore_hwfn *p_hwfn;
 514         uint8_t i;
 515         int rc = -1;
 516
 517         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 518         params.vport_id = 0;
 519         params.update_vport_active_rx_flg = 1;
 520         params.update_vport_active_tx_flg = 1;
 521         params.vport_active_rx_flg = flg;
 522         params.vport_active_tx_flg = flg;
 523         if ((qdev->enable_tx_switching == false) && (flg == true)) {
 524                 params.update_tx_switching_flg = 1;
 525                 params.tx_switching_flg = !flg;
 526         }
 527         for_each_hwfn(edev, i) {
 528                 p_hwfn = &edev->hwfns[i];
 529                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 530                 rc = ecore_sp_vport_update(p_hwfn, &params,
 531                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 532                 if (rc != ECORE_SUCCESS) {
 533                         DP_ERR(edev, "Failed to update vport\n");
 534                         break;
 535                 }
 536         }
 537         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 538
 539         return rc;
 540 }
 541
 542 static void
 543 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 544                            uint16_t mtu, bool enable)
 545 {
 546         /* Enable LRO in split mode */
 547         sge_tpa_params->tpa_ipv4_en_flg = enable;
 548         sge_tpa_params->tpa_ipv6_en_flg = enable;
 549         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 550         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 551         /* set if tpa enable changes */
 552         sge_tpa_params->update_tpa_en_flg = 1;
 553         /* set if tpa parameters should be handled */
 554         sge_tpa_params->update_tpa_param_flg = enable;
 555
 556         sge_tpa_params->max_buffers_per_cqe = 20;
 557         /* Enable TPA in split mode. In this mode each TPA segment
 558          * starts on the new BD, so there is one BD per segment.
 559          */
 560         sge_tpa_params->tpa_pkt_split_flg = 1;
 561         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 562         sge_tpa_params->tpa_gro_consistent_flg = 0;
 563         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 564         sge_tpa_params->tpa_max_size = 0x7FFF;
 565         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 566         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 567 }
 568
 569 /* Enable/disable LRO via vport-update */
 570 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 571 {
 572         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 573         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 574         struct ecore_sp_vport_update_params params;
 575         struct ecore_sge_tpa_params tpa_params;
 576         struct ecore_hwfn *p_hwfn;
 577         int rc;
 578         int i;
 579
 580         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 581         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 582         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 583         params.vport_id = 0;
 584         params.sge_tpa_params = &tpa_params;
 585         for_each_hwfn(edev, i) {
 586                 p_hwfn = &edev->hwfns[i];
 587                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 588                 rc = ecore_sp_vport_update(p_hwfn, &params,
 589                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 590                 if (rc != ECORE_SUCCESS) {
 591                         DP_ERR(edev, "Failed to update LRO\n");
 592                         return -1;
 593                 }
 594         }
 595         qdev->enable_lro = flg;
 596         eth_dev->data->lro = flg;
 597
 598         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 599
 600         return 0;
 601 }
 602
 603 static int
 604 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 605                              enum qed_filter_rx_mode_type type)
 606 {
 607         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 608         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 609         struct ecore_filter_accept_flags flags;
 610
 611         memset(&flags, 0, sizeof(flags));
 612
 613         flags.update_rx_mode_config = 1;
 614         flags.update_tx_mode_config = 1;
 615         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 616                 ECORE_ACCEPT_MCAST_MATCHED |
 617                 ECORE_ACCEPT_BCAST;
 618
 619         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 620                 ECORE_ACCEPT_MCAST_MATCHED |
 621                 ECORE_ACCEPT_BCAST;
 622
 623         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 624                 flags.rx_accept_filter |= (ECORE_ACCEPT_UCAST_UNMATCHED |
 625                                            ECORE_ACCEPT_MCAST_UNMATCHED);
 626                 if (IS_VF(edev)) {
 627                         flags.tx_accept_filter |=
 628                                                 (ECORE_ACCEPT_UCAST_UNMATCHED |
 629                                                  ECORE_ACCEPT_MCAST_UNMATCHED);
 630                         DP_INFO(edev, "Enabling Tx unmatched flags for VF\n");
 631                 }
 632         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 633                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 634         }
 635
 636         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 637                         ECORE_SPQ_MODE_CB, NULL);
 638 }
 639
 640 int
 641 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 642                   bool add)
 643 {
 644         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 645         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 646         struct qede_ucast_entry *tmp = NULL;
 647         struct qede_ucast_entry *u;
 648         struct rte_ether_addr *mac_addr;
 649
 650         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 651         if (add) {
 652                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 653                         if ((memcmp(mac_addr, &tmp->mac,
 654                                     RTE_ETHER_ADDR_LEN) == 0) &&
 655                              ucast->vni == tmp->vni &&
 656                              ucast->vlan == tmp->vlan) {
 657                                 DP_INFO(edev, "Unicast MAC is already added"
 658                                         " with vlan = %u, vni = %u\n",
 659                                         ucast->vlan,  ucast->vni);
 660                                         return 0;
 661                         }
 662                 }
 663                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 664                                RTE_CACHE_LINE_SIZE);
 665                 if (!u) {
 666                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 667                         return -ENOMEM;
 668                 }
 669                 rte_ether_addr_copy(mac_addr, &u->mac);
 670                 u->vlan = ucast->vlan;
 671                 u->vni = ucast->vni;
 672                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 673                 qdev->num_uc_addr++;
 674         } else {
 675                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 676                         if ((memcmp(mac_addr, &tmp->mac,
 677                                     RTE_ETHER_ADDR_LEN) == 0) &&
 678                             ucast->vlan == tmp->vlan      &&
 679                             ucast->vni == tmp->vni)
 680                         break;
 681                 }
 682                 if (tmp == NULL) {
 683                         DP_INFO(edev, "Unicast MAC is not found\n");
 684                         return -EINVAL;
 685                 }
 686                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 687                 qdev->num_uc_addr--;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int
 694 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 695                 struct rte_ether_addr *mc_addrs,
 696                 uint32_t mc_addrs_num)
 697 {
 698         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 699         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 700         struct ecore_filter_mcast mcast;
 701         struct qede_mcast_entry *m = NULL;
 702         uint8_t i;
 703         int rc;
 704
 705         for (i = 0; i < mc_addrs_num; i++) {
 706                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 707                                RTE_CACHE_LINE_SIZE);
 708                 if (!m) {
 709                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 710                         return -ENOMEM;
 711                 }
 712                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 713                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 714         }
 715         memset(&mcast, 0, sizeof(mcast));
 716         mcast.num_mc_addrs = mc_addrs_num;
 717         mcast.opcode = ECORE_FILTER_ADD;
 718         for (i = 0; i < mc_addrs_num; i++)
 719                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 720                                                         &mcast.mac[i]);
 721         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 722         if (rc != ECORE_SUCCESS) {
 723                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 724                 return -1;
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 731 {
 732         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 733         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 734         struct qede_mcast_entry *tmp = NULL;
 735         struct ecore_filter_mcast mcast;
 736         int j;
 737         int rc;
 738
 739         memset(&mcast, 0, sizeof(mcast));
 740         mcast.num_mc_addrs = qdev->num_mc_addr;
 741         mcast.opcode = ECORE_FILTER_REMOVE;
 742         j = 0;
 743         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 744                 rte_ether_addr_copy(&tmp->mac,
 745                                 (struct rte_ether_addr *)&mcast.mac[j]);
 746                 j++;
 747         }
 748         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 749         if (rc != ECORE_SUCCESS) {
 750                 DP_ERR(edev, "Failed to delete multicast filter\n");
 751                 return -1;
 752         }
 753         /* Init the list */
 754         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 755                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 756                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 757         }
 758         SLIST_INIT(&qdev->mc_list_head);
 759
 760         return 0;
 761 }
 762
 763 enum _ecore_status_t
 764 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 765                  bool add)
 766 {
 767         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 768         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 769         enum _ecore_status_t rc = ECORE_INVAL;
 770
 771         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 772                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 773                               " Please enable promisc mode\n");
 774                         return ECORE_INVAL;
 775         }
 776
 777         rc = qede_ucast_filter(eth_dev, ucast, add);
 778         if (rc == 0)
 779                 rc = ecore_filter_ucast_cmd(edev, ucast,
 780                                             ECORE_SPQ_MODE_CB, NULL);
 781         /* Indicate error only for add filter operation.
 782          * Delete filter operations are not severe.
 783          */
 784         if ((rc != ECORE_SUCCESS) && add)
 785                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 786                        rc, add);
 787
 788         return rc;
 789 }
 790
 791 static int
 792 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 793                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 794 {
 795         struct ecore_filter_ucast ucast;
 796         int re;
 797
 798         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 799                 return -EINVAL;
 800
 801         qede_set_ucast_cmn_params(&ucast);
 802         ucast.opcode = ECORE_FILTER_ADD;
 803         ucast.type = ECORE_FILTER_MAC;
 804         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 805         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 806         return re;
 807 }
 808
 809 static void
 810 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 811 {
 812         struct qede_dev *qdev = eth_dev->data->dev_private;
 813         struct ecore_dev *edev = &qdev->edev;
 814         struct ecore_filter_ucast ucast;
 815
 816         PMD_INIT_FUNC_TRACE(edev);
 817
 818         if (index >= qdev->dev_info.num_mac_filters) {
 819                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 820                        index, qdev->dev_info.num_mac_filters);
 821                 return;
 822         }
 823
 824         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 825                 return;
 826
 827         qede_set_ucast_cmn_params(&ucast);
 828         ucast.opcode = ECORE_FILTER_REMOVE;
 829         ucast.type = ECORE_FILTER_MAC;
 830
 831         /* Use the index maintained by rte */
 832         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 833                         (struct rte_ether_addr *)&ucast.mac);
 834
 835         qede_mac_int_ops(eth_dev, &ucast, false);
 836 }
 837
 838 static int
 839 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 840 {
 841         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 842         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 843
 844         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 845                                                mac_addr->addr_bytes)) {
 846                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 847                 return -EPERM;
 848         }
 849
 850         qede_mac_addr_remove(eth_dev, 0);
 851
 852         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 853 }
 854
 855 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 856 {
 857         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 858         struct ecore_sp_vport_update_params params;
 859         struct ecore_hwfn *p_hwfn;
 860         uint8_t i;
 861         int rc;
 862
 863         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 864         params.vport_id = 0;
 865         params.update_accept_any_vlan_flg = 1;
 866         params.accept_any_vlan = flg;
 867         for_each_hwfn(edev, i) {
 868                 p_hwfn = &edev->hwfns[i];
 869                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 870                 rc = ecore_sp_vport_update(p_hwfn, &params,
 871                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 872                 if (rc != ECORE_SUCCESS) {
 873                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 874                         return;
 875                 }
 876         }
 877
 878         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 879 }
 880
 881 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 882 {
 883         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 884         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 885         struct ecore_sp_vport_update_params params;
 886         struct ecore_hwfn *p_hwfn;
 887         uint8_t i;
 888         int rc;
 889
 890         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 891         params.vport_id = 0;
 892         params.update_inner_vlan_removal_flg = 1;
 893         params.inner_vlan_removal_flg = flg;
 894         for_each_hwfn(edev, i) {
 895                 p_hwfn = &edev->hwfns[i];
 896                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 897                 rc = ecore_sp_vport_update(p_hwfn, &params,
 898                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 899                 if (rc != ECORE_SUCCESS) {
 900                         DP_ERR(edev, "Failed to update vport\n");
 901                         return -1;
 902                 }
 903         }
 904
 905         qdev->vlan_strip_flg = flg;
 906
 907         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 908         return 0;
 909 }
 910
 911 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 912                                 uint16_t vlan_id, int on)
 913 {
 914         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 915         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 916         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 917         struct qede_vlan_entry *tmp = NULL;
 918         struct qede_vlan_entry *vlan;
 919         struct ecore_filter_ucast ucast;
 920         int rc;
 921
 922         if (on) {
 923                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 924                         DP_ERR(edev, "Reached max VLAN filter limit"
 925                                       " enabling accept_any_vlan\n");
 926                         qede_config_accept_any_vlan(qdev, true);
 927                         return 0;
 928                 }
 929
 930                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 931                         if (tmp->vid == vlan_id) {
 932                                 DP_INFO(edev, "VLAN %u already configured\n",
 933                                         vlan_id);
 934                                 return 0;
 935                         }
 936                 }
 937
 938                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 939                                   RTE_CACHE_LINE_SIZE);
 940
 941                 if (!vlan) {
 942                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 943                         return -ENOMEM;
 944                 }
 945
 946                 qede_set_ucast_cmn_params(&ucast);
 947                 ucast.opcode = ECORE_FILTER_ADD;
 948                 ucast.type = ECORE_FILTER_VLAN;
 949                 ucast.vlan = vlan_id;
 950                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 951                                             NULL);
 952                 if (rc != 0) {
 953                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 954                                rc);
 955                         rte_free(vlan);
 956                 } else {
 957                         vlan->vid = vlan_id;
 958                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 959                         qdev->configured_vlans++;
 960                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 961                                 vlan_id, qdev->configured_vlans);
 962                 }
 963         } else {
 964                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 965                         if (tmp->vid == vlan_id)
 966                                 break;
 967                 }
 968
 969                 if (!tmp) {
 970                         if (qdev->configured_vlans == 0) {
 971                                 DP_INFO(edev,
 972                                         "No VLAN filters configured yet\n");
 973                                 return 0;
 974                         }
 975
 976                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 977                         return -EINVAL;
 978                 }
 979
 980                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 981
 982                 qede_set_ucast_cmn_params(&ucast);
 983                 ucast.opcode = ECORE_FILTER_REMOVE;
 984                 ucast.type = ECORE_FILTER_VLAN;
 985                 ucast.vlan = vlan_id;
 986                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 987                                             NULL);
 988                 if (rc != 0) {
 989                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 990                                vlan_id, rc);
 991                 } else {
 992                         qdev->configured_vlans--;
 993                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 994                                 vlan_id, qdev->configured_vlans);
 995                 }
 996         }
 997
 998         return rc;
 999 }
1000
1001 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1002 {
1003         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1004         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1005         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1006
1007         if (mask & ETH_VLAN_STRIP_MASK) {
1008                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1009                         (void)qede_vlan_stripping(eth_dev, 1);
1010                 else
1011                         (void)qede_vlan_stripping(eth_dev, 0);
1012         }
1013
1014         if (mask & ETH_VLAN_FILTER_MASK) {
1015                 /* VLAN filtering kicks in when a VLAN is added */
1016                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1017                         qede_vlan_filter_set(eth_dev, 0, 1);
1018                 } else {
1019                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1020                                 DP_ERR(edev,
1021                                   " Please remove existing VLAN filters"
1022                                   " before disabling VLAN filtering\n");
1023                                 /* Signal app that VLAN filtering is still
1024                                  * enabled
1025                                  */
1026                                 eth_dev->data->dev_conf.rxmode.offloads |=
1027                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1028                         } else {
1029                                 qede_vlan_filter_set(eth_dev, 0, 0);
1030                         }
1031                 }
1032         }
1033
1034         if (mask & ETH_VLAN_EXTEND_MASK)
1035                 DP_ERR(edev, "Extend VLAN not supported\n");
1036
1037         qdev->vlan_offload_mask = mask;
1038
1039         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1040
1041         return 0;
1042 }
1043
1044 static void qede_prandom_bytes(uint32_t *buff)
1045 {
1046         uint8_t i;
1047
1048         srand((unsigned int)time(NULL));
1049         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1050                 buff[i] = rand();
1051 }
1052
1053 int qede_config_rss(struct rte_eth_dev *eth_dev)
1054 {
1055         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1056         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1057         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1058         struct rte_eth_rss_reta_entry64 reta_conf[2];
1059         struct rte_eth_rss_conf rss_conf;
1060         uint32_t i, id, pos, q;
1061
1062         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1063         if (!rss_conf.rss_key) {
1064                 DP_INFO(edev, "Applying driver default key\n");
1065                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1066                 qede_prandom_bytes(&def_rss_key[0]);
1067                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1068         }
1069
1070         /* Configure RSS hash */
1071         if (qede_rss_hash_update(eth_dev, &rss_conf))
1072                 return -EINVAL;
1073
1074         /* Configure default RETA */
1075         memset(reta_conf, 0, sizeof(reta_conf));
1076         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1077                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1078
1079         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1080                 id = i / RTE_RETA_GROUP_SIZE;
1081                 pos = i % RTE_RETA_GROUP_SIZE;
1082                 q = i % QEDE_RSS_COUNT(eth_dev);
1083                 reta_conf[id].reta[pos] = q;
1084         }
1085         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1086                                  ECORE_RSS_IND_TABLE_SIZE))
1087                 return -EINVAL;
1088
1089         return 0;
1090 }
1091
1092 static void qede_fastpath_start(struct ecore_dev *edev)
1093 {
1094         struct ecore_hwfn *p_hwfn;
1095         int i;
1096
1097         for_each_hwfn(edev, i) {
1098                 p_hwfn = &edev->hwfns[i];
1099                 ecore_hw_start_fastpath(p_hwfn);
1100         }
1101 }
1102
1103 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1104 {
1105         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1106         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1107         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1108
1109         PMD_INIT_FUNC_TRACE(edev);
1110
1111         /* Update MTU only if it has changed */
1112         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1113                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1114                         goto err;
1115                 qdev->mtu = qdev->new_mtu;
1116                 qdev->new_mtu = 0;
1117         }
1118
1119         /* Configure TPA parameters */
1120         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1121                 if (qede_enable_tpa(eth_dev, true))
1122                         return -EINVAL;
1123                 /* Enable scatter mode for LRO */
1124                 if (!eth_dev->data->scattered_rx)
1125                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1126         }
1127
1128         /* Start queues */
1129         if (qede_start_queues(eth_dev))
1130                 goto err;
1131
1132         if (IS_PF(edev))
1133                 qede_reset_queue_stats(qdev, true);
1134
1135         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1136          * enabling RSS. Hence RSS configuration is deferred up to this point.
1137          * Also, we would like to retain similar behavior in PF case, so we
1138          * don't do PF/VF specific check here.
1139          */
1140         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1141                 if (qede_config_rss(eth_dev))
1142                         goto err;
1143
1144         /* Enable vport*/
1145         if (qede_activate_vport(eth_dev, true))
1146                 goto err;
1147
1148         /* Bring-up the link */
1149         qede_dev_set_link_state(eth_dev, true);
1150
1151         /* Update link status */
1152         qede_link_update(eth_dev, 0);
1153
1154         /* Start/resume traffic */
1155         qede_fastpath_start(edev);
1156
1157         /* Assign I/O handlers */
1158         qede_assign_rxtx_handlers(eth_dev, false);
1159
1160         DP_INFO(edev, "Device started\n");
1161
1162         return 0;
1163 err:
1164         DP_ERR(edev, "Device start fails\n");
1165         return -1; /* common error code is < 0 */
1166 }
1167
1168 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1169 {
1170         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1171         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1172
1173         PMD_INIT_FUNC_TRACE(edev);
1174
1175         /* Bring the link down */
1176         qede_dev_set_link_state(eth_dev, false);
1177
1178         /* Update link status */
1179         qede_link_update(eth_dev, 0);
1180
1181         /* Replace I/O functions with dummy ones. It cannot
1182          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1183          */
1184         qede_assign_rxtx_handlers(eth_dev, true);
1185
1186         /* Disable vport */
1187         if (qede_activate_vport(eth_dev, false))
1188                 return;
1189
1190         if (qdev->enable_lro)
1191                 qede_enable_tpa(eth_dev, false);
1192
1193         /* Stop queues */
1194         qede_stop_queues(eth_dev);
1195
1196         /* Disable traffic */
1197         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1198
1199         DP_INFO(edev, "Device is stopped\n");
1200 }
1201
1202 static const char * const valid_args[] = {
1203         QEDE_NPAR_TX_SWITCHING,
1204         QEDE_VF_TX_SWITCHING,
1205         NULL,
1206 };
1207
1208 static int qede_args_check(const char *key, const char *val, void *opaque)
1209 {
1210         unsigned long tmp;
1211         int ret = 0;
1212         struct rte_eth_dev *eth_dev = opaque;
1213         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1214         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1215
1216         errno = 0;
1217         tmp = strtoul(val, NULL, 0);
1218         if (errno) {
1219                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1220                 return errno;
1221         }
1222
1223         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1224             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1225                 qdev->enable_tx_switching = !!tmp;
1226                 DP_INFO(edev, "Disabling %s tx-switching\n",
1227                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1228                         "VF" : "NPAR");
1229         }
1230
1231         return ret;
1232 }
1233
1234 static int qede_args(struct rte_eth_dev *eth_dev)
1235 {
1236         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1237         struct rte_kvargs *kvlist;
1238         struct rte_devargs *devargs;
1239         int ret;
1240         int i;
1241
1242         devargs = pci_dev->device.devargs;
1243         if (!devargs)
1244                 return 0; /* return success */
1245
1246         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1247         if (kvlist == NULL)
1248                 return -EINVAL;
1249
1250          /* Process parameters. */
1251         for (i = 0; (valid_args[i] != NULL); ++i) {
1252                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1253                         ret = rte_kvargs_process(kvlist, valid_args[i],
1254                                                  qede_args_check, eth_dev);
1255                         if (ret != ECORE_SUCCESS) {
1256                                 rte_kvargs_free(kvlist);
1257                                 return ret;
1258                         }
1259                 }
1260         }
1261         rte_kvargs_free(kvlist);
1262
1263         return 0;
1264 }
1265
1266 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1267 {
1268         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1269         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1270         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1271         uint8_t num_rxqs;
1272         uint8_t num_txqs;
1273         int ret;
1274
1275         PMD_INIT_FUNC_TRACE(edev);
1276
1277         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1278                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1279
1280         /* We need to have min 1 RX queue.There is no min check in
1281          * rte_eth_dev_configure(), so we are checking it here.
1282          */
1283         if (eth_dev->data->nb_rx_queues == 0) {
1284                 DP_ERR(edev, "Minimum one RX queue is required\n");
1285                 return -EINVAL;
1286         }
1287
1288         /* Enable Tx switching by default */
1289         qdev->enable_tx_switching = 1;
1290
1291         /* Parse devargs and fix up rxmode */
1292         if (qede_args(eth_dev))
1293                 DP_NOTICE(edev, false,
1294                           "Invalid devargs supplied, requested change will not take effect\n");
1295
1296         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1297               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1298                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1299                 return -ENOTSUP;
1300         }
1301         /* Flow director mode check */
1302         if (qede_check_fdir_support(eth_dev))
1303                 return -ENOTSUP;
1304
1305         /* Allocate/reallocate fastpath resources only for new queue config */
1306         num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1307         num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1308         if (qdev->num_tx_queues != num_txqs ||
1309             qdev->num_rx_queues != num_rxqs) {
1310                 qede_dealloc_fp_resc(eth_dev);
1311                 qdev->num_tx_queues = num_txqs;
1312                 qdev->num_rx_queues = num_rxqs;
1313                 if (qede_alloc_fp_resc(qdev))
1314                         return -ENOMEM;
1315         }
1316
1317         /* If jumbo enabled adjust MTU */
1318         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1319                 eth_dev->data->mtu =
1320                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1321                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1322
1323         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1324                 eth_dev->data->scattered_rx = 1;
1325
1326         if (qede_start_vport(qdev, eth_dev->data->mtu))
1327                 return -1;
1328
1329         qdev->mtu = eth_dev->data->mtu;
1330
1331         /* Enable VLAN offloads by default */
1332         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1333                                              ETH_VLAN_FILTER_MASK);
1334         if (ret)
1335                 return ret;
1336
1337         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1338                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1339
1340         if (ECORE_IS_CMT(edev))
1341                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1342                         qdev->num_rx_queues, qdev->num_tx_queues);
1343
1344
1345         return 0;
1346 }
1347
1348 /* Info about HW descriptor ring limitations */
1349 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1350         .nb_max = 0x8000, /* 32K */
1351         .nb_min = 128,
1352         .nb_align = 128 /* lowest common multiple */
1353 };
1354
1355 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1356         .nb_max = 0x8000, /* 32K */
1357         .nb_min = 256,
1358         .nb_align = 256,
1359         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1360         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1361 };
1362
1363 static int
1364 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1365                   struct rte_eth_dev_info *dev_info)
1366 {
1367         struct qede_dev *qdev = eth_dev->data->dev_private;
1368         struct ecore_dev *edev = &qdev->edev;
1369         struct qed_link_output link;
1370         uint32_t speed_cap = 0;
1371
1372         PMD_INIT_FUNC_TRACE(edev);
1373
1374         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1375         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1376         dev_info->rx_desc_lim = qede_rx_desc_lim;
1377         dev_info->tx_desc_lim = qede_tx_desc_lim;
1378
1379         if (IS_PF(edev))
1380                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1381                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1382         else
1383                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1384                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1385         /* Since CMT mode internally doubles the number of queues */
1386         if (ECORE_IS_CMT(edev))
1387                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1388
1389         dev_info->max_tx_queues = dev_info->max_rx_queues;
1390
1391         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1392         dev_info->max_vfs = 0;
1393         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1394         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1395         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1396         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1397                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1398                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1399                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1400                                      DEV_RX_OFFLOAD_TCP_LRO     |
1401                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1402                                      DEV_RX_OFFLOAD_SCATTER     |
1403                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1404                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1405                                      DEV_RX_OFFLOAD_VLAN_STRIP  |
1406                                      DEV_RX_OFFLOAD_RSS_HASH);
1407         dev_info->rx_queue_offload_capa = 0;
1408
1409         /* TX offloads are on a per-packet basis, so it is applicable
1410          * to both at port and queue levels.
1411          */
1412         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1413                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1414                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1415                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1416                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1417                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1418                                      DEV_TX_OFFLOAD_TCP_TSO     |
1419                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1420                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1421         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1422
1423         dev_info->default_txconf = (struct rte_eth_txconf) {
1424                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1425         };
1426
1427         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1428                 /* Packets are always dropped if no descriptors are available */
1429                 .rx_drop_en = 1,
1430                 .offloads = 0,
1431         };
1432
1433         memset(&link, 0, sizeof(struct qed_link_output));
1434         qdev->ops->common->get_link(edev, &link);
1435         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1436                 speed_cap |= ETH_LINK_SPEED_1G;
1437         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1438                 speed_cap |= ETH_LINK_SPEED_10G;
1439         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1440                 speed_cap |= ETH_LINK_SPEED_25G;
1441         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1442                 speed_cap |= ETH_LINK_SPEED_40G;
1443         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1444                 speed_cap |= ETH_LINK_SPEED_50G;
1445         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1446                 speed_cap |= ETH_LINK_SPEED_100G;
1447         dev_info->speed_capa = speed_cap;
1448
1449         return 0;
1450 }
1451
1452 /* return 0 means link status changed, -1 means not changed */
1453 int
1454 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1455 {
1456         struct qede_dev *qdev = eth_dev->data->dev_private;
1457         struct ecore_dev *edev = &qdev->edev;
1458         struct qed_link_output q_link;
1459         struct rte_eth_link link;
1460         uint16_t link_duplex;
1461
1462         memset(&q_link, 0, sizeof(q_link));
1463         memset(&link, 0, sizeof(link));
1464
1465         qdev->ops->common->get_link(edev, &q_link);
1466
1467         /* Link Speed */
1468         link.link_speed = q_link.speed;
1469
1470         /* Link Mode */
1471         switch (q_link.duplex) {
1472         case QEDE_DUPLEX_HALF:
1473                 link_duplex = ETH_LINK_HALF_DUPLEX;
1474                 break;
1475         case QEDE_DUPLEX_FULL:
1476                 link_duplex = ETH_LINK_FULL_DUPLEX;
1477                 break;
1478         case QEDE_DUPLEX_UNKNOWN:
1479         default:
1480                 link_duplex = -1;
1481         }
1482         link.link_duplex = link_duplex;
1483
1484         /* Link Status */
1485         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1486
1487         /* AN */
1488         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1489                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1490
1491         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1492                 link.link_speed, link.link_duplex,
1493                 link.link_autoneg, link.link_status);
1494
1495         return rte_eth_linkstatus_set(eth_dev, &link);
1496 }
1497
1498 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1499 {
1500         enum _ecore_status_t ecore_status;
1501         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1502         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1503         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1504
1505         PMD_INIT_FUNC_TRACE(edev);
1506
1507         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1508
1509         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1510 }
1511
1512 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1513 {
1514         struct qede_dev *qdev = eth_dev->data->dev_private;
1515         struct ecore_dev *edev = &qdev->edev;
1516         enum _ecore_status_t ecore_status;
1517
1518         PMD_INIT_FUNC_TRACE(edev);
1519
1520         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1521                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1522                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1523         else
1524                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1525                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1526
1527         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1528 }
1529
1530 static void qede_poll_sp_sb_cb(void *param)
1531 {
1532         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1533         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1534         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1535         int rc;
1536
1537         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1538         qede_interrupt_action(&edev->hwfns[1]);
1539
1540         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1541                                qede_poll_sp_sb_cb,
1542                                (void *)eth_dev);
1543         if (rc != 0) {
1544                 DP_ERR(edev, "Unable to start periodic"
1545                              " timer rc %d\n", rc);
1546         }
1547 }
1548
1549 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1550 {
1551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1552         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1553         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1554
1555         PMD_INIT_FUNC_TRACE(edev);
1556
1557         /* dev_stop() shall cleanup fp resources in hw but without releasing
1558          * dma memories and sw structures so that dev_start() can be called
1559          * by the app without reconfiguration. However, in dev_close() we
1560          * can release all the resources and device can be brought up newly
1561          */
1562         if (eth_dev->data->dev_started)
1563                 qede_dev_stop(eth_dev);
1564
1565         if (qdev->vport_started)
1566                 qede_stop_vport(edev);
1567         qdev->vport_started = false;
1568         qede_fdir_dealloc_resc(eth_dev);
1569         qede_dealloc_fp_resc(eth_dev);
1570
1571         eth_dev->data->nb_rx_queues = 0;
1572         eth_dev->data->nb_tx_queues = 0;
1573
1574         qdev->ops->common->slowpath_stop(edev);
1575         qdev->ops->common->remove(edev);
1576         rte_intr_disable(&pci_dev->intr_handle);
1577
1578         switch (pci_dev->intr_handle.type) {
1579         case RTE_INTR_HANDLE_UIO_INTX:
1580         case RTE_INTR_HANDLE_VFIO_LEGACY:
1581                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1582                                              qede_interrupt_handler_intx,
1583                                              (void *)eth_dev);
1584                 break;
1585         default:
1586                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1587                                            qede_interrupt_handler,
1588                                            (void *)eth_dev);
1589         }
1590
1591         if (ECORE_IS_CMT(edev))
1592                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1593 }
1594
1595 static int
1596 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1597 {
1598         struct qede_dev *qdev = eth_dev->data->dev_private;
1599         struct ecore_dev *edev = &qdev->edev;
1600         struct ecore_eth_stats stats;
1601         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1602         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1603         struct qede_tx_queue *txq;
1604
1605         ecore_get_vport_stats(edev, &stats);
1606
1607         /* RX Stats */
1608         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1609             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1610
1611         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1612             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1613
1614         eth_stats->ierrors = stats.common.rx_crc_errors +
1615             stats.common.rx_align_errors +
1616             stats.common.rx_carrier_errors +
1617             stats.common.rx_oversize_packets +
1618             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1619
1620         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1621
1622         eth_stats->imissed = stats.common.mftag_filter_discards +
1623             stats.common.mac_filter_discards +
1624             stats.common.no_buff_discards +
1625             stats.common.brb_truncates + stats.common.brb_discards;
1626
1627         /* TX stats */
1628         eth_stats->opackets = stats.common.tx_ucast_pkts +
1629             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1630
1631         eth_stats->obytes = stats.common.tx_ucast_bytes +
1632             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1633
1634         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1635
1636         /* Queue stats */
1637         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1638                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1639         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1640                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1641         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1642             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1643                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1644                        "Not all the queue stats will be displayed. Set"
1645                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1646                        " appropriately and retry.\n");
1647
1648         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1649                 eth_stats->q_ipackets[i] = 0;
1650                 eth_stats->q_errors[i] = 0;
1651
1652                 for_each_hwfn(edev, hw_fn) {
1653                         idx = qid * edev->num_hwfns + hw_fn;
1654
1655                         eth_stats->q_ipackets[i] +=
1656                                 *(uint64_t *)
1657                                         (((char *)(qdev->fp_array[idx].rxq)) +
1658                                          offsetof(struct qede_rx_queue,
1659                                          rcv_pkts));
1660                         eth_stats->q_errors[i] +=
1661                                 *(uint64_t *)
1662                                         (((char *)(qdev->fp_array[idx].rxq)) +
1663                                          offsetof(struct qede_rx_queue,
1664                                          rx_hw_errors)) +
1665                                 *(uint64_t *)
1666                                         (((char *)(qdev->fp_array[idx].rxq)) +
1667                                          offsetof(struct qede_rx_queue,
1668                                          rx_alloc_errors));
1669                 }
1670
1671                 i++;
1672                 if (i == rxq_stat_cntrs)
1673                         break;
1674         }
1675
1676         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1677                 eth_stats->q_opackets[j] = 0;
1678
1679                 for_each_hwfn(edev, hw_fn) {
1680                         idx = qid * edev->num_hwfns + hw_fn;
1681
1682                         txq = qdev->fp_array[idx].txq;
1683                         eth_stats->q_opackets[j] +=
1684                                 *((uint64_t *)(uintptr_t)
1685                                         (((uint64_t)(uintptr_t)(txq)) +
1686                                          offsetof(struct qede_tx_queue,
1687                                                   xmit_pkts)));
1688                 }
1689
1690                 j++;
1691                 if (j == txq_stat_cntrs)
1692                         break;
1693         }
1694
1695         return 0;
1696 }
1697
1698 static unsigned
1699 qede_get_xstats_count(struct qede_dev *qdev) {
1700         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1701
1702         if (ECORE_IS_BB(&qdev->edev))
1703                 return RTE_DIM(qede_xstats_strings) +
1704                        RTE_DIM(qede_bb_xstats_strings) +
1705                        (RTE_DIM(qede_rxq_xstats_strings) *
1706                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1707         else
1708                 return RTE_DIM(qede_xstats_strings) +
1709                        RTE_DIM(qede_ah_xstats_strings) +
1710                        (RTE_DIM(qede_rxq_xstats_strings) *
1711                         QEDE_RSS_COUNT(dev));
1712 }
1713
1714 static int
1715 qede_get_xstats_names(struct rte_eth_dev *dev,
1716                       struct rte_eth_xstat_name *xstats_names,
1717                       __rte_unused unsigned int limit)
1718 {
1719         struct qede_dev *qdev = dev->data->dev_private;
1720         struct ecore_dev *edev = &qdev->edev;
1721         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1722         unsigned int i, qid, hw_fn, stat_idx = 0;
1723
1724         if (xstats_names == NULL)
1725                 return stat_cnt;
1726
1727         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1728                 strlcpy(xstats_names[stat_idx].name,
1729                         qede_xstats_strings[i].name,
1730                         sizeof(xstats_names[stat_idx].name));
1731                 stat_idx++;
1732         }
1733
1734         if (ECORE_IS_BB(edev)) {
1735                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1736                         strlcpy(xstats_names[stat_idx].name,
1737                                 qede_bb_xstats_strings[i].name,
1738                                 sizeof(xstats_names[stat_idx].name));
1739                         stat_idx++;
1740                 }
1741         } else {
1742                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1743                         strlcpy(xstats_names[stat_idx].name,
1744                                 qede_ah_xstats_strings[i].name,
1745                                 sizeof(xstats_names[stat_idx].name));
1746                         stat_idx++;
1747                 }
1748         }
1749
1750         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1751                 for_each_hwfn(edev, hw_fn) {
1752                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1753                                 snprintf(xstats_names[stat_idx].name,
1754                                          RTE_ETH_XSTATS_NAME_SIZE,
1755                                          "%.4s%d.%d%s",
1756                                          qede_rxq_xstats_strings[i].name,
1757                                          hw_fn, qid,
1758                                          qede_rxq_xstats_strings[i].name + 4);
1759                                 stat_idx++;
1760                         }
1761                 }
1762         }
1763
1764         return stat_cnt;
1765 }
1766
1767 static int
1768 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1769                 unsigned int n)
1770 {
1771         struct qede_dev *qdev = dev->data->dev_private;
1772         struct ecore_dev *edev = &qdev->edev;
1773         struct ecore_eth_stats stats;
1774         const unsigned int num = qede_get_xstats_count(qdev);
1775         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1776
1777         if (n < num)
1778                 return num;
1779
1780         ecore_get_vport_stats(edev, &stats);
1781
1782         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1783                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1784                                              qede_xstats_strings[i].offset);
1785                 xstats[stat_idx].id = stat_idx;
1786                 stat_idx++;
1787         }
1788
1789         if (ECORE_IS_BB(edev)) {
1790                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1791                         xstats[stat_idx].value =
1792                                         *(uint64_t *)(((char *)&stats) +
1793                                         qede_bb_xstats_strings[i].offset);
1794                         xstats[stat_idx].id = stat_idx;
1795                         stat_idx++;
1796                 }
1797         } else {
1798                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1799                         xstats[stat_idx].value =
1800                                         *(uint64_t *)(((char *)&stats) +
1801                                         qede_ah_xstats_strings[i].offset);
1802                         xstats[stat_idx].id = stat_idx;
1803                         stat_idx++;
1804                 }
1805         }
1806
1807         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1808                 for_each_hwfn(edev, hw_fn) {
1809                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1810                                 fpidx = qid * edev->num_hwfns + hw_fn;
1811                                 xstats[stat_idx].value = *(uint64_t *)
1812                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1813                                          qede_rxq_xstats_strings[i].offset);
1814                                 xstats[stat_idx].id = stat_idx;
1815                                 stat_idx++;
1816                         }
1817
1818                 }
1819         }
1820
1821         return stat_idx;
1822 }
1823
1824 static int
1825 qede_reset_xstats(struct rte_eth_dev *dev)
1826 {
1827         struct qede_dev *qdev = dev->data->dev_private;
1828         struct ecore_dev *edev = &qdev->edev;
1829
1830         ecore_reset_vport_stats(edev);
1831         qede_reset_queue_stats(qdev, true);
1832
1833         return 0;
1834 }
1835
1836 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1837 {
1838         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1839         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1840         struct qed_link_params link_params;
1841         int rc;
1842
1843         DP_INFO(edev, "setting link state %d\n", link_up);
1844         memset(&link_params, 0, sizeof(link_params));
1845         link_params.link_up = link_up;
1846         rc = qdev->ops->common->set_link(edev, &link_params);
1847         if (rc != ECORE_SUCCESS)
1848                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1849
1850         return rc;
1851 }
1852
1853 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1854 {
1855         return qede_dev_set_link_state(eth_dev, true);
1856 }
1857
1858 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1859 {
1860         return qede_dev_set_link_state(eth_dev, false);
1861 }
1862
1863 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1864 {
1865         struct qede_dev *qdev = eth_dev->data->dev_private;
1866         struct ecore_dev *edev = &qdev->edev;
1867
1868         ecore_reset_vport_stats(edev);
1869         qede_reset_queue_stats(qdev, false);
1870
1871         return 0;
1872 }
1873
1874 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1875 {
1876         enum qed_filter_rx_mode_type type =
1877             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1878         enum _ecore_status_t ecore_status;
1879
1880         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1881
1882         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1883 }
1884
1885 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1886 {
1887         enum _ecore_status_t ecore_status;
1888
1889         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1890                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1891                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1892         else
1893                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1894                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1895
1896         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1897 }
1898
1899 static int
1900 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1901                 struct rte_ether_addr *mc_addrs,
1902                 uint32_t mc_addrs_num)
1903 {
1904         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1905         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1906         uint8_t i;
1907
1908         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1909                 DP_ERR(edev, "Reached max multicast filters limit,"
1910                              "Please enable multicast promisc mode\n");
1911                 return -ENOSPC;
1912         }
1913
1914         for (i = 0; i < mc_addrs_num; i++) {
1915                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1916                         DP_ERR(edev, "Not a valid multicast MAC\n");
1917                         return -EINVAL;
1918                 }
1919         }
1920
1921         /* Flush all existing entries */
1922         if (qede_del_mcast_filters(eth_dev))
1923                 return -1;
1924
1925         /* Set new mcast list */
1926         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1927 }
1928
1929 /* Update MTU via vport-update without doing port restart.
1930  * The vport must be deactivated before calling this API.
1931  */
1932 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1933 {
1934         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1935         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1936         struct ecore_hwfn *p_hwfn;
1937         int rc;
1938         int i;
1939
1940         if (IS_PF(edev)) {
1941                 struct ecore_sp_vport_update_params params;
1942
1943                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1944                 params.vport_id = 0;
1945                 params.mtu = mtu;
1946                 params.vport_id = 0;
1947                 for_each_hwfn(edev, i) {
1948                         p_hwfn = &edev->hwfns[i];
1949                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1950                         rc = ecore_sp_vport_update(p_hwfn, &params,
1951                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1952                         if (rc != ECORE_SUCCESS)
1953                                 goto err;
1954                 }
1955         } else {
1956                 for_each_hwfn(edev, i) {
1957                         p_hwfn = &edev->hwfns[i];
1958                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1959                         if (rc == ECORE_INVAL) {
1960                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1961                                 /* Recreate vport */
1962                                 rc = qede_start_vport(qdev, mtu);
1963                                 if (rc != ECORE_SUCCESS)
1964                                         goto err;
1965
1966                                 /* Restore config lost due to vport stop */
1967                                 if (eth_dev->data->promiscuous)
1968                                         qede_promiscuous_enable(eth_dev);
1969                                 else
1970                                         qede_promiscuous_disable(eth_dev);
1971
1972                                 if (eth_dev->data->all_multicast)
1973                                         qede_allmulticast_enable(eth_dev);
1974                                 else
1975                                         qede_allmulticast_disable(eth_dev);
1976
1977                                 qede_vlan_offload_set(eth_dev,
1978                                                       qdev->vlan_offload_mask);
1979                         } else if (rc != ECORE_SUCCESS) {
1980                                 goto err;
1981                         }
1982                 }
1983         }
1984         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1985
1986         return 0;
1987
1988 err:
1989         DP_ERR(edev, "Failed to update MTU\n");
1990         return -1;
1991 }
1992
1993 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1994                               struct rte_eth_fc_conf *fc_conf)
1995 {
1996         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1997         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1998         struct qed_link_output current_link;
1999         struct qed_link_params params;
2000
2001         memset(&current_link, 0, sizeof(current_link));
2002         qdev->ops->common->get_link(edev, &current_link);
2003
2004         memset(&params, 0, sizeof(params));
2005         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2006         if (fc_conf->autoneg) {
2007                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2008                         DP_ERR(edev, "Autoneg not supported\n");
2009                         return -EINVAL;
2010                 }
2011                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2012         }
2013
2014         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2015         if (fc_conf->mode == RTE_FC_FULL)
2016                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2017                                         QED_LINK_PAUSE_RX_ENABLE);
2018         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2019                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2020         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2021                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2022
2023         params.link_up = true;
2024         (void)qdev->ops->common->set_link(edev, &params);
2025
2026         return 0;
2027 }
2028
2029 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2030                               struct rte_eth_fc_conf *fc_conf)
2031 {
2032         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2033         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2034         struct qed_link_output current_link;
2035
2036         memset(&current_link, 0, sizeof(current_link));
2037         qdev->ops->common->get_link(edev, &current_link);
2038
2039         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2040                 fc_conf->autoneg = true;
2041
2042         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2043                                          QED_LINK_PAUSE_TX_ENABLE))
2044                 fc_conf->mode = RTE_FC_FULL;
2045         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2046                 fc_conf->mode = RTE_FC_RX_PAUSE;
2047         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2048                 fc_conf->mode = RTE_FC_TX_PAUSE;
2049         else
2050                 fc_conf->mode = RTE_FC_NONE;
2051
2052         return 0;
2053 }
2054
2055 static const uint32_t *
2056 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2057 {
2058         static const uint32_t ptypes[] = {
2059                 RTE_PTYPE_L2_ETHER,
2060                 RTE_PTYPE_L2_ETHER_VLAN,
2061                 RTE_PTYPE_L3_IPV4,
2062                 RTE_PTYPE_L3_IPV6,
2063                 RTE_PTYPE_L4_TCP,
2064                 RTE_PTYPE_L4_UDP,
2065                 RTE_PTYPE_TUNNEL_VXLAN,
2066                 RTE_PTYPE_L4_FRAG,
2067                 RTE_PTYPE_TUNNEL_GENEVE,
2068                 RTE_PTYPE_TUNNEL_GRE,
2069                 /* Inner */
2070                 RTE_PTYPE_INNER_L2_ETHER,
2071                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2072                 RTE_PTYPE_INNER_L3_IPV4,
2073                 RTE_PTYPE_INNER_L3_IPV6,
2074                 RTE_PTYPE_INNER_L4_TCP,
2075                 RTE_PTYPE_INNER_L4_UDP,
2076                 RTE_PTYPE_INNER_L4_FRAG,
2077                 RTE_PTYPE_UNKNOWN
2078         };
2079
2080         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2081             eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2082             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2083                 return ptypes;
2084
2085         return NULL;
2086 }
2087
2088 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2089 {
2090         *rss_caps = 0;
2091         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2092         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2093         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2094         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2095         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2096         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2097         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2098         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2099 }
2100
2101 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2102                          struct rte_eth_rss_conf *rss_conf)
2103 {
2104         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2105         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2106         struct ecore_sp_vport_update_params vport_update_params;
2107         struct ecore_rss_params rss_params;
2108         struct ecore_hwfn *p_hwfn;
2109         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2110         uint64_t hf = rss_conf->rss_hf;
2111         uint8_t len = rss_conf->rss_key_len;
2112         uint8_t idx, i, j, fpidx;
2113         int rc;
2114
2115         memset(&vport_update_params, 0, sizeof(vport_update_params));
2116         memset(&rss_params, 0, sizeof(rss_params));
2117
2118         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2119                 (unsigned long)hf, len, key);
2120
2121         if (hf != 0) {
2122                 /* Enabling RSS */
2123                 DP_INFO(edev, "Enabling rss\n");
2124
2125                 /* RSS caps */
2126                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2127                 rss_params.update_rss_capabilities = 1;
2128
2129                 /* RSS hash key */
2130                 if (key) {
2131                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2132                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2133                                 return -EINVAL;
2134                         }
2135                         DP_INFO(edev, "Applying user supplied hash key\n");
2136                         rss_params.update_rss_key = 1;
2137                         memcpy(&rss_params.rss_key, key, len);
2138                 }
2139                 rss_params.rss_enable = 1;
2140         }
2141
2142         rss_params.update_rss_config = 1;
2143         /* tbl_size has to be set with capabilities */
2144         rss_params.rss_table_size_log = 7;
2145         vport_update_params.vport_id = 0;
2146
2147         for_each_hwfn(edev, i) {
2148                 /* pass the L2 handles instead of qids */
2149                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2150                         idx = j % QEDE_RSS_COUNT(eth_dev);
2151                         fpidx = idx * edev->num_hwfns + i;
2152                         rss_params.rss_ind_table[j] =
2153                                 qdev->fp_array[fpidx].rxq->handle;
2154                 }
2155
2156                 vport_update_params.rss_params = &rss_params;
2157
2158                 p_hwfn = &edev->hwfns[i];
2159                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2160                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2161                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2162                 if (rc) {
2163                         DP_ERR(edev, "vport-update for RSS failed\n");
2164                         return rc;
2165                 }
2166         }
2167         qdev->rss_enable = rss_params.rss_enable;
2168
2169         /* Update local structure for hash query */
2170         qdev->rss_conf.rss_hf = hf;
2171         qdev->rss_conf.rss_key_len = len;
2172         if (qdev->rss_enable) {
2173                 if  (qdev->rss_conf.rss_key == NULL) {
2174                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2175                         if (qdev->rss_conf.rss_key == NULL) {
2176                                 DP_ERR(edev, "No memory to store RSS key\n");
2177                                 return -ENOMEM;
2178                         }
2179                 }
2180                 if (key && len) {
2181                         DP_INFO(edev, "Storing RSS key\n");
2182                         memcpy(qdev->rss_conf.rss_key, key, len);
2183                 }
2184         } else if (!qdev->rss_enable && len == 0) {
2185                 if (qdev->rss_conf.rss_key) {
2186                         free(qdev->rss_conf.rss_key);
2187                         qdev->rss_conf.rss_key = NULL;
2188                         DP_INFO(edev, "Free RSS key\n");
2189                 }
2190         }
2191
2192         return 0;
2193 }
2194
2195 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2196                            struct rte_eth_rss_conf *rss_conf)
2197 {
2198         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2199
2200         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2201         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2202
2203         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2204                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2205                        rss_conf->rss_key_len);
2206         return 0;
2207 }
2208
2209 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2210                          struct rte_eth_rss_reta_entry64 *reta_conf,
2211                          uint16_t reta_size)
2212 {
2213         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2214         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2215         struct ecore_sp_vport_update_params vport_update_params;
2216         struct ecore_rss_params *params;
2217         uint16_t i, j, idx, fid, shift;
2218         struct ecore_hwfn *p_hwfn;
2219         uint8_t entry;
2220         int rc = 0;
2221
2222         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2223                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2224                        reta_size);
2225                 return -EINVAL;
2226         }
2227
2228         memset(&vport_update_params, 0, sizeof(vport_update_params));
2229         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2230         if (params == NULL) {
2231                 DP_ERR(edev, "failed to allocate memory\n");
2232                 return -ENOMEM;
2233         }
2234
2235         params->update_rss_ind_table = 1;
2236         params->rss_table_size_log = 7;
2237         params->update_rss_config = 1;
2238
2239         vport_update_params.vport_id = 0;
2240         /* Use the current value of rss_enable */
2241         params->rss_enable = qdev->rss_enable;
2242         vport_update_params.rss_params = params;
2243
2244         for_each_hwfn(edev, i) {
2245                 for (j = 0; j < reta_size; j++) {
2246                         idx = j / RTE_RETA_GROUP_SIZE;
2247                         shift = j % RTE_RETA_GROUP_SIZE;
2248                         if (reta_conf[idx].mask & (1ULL << shift)) {
2249                                 entry = reta_conf[idx].reta[shift];
2250                                 fid = entry * edev->num_hwfns + i;
2251                                 /* Pass rxq handles to ecore */
2252                                 params->rss_ind_table[j] =
2253                                                 qdev->fp_array[fid].rxq->handle;
2254                                 /* Update the local copy for RETA query cmd */
2255                                 qdev->rss_ind_table[j] = entry;
2256                         }
2257                 }
2258
2259                 p_hwfn = &edev->hwfns[i];
2260                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2261                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2262                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2263                 if (rc) {
2264                         DP_ERR(edev, "vport-update for RSS failed\n");
2265                         goto out;
2266                 }
2267         }
2268
2269 out:
2270         rte_free(params);
2271         return rc;
2272 }
2273
2274 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2275                                struct rte_eth_rss_reta_entry64 *reta_conf,
2276                                uint16_t reta_size)
2277 {
2278         struct qede_dev *qdev = eth_dev->data->dev_private;
2279         struct ecore_dev *edev = &qdev->edev;
2280         uint16_t i, idx, shift;
2281         uint8_t entry;
2282
2283         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2284                 DP_ERR(edev, "reta_size %d is not supported\n",
2285                        reta_size);
2286                 return -EINVAL;
2287         }
2288
2289         for (i = 0; i < reta_size; i++) {
2290                 idx = i / RTE_RETA_GROUP_SIZE;
2291                 shift = i % RTE_RETA_GROUP_SIZE;
2292                 if (reta_conf[idx].mask & (1ULL << shift)) {
2293                         entry = qdev->rss_ind_table[i];
2294                         reta_conf[idx].reta[shift] = entry;
2295                 }
2296         }
2297
2298         return 0;
2299 }
2300
2301
2302
2303 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2304 {
2305         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2306         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2307         struct rte_eth_dev_info dev_info = {0};
2308         struct qede_fastpath *fp;
2309         uint32_t max_rx_pkt_len;
2310         uint32_t frame_size;
2311         uint16_t bufsz;
2312         bool restart = false;
2313         int i, rc;
2314
2315         PMD_INIT_FUNC_TRACE(edev);
2316         rc = qede_dev_info_get(dev, &dev_info);
2317         if (rc != 0) {
2318                 DP_ERR(edev, "Error during getting ethernet device info\n");
2319                 return rc;
2320         }
2321         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2322         frame_size = max_rx_pkt_len;
2323         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2324                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2325                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2326                        QEDE_ETH_OVERHEAD);
2327                 return -EINVAL;
2328         }
2329         if (!dev->data->scattered_rx &&
2330             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2331                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2332                         dev->data->min_rx_buf_size);
2333                 return -EINVAL;
2334         }
2335         if (dev->data->dev_started) {
2336                 dev->data->dev_started = 0;
2337                 qede_dev_stop(dev);
2338                 restart = true;
2339         }
2340         rte_delay_ms(1000);
2341         qdev->new_mtu = mtu;
2342
2343         /* Fix up RX buf size for all queues of the port */
2344         for (i = 0; i < qdev->num_rx_queues; i++) {
2345                 fp = &qdev->fp_array[i];
2346                 if (fp->rxq != NULL) {
2347                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2348                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2349                         /* cache align the mbuf size to simplfy rx_buf_size
2350                          * calculation
2351                          */
2352                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2353                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2354                         if (rc < 0)
2355                                 return rc;
2356
2357                         fp->rxq->rx_buf_size = rc;
2358                 }
2359         }
2360         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2361                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2362         else
2363                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2364
2365         if (!dev->data->dev_started && restart) {
2366                 qede_dev_start(dev);
2367                 dev->data->dev_started = 1;
2368         }
2369
2370         /* update max frame size */
2371         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2372
2373         return 0;
2374 }
2375
2376 static int
2377 qede_dev_reset(struct rte_eth_dev *dev)
2378 {
2379         int ret;
2380
2381         ret = qede_eth_dev_uninit(dev);
2382         if (ret)
2383                 return ret;
2384
2385         return qede_eth_dev_init(dev);
2386 }
2387
2388 static const struct eth_dev_ops qede_eth_dev_ops = {
2389         .dev_configure = qede_dev_configure,
2390         .dev_infos_get = qede_dev_info_get,
2391         .rx_queue_setup = qede_rx_queue_setup,
2392         .rx_queue_release = qede_rx_queue_release,
2393         .rx_descriptor_status = qede_rx_descriptor_status,
2394         .tx_queue_setup = qede_tx_queue_setup,
2395         .tx_queue_release = qede_tx_queue_release,
2396         .dev_start = qede_dev_start,
2397         .dev_reset = qede_dev_reset,
2398         .dev_set_link_up = qede_dev_set_link_up,
2399         .dev_set_link_down = qede_dev_set_link_down,
2400         .link_update = qede_link_update,
2401         .promiscuous_enable = qede_promiscuous_enable,
2402         .promiscuous_disable = qede_promiscuous_disable,
2403         .allmulticast_enable = qede_allmulticast_enable,
2404         .allmulticast_disable = qede_allmulticast_disable,
2405         .set_mc_addr_list = qede_set_mc_addr_list,
2406         .dev_stop = qede_dev_stop,
2407         .dev_close = qede_dev_close,
2408         .stats_get = qede_get_stats,
2409         .stats_reset = qede_reset_stats,
2410         .xstats_get = qede_get_xstats,
2411         .xstats_reset = qede_reset_xstats,
2412         .xstats_get_names = qede_get_xstats_names,
2413         .mac_addr_add = qede_mac_addr_add,
2414         .mac_addr_remove = qede_mac_addr_remove,
2415         .mac_addr_set = qede_mac_addr_set,
2416         .vlan_offload_set = qede_vlan_offload_set,
2417         .vlan_filter_set = qede_vlan_filter_set,
2418         .flow_ctrl_set = qede_flow_ctrl_set,
2419         .flow_ctrl_get = qede_flow_ctrl_get,
2420         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2421         .rss_hash_update = qede_rss_hash_update,
2422         .rss_hash_conf_get = qede_rss_hash_conf_get,
2423         .reta_update  = qede_rss_reta_update,
2424         .reta_query  = qede_rss_reta_query,
2425         .mtu_set = qede_set_mtu,
2426         .filter_ctrl = qede_dev_filter_ctrl,
2427         .udp_tunnel_port_add = qede_udp_dst_port_add,
2428         .udp_tunnel_port_del = qede_udp_dst_port_del,
2429         .fw_version_get = qede_fw_version_get,
2430 };
2431
2432 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2433         .dev_configure = qede_dev_configure,
2434         .dev_infos_get = qede_dev_info_get,
2435         .rx_queue_setup = qede_rx_queue_setup,
2436         .rx_queue_release = qede_rx_queue_release,
2437         .rx_descriptor_status = qede_rx_descriptor_status,
2438         .tx_queue_setup = qede_tx_queue_setup,
2439         .tx_queue_release = qede_tx_queue_release,
2440         .dev_start = qede_dev_start,
2441         .dev_reset = qede_dev_reset,
2442         .dev_set_link_up = qede_dev_set_link_up,
2443         .dev_set_link_down = qede_dev_set_link_down,
2444         .link_update = qede_link_update,
2445         .promiscuous_enable = qede_promiscuous_enable,
2446         .promiscuous_disable = qede_promiscuous_disable,
2447         .allmulticast_enable = qede_allmulticast_enable,
2448         .allmulticast_disable = qede_allmulticast_disable,
2449         .set_mc_addr_list = qede_set_mc_addr_list,
2450         .dev_stop = qede_dev_stop,
2451         .dev_close = qede_dev_close,
2452         .stats_get = qede_get_stats,
2453         .stats_reset = qede_reset_stats,
2454         .xstats_get = qede_get_xstats,
2455         .xstats_reset = qede_reset_xstats,
2456         .xstats_get_names = qede_get_xstats_names,
2457         .vlan_offload_set = qede_vlan_offload_set,
2458         .vlan_filter_set = qede_vlan_filter_set,
2459         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2460         .rss_hash_update = qede_rss_hash_update,
2461         .rss_hash_conf_get = qede_rss_hash_conf_get,
2462         .reta_update  = qede_rss_reta_update,
2463         .reta_query  = qede_rss_reta_query,
2464         .mtu_set = qede_set_mtu,
2465         .udp_tunnel_port_add = qede_udp_dst_port_add,
2466         .udp_tunnel_port_del = qede_udp_dst_port_del,
2467         .mac_addr_add = qede_mac_addr_add,
2468         .mac_addr_remove = qede_mac_addr_remove,
2469         .mac_addr_set = qede_mac_addr_set,
2470         .fw_version_get = qede_fw_version_get,
2471 };
2472
2473 static void qede_update_pf_params(struct ecore_dev *edev)
2474 {
2475         struct ecore_pf_params pf_params;
2476
2477         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2478         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2479         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2480         qed_ops->common->update_pf_params(edev, &pf_params);
2481 }
2482
2483 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2484 {
2485         struct rte_pci_device *pci_dev;
2486         struct rte_pci_addr pci_addr;
2487         struct qede_dev *adapter;
2488         struct ecore_dev *edev;
2489         struct qed_dev_eth_info dev_info;
2490         struct qed_slowpath_params params;
2491         static bool do_once = true;
2492         uint8_t bulletin_change;
2493         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2494         uint8_t is_mac_forced;
2495         bool is_mac_exist;
2496         /* Fix up ecore debug level */
2497         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2498         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2499         uint32_t int_mode;
2500         int rc;
2501
2502         /* Extract key data structures */
2503         adapter = eth_dev->data->dev_private;
2504         adapter->ethdev = eth_dev;
2505         edev = &adapter->edev;
2506         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2507         pci_addr = pci_dev->addr;
2508
2509         PMD_INIT_FUNC_TRACE(edev);
2510
2511         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2512                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2513                  eth_dev->data->port_id);
2514
2515         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2516                 DP_ERR(edev, "Skipping device init from secondary process\n");
2517                 return 0;
2518         }
2519
2520         rte_eth_copy_pci_info(eth_dev, pci_dev);
2521
2522         /* @DPDK */
2523         edev->vendor_id = pci_dev->id.vendor_id;
2524         edev->device_id = pci_dev->id.device_id;
2525
2526         qed_ops = qed_get_eth_ops();
2527         if (!qed_ops) {
2528                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2529                 rc = -EINVAL;
2530                 goto err;
2531         }
2532
2533         DP_INFO(edev, "Starting qede probe\n");
2534         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2535                                     dp_level, is_vf);
2536         if (rc != 0) {
2537                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2538                 rc = -ENODEV;
2539                 goto err;
2540         }
2541         qede_update_pf_params(edev);
2542
2543         switch (pci_dev->intr_handle.type) {
2544         case RTE_INTR_HANDLE_UIO_INTX:
2545         case RTE_INTR_HANDLE_VFIO_LEGACY:
2546                 int_mode = ECORE_INT_MODE_INTA;
2547                 rte_intr_callback_register(&pci_dev->intr_handle,
2548                                            qede_interrupt_handler_intx,
2549                                            (void *)eth_dev);
2550                 break;
2551         default:
2552                 int_mode = ECORE_INT_MODE_MSIX;
2553                 rte_intr_callback_register(&pci_dev->intr_handle,
2554                                            qede_interrupt_handler,
2555                                            (void *)eth_dev);
2556         }
2557
2558         if (rte_intr_enable(&pci_dev->intr_handle)) {
2559                 DP_ERR(edev, "rte_intr_enable() failed\n");
2560                 rc = -ENODEV;
2561                 goto err;
2562         }
2563
2564         /* Start the Slowpath-process */
2565         memset(&params, 0, sizeof(struct qed_slowpath_params));
2566
2567         params.int_mode = int_mode;
2568         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2569         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2570         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2571         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2572         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2573                 QEDE_PMD_DRV_VER_STR_SIZE);
2574
2575         qede_assign_rxtx_handlers(eth_dev, true);
2576         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2577
2578         /* For CMT mode device do periodic polling for slowpath events.
2579          * This is required since uio device uses only one MSI-x
2580          * interrupt vector but we need one for each engine.
2581          */
2582         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2583                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2584                                        qede_poll_sp_sb_cb,
2585                                        (void *)eth_dev);
2586                 if (rc != 0) {
2587                         DP_ERR(edev, "Unable to start periodic"
2588                                      " timer rc %d\n", rc);
2589                         rc = -EINVAL;
2590                         goto err;
2591                 }
2592         }
2593
2594         rc = qed_ops->common->slowpath_start(edev, &params);
2595         if (rc) {
2596                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2597                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2598                                      (void *)eth_dev);
2599                 rc = -ENODEV;
2600                 goto err;
2601         }
2602
2603         rc = qed_ops->fill_dev_info(edev, &dev_info);
2604         if (rc) {
2605                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2606                 qed_ops->common->slowpath_stop(edev);
2607                 qed_ops->common->remove(edev);
2608                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2609                                      (void *)eth_dev);
2610                 rc = -ENODEV;
2611                 goto err;
2612         }
2613
2614         qede_alloc_etherdev(adapter, &dev_info);
2615
2616         if (do_once) {
2617                 qede_print_adapter_info(eth_dev);
2618                 do_once = false;
2619         }
2620
2621         adapter->ops->common->set_name(edev, edev->name);
2622
2623         if (!is_vf)
2624                 adapter->dev_info.num_mac_filters =
2625                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2626                                             ECORE_MAC);
2627         else
2628                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2629                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2630
2631         /* Allocate memory for storing MAC addr */
2632         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2633                                         (RTE_ETHER_ADDR_LEN *
2634                                         adapter->dev_info.num_mac_filters),
2635                                         RTE_CACHE_LINE_SIZE);
2636
2637         if (eth_dev->data->mac_addrs == NULL) {
2638                 DP_ERR(edev, "Failed to allocate MAC address\n");
2639                 qed_ops->common->slowpath_stop(edev);
2640                 qed_ops->common->remove(edev);
2641                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2642                                      (void *)eth_dev);
2643                 return -ENOMEM;
2644         }
2645
2646         if (!is_vf) {
2647                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2648                                 hw_info.hw_mac_addr,
2649                                 &eth_dev->data->mac_addrs[0]);
2650                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2651                                 &adapter->primary_mac);
2652         } else {
2653                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2654                                        &bulletin_change);
2655                 if (bulletin_change) {
2656                         is_mac_exist =
2657                             ecore_vf_bulletin_get_forced_mac(
2658                                                 ECORE_LEADING_HWFN(edev),
2659                                                 vf_mac,
2660                                                 &is_mac_forced);
2661                         if (is_mac_exist) {
2662                                 DP_INFO(edev, "VF macaddr received from PF\n");
2663                                 rte_ether_addr_copy(
2664                                         (struct rte_ether_addr *)&vf_mac,
2665                                         &eth_dev->data->mac_addrs[0]);
2666                                 rte_ether_addr_copy(
2667                                         &eth_dev->data->mac_addrs[0],
2668                                         &adapter->primary_mac);
2669                         } else {
2670                                 DP_ERR(edev, "No VF macaddr assigned\n");
2671                         }
2672                 }
2673         }
2674
2675         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2676
2677         adapter->num_tx_queues = 0;
2678         adapter->num_rx_queues = 0;
2679         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2680         SLIST_INIT(&adapter->vlan_list_head);
2681         SLIST_INIT(&adapter->uc_list_head);
2682         SLIST_INIT(&adapter->mc_list_head);
2683         adapter->mtu = RTE_ETHER_MTU;
2684         adapter->vport_started = false;
2685
2686         /* VF tunnel offloads is enabled by default in PF driver */
2687         adapter->vxlan.num_filters = 0;
2688         adapter->geneve.num_filters = 0;
2689         adapter->ipgre.num_filters = 0;
2690         if (is_vf) {
2691                 adapter->vxlan.enable = true;
2692                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2693                                              ETH_TUNNEL_FILTER_IVLAN;
2694                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2695                 adapter->geneve.enable = true;
2696                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2697                                               ETH_TUNNEL_FILTER_IVLAN;
2698                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2699                 adapter->ipgre.enable = true;
2700                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2701                                              ETH_TUNNEL_FILTER_IVLAN;
2702         } else {
2703                 adapter->vxlan.enable = false;
2704                 adapter->geneve.enable = false;
2705                 adapter->ipgre.enable = false;
2706         }
2707
2708         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2709                 adapter->primary_mac.addr_bytes[0],
2710                 adapter->primary_mac.addr_bytes[1],
2711                 adapter->primary_mac.addr_bytes[2],
2712                 adapter->primary_mac.addr_bytes[3],
2713                 adapter->primary_mac.addr_bytes[4],
2714                 adapter->primary_mac.addr_bytes[5]);
2715
2716         DP_INFO(edev, "Device initialized\n");
2717
2718         return 0;
2719
2720 err:
2721         if (do_once) {
2722                 qede_print_adapter_info(eth_dev);
2723                 do_once = false;
2724         }
2725         return rc;
2726 }
2727
2728 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2729 {
2730         return qede_common_dev_init(eth_dev, 1);
2731 }
2732
2733 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2734 {
2735         return qede_common_dev_init(eth_dev, 0);
2736 }
2737
2738 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2739 {
2740         struct qede_dev *qdev = eth_dev->data->dev_private;
2741         struct ecore_dev *edev = &qdev->edev;
2742
2743         PMD_INIT_FUNC_TRACE(edev);
2744
2745         /* only uninitialize in the primary process */
2746         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2747                 return 0;
2748
2749         /* safe to close dev here */
2750         qede_dev_close(eth_dev);
2751
2752         eth_dev->dev_ops = NULL;
2753         eth_dev->rx_pkt_burst = NULL;
2754         eth_dev->tx_pkt_burst = NULL;
2755
2756         return 0;
2757 }
2758
2759 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2760 {
2761         return qede_dev_common_uninit(eth_dev);
2762 }
2763
2764 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2765 {
2766         return qede_dev_common_uninit(eth_dev);
2767 }
2768
2769 static const struct rte_pci_id pci_id_qedevf_map[] = {
2770 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2771         {
2772                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2773         },
2774         {
2775                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2776         },
2777         {
2778                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2779         },
2780         {.vendor_id = 0,}
2781 };
2782
2783 static const struct rte_pci_id pci_id_qede_map[] = {
2784 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2785         {
2786                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2787         },
2788         {
2789                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2790         },
2791         {
2792                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2793         },
2794         {
2795                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2796         },
2797         {
2798                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2799         },
2800         {
2801                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2802         },
2803         {
2804                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2805         },
2806         {
2807                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2808         },
2809         {
2810                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2811         },
2812         {
2813                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2814         },
2815         {.vendor_id = 0,}
2816 };
2817
2818 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2819         struct rte_pci_device *pci_dev)
2820 {
2821         return rte_eth_dev_pci_generic_probe(pci_dev,
2822                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2823 }
2824
2825 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2826 {
2827         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2828 }
2829
2830 static struct rte_pci_driver rte_qedevf_pmd = {
2831         .id_table = pci_id_qedevf_map,
2832         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2833         .probe = qedevf_eth_dev_pci_probe,
2834         .remove = qedevf_eth_dev_pci_remove,
2835 };
2836
2837 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2838         struct rte_pci_device *pci_dev)
2839 {
2840         return rte_eth_dev_pci_generic_probe(pci_dev,
2841                 sizeof(struct qede_dev), qede_eth_dev_init);
2842 }
2843
2844 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2845 {
2846         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2847 }
2848
2849 static struct rte_pci_driver rte_qede_pmd = {
2850         .id_table = pci_id_qede_map,
2851         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2852         .probe = qede_eth_dev_pci_probe,
2853         .remove = qede_eth_dev_pci_remove,
2854 };
2855
2856 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2857 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2858 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2859 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2860 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2861 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2862 RTE_LOG_REGISTER(qede_logtype_init, pmd.net.qede.init, NOTICE);
2863 RTE_LOG_REGISTER(qede_logtype_driver, pmd.net.qede.driver, NOTICE);