drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_hw_buffer_truncates",
 129                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 130         {"rx_hw_buffer_discards",
 131                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 132         {"tx_error_drop_packets",
 133                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 134
 135         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 136         {"rx_mac_unicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 138         {"rx_mac_multicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 140         {"rx_mac_broadcast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 142         {"rx_mac_frames_ok",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 144         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 145         {"tx_mac_unicast_packets",
 146                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 147         {"tx_mac_multicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 149         {"tx_mac_broadcast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 151
 152         {"lro_coalesced_packets",
 153                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 154         {"lro_coalesced_events",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 156         {"lro_aborts_num",
 157                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 158         {"lro_not_coalesced_packets",
 159                 offsetof(struct ecore_eth_stats_common,
 160                          tpa_not_coalesced_pkts)},
 161         {"lro_coalesced_bytes",
 162                 offsetof(struct ecore_eth_stats_common,
 163                          tpa_coalesced_bytes)},
 164 };
 165
 166 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 167         {"rx_1519_to_1522_byte_packets",
 168                 offsetof(struct ecore_eth_stats, bb) +
 169                 offsetof(struct ecore_eth_stats_bb,
 170                          rx_1519_to_1522_byte_packets)},
 171         {"rx_1519_to_2047_byte_packets",
 172                 offsetof(struct ecore_eth_stats, bb) +
 173                 offsetof(struct ecore_eth_stats_bb,
 174                          rx_1519_to_2047_byte_packets)},
 175         {"rx_2048_to_4095_byte_packets",
 176                 offsetof(struct ecore_eth_stats, bb) +
 177                 offsetof(struct ecore_eth_stats_bb,
 178                          rx_2048_to_4095_byte_packets)},
 179         {"rx_4096_to_9216_byte_packets",
 180                 offsetof(struct ecore_eth_stats, bb) +
 181                 offsetof(struct ecore_eth_stats_bb,
 182                          rx_4096_to_9216_byte_packets)},
 183         {"rx_9217_to_16383_byte_packets",
 184                 offsetof(struct ecore_eth_stats, bb) +
 185                 offsetof(struct ecore_eth_stats_bb,
 186                          rx_9217_to_16383_byte_packets)},
 187
 188         {"tx_1519_to_2047_byte_packets",
 189                 offsetof(struct ecore_eth_stats, bb) +
 190                 offsetof(struct ecore_eth_stats_bb,
 191                          tx_1519_to_2047_byte_packets)},
 192         {"tx_2048_to_4095_byte_packets",
 193                 offsetof(struct ecore_eth_stats, bb) +
 194                 offsetof(struct ecore_eth_stats_bb,
 195                          tx_2048_to_4095_byte_packets)},
 196         {"tx_4096_to_9216_byte_packets",
 197                 offsetof(struct ecore_eth_stats, bb) +
 198                 offsetof(struct ecore_eth_stats_bb,
 199                          tx_4096_to_9216_byte_packets)},
 200         {"tx_9217_to_16383_byte_packets",
 201                 offsetof(struct ecore_eth_stats, bb) +
 202                 offsetof(struct ecore_eth_stats_bb,
 203                          tx_9217_to_16383_byte_packets)},
 204
 205         {"tx_lpi_entry_count",
 206                 offsetof(struct ecore_eth_stats, bb) +
 207                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 208         {"tx_total_collisions",
 209                 offsetof(struct ecore_eth_stats, bb) +
 210                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 211 };
 212
 213 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 214         {"rx_1519_to_max_byte_packets",
 215                 offsetof(struct ecore_eth_stats, ah) +
 216                 offsetof(struct ecore_eth_stats_ah,
 217                          rx_1519_to_max_byte_packets)},
 218         {"tx_1519_to_max_byte_packets",
 219                 offsetof(struct ecore_eth_stats, ah) +
 220                 offsetof(struct ecore_eth_stats_ah,
 221                          tx_1519_to_max_byte_packets)},
 222 };
 223
 224 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 225         {"rx_q_segments",
 226                 offsetof(struct qede_rx_queue, rx_segs)},
 227         {"rx_q_hw_errors",
 228                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 229         {"rx_q_allocation_errors",
 230                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 231 };
 232
 233 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 234 {
 235         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 236 }
 237
 238 static void
 239 qede_interrupt_handler_intx(void *param)
 240 {
 241         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 242         struct qede_dev *qdev = eth_dev->data->dev_private;
 243         struct ecore_dev *edev = &qdev->edev;
 244         u64 status;
 245
 246         /* Check if our device actually raised an interrupt */
 247         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 248         if (status & 0x1) {
 249                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 250
 251                 if (rte_intr_ack(eth_dev->intr_handle))
 252                         DP_ERR(edev, "rte_intr_ack failed\n");
 253         }
 254 }
 255
 256 static void
 257 qede_interrupt_handler(void *param)
 258 {
 259         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 260         struct qede_dev *qdev = eth_dev->data->dev_private;
 261         struct ecore_dev *edev = &qdev->edev;
 262
 263         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 264         if (rte_intr_ack(eth_dev->intr_handle))
 265                 DP_ERR(edev, "rte_intr_ack failed\n");
 266 }
 267
 268 static void
 269 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 270 {
 271         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 272         qdev->ops = qed_ops;
 273 }
 274
 275 static void qede_print_adapter_info(struct qede_dev *qdev)
 276 {
 277         struct ecore_dev *edev = &qdev->edev;
 278         struct qed_dev_info *info = &qdev->dev_info.common;
 279         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 280         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 281
 282         DP_INFO(edev, "*********************************\n");
 283         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 284         DP_INFO(edev, " Chip details : %s %c%d\n",
 285                   ECORE_IS_BB(edev) ? "BB" : "AH",
 286                   'A' + edev->chip_rev,
 287                   (int)edev->chip_metal);
 288         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 289                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 290         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 291                  ver_str, QEDE_PMD_VERSION);
 292         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 293         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 294
 295         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 296                  "%d.%d.%d.%d",
 297                 (info->mfw_rev >> 24) & 0xff,
 298                 (info->mfw_rev >> 16) & 0xff,
 299                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 300         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 301         DP_INFO(edev, " Firmware file : %s\n", qede_fw_file);
 302         DP_INFO(edev, "*********************************\n");
 303 }
 304
 305 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 306 {
 307         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 308         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 309         unsigned int i = 0, j = 0, qid;
 310         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 311         struct qede_tx_queue *txq;
 312
 313         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 314
 315         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 316                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 317         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 318                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 319
 320         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 321                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 322                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 323                             sizeof(uint64_t));
 324                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 325                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 326                             sizeof(uint64_t));
 327                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 328                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 329                             sizeof(uint64_t));
 330
 331                 if (xstats)
 332                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 333                                 OSAL_MEMSET((((char *)
 334                                               (qdev->fp_array[qid].rxq)) +
 335                                              qede_rxq_xstats_strings[j].offset),
 336                                             0,
 337                                             sizeof(uint64_t));
 338
 339                 i++;
 340                 if (i == rxq_stat_cntrs)
 341                         break;
 342         }
 343
 344         i = 0;
 345
 346         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 347                 txq = qdev->fp_array[qid].txq;
 348
 349                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 350                                 (((uint64_t)(uintptr_t)(txq)) +
 351                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 352                             sizeof(uint64_t));
 353
 354                 i++;
 355                 if (i == txq_stat_cntrs)
 356                         break;
 357         }
 358 }
 359
 360 static int
 361 qede_stop_vport(struct ecore_dev *edev)
 362 {
 363         struct ecore_hwfn *p_hwfn;
 364         uint8_t vport_id;
 365         int rc;
 366         int i;
 367
 368         vport_id = 0;
 369         for_each_hwfn(edev, i) {
 370                 p_hwfn = &edev->hwfns[i];
 371                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 372                                          vport_id);
 373                 if (rc != ECORE_SUCCESS) {
 374                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 375                         return rc;
 376                 }
 377         }
 378
 379         DP_INFO(edev, "vport stopped\n");
 380
 381         return 0;
 382 }
 383
 384 static int
 385 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 386 {
 387         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 388         struct ecore_sp_vport_start_params params;
 389         struct ecore_hwfn *p_hwfn;
 390         int rc;
 391         int i;
 392
 393         if (qdev->vport_started)
 394                 qede_stop_vport(edev);
 395
 396         memset(&params, 0, sizeof(params));
 397         params.vport_id = 0;
 398         params.mtu = mtu;
 399         /* @DPDK - Disable FW placement */
 400         params.zero_placement_offset = 1;
 401         for_each_hwfn(edev, i) {
 402                 p_hwfn = &edev->hwfns[i];
 403                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 404                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 405                 rc = ecore_sp_vport_start(p_hwfn, &params);
 406                 if (rc != ECORE_SUCCESS) {
 407                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 408                         return rc;
 409                 }
 410         }
 411         ecore_reset_vport_stats(edev);
 412         qdev->vport_started = true;
 413         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 414
 415         return 0;
 416 }
 417
 418 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 419 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 420
 421 /* Activate or deactivate vport via vport-update */
 422 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 423 {
 424         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 425         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 426         struct ecore_sp_vport_update_params params;
 427         struct ecore_hwfn *p_hwfn;
 428         uint8_t i;
 429         int rc = -1;
 430
 431         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 432         params.vport_id = 0;
 433         params.update_vport_active_rx_flg = 1;
 434         params.update_vport_active_tx_flg = 1;
 435         params.vport_active_rx_flg = flg;
 436         params.vport_active_tx_flg = flg;
 437         if (~qdev->enable_tx_switching & flg) {
 438                 params.update_tx_switching_flg = 1;
 439                 params.tx_switching_flg = !flg;
 440         }
 441         for_each_hwfn(edev, i) {
 442                 p_hwfn = &edev->hwfns[i];
 443                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 444                 rc = ecore_sp_vport_update(p_hwfn, &params,
 445                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 446                 if (rc != ECORE_SUCCESS) {
 447                         DP_ERR(edev, "Failed to update vport\n");
 448                         break;
 449                 }
 450         }
 451         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 452
 453         return rc;
 454 }
 455
 456 static void
 457 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 458                            uint16_t mtu, bool enable)
 459 {
 460         /* Enable LRO in split mode */
 461         sge_tpa_params->tpa_ipv4_en_flg = enable;
 462         sge_tpa_params->tpa_ipv6_en_flg = enable;
 463         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 464         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 465         /* set if tpa enable changes */
 466         sge_tpa_params->update_tpa_en_flg = 1;
 467         /* set if tpa parameters should be handled */
 468         sge_tpa_params->update_tpa_param_flg = enable;
 469
 470         sge_tpa_params->max_buffers_per_cqe = 20;
 471         /* Enable TPA in split mode. In this mode each TPA segment
 472          * starts on the new BD, so there is one BD per segment.
 473          */
 474         sge_tpa_params->tpa_pkt_split_flg = 1;
 475         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 476         sge_tpa_params->tpa_gro_consistent_flg = 0;
 477         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 478         sge_tpa_params->tpa_max_size = 0x7FFF;
 479         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 480         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 481 }
 482
 483 /* Enable/disable LRO via vport-update */
 484 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 485 {
 486         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 487         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 488         struct ecore_sp_vport_update_params params;
 489         struct ecore_sge_tpa_params tpa_params;
 490         struct ecore_hwfn *p_hwfn;
 491         int rc;
 492         int i;
 493
 494         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 495         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 496         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 497         params.vport_id = 0;
 498         params.sge_tpa_params = &tpa_params;
 499         for_each_hwfn(edev, i) {
 500                 p_hwfn = &edev->hwfns[i];
 501                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 502                 rc = ecore_sp_vport_update(p_hwfn, &params,
 503                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 504                 if (rc != ECORE_SUCCESS) {
 505                         DP_ERR(edev, "Failed to update LRO\n");
 506                         return -1;
 507                 }
 508         }
 509         qdev->enable_lro = flg;
 510         eth_dev->data->lro = flg;
 511
 512         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 513
 514         return 0;
 515 }
 516
 517 static int
 518 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 519                              enum qed_filter_rx_mode_type type)
 520 {
 521         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 522         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 523         struct ecore_filter_accept_flags flags;
 524
 525         memset(&flags, 0, sizeof(flags));
 526
 527         flags.update_rx_mode_config = 1;
 528         flags.update_tx_mode_config = 1;
 529         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 530                 ECORE_ACCEPT_MCAST_MATCHED |
 531                 ECORE_ACCEPT_BCAST;
 532
 533         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 534                 ECORE_ACCEPT_MCAST_MATCHED |
 535                 ECORE_ACCEPT_BCAST;
 536
 537         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 538                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 539                 if (IS_VF(edev)) {
 540                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 541                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 542                 }
 543         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 544                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 545         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 546                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 547                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 548                         ECORE_ACCEPT_MCAST_UNMATCHED;
 549         }
 550
 551         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 552                         ECORE_SPQ_MODE_CB, NULL);
 553 }
 554
 555 int
 556 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 557                   bool add)
 558 {
 559         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 560         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 561         struct qede_ucast_entry *tmp = NULL;
 562         struct qede_ucast_entry *u;
 563         struct rte_ether_addr *mac_addr;
 564
 565         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 566         if (add) {
 567                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 568                         if ((memcmp(mac_addr, &tmp->mac,
 569                                     RTE_ETHER_ADDR_LEN) == 0) &&
 570                              ucast->vni == tmp->vni &&
 571                              ucast->vlan == tmp->vlan) {
 572                                 DP_INFO(edev, "Unicast MAC is already added"
 573                                         " with vlan = %u, vni = %u\n",
 574                                         ucast->vlan,  ucast->vni);
 575                                         return 0;
 576                         }
 577                 }
 578                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 579                                RTE_CACHE_LINE_SIZE);
 580                 if (!u) {
 581                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 582                         return -ENOMEM;
 583                 }
 584                 rte_ether_addr_copy(mac_addr, &u->mac);
 585                 u->vlan = ucast->vlan;
 586                 u->vni = ucast->vni;
 587                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 588                 qdev->num_uc_addr++;
 589         } else {
 590                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 591                         if ((memcmp(mac_addr, &tmp->mac,
 592                                     RTE_ETHER_ADDR_LEN) == 0) &&
 593                             ucast->vlan == tmp->vlan      &&
 594                             ucast->vni == tmp->vni)
 595                         break;
 596                 }
 597                 if (tmp == NULL) {
 598                         DP_INFO(edev, "Unicast MAC is not found\n");
 599                         return -EINVAL;
 600                 }
 601                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 602                 qdev->num_uc_addr--;
 603         }
 604
 605         return 0;
 606 }
 607
 608 static int
 609 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 610                 struct rte_ether_addr *mc_addrs,
 611                 uint32_t mc_addrs_num)
 612 {
 613         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 614         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 615         struct ecore_filter_mcast mcast;
 616         struct qede_mcast_entry *m = NULL;
 617         uint8_t i;
 618         int rc;
 619
 620         for (i = 0; i < mc_addrs_num; i++) {
 621                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 622                                RTE_CACHE_LINE_SIZE);
 623                 if (!m) {
 624                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 625                         return -ENOMEM;
 626                 }
 627                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 628                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 629         }
 630         memset(&mcast, 0, sizeof(mcast));
 631         mcast.num_mc_addrs = mc_addrs_num;
 632         mcast.opcode = ECORE_FILTER_ADD;
 633         for (i = 0; i < mc_addrs_num; i++)
 634                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 635                                                         &mcast.mac[i]);
 636         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 637         if (rc != ECORE_SUCCESS) {
 638                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 639                 return -1;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 646 {
 647         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 648         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 649         struct qede_mcast_entry *tmp = NULL;
 650         struct ecore_filter_mcast mcast;
 651         int j;
 652         int rc;
 653
 654         memset(&mcast, 0, sizeof(mcast));
 655         mcast.num_mc_addrs = qdev->num_mc_addr;
 656         mcast.opcode = ECORE_FILTER_REMOVE;
 657         j = 0;
 658         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 659                 rte_ether_addr_copy(&tmp->mac,
 660                                 (struct rte_ether_addr *)&mcast.mac[j]);
 661                 j++;
 662         }
 663         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 664         if (rc != ECORE_SUCCESS) {
 665                 DP_ERR(edev, "Failed to delete multicast filter\n");
 666                 return -1;
 667         }
 668         /* Init the list */
 669         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 670                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 671                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 672         }
 673         SLIST_INIT(&qdev->mc_list_head);
 674
 675         return 0;
 676 }
 677
 678 enum _ecore_status_t
 679 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 680                  bool add)
 681 {
 682         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 683         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 684         enum _ecore_status_t rc = ECORE_INVAL;
 685
 686         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 687                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 688                               " Please enable promisc mode\n");
 689                         return ECORE_INVAL;
 690         }
 691
 692         rc = qede_ucast_filter(eth_dev, ucast, add);
 693         if (rc == 0)
 694                 rc = ecore_filter_ucast_cmd(edev, ucast,
 695                                             ECORE_SPQ_MODE_CB, NULL);
 696         /* Indicate error only for add filter operation.
 697          * Delete filter operations are not severe.
 698          */
 699         if ((rc != ECORE_SUCCESS) && add)
 700                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 701                        rc, add);
 702
 703         return rc;
 704 }
 705
 706 static int
 707 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 708                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 709 {
 710         struct ecore_filter_ucast ucast;
 711         int re;
 712
 713         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 714                 return -EINVAL;
 715
 716         qede_set_ucast_cmn_params(&ucast);
 717         ucast.opcode = ECORE_FILTER_ADD;
 718         ucast.type = ECORE_FILTER_MAC;
 719         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 720         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 721         return re;
 722 }
 723
 724 static void
 725 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 726 {
 727         struct qede_dev *qdev = eth_dev->data->dev_private;
 728         struct ecore_dev *edev = &qdev->edev;
 729         struct ecore_filter_ucast ucast;
 730
 731         PMD_INIT_FUNC_TRACE(edev);
 732
 733         if (index >= qdev->dev_info.num_mac_filters) {
 734                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 735                        index, qdev->dev_info.num_mac_filters);
 736                 return;
 737         }
 738
 739         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 740                 return;
 741
 742         qede_set_ucast_cmn_params(&ucast);
 743         ucast.opcode = ECORE_FILTER_REMOVE;
 744         ucast.type = ECORE_FILTER_MAC;
 745
 746         /* Use the index maintained by rte */
 747         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 748                         (struct rte_ether_addr *)&ucast.mac);
 749
 750         qede_mac_int_ops(eth_dev, &ucast, false);
 751 }
 752
 753 static int
 754 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 755 {
 756         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 757         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 758
 759         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 760                                                mac_addr->addr_bytes)) {
 761                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 762                 return -EPERM;
 763         }
 764
 765         qede_mac_addr_remove(eth_dev, 0);
 766
 767         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 768 }
 769
 770 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 771 {
 772         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 773         struct ecore_sp_vport_update_params params;
 774         struct ecore_hwfn *p_hwfn;
 775         uint8_t i;
 776         int rc;
 777
 778         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 779         params.vport_id = 0;
 780         params.update_accept_any_vlan_flg = 1;
 781         params.accept_any_vlan = flg;
 782         for_each_hwfn(edev, i) {
 783                 p_hwfn = &edev->hwfns[i];
 784                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 785                 rc = ecore_sp_vport_update(p_hwfn, &params,
 786                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 787                 if (rc != ECORE_SUCCESS) {
 788                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 789                         return;
 790                 }
 791         }
 792
 793         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 794 }
 795
 796 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 797 {
 798         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 799         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 800         struct ecore_sp_vport_update_params params;
 801         struct ecore_hwfn *p_hwfn;
 802         uint8_t i;
 803         int rc;
 804
 805         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 806         params.vport_id = 0;
 807         params.update_inner_vlan_removal_flg = 1;
 808         params.inner_vlan_removal_flg = flg;
 809         for_each_hwfn(edev, i) {
 810                 p_hwfn = &edev->hwfns[i];
 811                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 812                 rc = ecore_sp_vport_update(p_hwfn, &params,
 813                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 814                 if (rc != ECORE_SUCCESS) {
 815                         DP_ERR(edev, "Failed to update vport\n");
 816                         return -1;
 817                 }
 818         }
 819
 820         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 821         return 0;
 822 }
 823
 824 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 825                                 uint16_t vlan_id, int on)
 826 {
 827         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 828         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 829         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 830         struct qede_vlan_entry *tmp = NULL;
 831         struct qede_vlan_entry *vlan;
 832         struct ecore_filter_ucast ucast;
 833         int rc;
 834
 835         if (on) {
 836                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 837                         DP_ERR(edev, "Reached max VLAN filter limit"
 838                                       " enabling accept_any_vlan\n");
 839                         qede_config_accept_any_vlan(qdev, true);
 840                         return 0;
 841                 }
 842
 843                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 844                         if (tmp->vid == vlan_id) {
 845                                 DP_INFO(edev, "VLAN %u already configured\n",
 846                                         vlan_id);
 847                                 return 0;
 848                         }
 849                 }
 850
 851                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 852                                   RTE_CACHE_LINE_SIZE);
 853
 854                 if (!vlan) {
 855                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 856                         return -ENOMEM;
 857                 }
 858
 859                 qede_set_ucast_cmn_params(&ucast);
 860                 ucast.opcode = ECORE_FILTER_ADD;
 861                 ucast.type = ECORE_FILTER_VLAN;
 862                 ucast.vlan = vlan_id;
 863                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 864                                             NULL);
 865                 if (rc != 0) {
 866                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 867                                rc);
 868                         rte_free(vlan);
 869                 } else {
 870                         vlan->vid = vlan_id;
 871                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 872                         qdev->configured_vlans++;
 873                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 874                                 vlan_id, qdev->configured_vlans);
 875                 }
 876         } else {
 877                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 878                         if (tmp->vid == vlan_id)
 879                                 break;
 880                 }
 881
 882                 if (!tmp) {
 883                         if (qdev->configured_vlans == 0) {
 884                                 DP_INFO(edev,
 885                                         "No VLAN filters configured yet\n");
 886                                 return 0;
 887                         }
 888
 889                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 890                         return -EINVAL;
 891                 }
 892
 893                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 894
 895                 qede_set_ucast_cmn_params(&ucast);
 896                 ucast.opcode = ECORE_FILTER_REMOVE;
 897                 ucast.type = ECORE_FILTER_VLAN;
 898                 ucast.vlan = vlan_id;
 899                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 900                                             NULL);
 901                 if (rc != 0) {
 902                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 903                                vlan_id, rc);
 904                 } else {
 905                         qdev->configured_vlans--;
 906                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 907                                 vlan_id, qdev->configured_vlans);
 908                 }
 909         }
 910
 911         return rc;
 912 }
 913
 914 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 915 {
 916         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 917         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 918         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 919
 920         if (mask & ETH_VLAN_STRIP_MASK) {
 921                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 922                         (void)qede_vlan_stripping(eth_dev, 1);
 923                 else
 924                         (void)qede_vlan_stripping(eth_dev, 0);
 925         }
 926
 927         if (mask & ETH_VLAN_FILTER_MASK) {
 928                 /* VLAN filtering kicks in when a VLAN is added */
 929                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 930                         qede_vlan_filter_set(eth_dev, 0, 1);
 931                 } else {
 932                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 933                                 DP_ERR(edev,
 934                                   " Please remove existing VLAN filters"
 935                                   " before disabling VLAN filtering\n");
 936                                 /* Signal app that VLAN filtering is still
 937                                  * enabled
 938                                  */
 939                                 eth_dev->data->dev_conf.rxmode.offloads |=
 940                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 941                         } else {
 942                                 qede_vlan_filter_set(eth_dev, 0, 0);
 943                         }
 944                 }
 945         }
 946
 947         if (mask & ETH_VLAN_EXTEND_MASK)
 948                 DP_ERR(edev, "Extend VLAN not supported\n");
 949
 950         qdev->vlan_offload_mask = mask;
 951
 952         DP_INFO(edev, "VLAN offload mask %d\n", mask);
 953
 954         return 0;
 955 }
 956
 957 static void qede_prandom_bytes(uint32_t *buff)
 958 {
 959         uint8_t i;
 960
 961         srand((unsigned int)time(NULL));
 962         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 963                 buff[i] = rand();
 964 }
 965
 966 int qede_config_rss(struct rte_eth_dev *eth_dev)
 967 {
 968         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 969         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 970         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 971         struct rte_eth_rss_reta_entry64 reta_conf[2];
 972         struct rte_eth_rss_conf rss_conf;
 973         uint32_t i, id, pos, q;
 974
 975         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 976         if (!rss_conf.rss_key) {
 977                 DP_INFO(edev, "Applying driver default key\n");
 978                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 979                 qede_prandom_bytes(&def_rss_key[0]);
 980                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 981         }
 982
 983         /* Configure RSS hash */
 984         if (qede_rss_hash_update(eth_dev, &rss_conf))
 985                 return -EINVAL;
 986
 987         /* Configure default RETA */
 988         memset(reta_conf, 0, sizeof(reta_conf));
 989         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 990                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 991
 992         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 993                 id = i / RTE_RETA_GROUP_SIZE;
 994                 pos = i % RTE_RETA_GROUP_SIZE;
 995                 q = i % QEDE_RSS_COUNT(eth_dev);
 996                 reta_conf[id].reta[pos] = q;
 997         }
 998         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 999                                  ECORE_RSS_IND_TABLE_SIZE))
1000                 return -EINVAL;
1001
1002         return 0;
1003 }
1004
1005 static void qede_fastpath_start(struct ecore_dev *edev)
1006 {
1007         struct ecore_hwfn *p_hwfn;
1008         int i;
1009
1010         for_each_hwfn(edev, i) {
1011                 p_hwfn = &edev->hwfns[i];
1012                 ecore_hw_start_fastpath(p_hwfn);
1013         }
1014 }
1015
1016 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1017 {
1018         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1019         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1020         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1021
1022         PMD_INIT_FUNC_TRACE(edev);
1023
1024         /* Update MTU only if it has changed */
1025         if (eth_dev->data->mtu != qdev->mtu) {
1026                 if (qede_update_mtu(eth_dev, qdev->mtu))
1027                         goto err;
1028         }
1029
1030         /* Configure TPA parameters */
1031         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1032                 if (qede_enable_tpa(eth_dev, true))
1033                         return -EINVAL;
1034                 /* Enable scatter mode for LRO */
1035                 if (!eth_dev->data->scattered_rx)
1036                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1037         }
1038
1039         /* Start queues */
1040         if (qede_start_queues(eth_dev))
1041                 goto err;
1042
1043         if (IS_PF(edev))
1044                 qede_reset_queue_stats(qdev, true);
1045
1046         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1047          * enabling RSS. Hence RSS configuration is deferred upto this point.
1048          * Also, we would like to retain similar behavior in PF case, so we
1049          * don't do PF/VF specific check here.
1050          */
1051         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1052                 if (qede_config_rss(eth_dev))
1053                         goto err;
1054
1055         /* Enable vport*/
1056         if (qede_activate_vport(eth_dev, true))
1057                 goto err;
1058
1059         /* Update link status */
1060         qede_link_update(eth_dev, 0);
1061
1062         /* Start/resume traffic */
1063         qede_fastpath_start(edev);
1064
1065         DP_INFO(edev, "Device started\n");
1066
1067         return 0;
1068 err:
1069         DP_ERR(edev, "Device start fails\n");
1070         return -1; /* common error code is < 0 */
1071 }
1072
1073 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1074 {
1075         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1076         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1077
1078         PMD_INIT_FUNC_TRACE(edev);
1079
1080         /* Disable vport */
1081         if (qede_activate_vport(eth_dev, false))
1082                 return;
1083
1084         if (qdev->enable_lro)
1085                 qede_enable_tpa(eth_dev, false);
1086
1087         /* Stop queues */
1088         qede_stop_queues(eth_dev);
1089
1090         /* Disable traffic */
1091         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1092
1093         DP_INFO(edev, "Device is stopped\n");
1094 }
1095
1096 static const char * const valid_args[] = {
1097         QEDE_NPAR_TX_SWITCHING,
1098         QEDE_VF_TX_SWITCHING,
1099         NULL,
1100 };
1101
1102 static int qede_args_check(const char *key, const char *val, void *opaque)
1103 {
1104         unsigned long tmp;
1105         int ret = 0;
1106         struct rte_eth_dev *eth_dev = opaque;
1107         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1108         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1109
1110         errno = 0;
1111         tmp = strtoul(val, NULL, 0);
1112         if (errno) {
1113                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1114                 return errno;
1115         }
1116
1117         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1118             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1119                 qdev->enable_tx_switching = !!tmp;
1120                 DP_INFO(edev, "Disabling %s tx-switching\n",
1121                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1122                         "VF" : "NPAR");
1123         }
1124
1125         return ret;
1126 }
1127
1128 static int qede_args(struct rte_eth_dev *eth_dev)
1129 {
1130         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1131         struct rte_kvargs *kvlist;
1132         struct rte_devargs *devargs;
1133         int ret;
1134         int i;
1135
1136         devargs = pci_dev->device.devargs;
1137         if (!devargs)
1138                 return 0; /* return success */
1139
1140         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1141         if (kvlist == NULL)
1142                 return -EINVAL;
1143
1144          /* Process parameters. */
1145         for (i = 0; (valid_args[i] != NULL); ++i) {
1146                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1147                         ret = rte_kvargs_process(kvlist, valid_args[i],
1148                                                  qede_args_check, eth_dev);
1149                         if (ret != ECORE_SUCCESS) {
1150                                 rte_kvargs_free(kvlist);
1151                                 return ret;
1152                         }
1153                 }
1154         }
1155         rte_kvargs_free(kvlist);
1156
1157         return 0;
1158 }
1159
1160 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1161 {
1162         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1163         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1164         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1165         int ret;
1166
1167         PMD_INIT_FUNC_TRACE(edev);
1168
1169         /* We need to have min 1 RX queue.There is no min check in
1170          * rte_eth_dev_configure(), so we are checking it here.
1171          */
1172         if (eth_dev->data->nb_rx_queues == 0) {
1173                 DP_ERR(edev, "Minimum one RX queue is required\n");
1174                 return -EINVAL;
1175         }
1176
1177         /* Enable Tx switching by default */
1178         qdev->enable_tx_switching = 1;
1179
1180         /* Parse devargs and fix up rxmode */
1181         if (qede_args(eth_dev))
1182                 DP_NOTICE(edev, false,
1183                           "Invalid devargs supplied, requested change will not take effect\n");
1184
1185         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1186               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1187                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1188                 return -ENOTSUP;
1189         }
1190         /* Flow director mode check */
1191         if (qede_check_fdir_support(eth_dev))
1192                 return -ENOTSUP;
1193
1194         qede_dealloc_fp_resc(eth_dev);
1195         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1196         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1197
1198         if (qede_alloc_fp_resc(qdev))
1199                 return -ENOMEM;
1200
1201         /* If jumbo enabled adjust MTU */
1202         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1203                 eth_dev->data->mtu =
1204                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1205                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1206
1207         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1208                 eth_dev->data->scattered_rx = 1;
1209
1210         if (qede_start_vport(qdev, eth_dev->data->mtu))
1211                 return -1;
1212
1213         qdev->mtu = eth_dev->data->mtu;
1214
1215         /* Enable VLAN offloads by default */
1216         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1217                                              ETH_VLAN_FILTER_MASK);
1218         if (ret)
1219                 return ret;
1220
1221         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1222                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1223
1224         if (ECORE_IS_CMT(edev))
1225                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1226                         qdev->num_rx_queues, qdev->num_tx_queues);
1227
1228
1229         return 0;
1230 }
1231
1232 /* Info about HW descriptor ring limitations */
1233 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1234         .nb_max = 0x8000, /* 32K */
1235         .nb_min = 128,
1236         .nb_align = 128 /* lowest common multiple */
1237 };
1238
1239 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1240         .nb_max = 0x8000, /* 32K */
1241         .nb_min = 256,
1242         .nb_align = 256,
1243         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1244         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1245 };
1246
1247 static void
1248 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1249                   struct rte_eth_dev_info *dev_info)
1250 {
1251         struct qede_dev *qdev = eth_dev->data->dev_private;
1252         struct ecore_dev *edev = &qdev->edev;
1253         struct qed_link_output link;
1254         uint32_t speed_cap = 0;
1255
1256         PMD_INIT_FUNC_TRACE(edev);
1257
1258         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1259         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1260         dev_info->rx_desc_lim = qede_rx_desc_lim;
1261         dev_info->tx_desc_lim = qede_tx_desc_lim;
1262
1263         if (IS_PF(edev))
1264                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1265                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1266         else
1267                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1268                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1269         /* Since CMT mode internally doubles the number of queues */
1270         if (ECORE_IS_CMT(edev))
1271                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1272
1273         dev_info->max_tx_queues = dev_info->max_rx_queues;
1274
1275         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1276         dev_info->max_vfs = 0;
1277         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1278         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1279         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1280         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1281                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1282                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1283                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1284                                      DEV_RX_OFFLOAD_TCP_LRO     |
1285                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1286                                      DEV_RX_OFFLOAD_SCATTER     |
1287                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1288                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1289                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1290         dev_info->rx_queue_offload_capa = 0;
1291
1292         /* TX offloads are on a per-packet basis, so it is applicable
1293          * to both at port and queue levels.
1294          */
1295         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1296                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1297                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1298                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1299                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1300                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1301                                      DEV_TX_OFFLOAD_TCP_TSO     |
1302                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1303                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1304         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1305
1306         dev_info->default_txconf = (struct rte_eth_txconf) {
1307                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1308         };
1309
1310         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1311                 /* Packets are always dropped if no descriptors are available */
1312                 .rx_drop_en = 1,
1313                 .offloads = 0,
1314         };
1315
1316         memset(&link, 0, sizeof(struct qed_link_output));
1317         qdev->ops->common->get_link(edev, &link);
1318         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1319                 speed_cap |= ETH_LINK_SPEED_1G;
1320         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1321                 speed_cap |= ETH_LINK_SPEED_10G;
1322         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1323                 speed_cap |= ETH_LINK_SPEED_25G;
1324         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1325                 speed_cap |= ETH_LINK_SPEED_40G;
1326         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1327                 speed_cap |= ETH_LINK_SPEED_50G;
1328         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1329                 speed_cap |= ETH_LINK_SPEED_100G;
1330         dev_info->speed_capa = speed_cap;
1331 }
1332
1333 /* return 0 means link status changed, -1 means not changed */
1334 int
1335 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1336 {
1337         struct qede_dev *qdev = eth_dev->data->dev_private;
1338         struct ecore_dev *edev = &qdev->edev;
1339         struct qed_link_output q_link;
1340         struct rte_eth_link link;
1341         uint16_t link_duplex;
1342
1343         memset(&q_link, 0, sizeof(q_link));
1344         memset(&link, 0, sizeof(link));
1345
1346         qdev->ops->common->get_link(edev, &q_link);
1347
1348         /* Link Speed */
1349         link.link_speed = q_link.speed;
1350
1351         /* Link Mode */
1352         switch (q_link.duplex) {
1353         case QEDE_DUPLEX_HALF:
1354                 link_duplex = ETH_LINK_HALF_DUPLEX;
1355                 break;
1356         case QEDE_DUPLEX_FULL:
1357                 link_duplex = ETH_LINK_FULL_DUPLEX;
1358                 break;
1359         case QEDE_DUPLEX_UNKNOWN:
1360         default:
1361                 link_duplex = -1;
1362         }
1363         link.link_duplex = link_duplex;
1364
1365         /* Link Status */
1366         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1367
1368         /* AN */
1369         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1370                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1371
1372         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1373                 link.link_speed, link.link_duplex,
1374                 link.link_autoneg, link.link_status);
1375
1376         return rte_eth_linkstatus_set(eth_dev, &link);
1377 }
1378
1379 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1380 {
1381         struct qede_dev *qdev = eth_dev->data->dev_private;
1382         struct ecore_dev *edev = &qdev->edev;
1383         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1384
1385         PMD_INIT_FUNC_TRACE(edev);
1386
1387         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1388                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1389
1390         qed_configure_filter_rx_mode(eth_dev, type);
1391 }
1392
1393 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1394 {
1395         struct qede_dev *qdev = eth_dev->data->dev_private;
1396         struct ecore_dev *edev = &qdev->edev;
1397
1398         PMD_INIT_FUNC_TRACE(edev);
1399
1400         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1401                 qed_configure_filter_rx_mode(eth_dev,
1402                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1403         else
1404                 qed_configure_filter_rx_mode(eth_dev,
1405                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1406 }
1407
1408 static void qede_poll_sp_sb_cb(void *param)
1409 {
1410         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1411         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1412         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1413         int rc;
1414
1415         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1416         qede_interrupt_action(&edev->hwfns[1]);
1417
1418         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1419                                qede_poll_sp_sb_cb,
1420                                (void *)eth_dev);
1421         if (rc != 0) {
1422                 DP_ERR(edev, "Unable to start periodic"
1423                              " timer rc %d\n", rc);
1424         }
1425 }
1426
1427 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1428 {
1429         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1430         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1431         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1432
1433         PMD_INIT_FUNC_TRACE(edev);
1434
1435         /* dev_stop() shall cleanup fp resources in hw but without releasing
1436          * dma memories and sw structures so that dev_start() can be called
1437          * by the app without reconfiguration. However, in dev_close() we
1438          * can release all the resources and device can be brought up newly
1439          */
1440         if (eth_dev->data->dev_started)
1441                 qede_dev_stop(eth_dev);
1442
1443         qede_stop_vport(edev);
1444         qdev->vport_started = false;
1445         qede_fdir_dealloc_resc(eth_dev);
1446         qede_dealloc_fp_resc(eth_dev);
1447
1448         eth_dev->data->nb_rx_queues = 0;
1449         eth_dev->data->nb_tx_queues = 0;
1450
1451         /* Bring the link down */
1452         qede_dev_set_link_state(eth_dev, false);
1453         qdev->ops->common->slowpath_stop(edev);
1454         qdev->ops->common->remove(edev);
1455         rte_intr_disable(&pci_dev->intr_handle);
1456
1457         switch (pci_dev->intr_handle.type) {
1458         case RTE_INTR_HANDLE_UIO_INTX:
1459         case RTE_INTR_HANDLE_VFIO_LEGACY:
1460                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1461                                              qede_interrupt_handler_intx,
1462                                              (void *)eth_dev);
1463                 break;
1464         default:
1465                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1466                                            qede_interrupt_handler,
1467                                            (void *)eth_dev);
1468         }
1469
1470         if (ECORE_IS_CMT(edev))
1471                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1472 }
1473
1474 static int
1475 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1476 {
1477         struct qede_dev *qdev = eth_dev->data->dev_private;
1478         struct ecore_dev *edev = &qdev->edev;
1479         struct ecore_eth_stats stats;
1480         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1481         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1482         struct qede_tx_queue *txq;
1483
1484         ecore_get_vport_stats(edev, &stats);
1485
1486         /* RX Stats */
1487         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1488             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1489
1490         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1491             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1492
1493         eth_stats->ierrors = stats.common.rx_crc_errors +
1494             stats.common.rx_align_errors +
1495             stats.common.rx_carrier_errors +
1496             stats.common.rx_oversize_packets +
1497             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1498
1499         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1500
1501         eth_stats->imissed = stats.common.mftag_filter_discards +
1502             stats.common.mac_filter_discards +
1503             stats.common.no_buff_discards +
1504             stats.common.brb_truncates + stats.common.brb_discards;
1505
1506         /* TX stats */
1507         eth_stats->opackets = stats.common.tx_ucast_pkts +
1508             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1509
1510         eth_stats->obytes = stats.common.tx_ucast_bytes +
1511             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1512
1513         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1514
1515         /* Queue stats */
1516         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1517                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1518         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1519                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1520         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1521             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1522                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1523                        "Not all the queue stats will be displayed. Set"
1524                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1525                        " appropriately and retry.\n");
1526
1527         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1528                 eth_stats->q_ipackets[i] = 0;
1529                 eth_stats->q_errors[i] = 0;
1530
1531                 for_each_hwfn(edev, hw_fn) {
1532                         idx = qid * edev->num_hwfns + hw_fn;
1533
1534                         eth_stats->q_ipackets[i] +=
1535                                 *(uint64_t *)
1536                                         (((char *)(qdev->fp_array[idx].rxq)) +
1537                                          offsetof(struct qede_rx_queue,
1538                                          rcv_pkts));
1539                         eth_stats->q_errors[i] +=
1540                                 *(uint64_t *)
1541                                         (((char *)(qdev->fp_array[idx].rxq)) +
1542                                          offsetof(struct qede_rx_queue,
1543                                          rx_hw_errors)) +
1544                                 *(uint64_t *)
1545                                         (((char *)(qdev->fp_array[idx].rxq)) +
1546                                          offsetof(struct qede_rx_queue,
1547                                          rx_alloc_errors));
1548                 }
1549
1550                 i++;
1551                 if (i == rxq_stat_cntrs)
1552                         break;
1553         }
1554
1555         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1556                 eth_stats->q_opackets[j] = 0;
1557
1558                 for_each_hwfn(edev, hw_fn) {
1559                         idx = qid * edev->num_hwfns + hw_fn;
1560
1561                         txq = qdev->fp_array[idx].txq;
1562                         eth_stats->q_opackets[j] +=
1563                                 *((uint64_t *)(uintptr_t)
1564                                         (((uint64_t)(uintptr_t)(txq)) +
1565                                          offsetof(struct qede_tx_queue,
1566                                                   xmit_pkts)));
1567                 }
1568
1569                 j++;
1570                 if (j == txq_stat_cntrs)
1571                         break;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static unsigned
1578 qede_get_xstats_count(struct qede_dev *qdev) {
1579         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1580
1581         if (ECORE_IS_BB(&qdev->edev))
1582                 return RTE_DIM(qede_xstats_strings) +
1583                        RTE_DIM(qede_bb_xstats_strings) +
1584                        (RTE_DIM(qede_rxq_xstats_strings) *
1585                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1586         else
1587                 return RTE_DIM(qede_xstats_strings) +
1588                        RTE_DIM(qede_ah_xstats_strings) +
1589                        (RTE_DIM(qede_rxq_xstats_strings) *
1590                         QEDE_RSS_COUNT(dev));
1591 }
1592
1593 static int
1594 qede_get_xstats_names(struct rte_eth_dev *dev,
1595                       struct rte_eth_xstat_name *xstats_names,
1596                       __rte_unused unsigned int limit)
1597 {
1598         struct qede_dev *qdev = dev->data->dev_private;
1599         struct ecore_dev *edev = &qdev->edev;
1600         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1601         unsigned int i, qid, hw_fn, stat_idx = 0;
1602
1603         if (xstats_names == NULL)
1604                 return stat_cnt;
1605
1606         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1607                 strlcpy(xstats_names[stat_idx].name,
1608                         qede_xstats_strings[i].name,
1609                         sizeof(xstats_names[stat_idx].name));
1610                 stat_idx++;
1611         }
1612
1613         if (ECORE_IS_BB(edev)) {
1614                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1615                         strlcpy(xstats_names[stat_idx].name,
1616                                 qede_bb_xstats_strings[i].name,
1617                                 sizeof(xstats_names[stat_idx].name));
1618                         stat_idx++;
1619                 }
1620         } else {
1621                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1622                         strlcpy(xstats_names[stat_idx].name,
1623                                 qede_ah_xstats_strings[i].name,
1624                                 sizeof(xstats_names[stat_idx].name));
1625                         stat_idx++;
1626                 }
1627         }
1628
1629         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1630                 for_each_hwfn(edev, hw_fn) {
1631                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1632                                 snprintf(xstats_names[stat_idx].name,
1633                                          RTE_ETH_XSTATS_NAME_SIZE,
1634                                          "%.4s%d.%d%s",
1635                                          qede_rxq_xstats_strings[i].name,
1636                                          hw_fn, qid,
1637                                          qede_rxq_xstats_strings[i].name + 4);
1638                                 stat_idx++;
1639                         }
1640                 }
1641         }
1642
1643         return stat_cnt;
1644 }
1645
1646 static int
1647 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1648                 unsigned int n)
1649 {
1650         struct qede_dev *qdev = dev->data->dev_private;
1651         struct ecore_dev *edev = &qdev->edev;
1652         struct ecore_eth_stats stats;
1653         const unsigned int num = qede_get_xstats_count(qdev);
1654         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1655
1656         if (n < num)
1657                 return num;
1658
1659         ecore_get_vport_stats(edev, &stats);
1660
1661         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1662                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1663                                              qede_xstats_strings[i].offset);
1664                 xstats[stat_idx].id = stat_idx;
1665                 stat_idx++;
1666         }
1667
1668         if (ECORE_IS_BB(edev)) {
1669                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1670                         xstats[stat_idx].value =
1671                                         *(uint64_t *)(((char *)&stats) +
1672                                         qede_bb_xstats_strings[i].offset);
1673                         xstats[stat_idx].id = stat_idx;
1674                         stat_idx++;
1675                 }
1676         } else {
1677                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1678                         xstats[stat_idx].value =
1679                                         *(uint64_t *)(((char *)&stats) +
1680                                         qede_ah_xstats_strings[i].offset);
1681                         xstats[stat_idx].id = stat_idx;
1682                         stat_idx++;
1683                 }
1684         }
1685
1686         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1687                 for_each_hwfn(edev, hw_fn) {
1688                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1689                                 fpidx = qid * edev->num_hwfns + hw_fn;
1690                                 xstats[stat_idx].value = *(uint64_t *)
1691                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1692                                          qede_rxq_xstats_strings[i].offset);
1693                                 xstats[stat_idx].id = stat_idx;
1694                                 stat_idx++;
1695                         }
1696
1697                 }
1698         }
1699
1700         return stat_idx;
1701 }
1702
1703 static void
1704 qede_reset_xstats(struct rte_eth_dev *dev)
1705 {
1706         struct qede_dev *qdev = dev->data->dev_private;
1707         struct ecore_dev *edev = &qdev->edev;
1708
1709         ecore_reset_vport_stats(edev);
1710         qede_reset_queue_stats(qdev, true);
1711 }
1712
1713 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1714 {
1715         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1716         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1717         struct qed_link_params link_params;
1718         int rc;
1719
1720         DP_INFO(edev, "setting link state %d\n", link_up);
1721         memset(&link_params, 0, sizeof(link_params));
1722         link_params.link_up = link_up;
1723         rc = qdev->ops->common->set_link(edev, &link_params);
1724         if (rc != ECORE_SUCCESS)
1725                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1726
1727         return rc;
1728 }
1729
1730 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1731 {
1732         return qede_dev_set_link_state(eth_dev, true);
1733 }
1734
1735 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1736 {
1737         return qede_dev_set_link_state(eth_dev, false);
1738 }
1739
1740 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1741 {
1742         struct qede_dev *qdev = eth_dev->data->dev_private;
1743         struct ecore_dev *edev = &qdev->edev;
1744
1745         ecore_reset_vport_stats(edev);
1746         qede_reset_queue_stats(qdev, false);
1747 }
1748
1749 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1750 {
1751         enum qed_filter_rx_mode_type type =
1752             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1753
1754         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1755                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1756
1757         qed_configure_filter_rx_mode(eth_dev, type);
1758 }
1759
1760 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1761 {
1762         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1763                 qed_configure_filter_rx_mode(eth_dev,
1764                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1765         else
1766                 qed_configure_filter_rx_mode(eth_dev,
1767                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1768 }
1769
1770 static int
1771 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1772                 struct rte_ether_addr *mc_addrs,
1773                 uint32_t mc_addrs_num)
1774 {
1775         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1776         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1777         uint8_t i;
1778
1779         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1780                 DP_ERR(edev, "Reached max multicast filters limit,"
1781                              "Please enable multicast promisc mode\n");
1782                 return -ENOSPC;
1783         }
1784
1785         for (i = 0; i < mc_addrs_num; i++) {
1786                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1787                         DP_ERR(edev, "Not a valid multicast MAC\n");
1788                         return -EINVAL;
1789                 }
1790         }
1791
1792         /* Flush all existing entries */
1793         if (qede_del_mcast_filters(eth_dev))
1794                 return -1;
1795
1796         /* Set new mcast list */
1797         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1798 }
1799
1800 /* Update MTU via vport-update without doing port restart.
1801  * The vport must be deactivated before calling this API.
1802  */
1803 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1804 {
1805         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1806         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1807         struct ecore_hwfn *p_hwfn;
1808         int rc;
1809         int i;
1810
1811         if (IS_PF(edev)) {
1812                 struct ecore_sp_vport_update_params params;
1813
1814                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1815                 params.vport_id = 0;
1816                 params.mtu = mtu;
1817                 params.vport_id = 0;
1818                 for_each_hwfn(edev, i) {
1819                         p_hwfn = &edev->hwfns[i];
1820                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1821                         rc = ecore_sp_vport_update(p_hwfn, &params,
1822                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1823                         if (rc != ECORE_SUCCESS)
1824                                 goto err;
1825                 }
1826         } else {
1827                 for_each_hwfn(edev, i) {
1828                         p_hwfn = &edev->hwfns[i];
1829                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1830                         if (rc == ECORE_INVAL) {
1831                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1832                                 /* Recreate vport */
1833                                 rc = qede_start_vport(qdev, mtu);
1834                                 if (rc != ECORE_SUCCESS)
1835                                         goto err;
1836
1837                                 /* Restore config lost due to vport stop */
1838                                 if (eth_dev->data->promiscuous)
1839                                         qede_promiscuous_enable(eth_dev);
1840                                 else
1841                                         qede_promiscuous_disable(eth_dev);
1842
1843                                 if (eth_dev->data->all_multicast)
1844                                         qede_allmulticast_enable(eth_dev);
1845                                 else
1846                                         qede_allmulticast_disable(eth_dev);
1847
1848                                 qede_vlan_offload_set(eth_dev,
1849                                                       qdev->vlan_offload_mask);
1850                         } else if (rc != ECORE_SUCCESS) {
1851                                 goto err;
1852                         }
1853                 }
1854         }
1855         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1856
1857         return 0;
1858
1859 err:
1860         DP_ERR(edev, "Failed to update MTU\n");
1861         return -1;
1862 }
1863
1864 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1865                               struct rte_eth_fc_conf *fc_conf)
1866 {
1867         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1868         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1869         struct qed_link_output current_link;
1870         struct qed_link_params params;
1871
1872         memset(&current_link, 0, sizeof(current_link));
1873         qdev->ops->common->get_link(edev, &current_link);
1874
1875         memset(&params, 0, sizeof(params));
1876         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1877         if (fc_conf->autoneg) {
1878                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1879                         DP_ERR(edev, "Autoneg not supported\n");
1880                         return -EINVAL;
1881                 }
1882                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1883         }
1884
1885         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1886         if (fc_conf->mode == RTE_FC_FULL)
1887                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1888                                         QED_LINK_PAUSE_RX_ENABLE);
1889         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1890                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1891         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1892                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1893
1894         params.link_up = true;
1895         (void)qdev->ops->common->set_link(edev, &params);
1896
1897         return 0;
1898 }
1899
1900 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1901                               struct rte_eth_fc_conf *fc_conf)
1902 {
1903         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1904         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1905         struct qed_link_output current_link;
1906
1907         memset(&current_link, 0, sizeof(current_link));
1908         qdev->ops->common->get_link(edev, &current_link);
1909
1910         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1911                 fc_conf->autoneg = true;
1912
1913         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1914                                          QED_LINK_PAUSE_TX_ENABLE))
1915                 fc_conf->mode = RTE_FC_FULL;
1916         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1917                 fc_conf->mode = RTE_FC_RX_PAUSE;
1918         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1919                 fc_conf->mode = RTE_FC_TX_PAUSE;
1920         else
1921                 fc_conf->mode = RTE_FC_NONE;
1922
1923         return 0;
1924 }
1925
1926 static const uint32_t *
1927 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1928 {
1929         static const uint32_t ptypes[] = {
1930                 RTE_PTYPE_L2_ETHER,
1931                 RTE_PTYPE_L2_ETHER_VLAN,
1932                 RTE_PTYPE_L3_IPV4,
1933                 RTE_PTYPE_L3_IPV6,
1934                 RTE_PTYPE_L4_TCP,
1935                 RTE_PTYPE_L4_UDP,
1936                 RTE_PTYPE_TUNNEL_VXLAN,
1937                 RTE_PTYPE_L4_FRAG,
1938                 RTE_PTYPE_TUNNEL_GENEVE,
1939                 RTE_PTYPE_TUNNEL_GRE,
1940                 /* Inner */
1941                 RTE_PTYPE_INNER_L2_ETHER,
1942                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1943                 RTE_PTYPE_INNER_L3_IPV4,
1944                 RTE_PTYPE_INNER_L3_IPV6,
1945                 RTE_PTYPE_INNER_L4_TCP,
1946                 RTE_PTYPE_INNER_L4_UDP,
1947                 RTE_PTYPE_INNER_L4_FRAG,
1948                 RTE_PTYPE_UNKNOWN
1949         };
1950
1951         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
1952             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
1953                 return ptypes;
1954
1955         return NULL;
1956 }
1957
1958 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1959 {
1960         *rss_caps = 0;
1961         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1962         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1963         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1964         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1965         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1966         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1967         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1968         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1969 }
1970
1971 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1972                          struct rte_eth_rss_conf *rss_conf)
1973 {
1974         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1975         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1976         struct ecore_sp_vport_update_params vport_update_params;
1977         struct ecore_rss_params rss_params;
1978         struct ecore_hwfn *p_hwfn;
1979         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1980         uint64_t hf = rss_conf->rss_hf;
1981         uint8_t len = rss_conf->rss_key_len;
1982         uint8_t idx, i, j, fpidx;
1983         int rc;
1984
1985         memset(&vport_update_params, 0, sizeof(vport_update_params));
1986         memset(&rss_params, 0, sizeof(rss_params));
1987
1988         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1989                 (unsigned long)hf, len, key);
1990
1991         if (hf != 0) {
1992                 /* Enabling RSS */
1993                 DP_INFO(edev, "Enabling rss\n");
1994
1995                 /* RSS caps */
1996                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1997                 rss_params.update_rss_capabilities = 1;
1998
1999                 /* RSS hash key */
2000                 if (key) {
2001                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2002                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2003                                 return -EINVAL;
2004                         }
2005                         DP_INFO(edev, "Applying user supplied hash key\n");
2006                         rss_params.update_rss_key = 1;
2007                         memcpy(&rss_params.rss_key, key, len);
2008                 }
2009                 rss_params.rss_enable = 1;
2010         }
2011
2012         rss_params.update_rss_config = 1;
2013         /* tbl_size has to be set with capabilities */
2014         rss_params.rss_table_size_log = 7;
2015         vport_update_params.vport_id = 0;
2016
2017         for_each_hwfn(edev, i) {
2018                 /* pass the L2 handles instead of qids */
2019                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2020                         idx = j % QEDE_RSS_COUNT(eth_dev);
2021                         fpidx = idx * edev->num_hwfns + i;
2022                         rss_params.rss_ind_table[j] =
2023                                 qdev->fp_array[fpidx].rxq->handle;
2024                 }
2025
2026                 vport_update_params.rss_params = &rss_params;
2027
2028                 p_hwfn = &edev->hwfns[i];
2029                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2030                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2031                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2032                 if (rc) {
2033                         DP_ERR(edev, "vport-update for RSS failed\n");
2034                         return rc;
2035                 }
2036         }
2037         qdev->rss_enable = rss_params.rss_enable;
2038
2039         /* Update local structure for hash query */
2040         qdev->rss_conf.rss_hf = hf;
2041         qdev->rss_conf.rss_key_len = len;
2042         if (qdev->rss_enable) {
2043                 if  (qdev->rss_conf.rss_key == NULL) {
2044                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2045                         if (qdev->rss_conf.rss_key == NULL) {
2046                                 DP_ERR(edev, "No memory to store RSS key\n");
2047                                 return -ENOMEM;
2048                         }
2049                 }
2050                 if (key && len) {
2051                         DP_INFO(edev, "Storing RSS key\n");
2052                         memcpy(qdev->rss_conf.rss_key, key, len);
2053                 }
2054         } else if (!qdev->rss_enable && len == 0) {
2055                 if (qdev->rss_conf.rss_key) {
2056                         free(qdev->rss_conf.rss_key);
2057                         qdev->rss_conf.rss_key = NULL;
2058                         DP_INFO(edev, "Free RSS key\n");
2059                 }
2060         }
2061
2062         return 0;
2063 }
2064
2065 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2066                            struct rte_eth_rss_conf *rss_conf)
2067 {
2068         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2069
2070         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2071         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2072
2073         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2074                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2075                        rss_conf->rss_key_len);
2076         return 0;
2077 }
2078
2079 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2080                          struct rte_eth_rss_reta_entry64 *reta_conf,
2081                          uint16_t reta_size)
2082 {
2083         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2084         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2085         struct ecore_sp_vport_update_params vport_update_params;
2086         struct ecore_rss_params *params;
2087         uint16_t i, j, idx, fid, shift;
2088         struct ecore_hwfn *p_hwfn;
2089         uint8_t entry;
2090         int rc = 0;
2091
2092         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2093                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2094                        reta_size);
2095                 return -EINVAL;
2096         }
2097
2098         memset(&vport_update_params, 0, sizeof(vport_update_params));
2099         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2100         if (params == NULL) {
2101                 DP_ERR(edev, "failed to allocate memory\n");
2102                 return -ENOMEM;
2103         }
2104
2105         params->update_rss_ind_table = 1;
2106         params->rss_table_size_log = 7;
2107         params->update_rss_config = 1;
2108
2109         vport_update_params.vport_id = 0;
2110         /* Use the current value of rss_enable */
2111         params->rss_enable = qdev->rss_enable;
2112         vport_update_params.rss_params = params;
2113
2114         for_each_hwfn(edev, i) {
2115                 for (j = 0; j < reta_size; j++) {
2116                         idx = j / RTE_RETA_GROUP_SIZE;
2117                         shift = j % RTE_RETA_GROUP_SIZE;
2118                         if (reta_conf[idx].mask & (1ULL << shift)) {
2119                                 entry = reta_conf[idx].reta[shift];
2120                                 fid = entry * edev->num_hwfns + i;
2121                                 /* Pass rxq handles to ecore */
2122                                 params->rss_ind_table[j] =
2123                                                 qdev->fp_array[fid].rxq->handle;
2124                                 /* Update the local copy for RETA query cmd */
2125                                 qdev->rss_ind_table[j] = entry;
2126                         }
2127                 }
2128
2129                 p_hwfn = &edev->hwfns[i];
2130                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2131                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2132                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2133                 if (rc) {
2134                         DP_ERR(edev, "vport-update for RSS failed\n");
2135                         goto out;
2136                 }
2137         }
2138
2139 out:
2140         rte_free(params);
2141         return rc;
2142 }
2143
2144 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2145                                struct rte_eth_rss_reta_entry64 *reta_conf,
2146                                uint16_t reta_size)
2147 {
2148         struct qede_dev *qdev = eth_dev->data->dev_private;
2149         struct ecore_dev *edev = &qdev->edev;
2150         uint16_t i, idx, shift;
2151         uint8_t entry;
2152
2153         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2154                 DP_ERR(edev, "reta_size %d is not supported\n",
2155                        reta_size);
2156                 return -EINVAL;
2157         }
2158
2159         for (i = 0; i < reta_size; i++) {
2160                 idx = i / RTE_RETA_GROUP_SIZE;
2161                 shift = i % RTE_RETA_GROUP_SIZE;
2162                 if (reta_conf[idx].mask & (1ULL << shift)) {
2163                         entry = qdev->rss_ind_table[i];
2164                         reta_conf[idx].reta[shift] = entry;
2165                 }
2166         }
2167
2168         return 0;
2169 }
2170
2171
2172
2173 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2174 {
2175         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2176         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2177         struct rte_eth_dev_info dev_info = {0};
2178         struct qede_fastpath *fp;
2179         uint32_t max_rx_pkt_len;
2180         uint32_t frame_size;
2181         uint16_t bufsz;
2182         bool restart = false;
2183         int i, rc;
2184
2185         PMD_INIT_FUNC_TRACE(edev);
2186         qede_dev_info_get(dev, &dev_info);
2187         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2188         frame_size = max_rx_pkt_len;
2189         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2190                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2191                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2192                        QEDE_ETH_OVERHEAD);
2193                 return -EINVAL;
2194         }
2195         if (!dev->data->scattered_rx &&
2196             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2197                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2198                         dev->data->min_rx_buf_size);
2199                 return -EINVAL;
2200         }
2201         /* Temporarily replace I/O functions with dummy ones. It cannot
2202          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2203          */
2204         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2205         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2206         if (dev->data->dev_started) {
2207                 dev->data->dev_started = 0;
2208                 qede_dev_stop(dev);
2209                 restart = true;
2210         }
2211         rte_delay_ms(1000);
2212         qdev->mtu = mtu;
2213
2214         /* Fix up RX buf size for all queues of the port */
2215         for (i = 0; i < qdev->num_rx_queues; i++) {
2216                 fp = &qdev->fp_array[i];
2217                 if (fp->rxq != NULL) {
2218                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2219                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2220                         /* cache align the mbuf size to simplfy rx_buf_size
2221                          * calculation
2222                          */
2223                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2224                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2225                         if (rc < 0)
2226                                 return rc;
2227
2228                         fp->rxq->rx_buf_size = rc;
2229                 }
2230         }
2231         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2232                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2233         else
2234                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2235
2236         if (!dev->data->dev_started && restart) {
2237                 qede_dev_start(dev);
2238                 dev->data->dev_started = 1;
2239         }
2240
2241         /* update max frame size */
2242         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2243         /* Reassign back */
2244         if (ECORE_IS_CMT(edev)) {
2245                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2246                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2247         } else {
2248                 dev->rx_pkt_burst = qede_recv_pkts;
2249                 dev->tx_pkt_burst = qede_xmit_pkts;
2250         }
2251         return 0;
2252 }
2253
2254 static int
2255 qede_dev_reset(struct rte_eth_dev *dev)
2256 {
2257         int ret;
2258
2259         ret = qede_eth_dev_uninit(dev);
2260         if (ret)
2261                 return ret;
2262
2263         return qede_eth_dev_init(dev);
2264 }
2265
2266 static const struct eth_dev_ops qede_eth_dev_ops = {
2267         .dev_configure = qede_dev_configure,
2268         .dev_infos_get = qede_dev_info_get,
2269         .rx_queue_setup = qede_rx_queue_setup,
2270         .rx_queue_release = qede_rx_queue_release,
2271         .rx_descriptor_status = qede_rx_descriptor_status,
2272         .tx_queue_setup = qede_tx_queue_setup,
2273         .tx_queue_release = qede_tx_queue_release,
2274         .dev_start = qede_dev_start,
2275         .dev_reset = qede_dev_reset,
2276         .dev_set_link_up = qede_dev_set_link_up,
2277         .dev_set_link_down = qede_dev_set_link_down,
2278         .link_update = qede_link_update,
2279         .promiscuous_enable = qede_promiscuous_enable,
2280         .promiscuous_disable = qede_promiscuous_disable,
2281         .allmulticast_enable = qede_allmulticast_enable,
2282         .allmulticast_disable = qede_allmulticast_disable,
2283         .set_mc_addr_list = qede_set_mc_addr_list,
2284         .dev_stop = qede_dev_stop,
2285         .dev_close = qede_dev_close,
2286         .stats_get = qede_get_stats,
2287         .stats_reset = qede_reset_stats,
2288         .xstats_get = qede_get_xstats,
2289         .xstats_reset = qede_reset_xstats,
2290         .xstats_get_names = qede_get_xstats_names,
2291         .mac_addr_add = qede_mac_addr_add,
2292         .mac_addr_remove = qede_mac_addr_remove,
2293         .mac_addr_set = qede_mac_addr_set,
2294         .vlan_offload_set = qede_vlan_offload_set,
2295         .vlan_filter_set = qede_vlan_filter_set,
2296         .flow_ctrl_set = qede_flow_ctrl_set,
2297         .flow_ctrl_get = qede_flow_ctrl_get,
2298         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2299         .rss_hash_update = qede_rss_hash_update,
2300         .rss_hash_conf_get = qede_rss_hash_conf_get,
2301         .reta_update  = qede_rss_reta_update,
2302         .reta_query  = qede_rss_reta_query,
2303         .mtu_set = qede_set_mtu,
2304         .filter_ctrl = qede_dev_filter_ctrl,
2305         .udp_tunnel_port_add = qede_udp_dst_port_add,
2306         .udp_tunnel_port_del = qede_udp_dst_port_del,
2307 };
2308
2309 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2310         .dev_configure = qede_dev_configure,
2311         .dev_infos_get = qede_dev_info_get,
2312         .rx_queue_setup = qede_rx_queue_setup,
2313         .rx_queue_release = qede_rx_queue_release,
2314         .rx_descriptor_status = qede_rx_descriptor_status,
2315         .tx_queue_setup = qede_tx_queue_setup,
2316         .tx_queue_release = qede_tx_queue_release,
2317         .dev_start = qede_dev_start,
2318         .dev_reset = qede_dev_reset,
2319         .dev_set_link_up = qede_dev_set_link_up,
2320         .dev_set_link_down = qede_dev_set_link_down,
2321         .link_update = qede_link_update,
2322         .promiscuous_enable = qede_promiscuous_enable,
2323         .promiscuous_disable = qede_promiscuous_disable,
2324         .allmulticast_enable = qede_allmulticast_enable,
2325         .allmulticast_disable = qede_allmulticast_disable,
2326         .set_mc_addr_list = qede_set_mc_addr_list,
2327         .dev_stop = qede_dev_stop,
2328         .dev_close = qede_dev_close,
2329         .stats_get = qede_get_stats,
2330         .stats_reset = qede_reset_stats,
2331         .xstats_get = qede_get_xstats,
2332         .xstats_reset = qede_reset_xstats,
2333         .xstats_get_names = qede_get_xstats_names,
2334         .vlan_offload_set = qede_vlan_offload_set,
2335         .vlan_filter_set = qede_vlan_filter_set,
2336         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2337         .rss_hash_update = qede_rss_hash_update,
2338         .rss_hash_conf_get = qede_rss_hash_conf_get,
2339         .reta_update  = qede_rss_reta_update,
2340         .reta_query  = qede_rss_reta_query,
2341         .mtu_set = qede_set_mtu,
2342         .udp_tunnel_port_add = qede_udp_dst_port_add,
2343         .udp_tunnel_port_del = qede_udp_dst_port_del,
2344         .mac_addr_add = qede_mac_addr_add,
2345         .mac_addr_remove = qede_mac_addr_remove,
2346         .mac_addr_set = qede_mac_addr_set,
2347 };
2348
2349 static void qede_update_pf_params(struct ecore_dev *edev)
2350 {
2351         struct ecore_pf_params pf_params;
2352
2353         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2354         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2355         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2356         qed_ops->common->update_pf_params(edev, &pf_params);
2357 }
2358
2359 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2360 {
2361         struct rte_pci_device *pci_dev;
2362         struct rte_pci_addr pci_addr;
2363         struct qede_dev *adapter;
2364         struct ecore_dev *edev;
2365         struct qed_dev_eth_info dev_info;
2366         struct qed_slowpath_params params;
2367         static bool do_once = true;
2368         uint8_t bulletin_change;
2369         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2370         uint8_t is_mac_forced;
2371         bool is_mac_exist;
2372         /* Fix up ecore debug level */
2373         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2374         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2375         uint32_t int_mode;
2376         int rc;
2377
2378         /* Extract key data structures */
2379         adapter = eth_dev->data->dev_private;
2380         adapter->ethdev = eth_dev;
2381         edev = &adapter->edev;
2382         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2383         pci_addr = pci_dev->addr;
2384
2385         PMD_INIT_FUNC_TRACE(edev);
2386
2387         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2388                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2389                  eth_dev->data->port_id);
2390
2391         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2392                 DP_ERR(edev, "Skipping device init from secondary process\n");
2393                 return 0;
2394         }
2395
2396         rte_eth_copy_pci_info(eth_dev, pci_dev);
2397
2398         /* @DPDK */
2399         edev->vendor_id = pci_dev->id.vendor_id;
2400         edev->device_id = pci_dev->id.device_id;
2401
2402         qed_ops = qed_get_eth_ops();
2403         if (!qed_ops) {
2404                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2405                 return -EINVAL;
2406         }
2407
2408         DP_INFO(edev, "Starting qede probe\n");
2409         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2410                                     dp_level, is_vf);
2411         if (rc != 0) {
2412                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2413                 return -ENODEV;
2414         }
2415         qede_update_pf_params(edev);
2416
2417         switch (pci_dev->intr_handle.type) {
2418         case RTE_INTR_HANDLE_UIO_INTX:
2419         case RTE_INTR_HANDLE_VFIO_LEGACY:
2420                 int_mode = ECORE_INT_MODE_INTA;
2421                 rte_intr_callback_register(&pci_dev->intr_handle,
2422                                            qede_interrupt_handler_intx,
2423                                            (void *)eth_dev);
2424                 break;
2425         default:
2426                 int_mode = ECORE_INT_MODE_MSIX;
2427                 rte_intr_callback_register(&pci_dev->intr_handle,
2428                                            qede_interrupt_handler,
2429                                            (void *)eth_dev);
2430         }
2431
2432         if (rte_intr_enable(&pci_dev->intr_handle)) {
2433                 DP_ERR(edev, "rte_intr_enable() failed\n");
2434                 return -ENODEV;
2435         }
2436
2437         /* Start the Slowpath-process */
2438         memset(&params, 0, sizeof(struct qed_slowpath_params));
2439
2440         params.int_mode = int_mode;
2441         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2442         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2443         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2444         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2445         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2446                 QEDE_PMD_DRV_VER_STR_SIZE);
2447
2448         if (ECORE_IS_CMT(edev)) {
2449                 eth_dev->rx_pkt_burst = qede_recv_pkts_cmt;
2450                 eth_dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2451         } else {
2452                 eth_dev->rx_pkt_burst = qede_recv_pkts;
2453                 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2454         }
2455
2456         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2457
2458         /* For CMT mode device do periodic polling for slowpath events.
2459          * This is required since uio device uses only one MSI-x
2460          * interrupt vector but we need one for each engine.
2461          */
2462         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2463                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2464                                        qede_poll_sp_sb_cb,
2465                                        (void *)eth_dev);
2466                 if (rc != 0) {
2467                         DP_ERR(edev, "Unable to start periodic"
2468                                      " timer rc %d\n", rc);
2469                         return -EINVAL;
2470                 }
2471         }
2472
2473         rc = qed_ops->common->slowpath_start(edev, &params);
2474         if (rc) {
2475                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2476                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2477                                      (void *)eth_dev);
2478                 return -ENODEV;
2479         }
2480
2481         rc = qed_ops->fill_dev_info(edev, &dev_info);
2482         if (rc) {
2483                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2484                 qed_ops->common->slowpath_stop(edev);
2485                 qed_ops->common->remove(edev);
2486                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2487                                      (void *)eth_dev);
2488                 return -ENODEV;
2489         }
2490
2491         qede_alloc_etherdev(adapter, &dev_info);
2492
2493         adapter->ops->common->set_name(edev, edev->name);
2494
2495         if (!is_vf)
2496                 adapter->dev_info.num_mac_filters =
2497                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2498                                             ECORE_MAC);
2499         else
2500                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2501                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2502
2503         /* Allocate memory for storing MAC addr */
2504         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2505                                         (RTE_ETHER_ADDR_LEN *
2506                                         adapter->dev_info.num_mac_filters),
2507                                         RTE_CACHE_LINE_SIZE);
2508
2509         if (eth_dev->data->mac_addrs == NULL) {
2510                 DP_ERR(edev, "Failed to allocate MAC address\n");
2511                 qed_ops->common->slowpath_stop(edev);
2512                 qed_ops->common->remove(edev);
2513                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2514                                      (void *)eth_dev);
2515                 return -ENOMEM;
2516         }
2517
2518         if (!is_vf) {
2519                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2520                                 hw_info.hw_mac_addr,
2521                                 &eth_dev->data->mac_addrs[0]);
2522                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2523                                 &adapter->primary_mac);
2524         } else {
2525                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2526                                        &bulletin_change);
2527                 if (bulletin_change) {
2528                         is_mac_exist =
2529                             ecore_vf_bulletin_get_forced_mac(
2530                                                 ECORE_LEADING_HWFN(edev),
2531                                                 vf_mac,
2532                                                 &is_mac_forced);
2533                         if (is_mac_exist) {
2534                                 DP_INFO(edev, "VF macaddr received from PF\n");
2535                                 rte_ether_addr_copy(
2536                                         (struct rte_ether_addr *)&vf_mac,
2537                                         &eth_dev->data->mac_addrs[0]);
2538                                 rte_ether_addr_copy(
2539                                         &eth_dev->data->mac_addrs[0],
2540                                         &adapter->primary_mac);
2541                         } else {
2542                                 DP_ERR(edev, "No VF macaddr assigned\n");
2543                         }
2544                 }
2545         }
2546
2547         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2548
2549         if (do_once) {
2550                 qede_print_adapter_info(adapter);
2551                 do_once = false;
2552         }
2553
2554         /* Bring-up the link */
2555         qede_dev_set_link_state(eth_dev, true);
2556
2557         adapter->num_tx_queues = 0;
2558         adapter->num_rx_queues = 0;
2559         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2560         SLIST_INIT(&adapter->vlan_list_head);
2561         SLIST_INIT(&adapter->uc_list_head);
2562         SLIST_INIT(&adapter->mc_list_head);
2563         adapter->mtu = RTE_ETHER_MTU;
2564         adapter->vport_started = false;
2565
2566         /* VF tunnel offloads is enabled by default in PF driver */
2567         adapter->vxlan.num_filters = 0;
2568         adapter->geneve.num_filters = 0;
2569         adapter->ipgre.num_filters = 0;
2570         if (is_vf) {
2571                 adapter->vxlan.enable = true;
2572                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2573                                              ETH_TUNNEL_FILTER_IVLAN;
2574                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2575                 adapter->geneve.enable = true;
2576                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2577                                               ETH_TUNNEL_FILTER_IVLAN;
2578                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2579                 adapter->ipgre.enable = true;
2580                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2581                                              ETH_TUNNEL_FILTER_IVLAN;
2582         } else {
2583                 adapter->vxlan.enable = false;
2584                 adapter->geneve.enable = false;
2585                 adapter->ipgre.enable = false;
2586         }
2587
2588         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2589                 adapter->primary_mac.addr_bytes[0],
2590                 adapter->primary_mac.addr_bytes[1],
2591                 adapter->primary_mac.addr_bytes[2],
2592                 adapter->primary_mac.addr_bytes[3],
2593                 adapter->primary_mac.addr_bytes[4],
2594                 adapter->primary_mac.addr_bytes[5]);
2595
2596         DP_INFO(edev, "Device initialized\n");
2597
2598         return 0;
2599 }
2600
2601 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2602 {
2603         return qede_common_dev_init(eth_dev, 1);
2604 }
2605
2606 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2607 {
2608         return qede_common_dev_init(eth_dev, 0);
2609 }
2610
2611 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2612 {
2613         struct qede_dev *qdev = eth_dev->data->dev_private;
2614         struct ecore_dev *edev = &qdev->edev;
2615
2616         PMD_INIT_FUNC_TRACE(edev);
2617
2618         /* only uninitialize in the primary process */
2619         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2620                 return 0;
2621
2622         /* safe to close dev here */
2623         qede_dev_close(eth_dev);
2624
2625         eth_dev->dev_ops = NULL;
2626         eth_dev->rx_pkt_burst = NULL;
2627         eth_dev->tx_pkt_burst = NULL;
2628
2629         return 0;
2630 }
2631
2632 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2633 {
2634         return qede_dev_common_uninit(eth_dev);
2635 }
2636
2637 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2638 {
2639         return qede_dev_common_uninit(eth_dev);
2640 }
2641
2642 static const struct rte_pci_id pci_id_qedevf_map[] = {
2643 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2644         {
2645                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2646         },
2647         {
2648                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2649         },
2650         {
2651                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2652         },
2653         {.vendor_id = 0,}
2654 };
2655
2656 static const struct rte_pci_id pci_id_qede_map[] = {
2657 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2658         {
2659                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2660         },
2661         {
2662                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2663         },
2664         {
2665                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2666         },
2667         {
2668                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2669         },
2670         {
2671                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2672         },
2673         {
2674                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2675         },
2676         {
2677                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2678         },
2679         {
2680                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2681         },
2682         {
2683                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2684         },
2685         {
2686                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2687         },
2688         {.vendor_id = 0,}
2689 };
2690
2691 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2692         struct rte_pci_device *pci_dev)
2693 {
2694         return rte_eth_dev_pci_generic_probe(pci_dev,
2695                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2696 }
2697
2698 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2699 {
2700         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2701 }
2702
2703 static struct rte_pci_driver rte_qedevf_pmd = {
2704         .id_table = pci_id_qedevf_map,
2705         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2706         .probe = qedevf_eth_dev_pci_probe,
2707         .remove = qedevf_eth_dev_pci_remove,
2708 };
2709
2710 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2711         struct rte_pci_device *pci_dev)
2712 {
2713         return rte_eth_dev_pci_generic_probe(pci_dev,
2714                 sizeof(struct qede_dev), qede_eth_dev_init);
2715 }
2716
2717 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2718 {
2719         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2720 }
2721
2722 static struct rte_pci_driver rte_qede_pmd = {
2723         .id_table = pci_id_qede_map,
2724         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2725         .probe = qede_eth_dev_pci_probe,
2726         .remove = qede_eth_dev_pci_remove,
2727 };
2728
2729 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2730 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2731 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2732 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2733 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2734 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2735
2736 RTE_INIT(qede_init_log)
2737 {
2738         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2739         if (qede_logtype_init >= 0)
2740                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2741         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2742         if (qede_logtype_driver >= 0)
2743                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2744 }