1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #include "qede_ethdev.h"
8 #include <rte_string_fns.h>
10 #include <rte_kvargs.h>
12 static const struct qed_eth_ops *qed_ops;
13 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
14 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
16 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */
18 struct rte_qede_xstats_name_off {
19 char name[RTE_ETH_XSTATS_NAME_SIZE];
23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
25 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
26 {"rx_multicast_bytes",
27 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
28 {"rx_broadcast_bytes",
29 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
30 {"rx_unicast_packets",
31 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
32 {"rx_multicast_packets",
33 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
34 {"rx_broadcast_packets",
35 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
38 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
39 {"tx_multicast_bytes",
40 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
41 {"tx_broadcast_bytes",
42 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
43 {"tx_unicast_packets",
44 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
45 {"tx_multicast_packets",
46 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
47 {"tx_broadcast_packets",
48 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
50 {"rx_64_byte_packets",
51 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
52 {"rx_65_to_127_byte_packets",
53 offsetof(struct ecore_eth_stats_common,
54 rx_65_to_127_byte_packets)},
55 {"rx_128_to_255_byte_packets",
56 offsetof(struct ecore_eth_stats_common,
57 rx_128_to_255_byte_packets)},
58 {"rx_256_to_511_byte_packets",
59 offsetof(struct ecore_eth_stats_common,
60 rx_256_to_511_byte_packets)},
61 {"rx_512_to_1023_byte_packets",
62 offsetof(struct ecore_eth_stats_common,
63 rx_512_to_1023_byte_packets)},
64 {"rx_1024_to_1518_byte_packets",
65 offsetof(struct ecore_eth_stats_common,
66 rx_1024_to_1518_byte_packets)},
67 {"tx_64_byte_packets",
68 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
69 {"tx_65_to_127_byte_packets",
70 offsetof(struct ecore_eth_stats_common,
71 tx_65_to_127_byte_packets)},
72 {"tx_128_to_255_byte_packets",
73 offsetof(struct ecore_eth_stats_common,
74 tx_128_to_255_byte_packets)},
75 {"tx_256_to_511_byte_packets",
76 offsetof(struct ecore_eth_stats_common,
77 tx_256_to_511_byte_packets)},
78 {"tx_512_to_1023_byte_packets",
79 offsetof(struct ecore_eth_stats_common,
80 tx_512_to_1023_byte_packets)},
81 {"tx_1024_to_1518_byte_packets",
82 offsetof(struct ecore_eth_stats_common,
83 tx_1024_to_1518_byte_packets)},
85 {"rx_mac_crtl_frames",
86 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
87 {"tx_mac_control_frames",
88 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
90 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
92 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
93 {"rx_priority_flow_control_frames",
94 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
95 {"tx_priority_flow_control_frames",
96 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
99 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
101 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
102 {"rx_carrier_errors",
103 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
104 {"rx_oversize_packet_errors",
105 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
107 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
108 {"rx_undersize_packet_errors",
109 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
110 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
111 {"rx_host_buffer_not_available",
112 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
113 /* Number of packets discarded because they are bigger than MTU */
114 {"rx_packet_too_big_discards",
115 offsetof(struct ecore_eth_stats_common,
116 packet_too_big_discard)},
117 {"rx_ttl_zero_discards",
118 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
119 {"rx_multi_function_tag_filter_discards",
120 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
121 {"rx_mac_filter_discards",
122 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
123 {"rx_gft_filter_drop",
124 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
125 {"rx_hw_buffer_truncates",
126 offsetof(struct ecore_eth_stats_common, brb_truncates)},
127 {"rx_hw_buffer_discards",
128 offsetof(struct ecore_eth_stats_common, brb_discards)},
129 {"tx_error_drop_packets",
130 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
132 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
133 {"rx_mac_unicast_packets",
134 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
135 {"rx_mac_multicast_packets",
136 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
137 {"rx_mac_broadcast_packets",
138 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
140 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
141 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
142 {"tx_mac_unicast_packets",
143 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
144 {"tx_mac_multicast_packets",
145 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
146 {"tx_mac_broadcast_packets",
147 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
149 {"lro_coalesced_packets",
150 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
151 {"lro_coalesced_events",
152 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
154 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
155 {"lro_not_coalesced_packets",
156 offsetof(struct ecore_eth_stats_common,
157 tpa_not_coalesced_pkts)},
158 {"lro_coalesced_bytes",
159 offsetof(struct ecore_eth_stats_common,
160 tpa_coalesced_bytes)},
163 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
164 {"rx_1519_to_1522_byte_packets",
165 offsetof(struct ecore_eth_stats, bb) +
166 offsetof(struct ecore_eth_stats_bb,
167 rx_1519_to_1522_byte_packets)},
168 {"rx_1519_to_2047_byte_packets",
169 offsetof(struct ecore_eth_stats, bb) +
170 offsetof(struct ecore_eth_stats_bb,
171 rx_1519_to_2047_byte_packets)},
172 {"rx_2048_to_4095_byte_packets",
173 offsetof(struct ecore_eth_stats, bb) +
174 offsetof(struct ecore_eth_stats_bb,
175 rx_2048_to_4095_byte_packets)},
176 {"rx_4096_to_9216_byte_packets",
177 offsetof(struct ecore_eth_stats, bb) +
178 offsetof(struct ecore_eth_stats_bb,
179 rx_4096_to_9216_byte_packets)},
180 {"rx_9217_to_16383_byte_packets",
181 offsetof(struct ecore_eth_stats, bb) +
182 offsetof(struct ecore_eth_stats_bb,
183 rx_9217_to_16383_byte_packets)},
185 {"tx_1519_to_2047_byte_packets",
186 offsetof(struct ecore_eth_stats, bb) +
187 offsetof(struct ecore_eth_stats_bb,
188 tx_1519_to_2047_byte_packets)},
189 {"tx_2048_to_4095_byte_packets",
190 offsetof(struct ecore_eth_stats, bb) +
191 offsetof(struct ecore_eth_stats_bb,
192 tx_2048_to_4095_byte_packets)},
193 {"tx_4096_to_9216_byte_packets",
194 offsetof(struct ecore_eth_stats, bb) +
195 offsetof(struct ecore_eth_stats_bb,
196 tx_4096_to_9216_byte_packets)},
197 {"tx_9217_to_16383_byte_packets",
198 offsetof(struct ecore_eth_stats, bb) +
199 offsetof(struct ecore_eth_stats_bb,
200 tx_9217_to_16383_byte_packets)},
202 {"tx_lpi_entry_count",
203 offsetof(struct ecore_eth_stats, bb) +
204 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
205 {"tx_total_collisions",
206 offsetof(struct ecore_eth_stats, bb) +
207 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
210 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
211 {"rx_1519_to_max_byte_packets",
212 offsetof(struct ecore_eth_stats, ah) +
213 offsetof(struct ecore_eth_stats_ah,
214 rx_1519_to_max_byte_packets)},
215 {"tx_1519_to_max_byte_packets",
216 offsetof(struct ecore_eth_stats, ah) +
217 offsetof(struct ecore_eth_stats_ah,
218 tx_1519_to_max_byte_packets)},
221 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
223 offsetof(struct qede_rx_queue, rx_segs)},
225 offsetof(struct qede_rx_queue, rx_hw_errors)},
226 {"rx_q_allocation_errors",
227 offsetof(struct qede_rx_queue, rx_alloc_errors)}
230 /* Get FW version string based on fw_size */
232 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
234 struct qede_dev *qdev = dev->data->dev_private;
235 struct ecore_dev *edev = &qdev->edev;
236 struct qed_dev_info *info = &qdev->dev_info.common;
237 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
241 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
242 QEDE_PMD_FW_VERSION);
244 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
245 info->fw_major, info->fw_minor,
246 info->fw_rev, info->fw_eng);
247 size = strlen(ver_str);
248 if (size + 1 <= fw_size) /* Add 1 byte for "\0" */
249 strlcpy(fw_ver, ver_str, fw_size);
253 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
255 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
256 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
257 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
258 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
259 size = strlen(ver_str);
260 if (size + 1 <= fw_size)
261 strlcpy(fw_ver, ver_str, fw_size);
266 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
268 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
269 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
270 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
271 size = strlen(ver_str);
272 if (size + 1 <= fw_size)
273 strlcpy(fw_ver, ver_str, fw_size);
279 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
281 OSAL_SPIN_LOCK(&p_hwfn->spq_lock);
282 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
283 OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);
287 qede_interrupt_handler_intx(void *param)
289 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
290 struct qede_dev *qdev = eth_dev->data->dev_private;
291 struct ecore_dev *edev = &qdev->edev;
294 /* Check if our device actually raised an interrupt */
295 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
297 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
299 if (rte_intr_ack(eth_dev->intr_handle))
300 DP_ERR(edev, "rte_intr_ack failed\n");
305 qede_interrupt_handler(void *param)
307 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
308 struct qede_dev *qdev = eth_dev->data->dev_private;
309 struct ecore_dev *edev = &qdev->edev;
311 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
312 if (rte_intr_ack(eth_dev->intr_handle))
313 DP_ERR(edev, "rte_intr_ack failed\n");
317 qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy)
319 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
320 struct qede_dev *qdev = dev->data->dev_private;
321 struct ecore_dev *edev = &qdev->edev;
322 bool use_tx_offload = false;
325 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
326 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
330 if (ECORE_IS_CMT(edev)) {
331 dev->rx_pkt_burst = qede_recv_pkts_cmt;
332 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
336 if (dev->data->lro || dev->data->scattered_rx) {
337 DP_INFO(edev, "Assigning qede_recv_pkts\n");
338 dev->rx_pkt_burst = qede_recv_pkts;
340 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
341 dev->rx_pkt_burst = qede_recv_pkts_regular;
344 use_tx_offload = !!(tx_offloads &
345 (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
346 RTE_ETH_TX_OFFLOAD_TCP_TSO | /* tso */
347 RTE_ETH_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
349 if (use_tx_offload) {
350 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
351 dev->tx_pkt_burst = qede_xmit_pkts;
353 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
354 dev->tx_pkt_burst = qede_xmit_pkts_regular;
359 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
361 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
365 static void qede_print_adapter_info(struct rte_eth_dev *dev)
367 struct qede_dev *qdev = dev->data->dev_private;
368 struct ecore_dev *edev = &qdev->edev;
369 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
371 DP_INFO(edev, "**************************************************\n");
372 DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
373 DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
374 ECORE_IS_BB(edev) ? "BB" : "AH",
375 'A' + edev->chip_rev,
376 (int)edev->chip_metal);
377 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
378 QEDE_PMD_DRV_VERSION);
379 DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
380 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
381 QEDE_PMD_BASE_VERSION);
382 DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
383 qede_fw_version_get(dev, ver_str, sizeof(ver_str));
384 DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
385 DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
386 DP_INFO(edev, "**************************************************\n");
389 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
391 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
393 unsigned int i = 0, j = 0, qid;
394 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
395 struct qede_tx_queue *txq;
397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
400 RTE_ETHDEV_QUEUE_STAT_CNTRS);
401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
402 RTE_ETHDEV_QUEUE_STAT_CNTRS);
404 for (qid = 0; qid < qdev->num_rx_queues; qid++) {
405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
406 offsetof(struct qede_rx_queue, rcv_pkts), 0,
408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
409 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
417 OSAL_MEMSET((((char *)
418 (qdev->fp_array[qid].rxq)) +
419 qede_rxq_xstats_strings[j].offset),
424 if (i == rxq_stat_cntrs)
430 for (qid = 0; qid < qdev->num_tx_queues; qid++) {
431 txq = qdev->fp_array[qid].txq;
433 OSAL_MEMSET((uint64_t *)(uintptr_t)
434 (((uint64_t)(uintptr_t)(txq)) +
435 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
439 if (i == txq_stat_cntrs)
445 qede_stop_vport(struct ecore_dev *edev)
447 struct ecore_hwfn *p_hwfn;
453 for_each_hwfn(edev, i) {
454 p_hwfn = &edev->hwfns[i];
455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
457 if (rc != ECORE_SUCCESS) {
458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
463 DP_INFO(edev, "vport stopped\n");
469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
472 struct ecore_sp_vport_start_params params;
473 struct ecore_hwfn *p_hwfn;
477 if (qdev->vport_started)
478 qede_stop_vport(edev);
480 memset(¶ms, 0, sizeof(params));
483 /* @DPDK - Disable FW placement */
484 params.zero_placement_offset = 1;
485 for_each_hwfn(edev, i) {
486 p_hwfn = &edev->hwfns[i];
487 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
488 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
489 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
490 if (rc != ECORE_SUCCESS) {
491 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
495 ecore_reset_vport_stats(edev);
496 qdev->vport_started = true;
497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
502 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
503 #define QEDE_VF_TX_SWITCHING "vf_tx_switching"
505 /* Activate or deactivate vport via vport-update */
506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
508 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
509 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
510 struct ecore_sp_vport_update_params params;
511 struct ecore_hwfn *p_hwfn;
515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
517 params.update_vport_active_rx_flg = 1;
518 params.update_vport_active_tx_flg = 1;
519 params.vport_active_rx_flg = flg;
520 params.vport_active_tx_flg = flg;
521 if ((qdev->enable_tx_switching == false) && (flg == true)) {
522 params.update_tx_switching_flg = 1;
523 params.tx_switching_flg = !flg;
525 for_each_hwfn(edev, i) {
526 p_hwfn = &edev->hwfns[i];
527 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
528 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
529 ECORE_SPQ_MODE_EBLOCK, NULL);
530 if (rc != ECORE_SUCCESS) {
531 DP_ERR(edev, "Failed to update vport\n");
535 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
542 uint16_t mtu, bool enable)
544 /* Enable LRO in split mode */
545 sge_tpa_params->tpa_ipv4_en_flg = enable;
546 sge_tpa_params->tpa_ipv6_en_flg = enable;
547 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
548 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
549 /* set if tpa enable changes */
550 sge_tpa_params->update_tpa_en_flg = 1;
551 /* set if tpa parameters should be handled */
552 sge_tpa_params->update_tpa_param_flg = enable;
554 sge_tpa_params->max_buffers_per_cqe = 20;
555 /* Enable TPA in split mode. In this mode each TPA segment
556 * starts on the new BD, so there is one BD per segment.
558 sge_tpa_params->tpa_pkt_split_flg = 1;
559 sge_tpa_params->tpa_hdr_data_split_flg = 0;
560 sge_tpa_params->tpa_gro_consistent_flg = 0;
561 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
562 sge_tpa_params->tpa_max_size = 0x7FFF;
563 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
564 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
567 /* Enable/disable LRO via vport-update */
568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
570 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
571 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
572 struct ecore_sp_vport_update_params params;
573 struct ecore_sge_tpa_params tpa_params;
574 struct ecore_hwfn *p_hwfn;
578 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
579 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
580 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
582 params.sge_tpa_params = &tpa_params;
583 for_each_hwfn(edev, i) {
584 p_hwfn = &edev->hwfns[i];
585 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
586 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
587 ECORE_SPQ_MODE_EBLOCK, NULL);
588 if (rc != ECORE_SUCCESS) {
589 DP_ERR(edev, "Failed to update LRO\n");
593 qdev->enable_lro = flg;
594 eth_dev->data->lro = flg;
596 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
602 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
603 enum qed_filter_rx_mode_type type)
605 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
606 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
607 struct ecore_filter_accept_flags flags;
609 memset(&flags, 0, sizeof(flags));
611 flags.update_rx_mode_config = 1;
612 flags.update_tx_mode_config = 1;
613 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
614 ECORE_ACCEPT_MCAST_MATCHED |
617 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
618 ECORE_ACCEPT_MCAST_MATCHED |
621 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
622 flags.rx_accept_filter |= (ECORE_ACCEPT_UCAST_UNMATCHED |
623 ECORE_ACCEPT_MCAST_UNMATCHED);
625 flags.tx_accept_filter |=
626 (ECORE_ACCEPT_UCAST_UNMATCHED |
627 ECORE_ACCEPT_MCAST_UNMATCHED);
628 DP_INFO(edev, "Enabling Tx unmatched flags for VF\n");
630 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
631 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
634 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
635 ECORE_SPQ_MODE_CB, NULL);
639 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
642 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
643 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
644 struct qede_ucast_entry *tmp = NULL;
645 struct qede_ucast_entry *u;
646 struct rte_ether_addr *mac_addr;
648 mac_addr = (struct rte_ether_addr *)ucast->mac;
650 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
651 if ((memcmp(mac_addr, &tmp->mac,
652 RTE_ETHER_ADDR_LEN) == 0) &&
653 ucast->vni == tmp->vni &&
654 ucast->vlan == tmp->vlan) {
655 DP_INFO(edev, "Unicast MAC is already added"
656 " with vlan = %u, vni = %u\n",
657 ucast->vlan, ucast->vni);
661 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
662 RTE_CACHE_LINE_SIZE);
664 DP_ERR(edev, "Did not allocate memory for ucast\n");
667 rte_ether_addr_copy(mac_addr, &u->mac);
668 u->vlan = ucast->vlan;
670 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
673 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
674 if ((memcmp(mac_addr, &tmp->mac,
675 RTE_ETHER_ADDR_LEN) == 0) &&
676 ucast->vlan == tmp->vlan &&
677 ucast->vni == tmp->vni)
681 DP_INFO(edev, "Unicast MAC is not found\n");
684 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
692 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
693 struct rte_ether_addr *mc_addrs,
694 uint32_t mc_addrs_num)
696 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
697 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
698 struct ecore_filter_mcast mcast;
699 struct qede_mcast_entry *m = NULL;
703 for (i = 0; i < mc_addrs_num; i++) {
704 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
705 RTE_CACHE_LINE_SIZE);
707 DP_ERR(edev, "Did not allocate memory for mcast\n");
710 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
711 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
713 memset(&mcast, 0, sizeof(mcast));
714 mcast.num_mc_addrs = mc_addrs_num;
715 mcast.opcode = ECORE_FILTER_ADD;
716 for (i = 0; i < mc_addrs_num; i++)
717 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
719 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
720 if (rc != ECORE_SUCCESS) {
721 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
728 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
730 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
731 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
732 struct qede_mcast_entry *tmp = NULL;
733 struct ecore_filter_mcast mcast;
737 memset(&mcast, 0, sizeof(mcast));
738 mcast.num_mc_addrs = qdev->num_mc_addr;
739 mcast.opcode = ECORE_FILTER_REMOVE;
741 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
742 rte_ether_addr_copy(&tmp->mac,
743 (struct rte_ether_addr *)&mcast.mac[j]);
746 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
747 if (rc != ECORE_SUCCESS) {
748 DP_ERR(edev, "Failed to delete multicast filter\n");
752 while (!SLIST_EMPTY(&qdev->mc_list_head)) {
753 tmp = SLIST_FIRST(&qdev->mc_list_head);
754 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
756 SLIST_INIT(&qdev->mc_list_head);
762 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
765 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
766 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
767 enum _ecore_status_t rc = ECORE_INVAL;
769 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
770 DP_ERR(edev, "Ucast filter table limit exceeded,"
771 " Please enable promisc mode\n");
775 rc = qede_ucast_filter(eth_dev, ucast, add);
777 rc = ecore_filter_ucast_cmd(edev, ucast,
778 ECORE_SPQ_MODE_CB, NULL);
779 /* Indicate error only for add filter operation.
780 * Delete filter operations are not severe.
782 if ((rc != ECORE_SUCCESS) && add)
783 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
790 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
791 __rte_unused uint32_t index, __rte_unused uint32_t pool)
793 struct ecore_filter_ucast ucast;
796 if (!rte_is_valid_assigned_ether_addr(mac_addr))
799 qede_set_ucast_cmn_params(&ucast);
800 ucast.opcode = ECORE_FILTER_ADD;
801 ucast.type = ECORE_FILTER_MAC;
802 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
803 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
808 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
810 struct qede_dev *qdev = eth_dev->data->dev_private;
811 struct ecore_dev *edev = &qdev->edev;
812 struct ecore_filter_ucast ucast;
814 PMD_INIT_FUNC_TRACE(edev);
816 if (index >= qdev->dev_info.num_mac_filters) {
817 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
818 index, qdev->dev_info.num_mac_filters);
822 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
825 qede_set_ucast_cmn_params(&ucast);
826 ucast.opcode = ECORE_FILTER_REMOVE;
827 ucast.type = ECORE_FILTER_MAC;
829 /* Use the index maintained by rte */
830 rte_ether_addr_copy(ð_dev->data->mac_addrs[index],
831 (struct rte_ether_addr *)&ucast.mac);
833 qede_mac_int_ops(eth_dev, &ucast, false);
837 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
839 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
840 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
842 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
843 mac_addr->addr_bytes)) {
844 DP_ERR(edev, "Setting MAC address is not allowed\n");
848 qede_mac_addr_remove(eth_dev, 0);
850 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
853 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
855 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
856 struct ecore_sp_vport_update_params params;
857 struct ecore_hwfn *p_hwfn;
861 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
863 params.update_accept_any_vlan_flg = 1;
864 params.accept_any_vlan = flg;
865 for_each_hwfn(edev, i) {
866 p_hwfn = &edev->hwfns[i];
867 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
868 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
869 ECORE_SPQ_MODE_EBLOCK, NULL);
870 if (rc != ECORE_SUCCESS) {
871 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
876 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
879 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
881 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
882 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
883 struct ecore_sp_vport_update_params params;
884 struct ecore_hwfn *p_hwfn;
888 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
890 params.update_inner_vlan_removal_flg = 1;
891 params.inner_vlan_removal_flg = flg;
892 for_each_hwfn(edev, i) {
893 p_hwfn = &edev->hwfns[i];
894 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
895 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
896 ECORE_SPQ_MODE_EBLOCK, NULL);
897 if (rc != ECORE_SUCCESS) {
898 DP_ERR(edev, "Failed to update vport\n");
903 qdev->vlan_strip_flg = flg;
905 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
909 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
910 uint16_t vlan_id, int on)
912 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
913 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
914 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
915 struct qede_vlan_entry *tmp = NULL;
916 struct qede_vlan_entry *vlan;
917 struct ecore_filter_ucast ucast;
921 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
922 DP_ERR(edev, "Reached max VLAN filter limit"
923 " enabling accept_any_vlan\n");
924 qede_config_accept_any_vlan(qdev, true);
928 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
929 if (tmp->vid == vlan_id) {
930 DP_INFO(edev, "VLAN %u already configured\n",
936 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
937 RTE_CACHE_LINE_SIZE);
940 DP_ERR(edev, "Did not allocate memory for VLAN\n");
944 qede_set_ucast_cmn_params(&ucast);
945 ucast.opcode = ECORE_FILTER_ADD;
946 ucast.type = ECORE_FILTER_VLAN;
947 ucast.vlan = vlan_id;
948 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
951 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
956 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
957 qdev->configured_vlans++;
958 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
959 vlan_id, qdev->configured_vlans);
962 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
963 if (tmp->vid == vlan_id)
968 if (qdev->configured_vlans == 0) {
970 "No VLAN filters configured yet\n");
974 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
978 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
980 qede_set_ucast_cmn_params(&ucast);
981 ucast.opcode = ECORE_FILTER_REMOVE;
982 ucast.type = ECORE_FILTER_VLAN;
983 ucast.vlan = vlan_id;
984 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
987 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
990 qdev->configured_vlans--;
991 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
992 vlan_id, qdev->configured_vlans);
999 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1001 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1002 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1003 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
1006 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1007 (void)qede_vlan_stripping(eth_dev, 1);
1009 (void)qede_vlan_stripping(eth_dev, 0);
1012 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
1013 /* VLAN filtering kicks in when a VLAN is added */
1014 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
1015 qede_vlan_filter_set(eth_dev, 0, 1);
1017 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1019 " Please remove existing VLAN filters"
1020 " before disabling VLAN filtering\n");
1021 /* Signal app that VLAN filtering is still
1024 eth_dev->data->dev_conf.rxmode.offloads |=
1025 RTE_ETH_RX_OFFLOAD_VLAN_FILTER;
1027 qede_vlan_filter_set(eth_dev, 0, 0);
1032 qdev->vlan_offload_mask = mask;
1034 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1039 static void qede_prandom_bytes(uint32_t *buff)
1043 srand((unsigned int)time(NULL));
1044 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1048 int qede_config_rss(struct rte_eth_dev *eth_dev)
1050 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1051 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1052 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1053 struct rte_eth_rss_reta_entry64 reta_conf[2];
1054 struct rte_eth_rss_conf rss_conf;
1055 uint32_t i, id, pos, q;
1057 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1058 if (!rss_conf.rss_key) {
1059 DP_INFO(edev, "Applying driver default key\n");
1060 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1061 qede_prandom_bytes(&def_rss_key[0]);
1062 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1065 /* Configure RSS hash */
1066 if (qede_rss_hash_update(eth_dev, &rss_conf))
1069 /* Configure default RETA */
1070 memset(reta_conf, 0, sizeof(reta_conf));
1071 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1072 reta_conf[i / RTE_ETH_RETA_GROUP_SIZE].mask = UINT64_MAX;
1074 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1075 id = i / RTE_ETH_RETA_GROUP_SIZE;
1076 pos = i % RTE_ETH_RETA_GROUP_SIZE;
1077 q = i % QEDE_RSS_COUNT(eth_dev);
1078 reta_conf[id].reta[pos] = q;
1080 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1081 ECORE_RSS_IND_TABLE_SIZE))
1087 static void qede_fastpath_start(struct ecore_dev *edev)
1089 struct ecore_hwfn *p_hwfn;
1092 for_each_hwfn(edev, i) {
1093 p_hwfn = &edev->hwfns[i];
1094 ecore_hw_start_fastpath(p_hwfn);
1098 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1100 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1101 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1102 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1104 PMD_INIT_FUNC_TRACE(edev);
1106 /* Update MTU only if it has changed */
1107 if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1108 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1110 qdev->mtu = qdev->new_mtu;
1114 /* Configure TPA parameters */
1115 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) {
1116 if (qede_enable_tpa(eth_dev, true))
1118 /* Enable scatter mode for LRO */
1119 if (!eth_dev->data->scattered_rx)
1120 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
1124 if (qede_start_queues(eth_dev))
1128 qede_reset_queue_stats(qdev, true);
1130 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1131 * enabling RSS. Hence RSS configuration is deferred up to this point.
1132 * Also, we would like to retain similar behavior in PF case, so we
1133 * don't do PF/VF specific check here.
1135 if (eth_dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS)
1136 if (qede_config_rss(eth_dev))
1140 if (qede_activate_vport(eth_dev, true))
1143 /* Bring-up the link */
1144 qede_dev_set_link_state(eth_dev, true);
1146 /* Update link status */
1147 qede_link_update(eth_dev, 0);
1149 /* Start/resume traffic */
1150 qede_fastpath_start(edev);
1152 /* Assign I/O handlers */
1153 qede_assign_rxtx_handlers(eth_dev, false);
1155 DP_INFO(edev, "Device started\n");
1159 DP_ERR(edev, "Device start fails\n");
1160 return -1; /* common error code is < 0 */
1163 static int qede_dev_stop(struct rte_eth_dev *eth_dev)
1165 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1166 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1168 PMD_INIT_FUNC_TRACE(edev);
1169 eth_dev->data->dev_started = 0;
1171 /* Bring the link down */
1172 qede_dev_set_link_state(eth_dev, false);
1174 /* Update link status */
1175 qede_link_update(eth_dev, 0);
1177 /* Replace I/O functions with dummy ones. It cannot
1178 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1180 qede_assign_rxtx_handlers(eth_dev, true);
1183 if (qede_activate_vport(eth_dev, false))
1186 if (qdev->enable_lro)
1187 qede_enable_tpa(eth_dev, false);
1190 qede_stop_queues(eth_dev);
1192 /* Disable traffic */
1193 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1195 DP_INFO(edev, "Device is stopped\n");
1200 static const char * const valid_args[] = {
1201 QEDE_NPAR_TX_SWITCHING,
1202 QEDE_VF_TX_SWITCHING,
1206 static int qede_args_check(const char *key, const char *val, void *opaque)
1210 struct rte_eth_dev *eth_dev = opaque;
1211 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1212 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1215 tmp = strtoul(val, NULL, 0);
1217 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1221 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1222 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1223 qdev->enable_tx_switching = !!tmp;
1224 DP_INFO(edev, "Disabling %s tx-switching\n",
1225 strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1232 static int qede_args(struct rte_eth_dev *eth_dev)
1234 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1235 struct rte_kvargs *kvlist;
1236 struct rte_devargs *devargs;
1240 devargs = pci_dev->device.devargs;
1242 return 0; /* return success */
1244 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1248 /* Process parameters. */
1249 for (i = 0; (valid_args[i] != NULL); ++i) {
1250 if (rte_kvargs_count(kvlist, valid_args[i])) {
1251 ret = rte_kvargs_process(kvlist, valid_args[i],
1252 qede_args_check, eth_dev);
1253 if (ret != ECORE_SUCCESS) {
1254 rte_kvargs_free(kvlist);
1259 rte_kvargs_free(kvlist);
1264 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1266 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1267 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1268 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1273 PMD_INIT_FUNC_TRACE(edev);
1275 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1276 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1278 /* We need to have min 1 RX queue.There is no min check in
1279 * rte_eth_dev_configure(), so we are checking it here.
1281 if (eth_dev->data->nb_rx_queues == 0) {
1282 DP_ERR(edev, "Minimum one RX queue is required\n");
1286 /* Enable Tx switching by default */
1287 qdev->enable_tx_switching = 1;
1289 /* Parse devargs and fix up rxmode */
1290 if (qede_args(eth_dev))
1291 DP_NOTICE(edev, false,
1292 "Invalid devargs supplied, requested change will not take effect\n");
1294 if (!(rxmode->mq_mode == RTE_ETH_MQ_RX_NONE ||
1295 rxmode->mq_mode == RTE_ETH_MQ_RX_RSS)) {
1296 DP_ERR(edev, "Unsupported multi-queue mode\n");
1299 /* Flow director mode check */
1300 if (qede_check_fdir_support(eth_dev))
1303 /* Allocate/reallocate fastpath resources only for new queue config */
1304 num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1305 num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1306 if (qdev->num_tx_queues != num_txqs ||
1307 qdev->num_rx_queues != num_rxqs) {
1308 qede_dealloc_fp_resc(eth_dev);
1309 qdev->num_tx_queues = num_txqs;
1310 qdev->num_rx_queues = num_rxqs;
1311 if (qede_alloc_fp_resc(qdev))
1315 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
1316 eth_dev->data->scattered_rx = 1;
1318 if (qede_start_vport(qdev, eth_dev->data->mtu))
1321 qdev->mtu = eth_dev->data->mtu;
1323 /* Enable VLAN offloads by default */
1324 ret = qede_vlan_offload_set(eth_dev, RTE_ETH_VLAN_STRIP_MASK |
1325 RTE_ETH_VLAN_FILTER_MASK);
1329 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1330 QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1332 if (ECORE_IS_CMT(edev))
1333 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1334 qdev->num_rx_queues, qdev->num_tx_queues);
1340 /* Info about HW descriptor ring limitations */
1341 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1342 .nb_max = 0x8000, /* 32K */
1344 .nb_align = 128 /* lowest common multiple */
1347 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1348 .nb_max = 0x8000, /* 32K */
1351 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1352 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1356 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1357 struct rte_eth_dev_info *dev_info)
1359 struct qede_dev *qdev = eth_dev->data->dev_private;
1360 struct ecore_dev *edev = &qdev->edev;
1361 struct qed_link_output link;
1362 uint32_t speed_cap = 0;
1364 PMD_INIT_FUNC_TRACE(edev);
1366 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1367 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1368 dev_info->rx_desc_lim = qede_rx_desc_lim;
1369 dev_info->tx_desc_lim = qede_tx_desc_lim;
1372 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1373 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1375 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1376 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1377 /* Since CMT mode internally doubles the number of queues */
1378 if (ECORE_IS_CMT(edev))
1379 dev_info->max_rx_queues = dev_info->max_rx_queues / 2;
1381 dev_info->max_tx_queues = dev_info->max_rx_queues;
1383 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1384 dev_info->max_vfs = 0;
1385 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1386 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1387 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1388 dev_info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1389 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1390 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1391 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1392 RTE_ETH_RX_OFFLOAD_TCP_LRO |
1393 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1394 RTE_ETH_RX_OFFLOAD_SCATTER |
1395 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
1396 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1397 RTE_ETH_RX_OFFLOAD_RSS_HASH);
1398 dev_info->rx_queue_offload_capa = 0;
1400 /* TX offloads are on a per-packet basis, so it is applicable
1401 * to both at port and queue levels.
1403 dev_info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
1404 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
1405 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
1406 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
1407 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1408 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
1409 RTE_ETH_TX_OFFLOAD_TCP_TSO |
1410 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
1411 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO);
1412 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1414 dev_info->default_txconf = (struct rte_eth_txconf) {
1415 .offloads = RTE_ETH_TX_OFFLOAD_MULTI_SEGS,
1418 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1419 /* Packets are always dropped if no descriptors are available */
1424 memset(&link, 0, sizeof(struct qed_link_output));
1425 qdev->ops->common->get_link(edev, &link);
1426 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1427 speed_cap |= RTE_ETH_LINK_SPEED_1G;
1428 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1429 speed_cap |= RTE_ETH_LINK_SPEED_10G;
1430 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1431 speed_cap |= RTE_ETH_LINK_SPEED_25G;
1432 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1433 speed_cap |= RTE_ETH_LINK_SPEED_40G;
1434 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1435 speed_cap |= RTE_ETH_LINK_SPEED_50G;
1436 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1437 speed_cap |= RTE_ETH_LINK_SPEED_100G;
1438 dev_info->speed_capa = speed_cap;
1443 /* return 0 means link status changed, -1 means not changed */
1445 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1447 struct qede_dev *qdev = eth_dev->data->dev_private;
1448 struct ecore_dev *edev = &qdev->edev;
1449 struct qed_link_output q_link;
1450 struct rte_eth_link link;
1451 uint16_t link_duplex;
1453 memset(&q_link, 0, sizeof(q_link));
1454 memset(&link, 0, sizeof(link));
1456 qdev->ops->common->get_link(edev, &q_link);
1459 link.link_speed = q_link.speed;
1462 switch (q_link.duplex) {
1463 case QEDE_DUPLEX_HALF:
1464 link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1466 case QEDE_DUPLEX_FULL:
1467 link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1469 case QEDE_DUPLEX_UNKNOWN:
1473 link.link_duplex = link_duplex;
1476 link.link_status = q_link.link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1479 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1480 RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
1482 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1483 link.link_speed, link.link_duplex,
1484 link.link_autoneg, link.link_status);
1486 return rte_eth_linkstatus_set(eth_dev, &link);
1489 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1491 enum _ecore_status_t ecore_status;
1492 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1493 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1494 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1496 PMD_INIT_FUNC_TRACE(edev);
1498 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1500 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1503 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1505 struct qede_dev *qdev = eth_dev->data->dev_private;
1506 struct ecore_dev *edev = &qdev->edev;
1507 enum _ecore_status_t ecore_status;
1509 PMD_INIT_FUNC_TRACE(edev);
1511 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1512 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1513 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1515 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1516 QED_FILTER_RX_MODE_TYPE_REGULAR);
1518 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1521 static void qede_poll_sp_sb_cb(void *param)
1523 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1524 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1525 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1528 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1529 qede_interrupt_action(&edev->hwfns[1]);
1531 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1535 DP_ERR(edev, "Unable to start periodic"
1536 " timer rc %d\n", rc);
1540 static int qede_dev_close(struct rte_eth_dev *eth_dev)
1542 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1543 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1544 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1547 PMD_INIT_FUNC_TRACE(edev);
1549 /* only close in case of the primary process */
1550 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1553 /* dev_stop() shall cleanup fp resources in hw but without releasing
1554 * dma memories and sw structures so that dev_start() can be called
1555 * by the app without reconfiguration. However, in dev_close() we
1556 * can release all the resources and device can be brought up newly
1558 if (eth_dev->data->dev_started)
1559 ret = qede_dev_stop(eth_dev);
1561 if (qdev->vport_started)
1562 qede_stop_vport(edev);
1563 qdev->vport_started = false;
1564 qede_fdir_dealloc_resc(eth_dev);
1565 qede_dealloc_fp_resc(eth_dev);
1567 eth_dev->data->nb_rx_queues = 0;
1568 eth_dev->data->nb_tx_queues = 0;
1570 qdev->ops->common->slowpath_stop(edev);
1571 qdev->ops->common->remove(edev);
1572 rte_intr_disable(&pci_dev->intr_handle);
1574 switch (pci_dev->intr_handle.type) {
1575 case RTE_INTR_HANDLE_UIO_INTX:
1576 case RTE_INTR_HANDLE_VFIO_LEGACY:
1577 rte_intr_callback_unregister(&pci_dev->intr_handle,
1578 qede_interrupt_handler_intx,
1582 rte_intr_callback_unregister(&pci_dev->intr_handle,
1583 qede_interrupt_handler,
1587 if (ECORE_IS_CMT(edev))
1588 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1594 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1596 struct qede_dev *qdev = eth_dev->data->dev_private;
1597 struct ecore_dev *edev = &qdev->edev;
1598 struct ecore_eth_stats stats;
1599 unsigned int i = 0, j = 0, qid, idx, hw_fn;
1600 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1601 struct qede_tx_queue *txq;
1603 ecore_get_vport_stats(edev, &stats);
1606 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1607 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1609 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1610 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1612 eth_stats->ierrors = stats.common.rx_crc_errors +
1613 stats.common.rx_align_errors +
1614 stats.common.rx_carrier_errors +
1615 stats.common.rx_oversize_packets +
1616 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1618 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1620 eth_stats->imissed = stats.common.mftag_filter_discards +
1621 stats.common.mac_filter_discards +
1622 stats.common.no_buff_discards +
1623 stats.common.brb_truncates + stats.common.brb_discards;
1626 eth_stats->opackets = stats.common.tx_ucast_pkts +
1627 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1629 eth_stats->obytes = stats.common.tx_ucast_bytes +
1630 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1632 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1635 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1636 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1637 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1638 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1639 if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1640 txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1641 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1642 "Not all the queue stats will be displayed. Set"
1643 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1644 " appropriately and retry.\n");
1646 for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1647 eth_stats->q_ipackets[i] = 0;
1648 eth_stats->q_errors[i] = 0;
1650 for_each_hwfn(edev, hw_fn) {
1651 idx = qid * edev->num_hwfns + hw_fn;
1653 eth_stats->q_ipackets[i] +=
1655 (((char *)(qdev->fp_array[idx].rxq)) +
1656 offsetof(struct qede_rx_queue,
1658 eth_stats->q_errors[i] +=
1660 (((char *)(qdev->fp_array[idx].rxq)) +
1661 offsetof(struct qede_rx_queue,
1664 (((char *)(qdev->fp_array[idx].rxq)) +
1665 offsetof(struct qede_rx_queue,
1670 if (i == rxq_stat_cntrs)
1674 for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1675 eth_stats->q_opackets[j] = 0;
1677 for_each_hwfn(edev, hw_fn) {
1678 idx = qid * edev->num_hwfns + hw_fn;
1680 txq = qdev->fp_array[idx].txq;
1681 eth_stats->q_opackets[j] +=
1682 *((uint64_t *)(uintptr_t)
1683 (((uint64_t)(uintptr_t)(txq)) +
1684 offsetof(struct qede_tx_queue,
1689 if (j == txq_stat_cntrs)
1697 qede_get_xstats_count(struct qede_dev *qdev) {
1698 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1700 if (ECORE_IS_BB(&qdev->edev))
1701 return RTE_DIM(qede_xstats_strings) +
1702 RTE_DIM(qede_bb_xstats_strings) +
1703 (RTE_DIM(qede_rxq_xstats_strings) *
1704 QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1706 return RTE_DIM(qede_xstats_strings) +
1707 RTE_DIM(qede_ah_xstats_strings) +
1708 (RTE_DIM(qede_rxq_xstats_strings) *
1709 QEDE_RSS_COUNT(dev));
1713 qede_get_xstats_names(struct rte_eth_dev *dev,
1714 struct rte_eth_xstat_name *xstats_names,
1715 __rte_unused unsigned int limit)
1717 struct qede_dev *qdev = dev->data->dev_private;
1718 struct ecore_dev *edev = &qdev->edev;
1719 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1720 unsigned int i, qid, hw_fn, stat_idx = 0;
1722 if (xstats_names == NULL)
1725 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1726 strlcpy(xstats_names[stat_idx].name,
1727 qede_xstats_strings[i].name,
1728 sizeof(xstats_names[stat_idx].name));
1732 if (ECORE_IS_BB(edev)) {
1733 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1734 strlcpy(xstats_names[stat_idx].name,
1735 qede_bb_xstats_strings[i].name,
1736 sizeof(xstats_names[stat_idx].name));
1740 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1741 strlcpy(xstats_names[stat_idx].name,
1742 qede_ah_xstats_strings[i].name,
1743 sizeof(xstats_names[stat_idx].name));
1748 for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1749 for_each_hwfn(edev, hw_fn) {
1750 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1751 snprintf(xstats_names[stat_idx].name,
1752 RTE_ETH_XSTATS_NAME_SIZE,
1754 qede_rxq_xstats_strings[i].name,
1756 qede_rxq_xstats_strings[i].name + 4);
1766 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1769 struct qede_dev *qdev = dev->data->dev_private;
1770 struct ecore_dev *edev = &qdev->edev;
1771 struct ecore_eth_stats stats;
1772 const unsigned int num = qede_get_xstats_count(qdev);
1773 unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1778 ecore_get_vport_stats(edev, &stats);
1780 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1781 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1782 qede_xstats_strings[i].offset);
1783 xstats[stat_idx].id = stat_idx;
1787 if (ECORE_IS_BB(edev)) {
1788 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1789 xstats[stat_idx].value =
1790 *(uint64_t *)(((char *)&stats) +
1791 qede_bb_xstats_strings[i].offset);
1792 xstats[stat_idx].id = stat_idx;
1796 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1797 xstats[stat_idx].value =
1798 *(uint64_t *)(((char *)&stats) +
1799 qede_ah_xstats_strings[i].offset);
1800 xstats[stat_idx].id = stat_idx;
1805 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1806 for_each_hwfn(edev, hw_fn) {
1807 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1808 fpidx = qid * edev->num_hwfns + hw_fn;
1809 xstats[stat_idx].value = *(uint64_t *)
1810 (((char *)(qdev->fp_array[fpidx].rxq)) +
1811 qede_rxq_xstats_strings[i].offset);
1812 xstats[stat_idx].id = stat_idx;
1823 qede_reset_xstats(struct rte_eth_dev *dev)
1825 struct qede_dev *qdev = dev->data->dev_private;
1826 struct ecore_dev *edev = &qdev->edev;
1828 ecore_reset_vport_stats(edev);
1829 qede_reset_queue_stats(qdev, true);
1834 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1836 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1837 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1838 struct qed_link_params link_params;
1841 DP_INFO(edev, "setting link state %d\n", link_up);
1842 memset(&link_params, 0, sizeof(link_params));
1843 link_params.link_up = link_up;
1844 rc = qdev->ops->common->set_link(edev, &link_params);
1845 if (rc != ECORE_SUCCESS)
1846 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1851 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1853 return qede_dev_set_link_state(eth_dev, true);
1856 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1858 return qede_dev_set_link_state(eth_dev, false);
1861 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1863 struct qede_dev *qdev = eth_dev->data->dev_private;
1864 struct ecore_dev *edev = &qdev->edev;
1866 ecore_reset_vport_stats(edev);
1867 qede_reset_queue_stats(qdev, false);
1872 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1874 enum qed_filter_rx_mode_type type =
1875 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1876 enum _ecore_status_t ecore_status;
1878 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1879 type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1880 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1882 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1885 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1887 enum _ecore_status_t ecore_status;
1889 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1890 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1891 QED_FILTER_RX_MODE_TYPE_PROMISC);
1893 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1894 QED_FILTER_RX_MODE_TYPE_REGULAR);
1896 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1900 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1901 struct rte_ether_addr *mc_addrs,
1902 uint32_t mc_addrs_num)
1904 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1905 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1908 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1909 DP_ERR(edev, "Reached max multicast filters limit,"
1910 "Please enable multicast promisc mode\n");
1914 for (i = 0; i < mc_addrs_num; i++) {
1915 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1916 DP_ERR(edev, "Not a valid multicast MAC\n");
1921 /* Flush all existing entries */
1922 if (qede_del_mcast_filters(eth_dev))
1925 /* Set new mcast list */
1926 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1929 /* Update MTU via vport-update without doing port restart.
1930 * The vport must be deactivated before calling this API.
1932 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1934 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1935 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1936 struct ecore_hwfn *p_hwfn;
1941 struct ecore_sp_vport_update_params params;
1943 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1944 params.vport_id = 0;
1946 params.vport_id = 0;
1947 for_each_hwfn(edev, i) {
1948 p_hwfn = &edev->hwfns[i];
1949 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1950 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1951 ECORE_SPQ_MODE_EBLOCK, NULL);
1952 if (rc != ECORE_SUCCESS)
1956 for_each_hwfn(edev, i) {
1957 p_hwfn = &edev->hwfns[i];
1958 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1959 if (rc == ECORE_INVAL) {
1960 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1961 /* Recreate vport */
1962 rc = qede_start_vport(qdev, mtu);
1963 if (rc != ECORE_SUCCESS)
1966 /* Restore config lost due to vport stop */
1967 if (eth_dev->data->promiscuous)
1968 qede_promiscuous_enable(eth_dev);
1970 qede_promiscuous_disable(eth_dev);
1972 if (eth_dev->data->all_multicast)
1973 qede_allmulticast_enable(eth_dev);
1975 qede_allmulticast_disable(eth_dev);
1977 qede_vlan_offload_set(eth_dev,
1978 qdev->vlan_offload_mask);
1979 } else if (rc != ECORE_SUCCESS) {
1984 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1989 DP_ERR(edev, "Failed to update MTU\n");
1993 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1994 struct rte_eth_fc_conf *fc_conf)
1996 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1997 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1998 struct qed_link_output current_link;
1999 struct qed_link_params params;
2001 memset(¤t_link, 0, sizeof(current_link));
2002 qdev->ops->common->get_link(edev, ¤t_link);
2004 memset(¶ms, 0, sizeof(params));
2005 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2006 if (fc_conf->autoneg) {
2007 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2008 DP_ERR(edev, "Autoneg not supported\n");
2011 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2014 /* Pause is assumed to be supported (SUPPORTED_Pause) */
2015 if (fc_conf->mode == RTE_ETH_FC_FULL)
2016 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2017 QED_LINK_PAUSE_RX_ENABLE);
2018 if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE)
2019 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2020 if (fc_conf->mode == RTE_ETH_FC_RX_PAUSE)
2021 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2023 params.link_up = true;
2024 (void)qdev->ops->common->set_link(edev, ¶ms);
2029 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2030 struct rte_eth_fc_conf *fc_conf)
2032 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2033 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2034 struct qed_link_output current_link;
2036 memset(¤t_link, 0, sizeof(current_link));
2037 qdev->ops->common->get_link(edev, ¤t_link);
2039 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2040 fc_conf->autoneg = true;
2042 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2043 QED_LINK_PAUSE_TX_ENABLE))
2044 fc_conf->mode = RTE_ETH_FC_FULL;
2045 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2046 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2047 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2048 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2050 fc_conf->mode = RTE_ETH_FC_NONE;
2055 static const uint32_t *
2056 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2058 static const uint32_t ptypes[] = {
2060 RTE_PTYPE_L2_ETHER_VLAN,
2065 RTE_PTYPE_TUNNEL_VXLAN,
2067 RTE_PTYPE_TUNNEL_GENEVE,
2068 RTE_PTYPE_TUNNEL_GRE,
2070 RTE_PTYPE_INNER_L2_ETHER,
2071 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2072 RTE_PTYPE_INNER_L3_IPV4,
2073 RTE_PTYPE_INNER_L3_IPV6,
2074 RTE_PTYPE_INNER_L4_TCP,
2075 RTE_PTYPE_INNER_L4_UDP,
2076 RTE_PTYPE_INNER_L4_FRAG,
2080 if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2081 eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2082 eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2088 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2091 *rss_caps |= (hf & RTE_ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2092 *rss_caps |= (hf & RTE_ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2093 *rss_caps |= (hf & RTE_ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2094 *rss_caps |= (hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2095 *rss_caps |= (hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2096 *rss_caps |= (hf & RTE_ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2097 *rss_caps |= (hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2098 *rss_caps |= (hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2101 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2102 struct rte_eth_rss_conf *rss_conf)
2104 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2105 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2106 struct ecore_sp_vport_update_params vport_update_params;
2107 struct ecore_rss_params rss_params;
2108 struct ecore_hwfn *p_hwfn;
2109 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2110 uint64_t hf = rss_conf->rss_hf;
2111 uint8_t len = rss_conf->rss_key_len;
2112 uint8_t idx, i, j, fpidx;
2115 memset(&vport_update_params, 0, sizeof(vport_update_params));
2116 memset(&rss_params, 0, sizeof(rss_params));
2118 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2119 (unsigned long)hf, len, key);
2123 DP_INFO(edev, "Enabling rss\n");
2126 qede_init_rss_caps(&rss_params.rss_caps, hf);
2127 rss_params.update_rss_capabilities = 1;
2131 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2132 len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
2133 DP_NOTICE(edev, false,
2134 "RSS key length too big, trimmed to %d\n",
2137 DP_INFO(edev, "Applying user supplied hash key\n");
2138 rss_params.update_rss_key = 1;
2139 memcpy(&rss_params.rss_key, key, len);
2141 rss_params.rss_enable = 1;
2144 rss_params.update_rss_config = 1;
2145 /* tbl_size has to be set with capabilities */
2146 rss_params.rss_table_size_log = 7;
2147 vport_update_params.vport_id = 0;
2149 for_each_hwfn(edev, i) {
2150 /* pass the L2 handles instead of qids */
2151 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2152 idx = j % QEDE_RSS_COUNT(eth_dev);
2153 fpidx = idx * edev->num_hwfns + i;
2154 rss_params.rss_ind_table[j] =
2155 qdev->fp_array[fpidx].rxq->handle;
2158 vport_update_params.rss_params = &rss_params;
2160 p_hwfn = &edev->hwfns[i];
2161 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2162 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2163 ECORE_SPQ_MODE_EBLOCK, NULL);
2165 DP_ERR(edev, "vport-update for RSS failed\n");
2169 qdev->rss_enable = rss_params.rss_enable;
2171 /* Update local structure for hash query */
2172 qdev->rss_conf.rss_hf = hf;
2173 qdev->rss_conf.rss_key_len = len;
2174 if (qdev->rss_enable) {
2175 if (qdev->rss_conf.rss_key == NULL) {
2176 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2177 if (qdev->rss_conf.rss_key == NULL) {
2178 DP_ERR(edev, "No memory to store RSS key\n");
2183 DP_INFO(edev, "Storing RSS key\n");
2184 memcpy(qdev->rss_conf.rss_key, key, len);
2186 } else if (!qdev->rss_enable && len == 0) {
2187 if (qdev->rss_conf.rss_key) {
2188 free(qdev->rss_conf.rss_key);
2189 qdev->rss_conf.rss_key = NULL;
2190 DP_INFO(edev, "Free RSS key\n");
2197 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2198 struct rte_eth_rss_conf *rss_conf)
2200 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2202 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2203 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2205 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2206 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2207 rss_conf->rss_key_len);
2211 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2212 struct rte_eth_rss_reta_entry64 *reta_conf,
2215 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2216 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2217 struct ecore_sp_vport_update_params vport_update_params;
2218 struct ecore_rss_params *params;
2219 uint16_t i, j, idx, fid, shift;
2220 struct ecore_hwfn *p_hwfn;
2224 if (reta_size > RTE_ETH_RSS_RETA_SIZE_128) {
2225 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2230 memset(&vport_update_params, 0, sizeof(vport_update_params));
2231 params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2232 if (params == NULL) {
2233 DP_ERR(edev, "failed to allocate memory\n");
2237 params->update_rss_ind_table = 1;
2238 params->rss_table_size_log = 7;
2239 params->update_rss_config = 1;
2241 vport_update_params.vport_id = 0;
2242 /* Use the current value of rss_enable */
2243 params->rss_enable = qdev->rss_enable;
2244 vport_update_params.rss_params = params;
2246 for_each_hwfn(edev, i) {
2247 for (j = 0; j < reta_size; j++) {
2248 idx = j / RTE_ETH_RETA_GROUP_SIZE;
2249 shift = j % RTE_ETH_RETA_GROUP_SIZE;
2250 if (reta_conf[idx].mask & (1ULL << shift)) {
2251 entry = reta_conf[idx].reta[shift];
2252 fid = entry * edev->num_hwfns + i;
2253 /* Pass rxq handles to ecore */
2254 params->rss_ind_table[j] =
2255 qdev->fp_array[fid].rxq->handle;
2256 /* Update the local copy for RETA query cmd */
2257 qdev->rss_ind_table[j] = entry;
2261 p_hwfn = &edev->hwfns[i];
2262 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2263 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2264 ECORE_SPQ_MODE_EBLOCK, NULL);
2266 DP_ERR(edev, "vport-update for RSS failed\n");
2276 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2277 struct rte_eth_rss_reta_entry64 *reta_conf,
2280 struct qede_dev *qdev = eth_dev->data->dev_private;
2281 struct ecore_dev *edev = &qdev->edev;
2282 uint16_t i, idx, shift;
2285 if (reta_size > RTE_ETH_RSS_RETA_SIZE_128) {
2286 DP_ERR(edev, "reta_size %d is not supported\n",
2291 for (i = 0; i < reta_size; i++) {
2292 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2293 shift = i % RTE_ETH_RETA_GROUP_SIZE;
2294 if (reta_conf[idx].mask & (1ULL << shift)) {
2295 entry = qdev->rss_ind_table[i];
2296 reta_conf[idx].reta[shift] = entry;
2305 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2307 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2308 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2309 struct qede_fastpath *fp;
2310 uint32_t frame_size;
2312 bool restart = false;
2315 PMD_INIT_FUNC_TRACE(edev);
2317 frame_size = mtu + QEDE_MAX_ETHER_HDR_LEN;
2318 if (!dev->data->scattered_rx &&
2319 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2320 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2321 dev->data->min_rx_buf_size);
2324 if (dev->data->dev_started) {
2325 dev->data->dev_started = 0;
2326 rc = qede_dev_stop(dev);
2332 qdev->new_mtu = mtu;
2334 /* Fix up RX buf size for all queues of the port */
2335 for (i = 0; i < qdev->num_rx_queues; i++) {
2336 fp = &qdev->fp_array[i];
2337 if (fp->rxq != NULL) {
2338 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2339 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2340 /* cache align the mbuf size to simplfy rx_buf_size
2343 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2344 rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2348 fp->rxq->rx_buf_size = rc;
2352 if (!dev->data->dev_started && restart) {
2353 qede_dev_start(dev);
2354 dev->data->dev_started = 1;
2361 qede_dev_reset(struct rte_eth_dev *dev)
2365 ret = qede_eth_dev_uninit(dev);
2369 return qede_eth_dev_init(dev);
2373 qede_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2375 qede_rx_queue_release(dev->data->rx_queues[qid]);
2379 qede_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2381 qede_tx_queue_release(dev->data->tx_queues[qid]);
2384 static const struct eth_dev_ops qede_eth_dev_ops = {
2385 .dev_configure = qede_dev_configure,
2386 .dev_infos_get = qede_dev_info_get,
2387 .rx_queue_setup = qede_rx_queue_setup,
2388 .rx_queue_release = qede_dev_rx_queue_release,
2389 .tx_queue_setup = qede_tx_queue_setup,
2390 .tx_queue_release = qede_dev_tx_queue_release,
2391 .dev_start = qede_dev_start,
2392 .dev_reset = qede_dev_reset,
2393 .dev_set_link_up = qede_dev_set_link_up,
2394 .dev_set_link_down = qede_dev_set_link_down,
2395 .link_update = qede_link_update,
2396 .promiscuous_enable = qede_promiscuous_enable,
2397 .promiscuous_disable = qede_promiscuous_disable,
2398 .allmulticast_enable = qede_allmulticast_enable,
2399 .allmulticast_disable = qede_allmulticast_disable,
2400 .set_mc_addr_list = qede_set_mc_addr_list,
2401 .dev_stop = qede_dev_stop,
2402 .dev_close = qede_dev_close,
2403 .stats_get = qede_get_stats,
2404 .stats_reset = qede_reset_stats,
2405 .xstats_get = qede_get_xstats,
2406 .xstats_reset = qede_reset_xstats,
2407 .xstats_get_names = qede_get_xstats_names,
2408 .mac_addr_add = qede_mac_addr_add,
2409 .mac_addr_remove = qede_mac_addr_remove,
2410 .mac_addr_set = qede_mac_addr_set,
2411 .vlan_offload_set = qede_vlan_offload_set,
2412 .vlan_filter_set = qede_vlan_filter_set,
2413 .flow_ctrl_set = qede_flow_ctrl_set,
2414 .flow_ctrl_get = qede_flow_ctrl_get,
2415 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2416 .rss_hash_update = qede_rss_hash_update,
2417 .rss_hash_conf_get = qede_rss_hash_conf_get,
2418 .reta_update = qede_rss_reta_update,
2419 .reta_query = qede_rss_reta_query,
2420 .mtu_set = qede_set_mtu,
2421 .flow_ops_get = qede_dev_flow_ops_get,
2422 .udp_tunnel_port_add = qede_udp_dst_port_add,
2423 .udp_tunnel_port_del = qede_udp_dst_port_del,
2424 .fw_version_get = qede_fw_version_get,
2425 .get_reg = qede_get_regs,
2428 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2429 .dev_configure = qede_dev_configure,
2430 .dev_infos_get = qede_dev_info_get,
2431 .rx_queue_setup = qede_rx_queue_setup,
2432 .rx_queue_release = qede_dev_rx_queue_release,
2433 .tx_queue_setup = qede_tx_queue_setup,
2434 .tx_queue_release = qede_dev_tx_queue_release,
2435 .dev_start = qede_dev_start,
2436 .dev_reset = qede_dev_reset,
2437 .dev_set_link_up = qede_dev_set_link_up,
2438 .dev_set_link_down = qede_dev_set_link_down,
2439 .link_update = qede_link_update,
2440 .promiscuous_enable = qede_promiscuous_enable,
2441 .promiscuous_disable = qede_promiscuous_disable,
2442 .allmulticast_enable = qede_allmulticast_enable,
2443 .allmulticast_disable = qede_allmulticast_disable,
2444 .set_mc_addr_list = qede_set_mc_addr_list,
2445 .dev_stop = qede_dev_stop,
2446 .dev_close = qede_dev_close,
2447 .stats_get = qede_get_stats,
2448 .stats_reset = qede_reset_stats,
2449 .xstats_get = qede_get_xstats,
2450 .xstats_reset = qede_reset_xstats,
2451 .xstats_get_names = qede_get_xstats_names,
2452 .vlan_offload_set = qede_vlan_offload_set,
2453 .vlan_filter_set = qede_vlan_filter_set,
2454 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2455 .rss_hash_update = qede_rss_hash_update,
2456 .rss_hash_conf_get = qede_rss_hash_conf_get,
2457 .reta_update = qede_rss_reta_update,
2458 .reta_query = qede_rss_reta_query,
2459 .mtu_set = qede_set_mtu,
2460 .udp_tunnel_port_add = qede_udp_dst_port_add,
2461 .udp_tunnel_port_del = qede_udp_dst_port_del,
2462 .mac_addr_add = qede_mac_addr_add,
2463 .mac_addr_remove = qede_mac_addr_remove,
2464 .mac_addr_set = qede_mac_addr_set,
2465 .fw_version_get = qede_fw_version_get,
2468 static void qede_update_pf_params(struct ecore_dev *edev)
2470 struct ecore_pf_params pf_params;
2472 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2473 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2474 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2475 qed_ops->common->update_pf_params(edev, &pf_params);
2478 static void qede_generate_random_mac_addr(struct rte_ether_addr *mac_addr)
2482 /* Set Organizationally Unique Identifier (OUI) prefix. */
2483 mac_addr->addr_bytes[0] = 0x00;
2484 mac_addr->addr_bytes[1] = 0x09;
2485 mac_addr->addr_bytes[2] = 0xC0;
2487 /* Force indication of locally assigned MAC address. */
2488 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
2490 /* Generate the last 3 bytes of the MAC address with a random number. */
2491 random = rte_rand();
2493 memcpy(&mac_addr->addr_bytes[3], &random, 3);
2496 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2498 struct rte_pci_device *pci_dev;
2499 struct rte_pci_addr pci_addr;
2500 struct qede_dev *adapter;
2501 struct ecore_dev *edev;
2502 struct qed_dev_eth_info dev_info;
2503 struct qed_slowpath_params params;
2504 static bool do_once = true;
2505 uint8_t bulletin_change;
2506 uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2507 uint8_t is_mac_forced;
2508 bool is_mac_exist = false;
2509 /* Fix up ecore debug level */
2510 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2511 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2515 /* Extract key data structures */
2516 adapter = eth_dev->data->dev_private;
2517 adapter->ethdev = eth_dev;
2518 edev = &adapter->edev;
2519 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2520 pci_addr = pci_dev->addr;
2522 PMD_INIT_FUNC_TRACE(edev);
2524 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2525 pci_addr.bus, pci_addr.devid, pci_addr.function,
2526 eth_dev->data->port_id);
2528 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2529 DP_ERR(edev, "Skipping device init from secondary process\n");
2533 rte_eth_copy_pci_info(eth_dev, pci_dev);
2534 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2537 edev->vendor_id = pci_dev->id.vendor_id;
2538 edev->device_id = pci_dev->id.device_id;
2540 qed_ops = qed_get_eth_ops();
2542 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2547 DP_INFO(edev, "Starting qede probe\n");
2548 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2551 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2555 qede_update_pf_params(edev);
2557 switch (pci_dev->intr_handle.type) {
2558 case RTE_INTR_HANDLE_UIO_INTX:
2559 case RTE_INTR_HANDLE_VFIO_LEGACY:
2560 int_mode = ECORE_INT_MODE_INTA;
2561 rte_intr_callback_register(&pci_dev->intr_handle,
2562 qede_interrupt_handler_intx,
2566 int_mode = ECORE_INT_MODE_MSIX;
2567 rte_intr_callback_register(&pci_dev->intr_handle,
2568 qede_interrupt_handler,
2572 if (rte_intr_enable(&pci_dev->intr_handle)) {
2573 DP_ERR(edev, "rte_intr_enable() failed\n");
2578 /* Start the Slowpath-process */
2579 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2581 params.int_mode = int_mode;
2582 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2583 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2584 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2585 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2586 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2587 QEDE_PMD_DRV_VER_STR_SIZE);
2589 qede_assign_rxtx_handlers(eth_dev, true);
2590 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2592 /* For CMT mode device do periodic polling for slowpath events.
2593 * This is required since uio device uses only one MSI-x
2594 * interrupt vector but we need one for each engine.
2596 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2597 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2601 DP_ERR(edev, "Unable to start periodic"
2602 " timer rc %d\n", rc);
2608 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2610 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2611 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2617 rc = qed_ops->fill_dev_info(edev, &dev_info);
2619 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2620 qed_ops->common->slowpath_stop(edev);
2621 qed_ops->common->remove(edev);
2622 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2628 qede_alloc_etherdev(adapter, &dev_info);
2631 qede_print_adapter_info(eth_dev);
2635 adapter->ops->common->set_name(edev, edev->name);
2638 adapter->dev_info.num_mac_filters =
2639 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2642 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2643 (uint32_t *)&adapter->dev_info.num_mac_filters);
2645 /* Allocate memory for storing MAC addr */
2646 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2647 (RTE_ETHER_ADDR_LEN *
2648 adapter->dev_info.num_mac_filters),
2649 RTE_CACHE_LINE_SIZE);
2651 if (eth_dev->data->mac_addrs == NULL) {
2652 DP_ERR(edev, "Failed to allocate MAC address\n");
2653 qed_ops->common->slowpath_stop(edev);
2654 qed_ops->common->remove(edev);
2655 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2661 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2662 hw_info.hw_mac_addr,
2663 ð_dev->data->mac_addrs[0]);
2664 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2665 &adapter->primary_mac);
2667 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2669 if (bulletin_change) {
2671 ecore_vf_bulletin_get_forced_mac(
2672 ECORE_LEADING_HWFN(edev),
2676 DP_INFO(edev, "VF macaddr received from PF\n");
2677 rte_ether_addr_copy(
2678 (struct rte_ether_addr *)&vf_mac,
2679 ð_dev->data->mac_addrs[0]);
2680 rte_ether_addr_copy(
2681 ð_dev->data->mac_addrs[0],
2682 &adapter->primary_mac);
2684 DP_ERR(edev, "No VF macaddr assigned\n");
2688 /* If MAC doesn't exist from PF, generate random one */
2689 if (!is_mac_exist) {
2690 struct rte_ether_addr *mac_addr;
2692 mac_addr = (struct rte_ether_addr *)&vf_mac;
2693 qede_generate_random_mac_addr(mac_addr);
2695 rte_ether_addr_copy(mac_addr,
2696 ð_dev->data->mac_addrs[0]);
2698 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2699 &adapter->primary_mac);
2703 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2704 eth_dev->rx_descriptor_status = qede_rx_descriptor_status;
2706 adapter->num_tx_queues = 0;
2707 adapter->num_rx_queues = 0;
2708 SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2709 SLIST_INIT(&adapter->vlan_list_head);
2710 SLIST_INIT(&adapter->uc_list_head);
2711 SLIST_INIT(&adapter->mc_list_head);
2712 adapter->mtu = RTE_ETHER_MTU;
2713 adapter->vport_started = false;
2715 /* VF tunnel offloads is enabled by default in PF driver */
2716 adapter->vxlan.num_filters = 0;
2717 adapter->geneve.num_filters = 0;
2718 adapter->ipgre.num_filters = 0;
2720 adapter->vxlan.enable = true;
2721 adapter->vxlan.filter_type = RTE_ETH_TUNNEL_FILTER_IMAC |
2722 RTE_ETH_TUNNEL_FILTER_IVLAN;
2723 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2724 adapter->geneve.enable = true;
2725 adapter->geneve.filter_type = RTE_ETH_TUNNEL_FILTER_IMAC |
2726 RTE_ETH_TUNNEL_FILTER_IVLAN;
2727 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2728 adapter->ipgre.enable = true;
2729 adapter->ipgre.filter_type = RTE_ETH_TUNNEL_FILTER_IMAC |
2730 RTE_ETH_TUNNEL_FILTER_IVLAN;
2732 adapter->vxlan.enable = false;
2733 adapter->geneve.enable = false;
2734 adapter->ipgre.enable = false;
2735 qed_ops->sriov_configure(edev, pci_dev->max_vfs);
2738 DP_INFO(edev, "MAC address : " RTE_ETHER_ADDR_PRT_FMT "\n",
2739 RTE_ETHER_ADDR_BYTES(&adapter->primary_mac));
2741 DP_INFO(edev, "Device initialized\n");
2747 qede_print_adapter_info(eth_dev);
2753 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2755 return qede_common_dev_init(eth_dev, 1);
2758 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2760 return qede_common_dev_init(eth_dev, 0);
2763 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2765 struct qede_dev *qdev = eth_dev->data->dev_private;
2766 struct ecore_dev *edev = &qdev->edev;
2767 PMD_INIT_FUNC_TRACE(edev);
2768 qede_dev_close(eth_dev);
2772 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2774 return qede_dev_common_uninit(eth_dev);
2777 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2779 return qede_dev_common_uninit(eth_dev);
2782 static const struct rte_pci_id pci_id_qedevf_map[] = {
2783 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2785 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2788 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2791 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2796 static const struct rte_pci_id pci_id_qede_map[] = {
2797 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2799 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2802 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2805 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2808 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2811 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2814 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2817 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2820 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2823 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2826 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2831 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2832 struct rte_pci_device *pci_dev)
2834 return rte_eth_dev_pci_generic_probe(pci_dev,
2835 sizeof(struct qede_dev), qedevf_eth_dev_init);
2838 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2840 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2843 static struct rte_pci_driver rte_qedevf_pmd = {
2844 .id_table = pci_id_qedevf_map,
2845 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2846 .probe = qedevf_eth_dev_pci_probe,
2847 .remove = qedevf_eth_dev_pci_remove,
2850 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2851 struct rte_pci_device *pci_dev)
2853 return rte_eth_dev_pci_generic_probe(pci_dev,
2854 sizeof(struct qede_dev), qede_eth_dev_init);
2857 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2859 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2862 static struct rte_pci_driver rte_qede_pmd = {
2863 .id_table = pci_id_qede_map,
2864 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2865 .probe = qede_eth_dev_pci_probe,
2866 .remove = qede_eth_dev_pci_remove,
2869 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2870 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2871 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2872 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2873 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2874 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2875 RTE_LOG_REGISTER_SUFFIX(qede_logtype_init, init, NOTICE);
2876 RTE_LOG_REGISTER_SUFFIX(qede_logtype_driver, driver, NOTICE);