2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static int64_t timer_period = 1;
17 /* VXLAN tunnel classification mapping */
18 const struct _qede_vxlan_tunn_types {
19 uint16_t rte_filter_type;
20 enum ecore_filter_ucast_type qede_type;
21 enum ecore_tunn_clss qede_tunn_clss;
23 } qede_tunn_types[] = {
25 ETH_TUNNEL_FILTER_OMAC,
27 ECORE_TUNN_CLSS_MAC_VLAN,
31 ETH_TUNNEL_FILTER_TENID,
33 ECORE_TUNN_CLSS_MAC_VNI,
37 ETH_TUNNEL_FILTER_IMAC,
38 ECORE_FILTER_INNER_MAC,
39 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
43 ETH_TUNNEL_FILTER_IVLAN,
44 ECORE_FILTER_INNER_VLAN,
45 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
50 ECORE_FILTER_MAC_VNI_PAIR,
51 ECORE_TUNN_CLSS_MAC_VNI,
55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
58 "outer-mac and inner-mac"
61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
64 "outer-mac and inner-vlan"
67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
68 ECORE_FILTER_INNER_MAC_VNI_PAIR,
69 ECORE_TUNN_CLSS_INNER_MAC_VNI,
73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
80 ECORE_FILTER_INNER_PAIR,
81 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
82 "inner-mac and inner-vlan",
85 ETH_TUNNEL_FILTER_OIP,
91 ETH_TUNNEL_FILTER_IIP,
97 RTE_TUNNEL_FILTER_IMAC_IVLAN,
103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
109 RTE_TUNNEL_FILTER_IMAC_TENID,
115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
122 struct rte_qede_xstats_name_off {
123 char name[RTE_ETH_XSTATS_NAME_SIZE];
127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
129 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
130 {"rx_multicast_bytes",
131 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
132 {"rx_broadcast_bytes",
133 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
134 {"rx_unicast_packets",
135 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
136 {"rx_multicast_packets",
137 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
138 {"rx_broadcast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
142 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
143 {"tx_multicast_bytes",
144 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
145 {"tx_broadcast_bytes",
146 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
147 {"tx_unicast_packets",
148 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
149 {"tx_multicast_packets",
150 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
151 {"tx_broadcast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
154 {"rx_64_byte_packets",
155 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
156 {"rx_65_to_127_byte_packets",
157 offsetof(struct ecore_eth_stats_common,
158 rx_65_to_127_byte_packets)},
159 {"rx_128_to_255_byte_packets",
160 offsetof(struct ecore_eth_stats_common,
161 rx_128_to_255_byte_packets)},
162 {"rx_256_to_511_byte_packets",
163 offsetof(struct ecore_eth_stats_common,
164 rx_256_to_511_byte_packets)},
165 {"rx_512_to_1023_byte_packets",
166 offsetof(struct ecore_eth_stats_common,
167 rx_512_to_1023_byte_packets)},
168 {"rx_1024_to_1518_byte_packets",
169 offsetof(struct ecore_eth_stats_common,
170 rx_1024_to_1518_byte_packets)},
171 {"tx_64_byte_packets",
172 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
173 {"tx_65_to_127_byte_packets",
174 offsetof(struct ecore_eth_stats_common,
175 tx_65_to_127_byte_packets)},
176 {"tx_128_to_255_byte_packets",
177 offsetof(struct ecore_eth_stats_common,
178 tx_128_to_255_byte_packets)},
179 {"tx_256_to_511_byte_packets",
180 offsetof(struct ecore_eth_stats_common,
181 tx_256_to_511_byte_packets)},
182 {"tx_512_to_1023_byte_packets",
183 offsetof(struct ecore_eth_stats_common,
184 tx_512_to_1023_byte_packets)},
185 {"tx_1024_to_1518_byte_packets",
186 offsetof(struct ecore_eth_stats_common,
187 tx_1024_to_1518_byte_packets)},
189 {"rx_mac_crtl_frames",
190 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
191 {"tx_mac_control_frames",
192 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
194 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
196 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
197 {"rx_priority_flow_control_frames",
198 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
199 {"tx_priority_flow_control_frames",
200 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
203 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
205 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
206 {"rx_carrier_errors",
207 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
208 {"rx_oversize_packet_errors",
209 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
211 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
212 {"rx_undersize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
214 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
215 {"rx_host_buffer_not_available",
216 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
217 /* Number of packets discarded because they are bigger than MTU */
218 {"rx_packet_too_big_discards",
219 offsetof(struct ecore_eth_stats_common,
220 packet_too_big_discard)},
221 {"rx_ttl_zero_discards",
222 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
223 {"rx_multi_function_tag_filter_discards",
224 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
225 {"rx_mac_filter_discards",
226 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
227 {"rx_hw_buffer_truncates",
228 offsetof(struct ecore_eth_stats_common, brb_truncates)},
229 {"rx_hw_buffer_discards",
230 offsetof(struct ecore_eth_stats_common, brb_discards)},
231 {"tx_error_drop_packets",
232 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
234 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
235 {"rx_mac_unicast_packets",
236 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
237 {"rx_mac_multicast_packets",
238 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
239 {"rx_mac_broadcast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
242 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
243 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
244 {"tx_mac_unicast_packets",
245 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
246 {"tx_mac_multicast_packets",
247 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
248 {"tx_mac_broadcast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
251 {"lro_coalesced_packets",
252 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
253 {"lro_coalesced_events",
254 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
256 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
257 {"lro_not_coalesced_packets",
258 offsetof(struct ecore_eth_stats_common,
259 tpa_not_coalesced_pkts)},
260 {"lro_coalesced_bytes",
261 offsetof(struct ecore_eth_stats_common,
262 tpa_coalesced_bytes)},
265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
266 {"rx_1519_to_1522_byte_packets",
267 offsetof(struct ecore_eth_stats, bb) +
268 offsetof(struct ecore_eth_stats_bb,
269 rx_1519_to_1522_byte_packets)},
270 {"rx_1519_to_2047_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_2047_byte_packets)},
274 {"rx_2048_to_4095_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_2048_to_4095_byte_packets)},
278 {"rx_4096_to_9216_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_4096_to_9216_byte_packets)},
282 {"rx_9217_to_16383_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_9217_to_16383_byte_packets)},
287 {"tx_1519_to_2047_byte_packets",
288 offsetof(struct ecore_eth_stats, bb) +
289 offsetof(struct ecore_eth_stats_bb,
290 tx_1519_to_2047_byte_packets)},
291 {"tx_2048_to_4095_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_2048_to_4095_byte_packets)},
295 {"tx_4096_to_9216_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_4096_to_9216_byte_packets)},
299 {"tx_9217_to_16383_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_9217_to_16383_byte_packets)},
304 {"tx_lpi_entry_count",
305 offsetof(struct ecore_eth_stats, bb) +
306 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
307 {"tx_total_collisions",
308 offsetof(struct ecore_eth_stats, bb) +
309 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
313 {"rx_1519_to_max_byte_packets",
314 offsetof(struct ecore_eth_stats, ah) +
315 offsetof(struct ecore_eth_stats_ah,
316 rx_1519_to_max_byte_packets)},
317 {"tx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 tx_1519_to_max_byte_packets)},
323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
325 offsetof(struct qede_rx_queue, rx_segs)},
327 offsetof(struct qede_rx_queue, rx_hw_errors)},
328 {"rx_q_allocation_errors",
329 offsetof(struct qede_rx_queue, rx_alloc_errors)}
332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
334 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
338 qede_interrupt_handler(void *param)
340 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
341 struct qede_dev *qdev = eth_dev->data->dev_private;
342 struct ecore_dev *edev = &qdev->edev;
344 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
345 if (rte_intr_enable(eth_dev->intr_handle))
346 DP_ERR(edev, "rte_intr_enable failed\n");
350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
352 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
357 static void qede_print_adapter_info(struct qede_dev *qdev)
359 struct ecore_dev *edev = &qdev->edev;
360 struct qed_dev_info *info = &qdev->dev_info.common;
361 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
362 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
364 DP_INFO(edev, "*********************************\n");
365 DP_INFO(edev, " DPDK version:%s\n", rte_version());
366 DP_INFO(edev, " Chip details : %s%d\n",
367 ECORE_IS_BB(edev) ? "BB" : "AH",
368 CHIP_REV_IS_A0(edev) ? 0 : 1);
369 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
370 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
371 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
372 ver_str, QEDE_PMD_VERSION);
373 DP_INFO(edev, " Driver version : %s\n", drv_ver);
374 DP_INFO(edev, " Firmware version : %s\n", ver_str);
376 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
378 (info->mfw_rev >> 24) & 0xff,
379 (info->mfw_rev >> 16) & 0xff,
380 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
381 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
382 DP_INFO(edev, " Firmware file : %s\n", fw_file);
383 DP_INFO(edev, "*********************************\n");
388 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
390 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
391 struct ecore_sp_vport_start_params params;
392 struct ecore_hwfn *p_hwfn;
396 memset(¶ms, 0, sizeof(params));
399 /* @DPDK - Disable FW placement */
400 params.zero_placement_offset = 1;
401 for_each_hwfn(edev, i) {
402 p_hwfn = &edev->hwfns[i];
403 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
404 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
405 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
406 if (rc != ECORE_SUCCESS) {
407 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
411 ecore_reset_vport_stats(edev);
412 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
418 qede_stop_vport(struct ecore_dev *edev)
420 struct ecore_hwfn *p_hwfn;
426 for_each_hwfn(edev, i) {
427 p_hwfn = &edev->hwfns[i];
428 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
430 if (rc != ECORE_SUCCESS) {
431 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
439 /* Activate or deactivate vport via vport-update */
440 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
442 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
443 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
444 struct ecore_sp_vport_update_params params;
445 struct ecore_hwfn *p_hwfn;
449 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
451 params.update_vport_active_rx_flg = 1;
452 params.update_vport_active_tx_flg = 1;
453 params.vport_active_rx_flg = flg;
454 params.vport_active_tx_flg = flg;
455 for_each_hwfn(edev, i) {
456 p_hwfn = &edev->hwfns[i];
457 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
458 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
459 ECORE_SPQ_MODE_EBLOCK, NULL);
460 if (rc != ECORE_SUCCESS) {
461 DP_ERR(edev, "Failed to update vport\n");
465 DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
470 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
471 uint16_t mtu, bool enable)
473 /* Enable LRO in split mode */
474 sge_tpa_params->tpa_ipv4_en_flg = enable;
475 sge_tpa_params->tpa_ipv6_en_flg = enable;
476 sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
477 sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
478 /* set if tpa enable changes */
479 sge_tpa_params->update_tpa_en_flg = 1;
480 /* set if tpa parameters should be handled */
481 sge_tpa_params->update_tpa_param_flg = enable;
483 sge_tpa_params->max_buffers_per_cqe = 20;
484 /* Enable TPA in split mode. In this mode each TPA segment
485 * starts on the new BD, so there is one BD per segment.
487 sge_tpa_params->tpa_pkt_split_flg = 1;
488 sge_tpa_params->tpa_hdr_data_split_flg = 0;
489 sge_tpa_params->tpa_gro_consistent_flg = 0;
490 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
491 sge_tpa_params->tpa_max_size = 0x7FFF;
492 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
493 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
496 /* Enable/disable LRO via vport-update */
497 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
499 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
500 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
501 struct ecore_sp_vport_update_params params;
502 struct ecore_sge_tpa_params tpa_params;
503 struct ecore_hwfn *p_hwfn;
507 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
508 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
509 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
511 params.sge_tpa_params = &tpa_params;
512 for_each_hwfn(edev, i) {
513 p_hwfn = &edev->hwfns[i];
514 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
515 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
516 ECORE_SPQ_MODE_EBLOCK, NULL);
517 if (rc != ECORE_SUCCESS) {
518 DP_ERR(edev, "Failed to update LRO\n");
523 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
528 /* Update MTU via vport-update without doing port restart.
529 * The vport must be deactivated before calling this API.
531 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
533 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
534 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
535 struct ecore_sp_vport_update_params params;
536 struct ecore_hwfn *p_hwfn;
540 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
544 for_each_hwfn(edev, i) {
545 p_hwfn = &edev->hwfns[i];
546 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
547 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
548 ECORE_SPQ_MODE_EBLOCK, NULL);
549 if (rc != ECORE_SUCCESS) {
550 DP_ERR(edev, "Failed to update MTU\n");
554 DP_INFO(edev, "MTU updated to %u\n", mtu);
559 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
561 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
562 ucast->is_rx_filter = true;
563 ucast->is_tx_filter = true;
564 /* ucast->assert_on_error = true; - For debug */
568 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
569 enum qed_filter_rx_mode_type type)
571 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
572 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
573 struct ecore_filter_accept_flags flags;
575 memset(&flags, 0, sizeof(flags));
577 flags.update_rx_mode_config = 1;
578 flags.update_tx_mode_config = 1;
579 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
580 ECORE_ACCEPT_MCAST_MATCHED |
583 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
584 ECORE_ACCEPT_MCAST_MATCHED |
587 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
588 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
590 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
591 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
593 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
594 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
595 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
596 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
597 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
598 ECORE_ACCEPT_MCAST_UNMATCHED;
601 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
602 ECORE_SPQ_MODE_CB, NULL);
604 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
605 uint8_t clss, bool mode, bool mask)
607 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
608 p_tunn->vxlan.b_update_mode = mode;
609 p_tunn->vxlan.b_mode_enabled = mask;
610 p_tunn->b_update_rx_cls = true;
611 p_tunn->b_update_tx_cls = true;
612 p_tunn->vxlan.tun_cls = clss;
616 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
619 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
620 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
621 struct qede_ucast_entry *tmp = NULL;
622 struct qede_ucast_entry *u;
623 struct ether_addr *mac_addr;
625 mac_addr = (struct ether_addr *)ucast->mac;
627 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
628 if ((memcmp(mac_addr, &tmp->mac,
629 ETHER_ADDR_LEN) == 0) &&
630 ucast->vni == tmp->vni &&
631 ucast->vlan == tmp->vlan) {
632 DP_ERR(edev, "Unicast MAC is already added"
633 " with vlan = %u, vni = %u\n",
634 ucast->vlan, ucast->vni);
638 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
639 RTE_CACHE_LINE_SIZE);
641 DP_ERR(edev, "Did not allocate memory for ucast\n");
644 ether_addr_copy(mac_addr, &u->mac);
645 u->vlan = ucast->vlan;
647 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
650 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
651 if ((memcmp(mac_addr, &tmp->mac,
652 ETHER_ADDR_LEN) == 0) &&
653 ucast->vlan == tmp->vlan &&
654 ucast->vni == tmp->vni)
658 DP_INFO(edev, "Unicast MAC is not found\n");
661 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
669 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
672 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
673 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
674 struct ether_addr *mac_addr;
675 struct qede_mcast_entry *tmp = NULL;
676 struct qede_mcast_entry *m;
678 mac_addr = (struct ether_addr *)mcast->mac;
680 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
681 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
683 "Multicast MAC is already added\n");
687 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
688 RTE_CACHE_LINE_SIZE);
691 "Did not allocate memory for mcast\n");
694 ether_addr_copy(mac_addr, &m->mac);
695 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
698 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
699 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
703 DP_INFO(edev, "Multicast mac is not found\n");
706 SLIST_REMOVE(&qdev->mc_list_head, tmp,
707 qede_mcast_entry, list);
714 static enum _ecore_status_t
715 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
718 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
719 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
720 enum _ecore_status_t rc;
721 struct ecore_filter_mcast mcast;
722 struct qede_mcast_entry *tmp;
726 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
728 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
730 "Mcast filter table limit exceeded, "
731 "Please enable mcast promisc mode\n");
735 rc = qede_mcast_filter(eth_dev, ucast, add);
737 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
738 memset(&mcast, 0, sizeof(mcast));
739 mcast.num_mc_addrs = qdev->num_mc_addr;
740 mcast.opcode = ECORE_FILTER_ADD;
741 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
742 ether_addr_copy(&tmp->mac,
743 (struct ether_addr *)&mcast.mac[j]);
746 rc = ecore_filter_mcast_cmd(edev, &mcast,
747 ECORE_SPQ_MODE_CB, NULL);
749 if (rc != ECORE_SUCCESS) {
750 DP_ERR(edev, "Failed to add multicast filter"
751 " rc = %d, op = %d\n", rc, add);
753 } else { /* Unicast */
755 if (qdev->num_uc_addr >=
756 qdev->dev_info.num_mac_filters) {
758 "Ucast filter table limit exceeded,"
759 " Please enable promisc mode\n");
763 rc = qede_ucast_filter(eth_dev, ucast, add);
765 rc = ecore_filter_ucast_cmd(edev, ucast,
766 ECORE_SPQ_MODE_CB, NULL);
767 if (rc != ECORE_SUCCESS) {
768 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
777 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
778 __rte_unused uint32_t index, __rte_unused uint32_t pool)
780 struct ecore_filter_ucast ucast;
783 qede_set_ucast_cmn_params(&ucast);
784 ucast.type = ECORE_FILTER_MAC;
785 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
786 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
791 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
793 struct qede_dev *qdev = eth_dev->data->dev_private;
794 struct ecore_dev *edev = &qdev->edev;
795 struct ecore_filter_ucast ucast;
797 PMD_INIT_FUNC_TRACE(edev);
799 if (index >= qdev->dev_info.num_mac_filters) {
800 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
801 index, qdev->dev_info.num_mac_filters);
805 qede_set_ucast_cmn_params(&ucast);
806 ucast.opcode = ECORE_FILTER_REMOVE;
807 ucast.type = ECORE_FILTER_MAC;
809 /* Use the index maintained by rte */
810 ether_addr_copy(ð_dev->data->mac_addrs[index],
811 (struct ether_addr *)&ucast.mac);
813 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
817 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
819 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
820 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
822 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
823 mac_addr->addr_bytes)) {
824 DP_ERR(edev, "Setting MAC address is not allowed\n");
825 ether_addr_copy(&qdev->primary_mac,
826 ð_dev->data->mac_addrs[0]);
830 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
833 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
835 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
836 struct ecore_sp_vport_update_params params;
837 struct ecore_hwfn *p_hwfn;
841 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
843 params.update_accept_any_vlan_flg = 1;
844 params.accept_any_vlan = flg;
845 for_each_hwfn(edev, i) {
846 p_hwfn = &edev->hwfns[i];
847 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
848 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
849 ECORE_SPQ_MODE_EBLOCK, NULL);
850 if (rc != ECORE_SUCCESS) {
851 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
856 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
859 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
861 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
862 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
863 struct ecore_sp_vport_update_params params;
864 struct ecore_hwfn *p_hwfn;
868 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
870 params.update_inner_vlan_removal_flg = 1;
871 params.inner_vlan_removal_flg = flg;
872 for_each_hwfn(edev, i) {
873 p_hwfn = &edev->hwfns[i];
874 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
875 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
876 ECORE_SPQ_MODE_EBLOCK, NULL);
877 if (rc != ECORE_SUCCESS) {
878 DP_ERR(edev, "Failed to update vport\n");
883 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
887 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
888 uint16_t vlan_id, int on)
890 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
891 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
892 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
893 struct qede_vlan_entry *tmp = NULL;
894 struct qede_vlan_entry *vlan;
895 struct ecore_filter_ucast ucast;
899 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
900 DP_ERR(edev, "Reached max VLAN filter limit"
901 " enabling accept_any_vlan\n");
902 qede_config_accept_any_vlan(qdev, true);
906 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
907 if (tmp->vid == vlan_id) {
908 DP_ERR(edev, "VLAN %u already configured\n",
914 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
915 RTE_CACHE_LINE_SIZE);
918 DP_ERR(edev, "Did not allocate memory for VLAN\n");
922 qede_set_ucast_cmn_params(&ucast);
923 ucast.opcode = ECORE_FILTER_ADD;
924 ucast.type = ECORE_FILTER_VLAN;
925 ucast.vlan = vlan_id;
926 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
929 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
934 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
935 qdev->configured_vlans++;
936 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
937 vlan_id, qdev->configured_vlans);
940 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
941 if (tmp->vid == vlan_id)
946 if (qdev->configured_vlans == 0) {
948 "No VLAN filters configured yet\n");
952 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
956 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
958 qede_set_ucast_cmn_params(&ucast);
959 ucast.opcode = ECORE_FILTER_REMOVE;
960 ucast.type = ECORE_FILTER_VLAN;
961 ucast.vlan = vlan_id;
962 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
965 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
968 qdev->configured_vlans--;
969 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
970 vlan_id, qdev->configured_vlans);
977 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
979 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
980 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
981 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
983 if (mask & ETH_VLAN_STRIP_MASK) {
984 if (rxmode->hw_vlan_strip)
985 (void)qede_vlan_stripping(eth_dev, 1);
987 (void)qede_vlan_stripping(eth_dev, 0);
990 if (mask & ETH_VLAN_FILTER_MASK) {
991 /* VLAN filtering kicks in when a VLAN is added */
992 if (rxmode->hw_vlan_filter) {
993 qede_vlan_filter_set(eth_dev, 0, 1);
995 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
997 " Please remove existing VLAN filters"
998 " before disabling VLAN filtering\n");
999 /* Signal app that VLAN filtering is still
1002 rxmode->hw_vlan_filter = true;
1004 qede_vlan_filter_set(eth_dev, 0, 0);
1009 if (mask & ETH_VLAN_EXTEND_MASK)
1010 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1011 " and classification is based on outer tag only\n");
1013 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1014 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1017 static void qede_prandom_bytes(uint32_t *buff)
1021 srand((unsigned int)time(NULL));
1022 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1026 int qede_config_rss(struct rte_eth_dev *eth_dev)
1028 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1029 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1030 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1032 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1033 struct rte_eth_rss_reta_entry64 reta_conf[2];
1034 struct rte_eth_rss_conf rss_conf;
1035 uint32_t i, id, pos, q;
1037 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1038 if (!rss_conf.rss_key) {
1039 DP_INFO(edev, "Applying driver default key\n");
1040 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1041 qede_prandom_bytes(&def_rss_key[0]);
1042 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1045 /* Configure RSS hash */
1046 if (qede_rss_hash_update(eth_dev, &rss_conf))
1049 /* Configure default RETA */
1050 memset(reta_conf, 0, sizeof(reta_conf));
1051 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1052 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1054 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1055 id = i / RTE_RETA_GROUP_SIZE;
1056 pos = i % RTE_RETA_GROUP_SIZE;
1057 q = i % QEDE_RSS_COUNT(qdev);
1058 reta_conf[id].reta[pos] = q;
1060 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1061 ECORE_RSS_IND_TABLE_SIZE))
1067 static void qede_fastpath_start(struct ecore_dev *edev)
1069 struct ecore_hwfn *p_hwfn;
1072 for_each_hwfn(edev, i) {
1073 p_hwfn = &edev->hwfns[i];
1074 ecore_hw_start_fastpath(p_hwfn);
1078 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1080 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1081 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1083 PMD_INIT_FUNC_TRACE(edev);
1085 /* Update MTU only if it has changed */
1086 if (qdev->mtu != qdev->new_mtu) {
1087 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1089 qdev->mtu = qdev->new_mtu;
1090 /* If MTU has changed then update TPA too */
1091 if (qdev->enable_lro)
1092 if (qede_enable_tpa(eth_dev, true))
1097 if (qede_start_queues(eth_dev))
1100 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1101 * enabling RSS. Hence RSS configuration is deferred upto this point.
1102 * Also, we would like to retain similar behavior in PF case, so we
1103 * don't do PF/VF specific check here.
1105 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1106 if (qede_config_rss(eth_dev))
1110 if (qede_activate_vport(eth_dev, true))
1113 /* Bring-up the link */
1114 qede_dev_set_link_state(eth_dev, true);
1116 /* Start/resume traffic */
1117 qede_fastpath_start(edev);
1119 DP_INFO(edev, "Device started\n");
1123 DP_ERR(edev, "Device start fails\n");
1124 return -1; /* common error code is < 0 */
1127 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1129 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1130 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1132 PMD_INIT_FUNC_TRACE(edev);
1135 if (qede_activate_vport(eth_dev, false))
1138 if (qdev->enable_lro)
1139 qede_enable_tpa(eth_dev, false);
1141 /* TODO: Do we need disable LRO or RSS */
1143 qede_stop_queues(eth_dev);
1145 /* Disable traffic */
1146 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1148 /* Bring the link down */
1149 qede_dev_set_link_state(eth_dev, false);
1151 DP_INFO(edev, "Device is stopped\n");
1154 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1156 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1157 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1158 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1160 PMD_INIT_FUNC_TRACE(edev);
1162 /* Check requirements for 100G mode */
1163 if (edev->num_hwfns > 1) {
1164 if (eth_dev->data->nb_rx_queues < 2 ||
1165 eth_dev->data->nb_tx_queues < 2) {
1166 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1170 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1171 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1173 "100G mode needs even no. of RX/TX queues\n");
1178 /* Sanity checks and throw warnings */
1179 if (rxmode->enable_scatter)
1180 eth_dev->data->scattered_rx = 1;
1182 if (!rxmode->hw_strip_crc)
1183 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1185 if (!rxmode->hw_ip_checksum)
1186 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1188 if (rxmode->header_split)
1189 DP_INFO(edev, "Header split enable is not supported\n");
1190 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1192 DP_ERR(edev, "Unsupported multi-queue mode\n");
1195 /* Flow director mode check */
1196 if (qede_check_fdir_support(eth_dev))
1199 /* Deallocate resources if held previously. It is needed only if the
1200 * queue count has been changed from previous configuration. If its
1201 * going to change then it means RX/TX queue setup will be called
1202 * again and the fastpath pointers will be reinitialized there.
1204 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1205 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1206 qede_dealloc_fp_resc(eth_dev);
1207 /* Proceed with updated queue count */
1208 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1209 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1210 if (qede_alloc_fp_resc(qdev))
1214 /* VF's MTU has to be set using vport-start where as
1215 * PF's MTU can be updated via vport-update.
1218 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1221 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1225 qdev->mtu = rxmode->max_rx_pkt_len;
1226 qdev->new_mtu = qdev->mtu;
1228 /* Configure TPA parameters */
1229 if (rxmode->enable_lro) {
1230 if (qede_enable_tpa(eth_dev, true))
1232 /* Enable scatter mode for LRO */
1233 if (!rxmode->enable_scatter)
1234 eth_dev->data->scattered_rx = 1;
1236 qdev->enable_lro = rxmode->enable_lro;
1238 /* Enable VLAN offloads by default */
1239 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1240 ETH_VLAN_FILTER_MASK |
1241 ETH_VLAN_EXTEND_MASK);
1243 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1244 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1249 /* Info about HW descriptor ring limitations */
1250 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1251 .nb_max = 0x8000, /* 32K */
1253 .nb_align = 128 /* lowest common multiple */
1256 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1257 .nb_max = 0x8000, /* 32K */
1260 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1261 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1265 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1266 struct rte_eth_dev_info *dev_info)
1268 struct qede_dev *qdev = eth_dev->data->dev_private;
1269 struct ecore_dev *edev = &qdev->edev;
1270 struct qed_link_output link;
1271 uint32_t speed_cap = 0;
1273 PMD_INIT_FUNC_TRACE(edev);
1275 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1276 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1277 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1278 dev_info->rx_desc_lim = qede_rx_desc_lim;
1279 dev_info->tx_desc_lim = qede_tx_desc_lim;
1282 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1283 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1285 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1286 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1287 dev_info->max_tx_queues = dev_info->max_rx_queues;
1289 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1290 dev_info->max_vfs = 0;
1291 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1292 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1293 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1295 dev_info->default_txconf = (struct rte_eth_txconf) {
1296 .txq_flags = QEDE_TXQ_FLAGS,
1299 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
1300 DEV_RX_OFFLOAD_IPV4_CKSUM |
1301 DEV_RX_OFFLOAD_UDP_CKSUM |
1302 DEV_RX_OFFLOAD_TCP_CKSUM |
1303 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1304 DEV_RX_OFFLOAD_TCP_LRO);
1306 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1307 DEV_TX_OFFLOAD_IPV4_CKSUM |
1308 DEV_TX_OFFLOAD_UDP_CKSUM |
1309 DEV_TX_OFFLOAD_TCP_CKSUM |
1310 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1311 DEV_TX_OFFLOAD_TCP_TSO |
1312 DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1314 memset(&link, 0, sizeof(struct qed_link_output));
1315 qdev->ops->common->get_link(edev, &link);
1316 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1317 speed_cap |= ETH_LINK_SPEED_1G;
1318 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1319 speed_cap |= ETH_LINK_SPEED_10G;
1320 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1321 speed_cap |= ETH_LINK_SPEED_25G;
1322 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1323 speed_cap |= ETH_LINK_SPEED_40G;
1324 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1325 speed_cap |= ETH_LINK_SPEED_50G;
1326 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1327 speed_cap |= ETH_LINK_SPEED_100G;
1328 dev_info->speed_capa = speed_cap;
1331 /* return 0 means link status changed, -1 means not changed */
1333 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1335 struct qede_dev *qdev = eth_dev->data->dev_private;
1336 struct ecore_dev *edev = &qdev->edev;
1337 uint16_t link_duplex;
1338 struct qed_link_output link;
1339 struct rte_eth_link *curr = ð_dev->data->dev_link;
1341 memset(&link, 0, sizeof(struct qed_link_output));
1342 qdev->ops->common->get_link(edev, &link);
1345 curr->link_speed = link.speed;
1348 switch (link.duplex) {
1349 case QEDE_DUPLEX_HALF:
1350 link_duplex = ETH_LINK_HALF_DUPLEX;
1352 case QEDE_DUPLEX_FULL:
1353 link_duplex = ETH_LINK_FULL_DUPLEX;
1355 case QEDE_DUPLEX_UNKNOWN:
1359 curr->link_duplex = link_duplex;
1362 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1365 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1366 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1368 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1369 curr->link_speed, curr->link_duplex,
1370 curr->link_autoneg, curr->link_status);
1372 /* return 0 means link status changed, -1 means not changed */
1373 return ((curr->link_status == link.link_up) ? -1 : 0);
1376 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1378 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1379 struct qede_dev *qdev = eth_dev->data->dev_private;
1380 struct ecore_dev *edev = &qdev->edev;
1382 PMD_INIT_FUNC_TRACE(edev);
1385 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1387 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1388 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1390 qed_configure_filter_rx_mode(eth_dev, type);
1393 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1395 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1396 struct qede_dev *qdev = eth_dev->data->dev_private;
1397 struct ecore_dev *edev = &qdev->edev;
1399 PMD_INIT_FUNC_TRACE(edev);
1402 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1403 qed_configure_filter_rx_mode(eth_dev,
1404 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1406 qed_configure_filter_rx_mode(eth_dev,
1407 QED_FILTER_RX_MODE_TYPE_REGULAR);
1410 static void qede_poll_sp_sb_cb(void *param)
1412 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1413 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1414 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1417 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1418 qede_interrupt_action(&edev->hwfns[1]);
1420 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1424 DP_ERR(edev, "Unable to start periodic"
1425 " timer rc %d\n", rc);
1426 assert(false && "Unable to start periodic timer");
1430 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1432 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1433 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1434 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1436 PMD_INIT_FUNC_TRACE(edev);
1438 /* dev_stop() shall cleanup fp resources in hw but without releasing
1439 * dma memories and sw structures so that dev_start() can be called
1440 * by the app without reconfiguration. However, in dev_close() we
1441 * can release all the resources and device can be brought up newly
1443 if (eth_dev->data->dev_started)
1444 qede_dev_stop(eth_dev);
1446 qede_stop_vport(edev);
1447 qede_fdir_dealloc_resc(eth_dev);
1448 qede_dealloc_fp_resc(eth_dev);
1450 eth_dev->data->nb_rx_queues = 0;
1451 eth_dev->data->nb_tx_queues = 0;
1453 qdev->ops->common->slowpath_stop(edev);
1454 qdev->ops->common->remove(edev);
1455 rte_intr_disable(&pci_dev->intr_handle);
1456 rte_intr_callback_unregister(&pci_dev->intr_handle,
1457 qede_interrupt_handler, (void *)eth_dev);
1458 if (edev->num_hwfns > 1)
1459 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1463 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1465 struct qede_dev *qdev = eth_dev->data->dev_private;
1466 struct ecore_dev *edev = &qdev->edev;
1467 struct ecore_eth_stats stats;
1468 unsigned int i = 0, j = 0, qid;
1469 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1470 struct qede_tx_queue *txq;
1472 ecore_get_vport_stats(edev, &stats);
1475 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1476 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1478 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1479 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1481 eth_stats->ierrors = stats.common.rx_crc_errors +
1482 stats.common.rx_align_errors +
1483 stats.common.rx_carrier_errors +
1484 stats.common.rx_oversize_packets +
1485 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1487 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1489 eth_stats->imissed = stats.common.mftag_filter_discards +
1490 stats.common.mac_filter_discards +
1491 stats.common.no_buff_discards +
1492 stats.common.brb_truncates + stats.common.brb_discards;
1495 eth_stats->opackets = stats.common.tx_ucast_pkts +
1496 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1498 eth_stats->obytes = stats.common.tx_ucast_bytes +
1499 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1501 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1504 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1505 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1506 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1507 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1508 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1509 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1510 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1511 "Not all the queue stats will be displayed. Set"
1512 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1513 " appropriately and retry.\n");
1516 eth_stats->q_ipackets[i] =
1518 ((char *)(qdev->fp_array[qid].rxq)) +
1519 offsetof(struct qede_rx_queue,
1521 eth_stats->q_errors[i] =
1523 ((char *)(qdev->fp_array[qid].rxq)) +
1524 offsetof(struct qede_rx_queue,
1527 ((char *)(qdev->fp_array[qid].rxq)) +
1528 offsetof(struct qede_rx_queue,
1531 if (i == rxq_stat_cntrs)
1536 txq = qdev->fp_array[qid].txq;
1537 eth_stats->q_opackets[j] =
1538 *((uint64_t *)(uintptr_t)
1539 (((uint64_t)(uintptr_t)(txq)) +
1540 offsetof(struct qede_tx_queue,
1543 if (j == txq_stat_cntrs)
1549 qede_get_xstats_count(struct qede_dev *qdev) {
1550 if (ECORE_IS_BB(&qdev->edev))
1551 return RTE_DIM(qede_xstats_strings) +
1552 RTE_DIM(qede_bb_xstats_strings) +
1553 (RTE_DIM(qede_rxq_xstats_strings) *
1554 RTE_MIN(QEDE_RSS_COUNT(qdev),
1555 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1557 return RTE_DIM(qede_xstats_strings) +
1558 RTE_DIM(qede_ah_xstats_strings) +
1559 (RTE_DIM(qede_rxq_xstats_strings) *
1560 RTE_MIN(QEDE_RSS_COUNT(qdev),
1561 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1565 qede_get_xstats_names(struct rte_eth_dev *dev,
1566 struct rte_eth_xstat_name *xstats_names,
1567 __rte_unused unsigned int limit)
1569 struct qede_dev *qdev = dev->data->dev_private;
1570 struct ecore_dev *edev = &qdev->edev;
1571 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1572 unsigned int i, qid, stat_idx = 0;
1573 unsigned int rxq_stat_cntrs;
1575 if (xstats_names != NULL) {
1576 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1577 snprintf(xstats_names[stat_idx].name,
1578 sizeof(xstats_names[stat_idx].name),
1580 qede_xstats_strings[i].name);
1584 if (ECORE_IS_BB(edev)) {
1585 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1586 snprintf(xstats_names[stat_idx].name,
1587 sizeof(xstats_names[stat_idx].name),
1589 qede_bb_xstats_strings[i].name);
1593 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1594 snprintf(xstats_names[stat_idx].name,
1595 sizeof(xstats_names[stat_idx].name),
1597 qede_ah_xstats_strings[i].name);
1602 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1603 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1604 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1605 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1606 snprintf(xstats_names[stat_idx].name,
1607 sizeof(xstats_names[stat_idx].name),
1609 qede_rxq_xstats_strings[i].name, qid,
1610 qede_rxq_xstats_strings[i].name + 4);
1620 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1623 struct qede_dev *qdev = dev->data->dev_private;
1624 struct ecore_dev *edev = &qdev->edev;
1625 struct ecore_eth_stats stats;
1626 const unsigned int num = qede_get_xstats_count(qdev);
1627 unsigned int i, qid, stat_idx = 0;
1628 unsigned int rxq_stat_cntrs;
1633 ecore_get_vport_stats(edev, &stats);
1635 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1636 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1637 qede_xstats_strings[i].offset);
1638 xstats[stat_idx].id = stat_idx;
1642 if (ECORE_IS_BB(edev)) {
1643 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1644 xstats[stat_idx].value =
1645 *(uint64_t *)(((char *)&stats) +
1646 qede_bb_xstats_strings[i].offset);
1647 xstats[stat_idx].id = stat_idx;
1651 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1652 xstats[stat_idx].value =
1653 *(uint64_t *)(((char *)&stats) +
1654 qede_ah_xstats_strings[i].offset);
1655 xstats[stat_idx].id = stat_idx;
1660 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1661 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1662 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1664 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1665 xstats[stat_idx].value = *(uint64_t *)(
1666 ((char *)(qdev->fp_array[qid].rxq)) +
1667 qede_rxq_xstats_strings[i].offset);
1668 xstats[stat_idx].id = stat_idx;
1678 qede_reset_xstats(struct rte_eth_dev *dev)
1680 struct qede_dev *qdev = dev->data->dev_private;
1681 struct ecore_dev *edev = &qdev->edev;
1683 ecore_reset_vport_stats(edev);
1686 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1688 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1689 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1690 struct qed_link_params link_params;
1693 DP_INFO(edev, "setting link state %d\n", link_up);
1694 memset(&link_params, 0, sizeof(link_params));
1695 link_params.link_up = link_up;
1696 rc = qdev->ops->common->set_link(edev, &link_params);
1697 if (rc != ECORE_SUCCESS)
1698 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1703 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1705 return qede_dev_set_link_state(eth_dev, true);
1708 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1710 return qede_dev_set_link_state(eth_dev, false);
1713 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1715 struct qede_dev *qdev = eth_dev->data->dev_private;
1716 struct ecore_dev *edev = &qdev->edev;
1718 ecore_reset_vport_stats(edev);
1721 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1723 enum qed_filter_rx_mode_type type =
1724 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1726 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1727 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1729 qed_configure_filter_rx_mode(eth_dev, type);
1732 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1734 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1735 qed_configure_filter_rx_mode(eth_dev,
1736 QED_FILTER_RX_MODE_TYPE_PROMISC);
1738 qed_configure_filter_rx_mode(eth_dev,
1739 QED_FILTER_RX_MODE_TYPE_REGULAR);
1742 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1743 struct rte_eth_fc_conf *fc_conf)
1745 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1746 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1747 struct qed_link_output current_link;
1748 struct qed_link_params params;
1750 memset(¤t_link, 0, sizeof(current_link));
1751 qdev->ops->common->get_link(edev, ¤t_link);
1753 memset(¶ms, 0, sizeof(params));
1754 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1755 if (fc_conf->autoneg) {
1756 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1757 DP_ERR(edev, "Autoneg not supported\n");
1760 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1763 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1764 if (fc_conf->mode == RTE_FC_FULL)
1765 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1766 QED_LINK_PAUSE_RX_ENABLE);
1767 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1768 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1769 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1770 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1772 params.link_up = true;
1773 (void)qdev->ops->common->set_link(edev, ¶ms);
1778 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1779 struct rte_eth_fc_conf *fc_conf)
1781 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1782 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1783 struct qed_link_output current_link;
1785 memset(¤t_link, 0, sizeof(current_link));
1786 qdev->ops->common->get_link(edev, ¤t_link);
1788 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1789 fc_conf->autoneg = true;
1791 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1792 QED_LINK_PAUSE_TX_ENABLE))
1793 fc_conf->mode = RTE_FC_FULL;
1794 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1795 fc_conf->mode = RTE_FC_RX_PAUSE;
1796 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1797 fc_conf->mode = RTE_FC_TX_PAUSE;
1799 fc_conf->mode = RTE_FC_NONE;
1804 static const uint32_t *
1805 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1807 static const uint32_t ptypes[] = {
1813 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1819 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1822 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1823 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1824 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1825 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1826 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1827 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1828 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
1829 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
1832 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1833 struct rte_eth_rss_conf *rss_conf)
1835 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1836 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1837 struct ecore_sp_vport_update_params vport_update_params;
1838 struct ecore_rss_params rss_params;
1839 struct ecore_hwfn *p_hwfn;
1840 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1841 uint64_t hf = rss_conf->rss_hf;
1842 uint8_t len = rss_conf->rss_key_len;
1847 memset(&vport_update_params, 0, sizeof(vport_update_params));
1848 memset(&rss_params, 0, sizeof(rss_params));
1850 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1851 (unsigned long)hf, len, key);
1855 DP_INFO(edev, "Enabling rss\n");
1858 qede_init_rss_caps(&rss_params.rss_caps, hf);
1859 rss_params.update_rss_capabilities = 1;
1863 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1864 DP_ERR(edev, "RSS key length exceeds limit\n");
1867 DP_INFO(edev, "Applying user supplied hash key\n");
1868 rss_params.update_rss_key = 1;
1869 memcpy(&rss_params.rss_key, key, len);
1871 rss_params.rss_enable = 1;
1874 rss_params.update_rss_config = 1;
1875 /* tbl_size has to be set with capabilities */
1876 rss_params.rss_table_size_log = 7;
1877 vport_update_params.vport_id = 0;
1878 /* pass the L2 handles instead of qids */
1879 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1880 idx = qdev->rss_ind_table[i];
1881 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1883 vport_update_params.rss_params = &rss_params;
1885 for_each_hwfn(edev, i) {
1886 p_hwfn = &edev->hwfns[i];
1887 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1888 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1889 ECORE_SPQ_MODE_EBLOCK, NULL);
1891 DP_ERR(edev, "vport-update for RSS failed\n");
1895 qdev->rss_enable = rss_params.rss_enable;
1897 /* Update local structure for hash query */
1898 qdev->rss_conf.rss_hf = hf;
1899 qdev->rss_conf.rss_key_len = len;
1900 if (qdev->rss_enable) {
1901 if (qdev->rss_conf.rss_key == NULL) {
1902 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1903 if (qdev->rss_conf.rss_key == NULL) {
1904 DP_ERR(edev, "No memory to store RSS key\n");
1909 DP_INFO(edev, "Storing RSS key\n");
1910 memcpy(qdev->rss_conf.rss_key, key, len);
1912 } else if (!qdev->rss_enable && len == 0) {
1913 if (qdev->rss_conf.rss_key) {
1914 free(qdev->rss_conf.rss_key);
1915 qdev->rss_conf.rss_key = NULL;
1916 DP_INFO(edev, "Free RSS key\n");
1923 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1924 struct rte_eth_rss_conf *rss_conf)
1926 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1928 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1929 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1931 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1932 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1933 rss_conf->rss_key_len);
1937 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1938 struct ecore_rss_params *rss)
1941 bool rss_mode = 1; /* enable */
1942 struct ecore_queue_cid *cid;
1943 struct ecore_rss_params *t_rss;
1945 /* In regular scenario, we'd simply need to take input handlers.
1946 * But in CMT, we'd have to split the handlers according to the
1947 * engine they were configured on. We'd then have to understand
1948 * whether RSS is really required, since 2-queues on CMT doesn't
1952 /* CMT should be round-robin */
1953 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1954 cid = rss->rss_ind_table[i];
1956 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1961 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
1965 t_rss->update_rss_ind_table = 1;
1966 t_rss->rss_table_size_log = 7;
1967 t_rss->update_rss_config = 1;
1969 /* Make sure RSS is actually required */
1970 for_each_hwfn(edev, fn) {
1971 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
1973 if (rss[fn].rss_ind_table[i] !=
1974 rss[fn].rss_ind_table[0])
1978 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
1980 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1987 t_rss->rss_enable = rss_mode;
1992 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1993 struct rte_eth_rss_reta_entry64 *reta_conf,
1996 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1997 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1998 struct ecore_sp_vport_update_params vport_update_params;
1999 struct ecore_rss_params *params;
2000 struct ecore_hwfn *p_hwfn;
2001 uint16_t i, idx, shift;
2005 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2006 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2011 memset(&vport_update_params, 0, sizeof(vport_update_params));
2012 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2013 RTE_CACHE_LINE_SIZE);
2015 for (i = 0; i < reta_size; i++) {
2016 idx = i / RTE_RETA_GROUP_SIZE;
2017 shift = i % RTE_RETA_GROUP_SIZE;
2018 if (reta_conf[idx].mask & (1ULL << shift)) {
2019 entry = reta_conf[idx].reta[shift];
2020 /* Pass rxq handles to ecore */
2021 params->rss_ind_table[i] =
2022 qdev->fp_array[entry].rxq->handle;
2023 /* Update the local copy for RETA query command */
2024 qdev->rss_ind_table[i] = entry;
2028 params->update_rss_ind_table = 1;
2029 params->rss_table_size_log = 7;
2030 params->update_rss_config = 1;
2032 /* Fix up RETA for CMT mode device */
2033 if (edev->num_hwfns > 1)
2034 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2036 vport_update_params.vport_id = 0;
2037 /* Use the current value of rss_enable */
2038 params->rss_enable = qdev->rss_enable;
2039 vport_update_params.rss_params = params;
2041 for_each_hwfn(edev, i) {
2042 p_hwfn = &edev->hwfns[i];
2043 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2044 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2045 ECORE_SPQ_MODE_EBLOCK, NULL);
2047 DP_ERR(edev, "vport-update for RSS failed\n");
2057 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2058 struct rte_eth_rss_reta_entry64 *reta_conf,
2061 struct qede_dev *qdev = eth_dev->data->dev_private;
2062 struct ecore_dev *edev = &qdev->edev;
2063 uint16_t i, idx, shift;
2066 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2067 DP_ERR(edev, "reta_size %d is not supported\n",
2072 for (i = 0; i < reta_size; i++) {
2073 idx = i / RTE_RETA_GROUP_SIZE;
2074 shift = i % RTE_RETA_GROUP_SIZE;
2075 if (reta_conf[idx].mask & (1ULL << shift)) {
2076 entry = qdev->rss_ind_table[i];
2077 reta_conf[idx].reta[shift] = entry;
2086 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2088 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2089 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2090 struct rte_eth_dev_info dev_info = {0};
2091 struct qede_fastpath *fp;
2092 uint32_t frame_size;
2093 uint16_t rx_buf_size;
2097 PMD_INIT_FUNC_TRACE(edev);
2098 qede_dev_info_get(dev, &dev_info);
2099 frame_size = mtu + QEDE_ETH_OVERHEAD;
2100 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2101 DP_ERR(edev, "MTU %u out of range\n", mtu);
2104 if (!dev->data->scattered_rx &&
2105 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2106 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2107 dev->data->min_rx_buf_size);
2110 /* Temporarily replace I/O functions with dummy ones. It cannot
2111 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2113 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2114 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2118 /* Fix up RX buf size for all queues of the port */
2120 fp = &qdev->fp_array[i];
2121 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2122 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2123 if (dev->data->scattered_rx)
2124 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2126 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2127 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2128 fp->rxq->rx_buf_size = rx_buf_size;
2129 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2131 qede_dev_start(dev);
2132 if (frame_size > ETHER_MAX_LEN)
2133 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2135 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2136 /* update max frame size */
2137 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2139 dev->rx_pkt_burst = qede_recv_pkts;
2140 dev->tx_pkt_burst = qede_xmit_pkts;
2146 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2147 struct rte_eth_udp_tunnel *tunnel_udp,
2150 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2151 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2152 struct ecore_tunnel_info tunn; /* @DPDK */
2153 struct ecore_hwfn *p_hwfn;
2156 PMD_INIT_FUNC_TRACE(edev);
2158 memset(&tunn, 0, sizeof(tunn));
2159 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2160 tunn.vxlan_port.b_update_port = true;
2161 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
2162 QEDE_VXLAN_DEF_PORT;
2163 for_each_hwfn(edev, i) {
2164 p_hwfn = &edev->hwfns[i];
2165 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2166 ECORE_SPQ_MODE_CB, NULL);
2167 if (rc != ECORE_SUCCESS) {
2168 DP_ERR(edev, "Unable to config UDP port %u\n",
2169 tunn.vxlan_port.port);
2179 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2180 struct rte_eth_udp_tunnel *tunnel_udp)
2182 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2186 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2187 struct rte_eth_udp_tunnel *tunnel_udp)
2189 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2192 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2193 uint32_t *clss, char *str)
2196 *clss = MAX_ECORE_TUNN_CLSS;
2198 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2199 if (filter == qede_tunn_types[j].rte_filter_type) {
2200 *type = qede_tunn_types[j].qede_type;
2201 *clss = qede_tunn_types[j].qede_tunn_clss;
2202 strcpy(str, qede_tunn_types[j].string);
2209 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2210 const struct rte_eth_tunnel_filter_conf *conf,
2213 /* Init commmon ucast params first */
2214 qede_set_ucast_cmn_params(ucast);
2216 /* Copy out the required fields based on classification type */
2220 case ECORE_FILTER_VNI:
2221 ucast->vni = conf->tenant_id;
2223 case ECORE_FILTER_INNER_VLAN:
2224 ucast->vlan = conf->inner_vlan;
2226 case ECORE_FILTER_MAC:
2227 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2230 case ECORE_FILTER_INNER_MAC:
2231 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2234 case ECORE_FILTER_MAC_VNI_PAIR:
2235 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2237 ucast->vni = conf->tenant_id;
2239 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2240 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2242 ucast->vni = conf->tenant_id;
2244 case ECORE_FILTER_INNER_PAIR:
2245 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2247 ucast->vlan = conf->inner_vlan;
2253 return ECORE_SUCCESS;
2256 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2257 enum rte_filter_op filter_op,
2258 const struct rte_eth_tunnel_filter_conf *conf)
2260 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2261 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2262 struct ecore_tunnel_info tunn;
2263 struct ecore_hwfn *p_hwfn;
2264 enum ecore_filter_ucast_type type;
2265 enum ecore_tunn_clss clss;
2266 struct ecore_filter_ucast ucast;
2268 uint16_t filter_type;
2271 PMD_INIT_FUNC_TRACE(edev);
2273 filter_type = conf->filter_type | qdev->vxlan_filter_type;
2274 /* First determine if the given filter classification is supported */
2275 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2276 if (clss == MAX_ECORE_TUNN_CLSS) {
2277 DP_ERR(edev, "Wrong filter type\n");
2280 /* Init tunnel ucast params */
2281 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2282 if (rc != ECORE_SUCCESS) {
2283 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2287 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2288 str, filter_op, ucast.type);
2289 switch (filter_op) {
2290 case RTE_ETH_FILTER_ADD:
2291 ucast.opcode = ECORE_FILTER_ADD;
2293 /* Skip MAC/VLAN if filter is based on VNI */
2294 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2295 rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2297 /* Enable accept anyvlan */
2298 qede_config_accept_any_vlan(qdev, true);
2301 rc = qede_ucast_filter(eth_dev, &ucast, 1);
2303 rc = ecore_filter_ucast_cmd(edev, &ucast,
2304 ECORE_SPQ_MODE_CB, NULL);
2307 if (rc != ECORE_SUCCESS)
2310 qdev->vxlan_filter_type = filter_type;
2312 DP_INFO(edev, "Enabling VXLAN tunneling\n");
2313 qede_set_cmn_tunn_param(&tunn, clss, true, true);
2314 for_each_hwfn(edev, i) {
2315 p_hwfn = &edev->hwfns[i];
2316 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
2317 &tunn, ECORE_SPQ_MODE_CB, NULL);
2318 if (rc != ECORE_SUCCESS) {
2319 DP_ERR(edev, "Failed to update tunn_clss %u\n",
2320 tunn.vxlan.tun_cls);
2323 qdev->num_tunn_filters++; /* Filter added successfully */
2325 case RTE_ETH_FILTER_DELETE:
2326 ucast.opcode = ECORE_FILTER_REMOVE;
2328 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2329 rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2331 rc = qede_ucast_filter(eth_dev, &ucast, 0);
2333 rc = ecore_filter_ucast_cmd(edev, &ucast,
2334 ECORE_SPQ_MODE_CB, NULL);
2336 if (rc != ECORE_SUCCESS)
2339 qdev->vxlan_filter_type = filter_type;
2340 qdev->num_tunn_filters--;
2342 /* Disable VXLAN if VXLAN filters become 0 */
2343 if (qdev->num_tunn_filters == 0) {
2344 DP_INFO(edev, "Disabling VXLAN tunneling\n");
2346 /* Use 0 as tunnel mode */
2347 qede_set_cmn_tunn_param(&tunn, clss, false, true);
2348 for_each_hwfn(edev, i) {
2349 p_hwfn = &edev->hwfns[i];
2350 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2351 ECORE_SPQ_MODE_CB, NULL);
2352 if (rc != ECORE_SUCCESS) {
2354 "Failed to update tunn_clss %u\n",
2355 tunn.vxlan.tun_cls);
2362 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2365 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
2370 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2371 enum rte_filter_type filter_type,
2372 enum rte_filter_op filter_op,
2375 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2376 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2377 struct rte_eth_tunnel_filter_conf *filter_conf =
2378 (struct rte_eth_tunnel_filter_conf *)arg;
2380 switch (filter_type) {
2381 case RTE_ETH_FILTER_TUNNEL:
2382 switch (filter_conf->tunnel_type) {
2383 case RTE_TUNNEL_TYPE_VXLAN:
2385 "Packet steering to the specified Rx queue"
2386 " is not supported with VXLAN tunneling");
2387 return(qede_vxlan_tunn_config(eth_dev, filter_op,
2389 /* Place holders for future tunneling support */
2390 case RTE_TUNNEL_TYPE_GENEVE:
2391 case RTE_TUNNEL_TYPE_TEREDO:
2392 case RTE_TUNNEL_TYPE_NVGRE:
2393 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2394 case RTE_L2_TUNNEL_TYPE_E_TAG:
2395 DP_ERR(edev, "Unsupported tunnel type %d\n",
2396 filter_conf->tunnel_type);
2398 case RTE_TUNNEL_TYPE_NONE:
2403 case RTE_ETH_FILTER_FDIR:
2404 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2405 case RTE_ETH_FILTER_NTUPLE:
2406 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2407 case RTE_ETH_FILTER_MACVLAN:
2408 case RTE_ETH_FILTER_ETHERTYPE:
2409 case RTE_ETH_FILTER_FLEXIBLE:
2410 case RTE_ETH_FILTER_SYN:
2411 case RTE_ETH_FILTER_HASH:
2412 case RTE_ETH_FILTER_L2_TUNNEL:
2413 case RTE_ETH_FILTER_MAX:
2415 DP_ERR(edev, "Unsupported filter type %d\n",
2423 static const struct eth_dev_ops qede_eth_dev_ops = {
2424 .dev_configure = qede_dev_configure,
2425 .dev_infos_get = qede_dev_info_get,
2426 .rx_queue_setup = qede_rx_queue_setup,
2427 .rx_queue_release = qede_rx_queue_release,
2428 .tx_queue_setup = qede_tx_queue_setup,
2429 .tx_queue_release = qede_tx_queue_release,
2430 .dev_start = qede_dev_start,
2431 .dev_set_link_up = qede_dev_set_link_up,
2432 .dev_set_link_down = qede_dev_set_link_down,
2433 .link_update = qede_link_update,
2434 .promiscuous_enable = qede_promiscuous_enable,
2435 .promiscuous_disable = qede_promiscuous_disable,
2436 .allmulticast_enable = qede_allmulticast_enable,
2437 .allmulticast_disable = qede_allmulticast_disable,
2438 .dev_stop = qede_dev_stop,
2439 .dev_close = qede_dev_close,
2440 .stats_get = qede_get_stats,
2441 .stats_reset = qede_reset_stats,
2442 .xstats_get = qede_get_xstats,
2443 .xstats_reset = qede_reset_xstats,
2444 .xstats_get_names = qede_get_xstats_names,
2445 .mac_addr_add = qede_mac_addr_add,
2446 .mac_addr_remove = qede_mac_addr_remove,
2447 .mac_addr_set = qede_mac_addr_set,
2448 .vlan_offload_set = qede_vlan_offload_set,
2449 .vlan_filter_set = qede_vlan_filter_set,
2450 .flow_ctrl_set = qede_flow_ctrl_set,
2451 .flow_ctrl_get = qede_flow_ctrl_get,
2452 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2453 .rss_hash_update = qede_rss_hash_update,
2454 .rss_hash_conf_get = qede_rss_hash_conf_get,
2455 .reta_update = qede_rss_reta_update,
2456 .reta_query = qede_rss_reta_query,
2457 .mtu_set = qede_set_mtu,
2458 .filter_ctrl = qede_dev_filter_ctrl,
2459 .udp_tunnel_port_add = qede_udp_dst_port_add,
2460 .udp_tunnel_port_del = qede_udp_dst_port_del,
2463 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2464 .dev_configure = qede_dev_configure,
2465 .dev_infos_get = qede_dev_info_get,
2466 .rx_queue_setup = qede_rx_queue_setup,
2467 .rx_queue_release = qede_rx_queue_release,
2468 .tx_queue_setup = qede_tx_queue_setup,
2469 .tx_queue_release = qede_tx_queue_release,
2470 .dev_start = qede_dev_start,
2471 .dev_set_link_up = qede_dev_set_link_up,
2472 .dev_set_link_down = qede_dev_set_link_down,
2473 .link_update = qede_link_update,
2474 .promiscuous_enable = qede_promiscuous_enable,
2475 .promiscuous_disable = qede_promiscuous_disable,
2476 .allmulticast_enable = qede_allmulticast_enable,
2477 .allmulticast_disable = qede_allmulticast_disable,
2478 .dev_stop = qede_dev_stop,
2479 .dev_close = qede_dev_close,
2480 .stats_get = qede_get_stats,
2481 .stats_reset = qede_reset_stats,
2482 .xstats_get = qede_get_xstats,
2483 .xstats_reset = qede_reset_xstats,
2484 .xstats_get_names = qede_get_xstats_names,
2485 .vlan_offload_set = qede_vlan_offload_set,
2486 .vlan_filter_set = qede_vlan_filter_set,
2487 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2488 .rss_hash_update = qede_rss_hash_update,
2489 .rss_hash_conf_get = qede_rss_hash_conf_get,
2490 .reta_update = qede_rss_reta_update,
2491 .reta_query = qede_rss_reta_query,
2492 .mtu_set = qede_set_mtu,
2495 static void qede_update_pf_params(struct ecore_dev *edev)
2497 struct ecore_pf_params pf_params;
2499 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2500 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2501 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2502 qed_ops->common->update_pf_params(edev, &pf_params);
2505 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2507 struct rte_pci_device *pci_dev;
2508 struct rte_pci_addr pci_addr;
2509 struct qede_dev *adapter;
2510 struct ecore_dev *edev;
2511 struct qed_dev_eth_info dev_info;
2512 struct qed_slowpath_params params;
2513 static bool do_once = true;
2514 uint8_t bulletin_change;
2515 uint8_t vf_mac[ETHER_ADDR_LEN];
2516 uint8_t is_mac_forced;
2518 /* Fix up ecore debug level */
2519 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2520 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2523 /* Extract key data structures */
2524 adapter = eth_dev->data->dev_private;
2525 edev = &adapter->edev;
2526 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2527 pci_addr = pci_dev->addr;
2529 PMD_INIT_FUNC_TRACE(edev);
2531 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2532 pci_addr.bus, pci_addr.devid, pci_addr.function,
2533 eth_dev->data->port_id);
2535 eth_dev->rx_pkt_burst = qede_recv_pkts;
2536 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2537 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2539 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2540 DP_ERR(edev, "Skipping device init from secondary process\n");
2544 rte_eth_copy_pci_info(eth_dev, pci_dev);
2547 edev->vendor_id = pci_dev->id.vendor_id;
2548 edev->device_id = pci_dev->id.device_id;
2550 qed_ops = qed_get_eth_ops();
2552 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2556 DP_INFO(edev, "Starting qede probe\n");
2557 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2560 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2563 qede_update_pf_params(edev);
2564 rte_intr_callback_register(&pci_dev->intr_handle,
2565 qede_interrupt_handler, (void *)eth_dev);
2566 if (rte_intr_enable(&pci_dev->intr_handle)) {
2567 DP_ERR(edev, "rte_intr_enable() failed\n");
2571 /* Start the Slowpath-process */
2572 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2573 params.int_mode = ECORE_INT_MODE_MSIX;
2574 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2575 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2576 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2577 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2578 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2579 QEDE_PMD_DRV_VER_STR_SIZE);
2581 /* For CMT mode device do periodic polling for slowpath events.
2582 * This is required since uio device uses only one MSI-x
2583 * interrupt vector but we need one for each engine.
2585 if (edev->num_hwfns > 1 && IS_PF(edev)) {
2586 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2590 DP_ERR(edev, "Unable to start periodic"
2591 " timer rc %d\n", rc);
2596 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2598 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2599 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2604 rc = qed_ops->fill_dev_info(edev, &dev_info);
2606 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2607 qed_ops->common->slowpath_stop(edev);
2608 qed_ops->common->remove(edev);
2609 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2614 qede_alloc_etherdev(adapter, &dev_info);
2616 adapter->ops->common->set_name(edev, edev->name);
2619 adapter->dev_info.num_mac_filters =
2620 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2623 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2624 (uint32_t *)&adapter->dev_info.num_mac_filters);
2626 /* Allocate memory for storing MAC addr */
2627 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2629 adapter->dev_info.num_mac_filters),
2630 RTE_CACHE_LINE_SIZE);
2632 if (eth_dev->data->mac_addrs == NULL) {
2633 DP_ERR(edev, "Failed to allocate MAC address\n");
2634 qed_ops->common->slowpath_stop(edev);
2635 qed_ops->common->remove(edev);
2636 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2642 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2643 hw_info.hw_mac_addr,
2644 ð_dev->data->mac_addrs[0]);
2645 ether_addr_copy(ð_dev->data->mac_addrs[0],
2646 &adapter->primary_mac);
2648 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2650 if (bulletin_change) {
2652 ecore_vf_bulletin_get_forced_mac(
2653 ECORE_LEADING_HWFN(edev),
2656 if (is_mac_exist && is_mac_forced) {
2657 DP_INFO(edev, "VF macaddr received from PF\n");
2658 ether_addr_copy((struct ether_addr *)&vf_mac,
2659 ð_dev->data->mac_addrs[0]);
2660 ether_addr_copy(ð_dev->data->mac_addrs[0],
2661 &adapter->primary_mac);
2663 DP_ERR(edev, "No VF macaddr assigned\n");
2668 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2671 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2672 qede_print_adapter_info(adapter);
2677 adapter->num_tx_queues = 0;
2678 adapter->num_rx_queues = 0;
2679 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2680 SLIST_INIT(&adapter->vlan_list_head);
2681 SLIST_INIT(&adapter->uc_list_head);
2682 adapter->mtu = ETHER_MTU;
2683 adapter->new_mtu = ETHER_MTU;
2685 if (qede_start_vport(adapter, adapter->mtu))
2688 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2689 adapter->primary_mac.addr_bytes[0],
2690 adapter->primary_mac.addr_bytes[1],
2691 adapter->primary_mac.addr_bytes[2],
2692 adapter->primary_mac.addr_bytes[3],
2693 adapter->primary_mac.addr_bytes[4],
2694 adapter->primary_mac.addr_bytes[5]);
2696 DP_INFO(edev, "Device initialized\n");
2701 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2703 return qede_common_dev_init(eth_dev, 1);
2706 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2708 return qede_common_dev_init(eth_dev, 0);
2711 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2713 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2714 struct qede_dev *qdev = eth_dev->data->dev_private;
2715 struct ecore_dev *edev = &qdev->edev;
2717 PMD_INIT_FUNC_TRACE(edev);
2720 /* only uninitialize in the primary process */
2721 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2724 /* safe to close dev here */
2725 qede_dev_close(eth_dev);
2727 eth_dev->dev_ops = NULL;
2728 eth_dev->rx_pkt_burst = NULL;
2729 eth_dev->tx_pkt_burst = NULL;
2731 if (eth_dev->data->mac_addrs)
2732 rte_free(eth_dev->data->mac_addrs);
2734 eth_dev->data->mac_addrs = NULL;
2739 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2741 return qede_dev_common_uninit(eth_dev);
2744 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2746 return qede_dev_common_uninit(eth_dev);
2749 static const struct rte_pci_id pci_id_qedevf_map[] = {
2750 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2752 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2755 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2758 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2763 static const struct rte_pci_id pci_id_qede_map[] = {
2764 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2766 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2769 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2772 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2775 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2778 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2781 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2784 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2787 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2790 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2793 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2798 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2799 struct rte_pci_device *pci_dev)
2801 return rte_eth_dev_pci_generic_probe(pci_dev,
2802 sizeof(struct qede_dev), qedevf_eth_dev_init);
2805 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2807 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2810 static struct rte_pci_driver rte_qedevf_pmd = {
2811 .id_table = pci_id_qedevf_map,
2812 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2813 .probe = qedevf_eth_dev_pci_probe,
2814 .remove = qedevf_eth_dev_pci_remove,
2817 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2818 struct rte_pci_device *pci_dev)
2820 return rte_eth_dev_pci_generic_probe(pci_dev,
2821 sizeof(struct qede_dev), qede_eth_dev_init);
2824 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2826 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2829 static struct rte_pci_driver rte_qede_pmd = {
2830 .id_table = pci_id_qede_map,
2831 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2832 .probe = qede_eth_dev_pci_probe,
2833 .remove = qede_eth_dev_pci_remove,
2836 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2837 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2838 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2839 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2840 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2841 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");