drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 static int64_t timer_period = 1;
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for_each_rss(qid) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for_each_tss(qid) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 446 {
 447         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 448         struct ecore_sp_vport_start_params params;
 449         struct ecore_hwfn *p_hwfn;
 450         int rc;
 451         int i;
 452
 453         memset(&params, 0, sizeof(params));
 454         params.vport_id = 0;
 455         params.mtu = mtu;
 456         /* @DPDK - Disable FW placement */
 457         params.zero_placement_offset = 1;
 458         for_each_hwfn(edev, i) {
 459                 p_hwfn = &edev->hwfns[i];
 460                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 461                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 462                 rc = ecore_sp_vport_start(p_hwfn, &params);
 463                 if (rc != ECORE_SUCCESS) {
 464                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 465                         return rc;
 466                 }
 467         }
 468         ecore_reset_vport_stats(edev);
 469         if (IS_PF(edev))
 470                 qede_reset_queue_stats(qdev, true);
 471         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 472
 473         return 0;
 474 }
 475
 476 static int
 477 qede_stop_vport(struct ecore_dev *edev)
 478 {
 479         struct ecore_hwfn *p_hwfn;
 480         uint8_t vport_id;
 481         int rc;
 482         int i;
 483
 484         vport_id = 0;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 488                                          vport_id);
 489                 if (rc != ECORE_SUCCESS) {
 490                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 491                         return rc;
 492                 }
 493         }
 494
 495         return 0;
 496 }
 497
 498 /* Activate or deactivate vport via vport-update */
 499 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 500 {
 501         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 502         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 503         struct ecore_sp_vport_update_params params;
 504         struct ecore_hwfn *p_hwfn;
 505         uint8_t i;
 506         int rc = -1;
 507
 508         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 509         params.vport_id = 0;
 510         params.update_vport_active_rx_flg = 1;
 511         params.update_vport_active_tx_flg = 1;
 512         params.vport_active_rx_flg = flg;
 513         params.vport_active_tx_flg = flg;
 514         if (!qdev->enable_tx_switching) {
 515                 if (IS_VF(edev)) {
 516                         params.update_tx_switching_flg = 1;
 517                         params.tx_switching_flg = !flg;
 518                         DP_INFO(edev, "VF tx-switching is disabled\n");
 519                 }
 520         }
 521         for_each_hwfn(edev, i) {
 522                 p_hwfn = &edev->hwfns[i];
 523                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 524                 rc = ecore_sp_vport_update(p_hwfn, &params,
 525                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 526                 if (rc != ECORE_SUCCESS) {
 527                         DP_ERR(edev, "Failed to update vport\n");
 528                         break;
 529                 }
 530         }
 531         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 532
 533         return rc;
 534 }
 535
 536 static void
 537 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 538                            uint16_t mtu, bool enable)
 539 {
 540         /* Enable LRO in split mode */
 541         sge_tpa_params->tpa_ipv4_en_flg = enable;
 542         sge_tpa_params->tpa_ipv6_en_flg = enable;
 543         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 544         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 545         /* set if tpa enable changes */
 546         sge_tpa_params->update_tpa_en_flg = 1;
 547         /* set if tpa parameters should be handled */
 548         sge_tpa_params->update_tpa_param_flg = enable;
 549
 550         sge_tpa_params->max_buffers_per_cqe = 20;
 551         /* Enable TPA in split mode. In this mode each TPA segment
 552          * starts on the new BD, so there is one BD per segment.
 553          */
 554         sge_tpa_params->tpa_pkt_split_flg = 1;
 555         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 556         sge_tpa_params->tpa_gro_consistent_flg = 0;
 557         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 558         sge_tpa_params->tpa_max_size = 0x7FFF;
 559         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 560         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 561 }
 562
 563 /* Enable/disable LRO via vport-update */
 564 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 565 {
 566         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 567         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 568         struct ecore_sp_vport_update_params params;
 569         struct ecore_sge_tpa_params tpa_params;
 570         struct ecore_hwfn *p_hwfn;
 571         int rc;
 572         int i;
 573
 574         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 575         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 576         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 577         params.vport_id = 0;
 578         params.sge_tpa_params = &tpa_params;
 579         for_each_hwfn(edev, i) {
 580                 p_hwfn = &edev->hwfns[i];
 581                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 582                 rc = ecore_sp_vport_update(p_hwfn, &params,
 583                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 584                 if (rc != ECORE_SUCCESS) {
 585                         DP_ERR(edev, "Failed to update LRO\n");
 586                         return -1;
 587                 }
 588         }
 589         qdev->enable_lro = flg;
 590         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 591
 592         return 0;
 593 }
 594
 595 /* Update MTU via vport-update without doing port restart.
 596  * The vport must be deactivated before calling this API.
 597  */
 598 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 599 {
 600         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 601         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 602         struct ecore_sp_vport_update_params params;
 603         struct ecore_hwfn *p_hwfn;
 604         int rc;
 605         int i;
 606
 607         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 608         params.vport_id = 0;
 609         params.mtu = mtu;
 610         params.vport_id = 0;
 611         for_each_hwfn(edev, i) {
 612                 p_hwfn = &edev->hwfns[i];
 613                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 614                 rc = ecore_sp_vport_update(p_hwfn, &params,
 615                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 616                 if (rc != ECORE_SUCCESS) {
 617                         DP_ERR(edev, "Failed to update MTU\n");
 618                         return -1;
 619                 }
 620         }
 621         DP_INFO(edev, "MTU updated to %u\n", mtu);
 622
 623         return 0;
 624 }
 625
 626 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 627 {
 628         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 629         ucast->is_rx_filter = true;
 630         ucast->is_tx_filter = true;
 631         /* ucast->assert_on_error = true; - For debug */
 632 }
 633
 634 static int
 635 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 636                              enum qed_filter_rx_mode_type type)
 637 {
 638         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 639         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 640         struct ecore_filter_accept_flags flags;
 641
 642         memset(&flags, 0, sizeof(flags));
 643
 644         flags.update_rx_mode_config = 1;
 645         flags.update_tx_mode_config = 1;
 646         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 647                 ECORE_ACCEPT_MCAST_MATCHED |
 648                 ECORE_ACCEPT_BCAST;
 649
 650         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 651                 ECORE_ACCEPT_MCAST_MATCHED |
 652                 ECORE_ACCEPT_BCAST;
 653
 654         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 655                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 656                 if (IS_VF(edev)) {
 657                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 658                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 659                 }
 660         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 661                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 662         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 663                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 664                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 665                         ECORE_ACCEPT_MCAST_UNMATCHED;
 666         }
 667
 668         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 669                         ECORE_SPQ_MODE_CB, NULL);
 670 }
 671
 672 static int
 673 qede_tunnel_update(struct qede_dev *qdev,
 674                    struct ecore_tunnel_info *tunn_info)
 675 {
 676         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 677         enum _ecore_status_t rc = ECORE_INVAL;
 678         struct ecore_hwfn *p_hwfn;
 679         struct ecore_ptt *p_ptt;
 680         int i;
 681
 682         for_each_hwfn(edev, i) {
 683                 p_hwfn = &edev->hwfns[i];
 684                 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
 685                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 686                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 687                 if (IS_PF(edev))
 688                         ecore_ptt_release(p_hwfn, p_ptt);
 689
 690                 if (rc != ECORE_SUCCESS)
 691                         break;
 692         }
 693
 694         return rc;
 695 }
 696
 697 static int
 698 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 699                   bool enable)
 700 {
 701         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 702         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 703         enum _ecore_status_t rc = ECORE_INVAL;
 704         struct ecore_tunnel_info tunn;
 705
 706         if (qdev->vxlan.enable == enable)
 707                 return ECORE_SUCCESS;
 708
 709         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 710         tunn.vxlan.b_update_mode = true;
 711         tunn.vxlan.b_mode_enabled = enable;
 712         tunn.b_update_rx_cls = true;
 713         tunn.b_update_tx_cls = true;
 714         tunn.vxlan.tun_cls = clss;
 715
 716         tunn.vxlan_port.b_update_port = true;
 717         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 718
 719         rc = qede_tunnel_update(qdev, &tunn);
 720         if (rc == ECORE_SUCCESS) {
 721                 qdev->vxlan.enable = enable;
 722                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 723                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 724                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 725         } else {
 726                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 727                        tunn.vxlan.tun_cls);
 728         }
 729
 730         return rc;
 731 }
 732
 733 static int
 734 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 735                   bool enable)
 736 {
 737         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 738         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 739         enum _ecore_status_t rc = ECORE_INVAL;
 740         struct ecore_tunnel_info tunn;
 741
 742         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 743         tunn.l2_geneve.b_update_mode = true;
 744         tunn.l2_geneve.b_mode_enabled = enable;
 745         tunn.ip_geneve.b_update_mode = true;
 746         tunn.ip_geneve.b_mode_enabled = enable;
 747         tunn.l2_geneve.tun_cls = clss;
 748         tunn.ip_geneve.tun_cls = clss;
 749         tunn.b_update_rx_cls = true;
 750         tunn.b_update_tx_cls = true;
 751
 752         tunn.geneve_port.b_update_port = true;
 753         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 754
 755         rc = qede_tunnel_update(qdev, &tunn);
 756         if (rc == ECORE_SUCCESS) {
 757                 qdev->geneve.enable = enable;
 758                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 759                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 760                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 761         } else {
 762                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 763                        clss);
 764         }
 765
 766         return rc;
 767 }
 768
 769 static int
 770 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 771                  enum rte_eth_tunnel_type tunn_type, bool enable)
 772 {
 773         int rc = -EINVAL;
 774
 775         switch (tunn_type) {
 776         case RTE_TUNNEL_TYPE_VXLAN:
 777                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 778                 break;
 779         case RTE_TUNNEL_TYPE_GENEVE:
 780                 rc = qede_geneve_enable(eth_dev, clss, enable);
 781                 break;
 782         default:
 783                 rc = -EINVAL;
 784                 break;
 785         }
 786
 787         return rc;
 788 }
 789
 790 static int
 791 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 792                   bool add)
 793 {
 794         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 795         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 796         struct qede_ucast_entry *tmp = NULL;
 797         struct qede_ucast_entry *u;
 798         struct ether_addr *mac_addr;
 799
 800         mac_addr  = (struct ether_addr *)ucast->mac;
 801         if (add) {
 802                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 803                         if ((memcmp(mac_addr, &tmp->mac,
 804                                     ETHER_ADDR_LEN) == 0) &&
 805                              ucast->vni == tmp->vni &&
 806                              ucast->vlan == tmp->vlan) {
 807                                 DP_ERR(edev, "Unicast MAC is already added"
 808                                        " with vlan = %u, vni = %u\n",
 809                                        ucast->vlan,  ucast->vni);
 810                                         return -EEXIST;
 811                         }
 812                 }
 813                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 814                                RTE_CACHE_LINE_SIZE);
 815                 if (!u) {
 816                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 817                         return -ENOMEM;
 818                 }
 819                 ether_addr_copy(mac_addr, &u->mac);
 820                 u->vlan = ucast->vlan;
 821                 u->vni = ucast->vni;
 822                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 823                 qdev->num_uc_addr++;
 824         } else {
 825                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 826                         if ((memcmp(mac_addr, &tmp->mac,
 827                                     ETHER_ADDR_LEN) == 0) &&
 828                             ucast->vlan == tmp->vlan      &&
 829                             ucast->vni == tmp->vni)
 830                         break;
 831                 }
 832                 if (tmp == NULL) {
 833                         DP_INFO(edev, "Unicast MAC is not found\n");
 834                         return -EINVAL;
 835                 }
 836                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 837                 qdev->num_uc_addr--;
 838         }
 839
 840         return 0;
 841 }
 842
 843 static int
 844 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 845                   bool add)
 846 {
 847         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 848         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 849         struct ether_addr *mac_addr;
 850         struct qede_mcast_entry *tmp = NULL;
 851         struct qede_mcast_entry *m;
 852
 853         mac_addr  = (struct ether_addr *)mcast->mac;
 854         if (add) {
 855                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 856                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 857                                 DP_ERR(edev,
 858                                         "Multicast MAC is already added\n");
 859                                 return -EEXIST;
 860                         }
 861                 }
 862                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 863                         RTE_CACHE_LINE_SIZE);
 864                 if (!m) {
 865                         DP_ERR(edev,
 866                                 "Did not allocate memory for mcast\n");
 867                         return -ENOMEM;
 868                 }
 869                 ether_addr_copy(mac_addr, &m->mac);
 870                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 871                 qdev->num_mc_addr++;
 872         } else {
 873                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 874                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 875                                 break;
 876                 }
 877                 if (tmp == NULL) {
 878                         DP_INFO(edev, "Multicast mac is not found\n");
 879                         return -EINVAL;
 880                 }
 881                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 882                              qede_mcast_entry, list);
 883                 qdev->num_mc_addr--;
 884         }
 885
 886         return 0;
 887 }
 888
 889 static enum _ecore_status_t
 890 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 891                  bool add)
 892 {
 893         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 894         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 895         enum _ecore_status_t rc;
 896         struct ecore_filter_mcast mcast;
 897         struct qede_mcast_entry *tmp;
 898         uint16_t j = 0;
 899
 900         /* Multicast */
 901         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 902                 if (add) {
 903                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 904                                 DP_ERR(edev,
 905                                        "Mcast filter table limit exceeded, "
 906                                        "Please enable mcast promisc mode\n");
 907                                 return -ECORE_INVAL;
 908                         }
 909                 }
 910                 rc = qede_mcast_filter(eth_dev, ucast, add);
 911                 if (rc == 0) {
 912                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 913                         memset(&mcast, 0, sizeof(mcast));
 914                         mcast.num_mc_addrs = qdev->num_mc_addr;
 915                         mcast.opcode = ECORE_FILTER_ADD;
 916                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 917                                 ether_addr_copy(&tmp->mac,
 918                                         (struct ether_addr *)&mcast.mac[j]);
 919                                 j++;
 920                         }
 921                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 922                                                     ECORE_SPQ_MODE_CB, NULL);
 923                 }
 924                 if (rc != ECORE_SUCCESS) {
 925                         DP_ERR(edev, "Failed to add multicast filter"
 926                                " rc = %d, op = %d\n", rc, add);
 927                 }
 928         } else { /* Unicast */
 929                 if (add) {
 930                         if (qdev->num_uc_addr >=
 931                             qdev->dev_info.num_mac_filters) {
 932                                 DP_ERR(edev,
 933                                        "Ucast filter table limit exceeded,"
 934                                        " Please enable promisc mode\n");
 935                                 return -ECORE_INVAL;
 936                         }
 937                 }
 938                 rc = qede_ucast_filter(eth_dev, ucast, add);
 939                 if (rc == 0)
 940                         rc = ecore_filter_ucast_cmd(edev, ucast,
 941                                                     ECORE_SPQ_MODE_CB, NULL);
 942                 if (rc != ECORE_SUCCESS) {
 943                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 944                                rc, add);
 945                 }
 946         }
 947
 948         return rc;
 949 }
 950
 951 static int
 952 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 953                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 954 {
 955         struct ecore_filter_ucast ucast;
 956         int re;
 957
 958         qede_set_ucast_cmn_params(&ucast);
 959         ucast.type = ECORE_FILTER_MAC;
 960         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 961         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 962         return re;
 963 }
 964
 965 static void
 966 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 967 {
 968         struct qede_dev *qdev = eth_dev->data->dev_private;
 969         struct ecore_dev *edev = &qdev->edev;
 970         struct ecore_filter_ucast ucast;
 971
 972         PMD_INIT_FUNC_TRACE(edev);
 973
 974         if (index >= qdev->dev_info.num_mac_filters) {
 975                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 976                        index, qdev->dev_info.num_mac_filters);
 977                 return;
 978         }
 979
 980         qede_set_ucast_cmn_params(&ucast);
 981         ucast.opcode = ECORE_FILTER_REMOVE;
 982         ucast.type = ECORE_FILTER_MAC;
 983
 984         /* Use the index maintained by rte */
 985         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 986                         (struct ether_addr *)&ucast.mac);
 987
 988         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 989 }
 990
 991 static void
 992 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 993 {
 994         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 995         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 996
 997         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 998                                                mac_addr->addr_bytes)) {
 999                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1000                 ether_addr_copy(&qdev->primary_mac,
1001                                 &eth_dev->data->mac_addrs[0]);
1002                 return;
1003         }
1004
1005         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1006 }
1007
1008 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1009 {
1010         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1011         struct ecore_sp_vport_update_params params;
1012         struct ecore_hwfn *p_hwfn;
1013         uint8_t i;
1014         int rc;
1015
1016         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1017         params.vport_id = 0;
1018         params.update_accept_any_vlan_flg = 1;
1019         params.accept_any_vlan = flg;
1020         for_each_hwfn(edev, i) {
1021                 p_hwfn = &edev->hwfns[i];
1022                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1023                 rc = ecore_sp_vport_update(p_hwfn, &params,
1024                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1025                 if (rc != ECORE_SUCCESS) {
1026                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1027                         return;
1028                 }
1029         }
1030
1031         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1032 }
1033
1034 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1035 {
1036         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1037         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1038         struct ecore_sp_vport_update_params params;
1039         struct ecore_hwfn *p_hwfn;
1040         uint8_t i;
1041         int rc;
1042
1043         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1044         params.vport_id = 0;
1045         params.update_inner_vlan_removal_flg = 1;
1046         params.inner_vlan_removal_flg = flg;
1047         for_each_hwfn(edev, i) {
1048                 p_hwfn = &edev->hwfns[i];
1049                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1050                 rc = ecore_sp_vport_update(p_hwfn, &params,
1051                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1052                 if (rc != ECORE_SUCCESS) {
1053                         DP_ERR(edev, "Failed to update vport\n");
1054                         return -1;
1055                 }
1056         }
1057
1058         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1059         return 0;
1060 }
1061
1062 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1063                                 uint16_t vlan_id, int on)
1064 {
1065         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1066         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1067         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1068         struct qede_vlan_entry *tmp = NULL;
1069         struct qede_vlan_entry *vlan;
1070         struct ecore_filter_ucast ucast;
1071         int rc;
1072
1073         if (on) {
1074                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1075                         DP_ERR(edev, "Reached max VLAN filter limit"
1076                                       " enabling accept_any_vlan\n");
1077                         qede_config_accept_any_vlan(qdev, true);
1078                         return 0;
1079                 }
1080
1081                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1082                         if (tmp->vid == vlan_id) {
1083                                 DP_ERR(edev, "VLAN %u already configured\n",
1084                                        vlan_id);
1085                                 return -EEXIST;
1086                         }
1087                 }
1088
1089                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1090                                   RTE_CACHE_LINE_SIZE);
1091
1092                 if (!vlan) {
1093                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1094                         return -ENOMEM;
1095                 }
1096
1097                 qede_set_ucast_cmn_params(&ucast);
1098                 ucast.opcode = ECORE_FILTER_ADD;
1099                 ucast.type = ECORE_FILTER_VLAN;
1100                 ucast.vlan = vlan_id;
1101                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1102                                             NULL);
1103                 if (rc != 0) {
1104                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1105                                rc);
1106                         rte_free(vlan);
1107                 } else {
1108                         vlan->vid = vlan_id;
1109                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1110                         qdev->configured_vlans++;
1111                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1112                                 vlan_id, qdev->configured_vlans);
1113                 }
1114         } else {
1115                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1116                         if (tmp->vid == vlan_id)
1117                                 break;
1118                 }
1119
1120                 if (!tmp) {
1121                         if (qdev->configured_vlans == 0) {
1122                                 DP_INFO(edev,
1123                                         "No VLAN filters configured yet\n");
1124                                 return 0;
1125                         }
1126
1127                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1128                         return -EINVAL;
1129                 }
1130
1131                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1132
1133                 qede_set_ucast_cmn_params(&ucast);
1134                 ucast.opcode = ECORE_FILTER_REMOVE;
1135                 ucast.type = ECORE_FILTER_VLAN;
1136                 ucast.vlan = vlan_id;
1137                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1138                                             NULL);
1139                 if (rc != 0) {
1140                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1141                                vlan_id, rc);
1142                 } else {
1143                         qdev->configured_vlans--;
1144                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1145                                 vlan_id, qdev->configured_vlans);
1146                 }
1147         }
1148
1149         return rc;
1150 }
1151
1152 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1153 {
1154         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1155         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1156         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1157
1158         if (mask & ETH_VLAN_STRIP_MASK) {
1159                 if (rxmode->hw_vlan_strip)
1160                         (void)qede_vlan_stripping(eth_dev, 1);
1161                 else
1162                         (void)qede_vlan_stripping(eth_dev, 0);
1163         }
1164
1165         if (mask & ETH_VLAN_FILTER_MASK) {
1166                 /* VLAN filtering kicks in when a VLAN is added */
1167                 if (rxmode->hw_vlan_filter) {
1168                         qede_vlan_filter_set(eth_dev, 0, 1);
1169                 } else {
1170                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1171                                 DP_ERR(edev,
1172                                   " Please remove existing VLAN filters"
1173                                   " before disabling VLAN filtering\n");
1174                                 /* Signal app that VLAN filtering is still
1175                                  * enabled
1176                                  */
1177                                 rxmode->hw_vlan_filter = true;
1178                         } else {
1179                                 qede_vlan_filter_set(eth_dev, 0, 0);
1180                         }
1181                 }
1182         }
1183
1184         if (mask & ETH_VLAN_EXTEND_MASK)
1185                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1186                         " and classification is based on outer tag only\n");
1187
1188         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1189                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1190
1191         return 0;
1192 }
1193
1194 static void qede_prandom_bytes(uint32_t *buff)
1195 {
1196         uint8_t i;
1197
1198         srand((unsigned int)time(NULL));
1199         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1200                 buff[i] = rand();
1201 }
1202
1203 int qede_config_rss(struct rte_eth_dev *eth_dev)
1204 {
1205         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1206         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1207         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1208         struct rte_eth_rss_reta_entry64 reta_conf[2];
1209         struct rte_eth_rss_conf rss_conf;
1210         uint32_t i, id, pos, q;
1211
1212         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1213         if (!rss_conf.rss_key) {
1214                 DP_INFO(edev, "Applying driver default key\n");
1215                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1216                 qede_prandom_bytes(&def_rss_key[0]);
1217                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1218         }
1219
1220         /* Configure RSS hash */
1221         if (qede_rss_hash_update(eth_dev, &rss_conf))
1222                 return -EINVAL;
1223
1224         /* Configure default RETA */
1225         memset(reta_conf, 0, sizeof(reta_conf));
1226         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1227                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1228
1229         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1230                 id = i / RTE_RETA_GROUP_SIZE;
1231                 pos = i % RTE_RETA_GROUP_SIZE;
1232                 q = i % QEDE_RSS_COUNT(qdev);
1233                 reta_conf[id].reta[pos] = q;
1234         }
1235         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1236                                  ECORE_RSS_IND_TABLE_SIZE))
1237                 return -EINVAL;
1238
1239         return 0;
1240 }
1241
1242 static void qede_fastpath_start(struct ecore_dev *edev)
1243 {
1244         struct ecore_hwfn *p_hwfn;
1245         int i;
1246
1247         for_each_hwfn(edev, i) {
1248                 p_hwfn = &edev->hwfns[i];
1249                 ecore_hw_start_fastpath(p_hwfn);
1250         }
1251 }
1252
1253 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1254 {
1255         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1256         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1257         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1258
1259         PMD_INIT_FUNC_TRACE(edev);
1260
1261         /* Update MTU only if it has changed */
1262         if (qdev->mtu != qdev->new_mtu) {
1263                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1264                         goto err;
1265                 qdev->mtu = qdev->new_mtu;
1266         }
1267
1268         /* Configure TPA parameters */
1269         if (rxmode->enable_lro) {
1270                 if (qede_enable_tpa(eth_dev, true))
1271                         return -EINVAL;
1272                 /* Enable scatter mode for LRO */
1273                 if (!rxmode->enable_scatter)
1274                         eth_dev->data->scattered_rx = 1;
1275         }
1276
1277         /* Start queues */
1278         if (qede_start_queues(eth_dev))
1279                 goto err;
1280
1281         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1282          * enabling RSS. Hence RSS configuration is deferred upto this point.
1283          * Also, we would like to retain similar behavior in PF case, so we
1284          * don't do PF/VF specific check here.
1285          */
1286         if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1287                 if (qede_config_rss(eth_dev))
1288                         goto err;
1289
1290         /* Enable vport*/
1291         if (qede_activate_vport(eth_dev, true))
1292                 goto err;
1293
1294         /* Bring-up the link */
1295         qede_dev_set_link_state(eth_dev, true);
1296
1297         /* Update link status */
1298         qede_link_update(eth_dev, 0);
1299
1300         /* Start/resume traffic */
1301         qede_fastpath_start(edev);
1302
1303         DP_INFO(edev, "Device started\n");
1304
1305         return 0;
1306 err:
1307         DP_ERR(edev, "Device start fails\n");
1308         return -1; /* common error code is < 0 */
1309 }
1310
1311 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1312 {
1313         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1314         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1315
1316         PMD_INIT_FUNC_TRACE(edev);
1317
1318         /* Disable vport */
1319         if (qede_activate_vport(eth_dev, false))
1320                 return;
1321
1322         if (qdev->enable_lro)
1323                 qede_enable_tpa(eth_dev, false);
1324
1325         /* Stop queues */
1326         qede_stop_queues(eth_dev);
1327
1328         /* Disable traffic */
1329         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1330
1331         /* Bring the link down */
1332         qede_dev_set_link_state(eth_dev, false);
1333
1334         DP_INFO(edev, "Device is stopped\n");
1335 }
1336
1337 #define QEDE_TX_SWITCHING               "vf_txswitch"
1338
1339 const char *valid_args[] = {
1340         QEDE_TX_SWITCHING,
1341         NULL,
1342 };
1343
1344 static int qede_args_check(const char *key, const char *val, void *opaque)
1345 {
1346         unsigned long tmp;
1347         int ret = 0;
1348         struct rte_eth_dev *eth_dev = opaque;
1349         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1350         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1351
1352         errno = 0;
1353         tmp = strtoul(val, NULL, 0);
1354         if (errno) {
1355                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1356                 return errno;
1357         }
1358
1359         if (strcmp(QEDE_TX_SWITCHING, key) == 0)
1360                 qdev->enable_tx_switching = !!tmp;
1361
1362         return ret;
1363 }
1364
1365 static int qede_args(struct rte_eth_dev *eth_dev)
1366 {
1367         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1368         struct rte_kvargs *kvlist;
1369         struct rte_devargs *devargs;
1370         int ret;
1371         int i;
1372
1373         devargs = pci_dev->device.devargs;
1374         if (!devargs)
1375                 return 0; /* return success */
1376
1377         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1378         if (kvlist == NULL)
1379                 return -EINVAL;
1380
1381          /* Process parameters. */
1382         for (i = 0; (valid_args[i] != NULL); ++i) {
1383                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1384                         ret = rte_kvargs_process(kvlist, valid_args[i],
1385                                                  qede_args_check, eth_dev);
1386                         if (ret != ECORE_SUCCESS) {
1387                                 rte_kvargs_free(kvlist);
1388                                 return ret;
1389                         }
1390                 }
1391         }
1392         rte_kvargs_free(kvlist);
1393
1394         return 0;
1395 }
1396
1397 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1398 {
1399         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1400         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1401         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1402         int ret;
1403
1404         PMD_INIT_FUNC_TRACE(edev);
1405
1406         /* Check requirements for 100G mode */
1407         if (ECORE_IS_CMT(edev)) {
1408                 if (eth_dev->data->nb_rx_queues < 2 ||
1409                                 eth_dev->data->nb_tx_queues < 2) {
1410                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1411                         return -EINVAL;
1412                 }
1413
1414                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1415                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1416                         DP_ERR(edev,
1417                                         "100G mode needs even no. of RX/TX queues\n");
1418                         return -EINVAL;
1419                 }
1420         }
1421
1422         /* We need to have min 1 RX queue.There is no min check in
1423          * rte_eth_dev_configure(), so we are checking it here.
1424          */
1425         if (eth_dev->data->nb_rx_queues == 0) {
1426                 DP_ERR(edev, "Minimum one RX queue is required\n");
1427                 return -EINVAL;
1428         }
1429
1430         /* Enable Tx switching by default */
1431         qdev->enable_tx_switching = 1;
1432
1433         /* Parse devargs and fix up rxmode */
1434         if (qede_args(eth_dev))
1435                 return -ENOTSUP;
1436
1437         /* Sanity checks and throw warnings */
1438         if (rxmode->enable_scatter)
1439                 eth_dev->data->scattered_rx = 1;
1440
1441         if (!rxmode->hw_strip_crc)
1442                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1443
1444         if (!rxmode->hw_ip_checksum)
1445                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1446                                 "in hw\n");
1447         if (rxmode->header_split)
1448                 DP_INFO(edev, "Header split enable is not supported\n");
1449         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1450                                 ETH_MQ_RX_RSS)) {
1451                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1452                 return -ENOTSUP;
1453         }
1454         /* Flow director mode check */
1455         if (qede_check_fdir_support(eth_dev))
1456                 return -ENOTSUP;
1457
1458         /* Deallocate resources if held previously. It is needed only if the
1459          * queue count has been changed from previous configuration. If its
1460          * going to change then it means RX/TX queue setup will be called
1461          * again and the fastpath pointers will be reinitialized there.
1462          */
1463         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1464             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1465                 qede_dealloc_fp_resc(eth_dev);
1466                 /* Proceed with updated queue count */
1467                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1468                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1469                 if (qede_alloc_fp_resc(qdev))
1470                         return -ENOMEM;
1471         }
1472
1473         /* If jumbo enabled adjust MTU */
1474         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
1475                 eth_dev->data->mtu =
1476                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1477                                 ETHER_HDR_LEN - ETHER_CRC_LEN;
1478
1479         /* VF's MTU has to be set using vport-start where as
1480          * PF's MTU can be updated via vport-update.
1481          */
1482         if (IS_VF(edev)) {
1483                 if (qede_start_vport(qdev, eth_dev->data->mtu))
1484                         return -1;
1485         } else {
1486                 if (qede_update_mtu(eth_dev, eth_dev->data->mtu))
1487                         return -1;
1488         }
1489
1490         qdev->mtu = eth_dev->data->mtu;
1491         qdev->new_mtu = qdev->mtu;
1492
1493         /* Enable VLAN offloads by default */
1494         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1495                         ETH_VLAN_FILTER_MASK |
1496                         ETH_VLAN_EXTEND_MASK);
1497         if (ret)
1498                 return ret;
1499
1500         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1501                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1502
1503         return 0;
1504 }
1505
1506 /* Info about HW descriptor ring limitations */
1507 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1508         .nb_max = 0x8000, /* 32K */
1509         .nb_min = 128,
1510         .nb_align = 128 /* lowest common multiple */
1511 };
1512
1513 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1514         .nb_max = 0x8000, /* 32K */
1515         .nb_min = 256,
1516         .nb_align = 256,
1517         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1518         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1519 };
1520
1521 static void
1522 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1523                   struct rte_eth_dev_info *dev_info)
1524 {
1525         struct qede_dev *qdev = eth_dev->data->dev_private;
1526         struct ecore_dev *edev = &qdev->edev;
1527         struct qed_link_output link;
1528         uint32_t speed_cap = 0;
1529
1530         PMD_INIT_FUNC_TRACE(edev);
1531
1532         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1533         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1534         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1535         dev_info->rx_desc_lim = qede_rx_desc_lim;
1536         dev_info->tx_desc_lim = qede_tx_desc_lim;
1537
1538         if (IS_PF(edev))
1539                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1540                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1541         else
1542                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1543                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1544         dev_info->max_tx_queues = dev_info->max_rx_queues;
1545
1546         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1547         dev_info->max_vfs = 0;
1548         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1549         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1550         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1551
1552         dev_info->default_txconf = (struct rte_eth_txconf) {
1553                 .txq_flags = QEDE_TXQ_FLAGS,
1554         };
1555
1556         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1557                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1558                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1559                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1560                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1561                                      DEV_RX_OFFLOAD_TCP_LRO);
1562
1563         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1564                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1565                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1566                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1567                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1568                                      DEV_TX_OFFLOAD_TCP_TSO |
1569                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1570                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1571
1572         memset(&link, 0, sizeof(struct qed_link_output));
1573         qdev->ops->common->get_link(edev, &link);
1574         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1575                 speed_cap |= ETH_LINK_SPEED_1G;
1576         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1577                 speed_cap |= ETH_LINK_SPEED_10G;
1578         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1579                 speed_cap |= ETH_LINK_SPEED_25G;
1580         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1581                 speed_cap |= ETH_LINK_SPEED_40G;
1582         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1583                 speed_cap |= ETH_LINK_SPEED_50G;
1584         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1585                 speed_cap |= ETH_LINK_SPEED_100G;
1586         dev_info->speed_capa = speed_cap;
1587 }
1588
1589 /* return 0 means link status changed, -1 means not changed */
1590 int
1591 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1592 {
1593         struct qede_dev *qdev = eth_dev->data->dev_private;
1594         struct ecore_dev *edev = &qdev->edev;
1595         uint16_t link_duplex;
1596         struct qed_link_output link;
1597         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1598
1599         memset(&link, 0, sizeof(struct qed_link_output));
1600         qdev->ops->common->get_link(edev, &link);
1601
1602         /* Link Speed */
1603         curr->link_speed = link.speed;
1604
1605         /* Link Mode */
1606         switch (link.duplex) {
1607         case QEDE_DUPLEX_HALF:
1608                 link_duplex = ETH_LINK_HALF_DUPLEX;
1609                 break;
1610         case QEDE_DUPLEX_FULL:
1611                 link_duplex = ETH_LINK_FULL_DUPLEX;
1612                 break;
1613         case QEDE_DUPLEX_UNKNOWN:
1614         default:
1615                 link_duplex = -1;
1616         }
1617         curr->link_duplex = link_duplex;
1618
1619         /* Link Status */
1620         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1621
1622         /* AN */
1623         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1624                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1625
1626         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1627                 curr->link_speed, curr->link_duplex,
1628                 curr->link_autoneg, curr->link_status);
1629
1630         /* return 0 means link status changed, -1 means not changed */
1631         return ((curr->link_status == link.link_up) ? -1 : 0);
1632 }
1633
1634 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1635 {
1636 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1637         struct qede_dev *qdev = eth_dev->data->dev_private;
1638         struct ecore_dev *edev = &qdev->edev;
1639
1640         PMD_INIT_FUNC_TRACE(edev);
1641 #endif
1642
1643         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1644
1645         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1646                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1647
1648         qed_configure_filter_rx_mode(eth_dev, type);
1649 }
1650
1651 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1652 {
1653 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1654         struct qede_dev *qdev = eth_dev->data->dev_private;
1655         struct ecore_dev *edev = &qdev->edev;
1656
1657         PMD_INIT_FUNC_TRACE(edev);
1658 #endif
1659
1660         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1661                 qed_configure_filter_rx_mode(eth_dev,
1662                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1663         else
1664                 qed_configure_filter_rx_mode(eth_dev,
1665                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1666 }
1667
1668 static void qede_poll_sp_sb_cb(void *param)
1669 {
1670         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1671         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1672         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1673         int rc;
1674
1675         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1676         qede_interrupt_action(&edev->hwfns[1]);
1677
1678         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1679                                qede_poll_sp_sb_cb,
1680                                (void *)eth_dev);
1681         if (rc != 0) {
1682                 DP_ERR(edev, "Unable to start periodic"
1683                              " timer rc %d\n", rc);
1684                 assert(false && "Unable to start periodic timer");
1685         }
1686 }
1687
1688 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1689 {
1690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1691         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1692         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1693
1694         PMD_INIT_FUNC_TRACE(edev);
1695
1696         /* dev_stop() shall cleanup fp resources in hw but without releasing
1697          * dma memories and sw structures so that dev_start() can be called
1698          * by the app without reconfiguration. However, in dev_close() we
1699          * can release all the resources and device can be brought up newly
1700          */
1701         if (eth_dev->data->dev_started)
1702                 qede_dev_stop(eth_dev);
1703
1704         qede_stop_vport(edev);
1705         qede_fdir_dealloc_resc(eth_dev);
1706         qede_dealloc_fp_resc(eth_dev);
1707
1708         eth_dev->data->nb_rx_queues = 0;
1709         eth_dev->data->nb_tx_queues = 0;
1710
1711         qdev->ops->common->slowpath_stop(edev);
1712         qdev->ops->common->remove(edev);
1713         rte_intr_disable(&pci_dev->intr_handle);
1714         rte_intr_callback_unregister(&pci_dev->intr_handle,
1715                                      qede_interrupt_handler, (void *)eth_dev);
1716         if (ECORE_IS_CMT(edev))
1717                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1718 }
1719
1720 static int
1721 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1722 {
1723         struct qede_dev *qdev = eth_dev->data->dev_private;
1724         struct ecore_dev *edev = &qdev->edev;
1725         struct ecore_eth_stats stats;
1726         unsigned int i = 0, j = 0, qid;
1727         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1728         struct qede_tx_queue *txq;
1729
1730         ecore_get_vport_stats(edev, &stats);
1731
1732         /* RX Stats */
1733         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1734             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1735
1736         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1737             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1738
1739         eth_stats->ierrors = stats.common.rx_crc_errors +
1740             stats.common.rx_align_errors +
1741             stats.common.rx_carrier_errors +
1742             stats.common.rx_oversize_packets +
1743             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1744
1745         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1746
1747         eth_stats->imissed = stats.common.mftag_filter_discards +
1748             stats.common.mac_filter_discards +
1749             stats.common.no_buff_discards +
1750             stats.common.brb_truncates + stats.common.brb_discards;
1751
1752         /* TX stats */
1753         eth_stats->opackets = stats.common.tx_ucast_pkts +
1754             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1755
1756         eth_stats->obytes = stats.common.tx_ucast_bytes +
1757             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1758
1759         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1760
1761         /* Queue stats */
1762         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1763                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1764         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1765                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1766         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1767             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1768                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1769                        "Not all the queue stats will be displayed. Set"
1770                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1771                        " appropriately and retry.\n");
1772
1773         for_each_rss(qid) {
1774                 eth_stats->q_ipackets[i] =
1775                         *(uint64_t *)(
1776                                 ((char *)(qdev->fp_array[qid].rxq)) +
1777                                 offsetof(struct qede_rx_queue,
1778                                 rcv_pkts));
1779                 eth_stats->q_errors[i] =
1780                         *(uint64_t *)(
1781                                 ((char *)(qdev->fp_array[qid].rxq)) +
1782                                 offsetof(struct qede_rx_queue,
1783                                 rx_hw_errors)) +
1784                         *(uint64_t *)(
1785                                 ((char *)(qdev->fp_array[qid].rxq)) +
1786                                 offsetof(struct qede_rx_queue,
1787                                 rx_alloc_errors));
1788                 i++;
1789                 if (i == rxq_stat_cntrs)
1790                         break;
1791         }
1792
1793         for_each_tss(qid) {
1794                 txq = qdev->fp_array[qid].txq;
1795                 eth_stats->q_opackets[j] =
1796                         *((uint64_t *)(uintptr_t)
1797                                 (((uint64_t)(uintptr_t)(txq)) +
1798                                  offsetof(struct qede_tx_queue,
1799                                           xmit_pkts)));
1800                 j++;
1801                 if (j == txq_stat_cntrs)
1802                         break;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static unsigned
1809 qede_get_xstats_count(struct qede_dev *qdev) {
1810         if (ECORE_IS_BB(&qdev->edev))
1811                 return RTE_DIM(qede_xstats_strings) +
1812                        RTE_DIM(qede_bb_xstats_strings) +
1813                        (RTE_DIM(qede_rxq_xstats_strings) *
1814                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1815                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1816         else
1817                 return RTE_DIM(qede_xstats_strings) +
1818                        RTE_DIM(qede_ah_xstats_strings) +
1819                        (RTE_DIM(qede_rxq_xstats_strings) *
1820                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1821                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1822 }
1823
1824 static int
1825 qede_get_xstats_names(struct rte_eth_dev *dev,
1826                       struct rte_eth_xstat_name *xstats_names,
1827                       __rte_unused unsigned int limit)
1828 {
1829         struct qede_dev *qdev = dev->data->dev_private;
1830         struct ecore_dev *edev = &qdev->edev;
1831         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1832         unsigned int i, qid, stat_idx = 0;
1833         unsigned int rxq_stat_cntrs;
1834
1835         if (xstats_names != NULL) {
1836                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1837                         snprintf(xstats_names[stat_idx].name,
1838                                 sizeof(xstats_names[stat_idx].name),
1839                                 "%s",
1840                                 qede_xstats_strings[i].name);
1841                         stat_idx++;
1842                 }
1843
1844                 if (ECORE_IS_BB(edev)) {
1845                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1846                                 snprintf(xstats_names[stat_idx].name,
1847                                         sizeof(xstats_names[stat_idx].name),
1848                                         "%s",
1849                                         qede_bb_xstats_strings[i].name);
1850                                 stat_idx++;
1851                         }
1852                 } else {
1853                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1854                                 snprintf(xstats_names[stat_idx].name,
1855                                         sizeof(xstats_names[stat_idx].name),
1856                                         "%s",
1857                                         qede_ah_xstats_strings[i].name);
1858                                 stat_idx++;
1859                         }
1860                 }
1861
1862                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1863                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1864                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1865                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1866                                 snprintf(xstats_names[stat_idx].name,
1867                                         sizeof(xstats_names[stat_idx].name),
1868                                         "%.4s%d%s",
1869                                         qede_rxq_xstats_strings[i].name, qid,
1870                                         qede_rxq_xstats_strings[i].name + 4);
1871                                 stat_idx++;
1872                         }
1873                 }
1874         }
1875
1876         return stat_cnt;
1877 }
1878
1879 static int
1880 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1881                 unsigned int n)
1882 {
1883         struct qede_dev *qdev = dev->data->dev_private;
1884         struct ecore_dev *edev = &qdev->edev;
1885         struct ecore_eth_stats stats;
1886         const unsigned int num = qede_get_xstats_count(qdev);
1887         unsigned int i, qid, stat_idx = 0;
1888         unsigned int rxq_stat_cntrs;
1889
1890         if (n < num)
1891                 return num;
1892
1893         ecore_get_vport_stats(edev, &stats);
1894
1895         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1896                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1897                                              qede_xstats_strings[i].offset);
1898                 xstats[stat_idx].id = stat_idx;
1899                 stat_idx++;
1900         }
1901
1902         if (ECORE_IS_BB(edev)) {
1903                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1904                         xstats[stat_idx].value =
1905                                         *(uint64_t *)(((char *)&stats) +
1906                                         qede_bb_xstats_strings[i].offset);
1907                         xstats[stat_idx].id = stat_idx;
1908                         stat_idx++;
1909                 }
1910         } else {
1911                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1912                         xstats[stat_idx].value =
1913                                         *(uint64_t *)(((char *)&stats) +
1914                                         qede_ah_xstats_strings[i].offset);
1915                         xstats[stat_idx].id = stat_idx;
1916                         stat_idx++;
1917                 }
1918         }
1919
1920         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1921                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1922         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1923                 for_each_rss(qid) {
1924                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1925                                 xstats[stat_idx].value = *(uint64_t *)(
1926                                         ((char *)(qdev->fp_array[qid].rxq)) +
1927                                          qede_rxq_xstats_strings[i].offset);
1928                                 xstats[stat_idx].id = stat_idx;
1929                                 stat_idx++;
1930                         }
1931                 }
1932         }
1933
1934         return stat_idx;
1935 }
1936
1937 static void
1938 qede_reset_xstats(struct rte_eth_dev *dev)
1939 {
1940         struct qede_dev *qdev = dev->data->dev_private;
1941         struct ecore_dev *edev = &qdev->edev;
1942
1943         ecore_reset_vport_stats(edev);
1944         qede_reset_queue_stats(qdev, true);
1945 }
1946
1947 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1948 {
1949         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1950         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1951         struct qed_link_params link_params;
1952         int rc;
1953
1954         DP_INFO(edev, "setting link state %d\n", link_up);
1955         memset(&link_params, 0, sizeof(link_params));
1956         link_params.link_up = link_up;
1957         rc = qdev->ops->common->set_link(edev, &link_params);
1958         if (rc != ECORE_SUCCESS)
1959                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1960
1961         return rc;
1962 }
1963
1964 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1965 {
1966         return qede_dev_set_link_state(eth_dev, true);
1967 }
1968
1969 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1970 {
1971         return qede_dev_set_link_state(eth_dev, false);
1972 }
1973
1974 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1975 {
1976         struct qede_dev *qdev = eth_dev->data->dev_private;
1977         struct ecore_dev *edev = &qdev->edev;
1978
1979         ecore_reset_vport_stats(edev);
1980         qede_reset_queue_stats(qdev, false);
1981 }
1982
1983 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1984 {
1985         enum qed_filter_rx_mode_type type =
1986             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1987
1988         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1989                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1990
1991         qed_configure_filter_rx_mode(eth_dev, type);
1992 }
1993
1994 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1995 {
1996         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1997                 qed_configure_filter_rx_mode(eth_dev,
1998                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1999         else
2000                 qed_configure_filter_rx_mode(eth_dev,
2001                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2002 }
2003
2004 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2005                               struct rte_eth_fc_conf *fc_conf)
2006 {
2007         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2008         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2009         struct qed_link_output current_link;
2010         struct qed_link_params params;
2011
2012         memset(&current_link, 0, sizeof(current_link));
2013         qdev->ops->common->get_link(edev, &current_link);
2014
2015         memset(&params, 0, sizeof(params));
2016         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2017         if (fc_conf->autoneg) {
2018                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2019                         DP_ERR(edev, "Autoneg not supported\n");
2020                         return -EINVAL;
2021                 }
2022                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2023         }
2024
2025         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2026         if (fc_conf->mode == RTE_FC_FULL)
2027                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2028                                         QED_LINK_PAUSE_RX_ENABLE);
2029         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2030                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2031         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2032                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2033
2034         params.link_up = true;
2035         (void)qdev->ops->common->set_link(edev, &params);
2036
2037         return 0;
2038 }
2039
2040 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2041                               struct rte_eth_fc_conf *fc_conf)
2042 {
2043         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2044         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2045         struct qed_link_output current_link;
2046
2047         memset(&current_link, 0, sizeof(current_link));
2048         qdev->ops->common->get_link(edev, &current_link);
2049
2050         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2051                 fc_conf->autoneg = true;
2052
2053         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2054                                          QED_LINK_PAUSE_TX_ENABLE))
2055                 fc_conf->mode = RTE_FC_FULL;
2056         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2057                 fc_conf->mode = RTE_FC_RX_PAUSE;
2058         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2059                 fc_conf->mode = RTE_FC_TX_PAUSE;
2060         else
2061                 fc_conf->mode = RTE_FC_NONE;
2062
2063         return 0;
2064 }
2065
2066 static const uint32_t *
2067 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2068 {
2069         static const uint32_t ptypes[] = {
2070                 RTE_PTYPE_L2_ETHER,
2071                 RTE_PTYPE_L2_ETHER_VLAN,
2072                 RTE_PTYPE_L3_IPV4,
2073                 RTE_PTYPE_L3_IPV6,
2074                 RTE_PTYPE_L4_TCP,
2075                 RTE_PTYPE_L4_UDP,
2076                 RTE_PTYPE_TUNNEL_VXLAN,
2077                 RTE_PTYPE_L4_FRAG,
2078                 RTE_PTYPE_TUNNEL_GENEVE,
2079                 /* Inner */
2080                 RTE_PTYPE_INNER_L2_ETHER,
2081                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2082                 RTE_PTYPE_INNER_L3_IPV4,
2083                 RTE_PTYPE_INNER_L3_IPV6,
2084                 RTE_PTYPE_INNER_L4_TCP,
2085                 RTE_PTYPE_INNER_L4_UDP,
2086                 RTE_PTYPE_INNER_L4_FRAG,
2087                 RTE_PTYPE_UNKNOWN
2088         };
2089
2090         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2091                 return ptypes;
2092
2093         return NULL;
2094 }
2095
2096 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2097 {
2098         *rss_caps = 0;
2099         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2100         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2101         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2102         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2103         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2104         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2105         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2106         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2107 }
2108
2109 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2110                          struct rte_eth_rss_conf *rss_conf)
2111 {
2112         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2113         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2114         struct ecore_sp_vport_update_params vport_update_params;
2115         struct ecore_rss_params rss_params;
2116         struct ecore_hwfn *p_hwfn;
2117         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2118         uint64_t hf = rss_conf->rss_hf;
2119         uint8_t len = rss_conf->rss_key_len;
2120         uint8_t idx;
2121         uint8_t i;
2122         int rc;
2123
2124         memset(&vport_update_params, 0, sizeof(vport_update_params));
2125         memset(&rss_params, 0, sizeof(rss_params));
2126
2127         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2128                 (unsigned long)hf, len, key);
2129
2130         if (hf != 0) {
2131                 /* Enabling RSS */
2132                 DP_INFO(edev, "Enabling rss\n");
2133
2134                 /* RSS caps */
2135                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2136                 rss_params.update_rss_capabilities = 1;
2137
2138                 /* RSS hash key */
2139                 if (key) {
2140                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2141                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2142                                 return -EINVAL;
2143                         }
2144                         DP_INFO(edev, "Applying user supplied hash key\n");
2145                         rss_params.update_rss_key = 1;
2146                         memcpy(&rss_params.rss_key, key, len);
2147                 }
2148                 rss_params.rss_enable = 1;
2149         }
2150
2151         rss_params.update_rss_config = 1;
2152         /* tbl_size has to be set with capabilities */
2153         rss_params.rss_table_size_log = 7;
2154         vport_update_params.vport_id = 0;
2155         /* pass the L2 handles instead of qids */
2156         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2157                 idx = qdev->rss_ind_table[i];
2158                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2159         }
2160         vport_update_params.rss_params = &rss_params;
2161
2162         for_each_hwfn(edev, i) {
2163                 p_hwfn = &edev->hwfns[i];
2164                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2165                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2166                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2167                 if (rc) {
2168                         DP_ERR(edev, "vport-update for RSS failed\n");
2169                         return rc;
2170                 }
2171         }
2172         qdev->rss_enable = rss_params.rss_enable;
2173
2174         /* Update local structure for hash query */
2175         qdev->rss_conf.rss_hf = hf;
2176         qdev->rss_conf.rss_key_len = len;
2177         if (qdev->rss_enable) {
2178                 if  (qdev->rss_conf.rss_key == NULL) {
2179                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2180                         if (qdev->rss_conf.rss_key == NULL) {
2181                                 DP_ERR(edev, "No memory to store RSS key\n");
2182                                 return -ENOMEM;
2183                         }
2184                 }
2185                 if (key && len) {
2186                         DP_INFO(edev, "Storing RSS key\n");
2187                         memcpy(qdev->rss_conf.rss_key, key, len);
2188                 }
2189         } else if (!qdev->rss_enable && len == 0) {
2190                 if (qdev->rss_conf.rss_key) {
2191                         free(qdev->rss_conf.rss_key);
2192                         qdev->rss_conf.rss_key = NULL;
2193                         DP_INFO(edev, "Free RSS key\n");
2194                 }
2195         }
2196
2197         return 0;
2198 }
2199
2200 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2201                            struct rte_eth_rss_conf *rss_conf)
2202 {
2203         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2204
2205         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2206         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2207
2208         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2209                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2210                        rss_conf->rss_key_len);
2211         return 0;
2212 }
2213
2214 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2215                                     struct ecore_rss_params *rss)
2216 {
2217         int i, fn;
2218         bool rss_mode = 1; /* enable */
2219         struct ecore_queue_cid *cid;
2220         struct ecore_rss_params *t_rss;
2221
2222         /* In regular scenario, we'd simply need to take input handlers.
2223          * But in CMT, we'd have to split the handlers according to the
2224          * engine they were configured on. We'd then have to understand
2225          * whether RSS is really required, since 2-queues on CMT doesn't
2226          * require RSS.
2227          */
2228
2229         /* CMT should be round-robin */
2230         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2231                 cid = rss->rss_ind_table[i];
2232
2233                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2234                         t_rss = &rss[0];
2235                 else
2236                         t_rss = &rss[1];
2237
2238                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2239         }
2240
2241         t_rss = &rss[1];
2242         t_rss->update_rss_ind_table = 1;
2243         t_rss->rss_table_size_log = 7;
2244         t_rss->update_rss_config = 1;
2245
2246         /* Make sure RSS is actually required */
2247         for_each_hwfn(edev, fn) {
2248                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2249                      i++) {
2250                         if (rss[fn].rss_ind_table[i] !=
2251                             rss[fn].rss_ind_table[0])
2252                                 break;
2253                 }
2254
2255                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2256                         DP_INFO(edev,
2257                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2258                         rss_mode = 0;
2259                         goto out;
2260                 }
2261         }
2262
2263 out:
2264         t_rss->rss_enable = rss_mode;
2265
2266         return rss_mode;
2267 }
2268
2269 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2270                          struct rte_eth_rss_reta_entry64 *reta_conf,
2271                          uint16_t reta_size)
2272 {
2273         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2274         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2275         struct ecore_sp_vport_update_params vport_update_params;
2276         struct ecore_rss_params *params;
2277         struct ecore_hwfn *p_hwfn;
2278         uint16_t i, idx, shift;
2279         uint8_t entry;
2280         int rc = 0;
2281
2282         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2283                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2284                        reta_size);
2285                 return -EINVAL;
2286         }
2287
2288         memset(&vport_update_params, 0, sizeof(vport_update_params));
2289         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2290                              RTE_CACHE_LINE_SIZE);
2291         if (params == NULL) {
2292                 DP_ERR(edev, "failed to allocate memory\n");
2293                 return -ENOMEM;
2294         }
2295
2296         for (i = 0; i < reta_size; i++) {
2297                 idx = i / RTE_RETA_GROUP_SIZE;
2298                 shift = i % RTE_RETA_GROUP_SIZE;
2299                 if (reta_conf[idx].mask & (1ULL << shift)) {
2300                         entry = reta_conf[idx].reta[shift];
2301                         /* Pass rxq handles to ecore */
2302                         params->rss_ind_table[i] =
2303                                         qdev->fp_array[entry].rxq->handle;
2304                         /* Update the local copy for RETA query command */
2305                         qdev->rss_ind_table[i] = entry;
2306                 }
2307         }
2308
2309         params->update_rss_ind_table = 1;
2310         params->rss_table_size_log = 7;
2311         params->update_rss_config = 1;
2312
2313         /* Fix up RETA for CMT mode device */
2314         if (ECORE_IS_CMT(edev))
2315                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2316                                                             params);
2317         vport_update_params.vport_id = 0;
2318         /* Use the current value of rss_enable */
2319         params->rss_enable = qdev->rss_enable;
2320         vport_update_params.rss_params = params;
2321
2322         for_each_hwfn(edev, i) {
2323                 p_hwfn = &edev->hwfns[i];
2324                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2325                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2326                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2327                 if (rc) {
2328                         DP_ERR(edev, "vport-update for RSS failed\n");
2329                         goto out;
2330                 }
2331         }
2332
2333 out:
2334         rte_free(params);
2335         return rc;
2336 }
2337
2338 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2339                                struct rte_eth_rss_reta_entry64 *reta_conf,
2340                                uint16_t reta_size)
2341 {
2342         struct qede_dev *qdev = eth_dev->data->dev_private;
2343         struct ecore_dev *edev = &qdev->edev;
2344         uint16_t i, idx, shift;
2345         uint8_t entry;
2346
2347         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2348                 DP_ERR(edev, "reta_size %d is not supported\n",
2349                        reta_size);
2350                 return -EINVAL;
2351         }
2352
2353         for (i = 0; i < reta_size; i++) {
2354                 idx = i / RTE_RETA_GROUP_SIZE;
2355                 shift = i % RTE_RETA_GROUP_SIZE;
2356                 if (reta_conf[idx].mask & (1ULL << shift)) {
2357                         entry = qdev->rss_ind_table[i];
2358                         reta_conf[idx].reta[shift] = entry;
2359                 }
2360         }
2361
2362         return 0;
2363 }
2364
2365
2366
2367 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2368 {
2369         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2370         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2371         struct rte_eth_dev_info dev_info = {0};
2372         struct qede_fastpath *fp;
2373         uint32_t max_rx_pkt_len;
2374         uint32_t frame_size;
2375         uint16_t rx_buf_size;
2376         uint16_t bufsz;
2377         bool restart = false;
2378         int i;
2379
2380         PMD_INIT_FUNC_TRACE(edev);
2381         if (IS_VF(edev))
2382                 return -ENOTSUP;
2383         qede_dev_info_get(dev, &dev_info);
2384         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2385         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2386         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2387                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2388                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2389                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2390                 return -EINVAL;
2391         }
2392         if (!dev->data->scattered_rx &&
2393             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2394                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2395                         dev->data->min_rx_buf_size);
2396                 return -EINVAL;
2397         }
2398         /* Temporarily replace I/O functions with dummy ones. It cannot
2399          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2400          */
2401         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2402         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2403         if (dev->data->dev_started) {
2404                 dev->data->dev_started = 0;
2405                 qede_dev_stop(dev);
2406                 restart = true;
2407         }
2408         rte_delay_ms(1000);
2409         qdev->new_mtu = mtu;
2410         /* Fix up RX buf size for all queues of the port */
2411         for_each_rss(i) {
2412                 fp = &qdev->fp_array[i];
2413                 if (fp->rxq != NULL) {
2414                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2415                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2416                         if (dev->data->scattered_rx)
2417                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2418                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2419                         else
2420                                 rx_buf_size = frame_size;
2421                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2422                         fp->rxq->rx_buf_size = rx_buf_size;
2423                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2424                 }
2425         }
2426         if (max_rx_pkt_len > ETHER_MAX_LEN)
2427                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2428         else
2429                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2430         if (!dev->data->dev_started && restart) {
2431                 qede_dev_start(dev);
2432                 dev->data->dev_started = 1;
2433         }
2434         /* update max frame size */
2435         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2436         /* Reassign back */
2437         dev->rx_pkt_burst = qede_recv_pkts;
2438         dev->tx_pkt_burst = qede_xmit_pkts;
2439
2440         return 0;
2441 }
2442
2443 static int
2444 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2445                       struct rte_eth_udp_tunnel *tunnel_udp)
2446 {
2447         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2448         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2449         struct ecore_tunnel_info tunn; /* @DPDK */
2450         uint16_t udp_port;
2451         int rc;
2452
2453         PMD_INIT_FUNC_TRACE(edev);
2454
2455         memset(&tunn, 0, sizeof(tunn));
2456
2457         switch (tunnel_udp->prot_type) {
2458         case RTE_TUNNEL_TYPE_VXLAN:
2459                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2460                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2461                                 tunnel_udp->udp_port);
2462                         return ECORE_INVAL;
2463                 }
2464                 udp_port = 0;
2465
2466                 tunn.vxlan_port.b_update_port = true;
2467                 tunn.vxlan_port.port = udp_port;
2468
2469                 rc = qede_tunnel_update(qdev, &tunn);
2470                 if (rc != ECORE_SUCCESS) {
2471                         DP_ERR(edev, "Unable to config UDP port %u\n",
2472                                tunn.vxlan_port.port);
2473                         return rc;
2474                 }
2475
2476                 qdev->vxlan.udp_port = udp_port;
2477                 /* If the request is to delete UDP port and if the number of
2478                  * VXLAN filters have reached 0 then VxLAN offload can be be
2479                  * disabled.
2480                  */
2481                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2482                         return qede_vxlan_enable(eth_dev,
2483                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2484
2485                 break;
2486
2487         case RTE_TUNNEL_TYPE_GENEVE:
2488                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2489                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2490                                 tunnel_udp->udp_port);
2491                         return ECORE_INVAL;
2492                 }
2493
2494                 udp_port = 0;
2495
2496                 tunn.geneve_port.b_update_port = true;
2497                 tunn.geneve_port.port = udp_port;
2498
2499                 rc = qede_tunnel_update(qdev, &tunn);
2500                 if (rc != ECORE_SUCCESS) {
2501                         DP_ERR(edev, "Unable to config UDP port %u\n",
2502                                tunn.vxlan_port.port);
2503                         return rc;
2504                 }
2505
2506                 qdev->vxlan.udp_port = udp_port;
2507                 /* If the request is to delete UDP port and if the number of
2508                  * GENEVE filters have reached 0 then GENEVE offload can be be
2509                  * disabled.
2510                  */
2511                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2512                         return qede_geneve_enable(eth_dev,
2513                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2514
2515                 break;
2516
2517         default:
2518                 return ECORE_INVAL;
2519         }
2520
2521         return 0;
2522
2523 }
2524 static int
2525 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2526                       struct rte_eth_udp_tunnel *tunnel_udp)
2527 {
2528         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2529         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2530         struct ecore_tunnel_info tunn; /* @DPDK */
2531         uint16_t udp_port;
2532         int rc;
2533
2534         PMD_INIT_FUNC_TRACE(edev);
2535
2536         memset(&tunn, 0, sizeof(tunn));
2537
2538         switch (tunnel_udp->prot_type) {
2539         case RTE_TUNNEL_TYPE_VXLAN:
2540                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2541                         DP_INFO(edev,
2542                                 "UDP port %u for VXLAN was already configured\n",
2543                                 tunnel_udp->udp_port);
2544                         return ECORE_SUCCESS;
2545                 }
2546
2547                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2548                  * it was not enabled while adding VXLAN filter before UDP port
2549                  * update.
2550                  */
2551                 if (!qdev->vxlan.enable) {
2552                         rc = qede_vxlan_enable(eth_dev,
2553                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2554                         if (rc != ECORE_SUCCESS) {
2555                                 DP_ERR(edev, "Failed to enable VXLAN "
2556                                         "prior to updating UDP port\n");
2557                                 return rc;
2558                         }
2559                 }
2560                 udp_port = tunnel_udp->udp_port;
2561
2562                 tunn.vxlan_port.b_update_port = true;
2563                 tunn.vxlan_port.port = udp_port;
2564
2565                 rc = qede_tunnel_update(qdev, &tunn);
2566                 if (rc != ECORE_SUCCESS) {
2567                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2568                                udp_port);
2569                         return rc;
2570                 }
2571
2572                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2573
2574                 qdev->vxlan.udp_port = udp_port;
2575                 break;
2576
2577         case RTE_TUNNEL_TYPE_GENEVE:
2578                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2579                         DP_INFO(edev,
2580                                 "UDP port %u for GENEVE was already configured\n",
2581                                 tunnel_udp->udp_port);
2582                         return ECORE_SUCCESS;
2583                 }
2584
2585                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2586                  * it was not enabled while adding GENEVE filter before UDP port
2587                  * update.
2588                  */
2589                 if (!qdev->geneve.enable) {
2590                         rc = qede_geneve_enable(eth_dev,
2591                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2592                         if (rc != ECORE_SUCCESS) {
2593                                 DP_ERR(edev, "Failed to enable GENEVE "
2594                                         "prior to updating UDP port\n");
2595                                 return rc;
2596                         }
2597                 }
2598                 udp_port = tunnel_udp->udp_port;
2599
2600                 tunn.geneve_port.b_update_port = true;
2601                 tunn.geneve_port.port = udp_port;
2602
2603                 rc = qede_tunnel_update(qdev, &tunn);
2604                 if (rc != ECORE_SUCCESS) {
2605                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2606                                udp_port);
2607                         return rc;
2608                 }
2609
2610                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2611
2612                 qdev->geneve.udp_port = udp_port;
2613                 break;
2614
2615         default:
2616                 return ECORE_INVAL;
2617         }
2618
2619         return 0;
2620 }
2621
2622 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2623                                        uint32_t *clss, char *str)
2624 {
2625         uint16_t j;
2626         *clss = MAX_ECORE_TUNN_CLSS;
2627
2628         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2629                 if (filter == qede_tunn_types[j].rte_filter_type) {
2630                         *type = qede_tunn_types[j].qede_type;
2631                         *clss = qede_tunn_types[j].qede_tunn_clss;
2632                         strcpy(str, qede_tunn_types[j].string);
2633                         return;
2634                 }
2635         }
2636 }
2637
2638 static int
2639 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2640                               const struct rte_eth_tunnel_filter_conf *conf,
2641                               uint32_t type)
2642 {
2643         /* Init commmon ucast params first */
2644         qede_set_ucast_cmn_params(ucast);
2645
2646         /* Copy out the required fields based on classification type */
2647         ucast->type = type;
2648
2649         switch (type) {
2650         case ECORE_FILTER_VNI:
2651                 ucast->vni = conf->tenant_id;
2652         break;
2653         case ECORE_FILTER_INNER_VLAN:
2654                 ucast->vlan = conf->inner_vlan;
2655         break;
2656         case ECORE_FILTER_MAC:
2657                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2658                        ETHER_ADDR_LEN);
2659         break;
2660         case ECORE_FILTER_INNER_MAC:
2661                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2662                        ETHER_ADDR_LEN);
2663         break;
2664         case ECORE_FILTER_MAC_VNI_PAIR:
2665                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2666                         ETHER_ADDR_LEN);
2667                 ucast->vni = conf->tenant_id;
2668         break;
2669         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2670                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2671                         ETHER_ADDR_LEN);
2672                 ucast->vni = conf->tenant_id;
2673         break;
2674         case ECORE_FILTER_INNER_PAIR:
2675                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2676                         ETHER_ADDR_LEN);
2677                 ucast->vlan = conf->inner_vlan;
2678         break;
2679         default:
2680                 return -EINVAL;
2681         }
2682
2683         return ECORE_SUCCESS;
2684 }
2685
2686 static int
2687 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2688                          const struct rte_eth_tunnel_filter_conf *conf,
2689                          __attribute__((unused)) enum rte_filter_op filter_op,
2690                          enum ecore_tunn_clss *clss,
2691                          bool add)
2692 {
2693         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2694         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2695         struct ecore_filter_ucast ucast = {0};
2696         enum ecore_filter_ucast_type type;
2697         uint16_t filter_type = 0;
2698         char str[80];
2699         int rc;
2700
2701         filter_type = conf->filter_type;
2702         /* Determine if the given filter classification is supported */
2703         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2704         if (*clss == MAX_ECORE_TUNN_CLSS) {
2705                 DP_ERR(edev, "Unsupported filter type\n");
2706                 return -EINVAL;
2707         }
2708         /* Init tunnel ucast params */
2709         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2710         if (rc != ECORE_SUCCESS) {
2711                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2712                 conf->filter_type);
2713                 return rc;
2714         }
2715         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2716                 str, filter_op, ucast.type);
2717
2718         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2719
2720         /* Skip MAC/VLAN if filter is based on VNI */
2721         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2722                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2723                 if ((rc == 0) && add) {
2724                         /* Enable accept anyvlan */
2725                         qede_config_accept_any_vlan(qdev, true);
2726                 }
2727         } else {
2728                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2729                 if (rc == 0)
2730                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2731                                             ECORE_SPQ_MODE_CB, NULL);
2732         }
2733
2734         return rc;
2735 }
2736
2737 static int
2738 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2739                         enum rte_filter_op filter_op,
2740                         const struct rte_eth_tunnel_filter_conf *conf)
2741 {
2742         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2743         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2744         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2745         bool add;
2746         int rc;
2747
2748         PMD_INIT_FUNC_TRACE(edev);
2749
2750         switch (filter_op) {
2751         case RTE_ETH_FILTER_ADD:
2752                 add = true;
2753                 break;
2754         case RTE_ETH_FILTER_DELETE:
2755                 add = false;
2756                 break;
2757         default:
2758                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2759                 return -EINVAL;
2760         }
2761
2762         if (IS_VF(edev))
2763                 return qede_tunn_enable(eth_dev,
2764                                         ECORE_TUNN_CLSS_MAC_VLAN,
2765                                         conf->tunnel_type, add);
2766
2767         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2768         if (rc != ECORE_SUCCESS)
2769                 return rc;
2770
2771         if (add) {
2772                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2773                         qdev->vxlan.num_filters++;
2774                         qdev->vxlan.filter_type = conf->filter_type;
2775                 } else { /* GENEVE */
2776                         qdev->geneve.num_filters++;
2777                         qdev->geneve.filter_type = conf->filter_type;
2778                 }
2779
2780                 if (!qdev->vxlan.enable || !qdev->geneve.enable)
2781                         return qede_tunn_enable(eth_dev, clss,
2782                                                 conf->tunnel_type,
2783                                                 true);
2784         } else {
2785                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2786                         qdev->vxlan.num_filters--;
2787                 else /*GENEVE*/
2788                         qdev->geneve.num_filters--;
2789
2790                 /* Disable VXLAN if VXLAN filters become 0 */
2791                 if ((qdev->vxlan.num_filters == 0) ||
2792                     (qdev->geneve.num_filters == 0))
2793                         return qede_tunn_enable(eth_dev, clss,
2794                                                 conf->tunnel_type,
2795                                                 false);
2796         }
2797
2798         return 0;
2799 }
2800
2801 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2802                          enum rte_filter_type filter_type,
2803                          enum rte_filter_op filter_op,
2804                          void *arg)
2805 {
2806         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2807         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2808         struct rte_eth_tunnel_filter_conf *filter_conf =
2809                         (struct rte_eth_tunnel_filter_conf *)arg;
2810
2811         switch (filter_type) {
2812         case RTE_ETH_FILTER_TUNNEL:
2813                 switch (filter_conf->tunnel_type) {
2814                 case RTE_TUNNEL_TYPE_VXLAN:
2815                 case RTE_TUNNEL_TYPE_GENEVE:
2816                         DP_INFO(edev,
2817                                 "Packet steering to the specified Rx queue"
2818                                 " is not supported with UDP tunneling");
2819                         return(qede_tunn_filter_config(eth_dev, filter_op,
2820                                                       filter_conf));
2821                 /* Place holders for future tunneling support */
2822                 case RTE_TUNNEL_TYPE_TEREDO:
2823                 case RTE_TUNNEL_TYPE_NVGRE:
2824                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2825                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2826                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2827                                 filter_conf->tunnel_type);
2828                         return -EINVAL;
2829                 case RTE_TUNNEL_TYPE_NONE:
2830                 default:
2831                         return 0;
2832                 }
2833                 break;
2834         case RTE_ETH_FILTER_FDIR:
2835                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2836         case RTE_ETH_FILTER_NTUPLE:
2837                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2838         case RTE_ETH_FILTER_MACVLAN:
2839         case RTE_ETH_FILTER_ETHERTYPE:
2840         case RTE_ETH_FILTER_FLEXIBLE:
2841         case RTE_ETH_FILTER_SYN:
2842         case RTE_ETH_FILTER_HASH:
2843         case RTE_ETH_FILTER_L2_TUNNEL:
2844         case RTE_ETH_FILTER_MAX:
2845         default:
2846                 DP_ERR(edev, "Unsupported filter type %d\n",
2847                         filter_type);
2848                 return -EINVAL;
2849         }
2850
2851         return 0;
2852 }
2853
2854 static const struct eth_dev_ops qede_eth_dev_ops = {
2855         .dev_configure = qede_dev_configure,
2856         .dev_infos_get = qede_dev_info_get,
2857         .rx_queue_setup = qede_rx_queue_setup,
2858         .rx_queue_release = qede_rx_queue_release,
2859         .tx_queue_setup = qede_tx_queue_setup,
2860         .tx_queue_release = qede_tx_queue_release,
2861         .dev_start = qede_dev_start,
2862         .dev_set_link_up = qede_dev_set_link_up,
2863         .dev_set_link_down = qede_dev_set_link_down,
2864         .link_update = qede_link_update,
2865         .promiscuous_enable = qede_promiscuous_enable,
2866         .promiscuous_disable = qede_promiscuous_disable,
2867         .allmulticast_enable = qede_allmulticast_enable,
2868         .allmulticast_disable = qede_allmulticast_disable,
2869         .dev_stop = qede_dev_stop,
2870         .dev_close = qede_dev_close,
2871         .stats_get = qede_get_stats,
2872         .stats_reset = qede_reset_stats,
2873         .xstats_get = qede_get_xstats,
2874         .xstats_reset = qede_reset_xstats,
2875         .xstats_get_names = qede_get_xstats_names,
2876         .mac_addr_add = qede_mac_addr_add,
2877         .mac_addr_remove = qede_mac_addr_remove,
2878         .mac_addr_set = qede_mac_addr_set,
2879         .vlan_offload_set = qede_vlan_offload_set,
2880         .vlan_filter_set = qede_vlan_filter_set,
2881         .flow_ctrl_set = qede_flow_ctrl_set,
2882         .flow_ctrl_get = qede_flow_ctrl_get,
2883         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2884         .rss_hash_update = qede_rss_hash_update,
2885         .rss_hash_conf_get = qede_rss_hash_conf_get,
2886         .reta_update  = qede_rss_reta_update,
2887         .reta_query  = qede_rss_reta_query,
2888         .mtu_set = qede_set_mtu,
2889         .filter_ctrl = qede_dev_filter_ctrl,
2890         .udp_tunnel_port_add = qede_udp_dst_port_add,
2891         .udp_tunnel_port_del = qede_udp_dst_port_del,
2892 };
2893
2894 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2895         .dev_configure = qede_dev_configure,
2896         .dev_infos_get = qede_dev_info_get,
2897         .rx_queue_setup = qede_rx_queue_setup,
2898         .rx_queue_release = qede_rx_queue_release,
2899         .tx_queue_setup = qede_tx_queue_setup,
2900         .tx_queue_release = qede_tx_queue_release,
2901         .dev_start = qede_dev_start,
2902         .dev_set_link_up = qede_dev_set_link_up,
2903         .dev_set_link_down = qede_dev_set_link_down,
2904         .link_update = qede_link_update,
2905         .promiscuous_enable = qede_promiscuous_enable,
2906         .promiscuous_disable = qede_promiscuous_disable,
2907         .allmulticast_enable = qede_allmulticast_enable,
2908         .allmulticast_disable = qede_allmulticast_disable,
2909         .dev_stop = qede_dev_stop,
2910         .dev_close = qede_dev_close,
2911         .stats_get = qede_get_stats,
2912         .stats_reset = qede_reset_stats,
2913         .xstats_get = qede_get_xstats,
2914         .xstats_reset = qede_reset_xstats,
2915         .xstats_get_names = qede_get_xstats_names,
2916         .vlan_offload_set = qede_vlan_offload_set,
2917         .vlan_filter_set = qede_vlan_filter_set,
2918         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2919         .rss_hash_update = qede_rss_hash_update,
2920         .rss_hash_conf_get = qede_rss_hash_conf_get,
2921         .reta_update  = qede_rss_reta_update,
2922         .reta_query  = qede_rss_reta_query,
2923         .mtu_set = qede_set_mtu,
2924         .udp_tunnel_port_add = qede_udp_dst_port_add,
2925         .udp_tunnel_port_del = qede_udp_dst_port_del,
2926 };
2927
2928 static void qede_update_pf_params(struct ecore_dev *edev)
2929 {
2930         struct ecore_pf_params pf_params;
2931
2932         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2933         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2934         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2935         qed_ops->common->update_pf_params(edev, &pf_params);
2936 }
2937
2938 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2939 {
2940         struct rte_pci_device *pci_dev;
2941         struct rte_pci_addr pci_addr;
2942         struct qede_dev *adapter;
2943         struct ecore_dev *edev;
2944         struct qed_dev_eth_info dev_info;
2945         struct qed_slowpath_params params;
2946         static bool do_once = true;
2947         uint8_t bulletin_change;
2948         uint8_t vf_mac[ETHER_ADDR_LEN];
2949         uint8_t is_mac_forced;
2950         bool is_mac_exist;
2951         /* Fix up ecore debug level */
2952         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2953         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2954         int rc;
2955
2956         /* Extract key data structures */
2957         adapter = eth_dev->data->dev_private;
2958         adapter->ethdev = eth_dev;
2959         edev = &adapter->edev;
2960         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2961         pci_addr = pci_dev->addr;
2962
2963         PMD_INIT_FUNC_TRACE(edev);
2964
2965         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2966                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2967                  eth_dev->data->port_id);
2968
2969         eth_dev->rx_pkt_burst = qede_recv_pkts;
2970         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2971         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2972
2973         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2974                 DP_ERR(edev, "Skipping device init from secondary process\n");
2975                 return 0;
2976         }
2977
2978         rte_eth_copy_pci_info(eth_dev, pci_dev);
2979
2980         /* @DPDK */
2981         edev->vendor_id = pci_dev->id.vendor_id;
2982         edev->device_id = pci_dev->id.device_id;
2983
2984         qed_ops = qed_get_eth_ops();
2985         if (!qed_ops) {
2986                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2987                 return -EINVAL;
2988         }
2989
2990         DP_INFO(edev, "Starting qede probe\n");
2991         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2992                                     dp_level, is_vf);
2993         if (rc != 0) {
2994                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2995                 return -ENODEV;
2996         }
2997         qede_update_pf_params(edev);
2998         rte_intr_callback_register(&pci_dev->intr_handle,
2999                                    qede_interrupt_handler, (void *)eth_dev);
3000         if (rte_intr_enable(&pci_dev->intr_handle)) {
3001                 DP_ERR(edev, "rte_intr_enable() failed\n");
3002                 return -ENODEV;
3003         }
3004
3005         /* Start the Slowpath-process */
3006         memset(&params, 0, sizeof(struct qed_slowpath_params));
3007         params.int_mode = ECORE_INT_MODE_MSIX;
3008         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3009         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3010         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3011         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3012         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3013                 QEDE_PMD_DRV_VER_STR_SIZE);
3014
3015         /* For CMT mode device do periodic polling for slowpath events.
3016          * This is required since uio device uses only one MSI-x
3017          * interrupt vector but we need one for each engine.
3018          */
3019         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3020                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
3021                                        qede_poll_sp_sb_cb,
3022                                        (void *)eth_dev);
3023                 if (rc != 0) {
3024                         DP_ERR(edev, "Unable to start periodic"
3025                                      " timer rc %d\n", rc);
3026                         return -EINVAL;
3027                 }
3028         }
3029
3030         rc = qed_ops->common->slowpath_start(edev, &params);
3031         if (rc) {
3032                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3033                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3034                                      (void *)eth_dev);
3035                 return -ENODEV;
3036         }
3037
3038         rc = qed_ops->fill_dev_info(edev, &dev_info);
3039         if (rc) {
3040                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3041                 qed_ops->common->slowpath_stop(edev);
3042                 qed_ops->common->remove(edev);
3043                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3044                                      (void *)eth_dev);
3045                 return -ENODEV;
3046         }
3047
3048         qede_alloc_etherdev(adapter, &dev_info);
3049
3050         adapter->ops->common->set_name(edev, edev->name);
3051
3052         if (!is_vf)
3053                 adapter->dev_info.num_mac_filters =
3054                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3055                                             ECORE_MAC);
3056         else
3057                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3058                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3059
3060         /* Allocate memory for storing MAC addr */
3061         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3062                                         (ETHER_ADDR_LEN *
3063                                         adapter->dev_info.num_mac_filters),
3064                                         RTE_CACHE_LINE_SIZE);
3065
3066         if (eth_dev->data->mac_addrs == NULL) {
3067                 DP_ERR(edev, "Failed to allocate MAC address\n");
3068                 qed_ops->common->slowpath_stop(edev);
3069                 qed_ops->common->remove(edev);
3070                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3071                                      (void *)eth_dev);
3072                 return -ENOMEM;
3073         }
3074
3075         if (!is_vf) {
3076                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3077                                 hw_info.hw_mac_addr,
3078                                 &eth_dev->data->mac_addrs[0]);
3079                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3080                                 &adapter->primary_mac);
3081         } else {
3082                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3083                                        &bulletin_change);
3084                 if (bulletin_change) {
3085                         is_mac_exist =
3086                             ecore_vf_bulletin_get_forced_mac(
3087                                                 ECORE_LEADING_HWFN(edev),
3088                                                 vf_mac,
3089                                                 &is_mac_forced);
3090                         if (is_mac_exist && is_mac_forced) {
3091                                 DP_INFO(edev, "VF macaddr received from PF\n");
3092                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3093                                                 &eth_dev->data->mac_addrs[0]);
3094                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3095                                                 &adapter->primary_mac);
3096                         } else {
3097                                 DP_ERR(edev, "No VF macaddr assigned\n");
3098                         }
3099                 }
3100         }
3101
3102         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3103
3104         if (do_once) {
3105                 qede_print_adapter_info(adapter);
3106                 do_once = false;
3107         }
3108
3109         adapter->num_tx_queues = 0;
3110         adapter->num_rx_queues = 0;
3111         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3112         SLIST_INIT(&adapter->vlan_list_head);
3113         SLIST_INIT(&adapter->uc_list_head);
3114         adapter->mtu = ETHER_MTU;
3115         adapter->new_mtu = ETHER_MTU;
3116         if (!is_vf) {
3117                 if (qede_start_vport(adapter, adapter->mtu))
3118                         return -1;
3119         } else {
3120                 /* VF tunnel offloads is enabled by default in PF driver */
3121                 adapter->vxlan.enable = true;
3122                 adapter->vxlan.num_filters = 0;
3123                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3124                                              ETH_TUNNEL_FILTER_IVLAN;
3125                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3126                 adapter->geneve.enable = true;
3127                 adapter->vxlan.num_filters = 0;
3128                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3129                                              ETH_TUNNEL_FILTER_IVLAN;
3130                 adapter->vxlan.udp_port = QEDE_GENEVE_DEF_PORT;
3131         }
3132
3133         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3134                 adapter->primary_mac.addr_bytes[0],
3135                 adapter->primary_mac.addr_bytes[1],
3136                 adapter->primary_mac.addr_bytes[2],
3137                 adapter->primary_mac.addr_bytes[3],
3138                 adapter->primary_mac.addr_bytes[4],
3139                 adapter->primary_mac.addr_bytes[5]);
3140
3141         DP_INFO(edev, "Device initialized\n");
3142
3143         return 0;
3144 }
3145
3146 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3147 {
3148         return qede_common_dev_init(eth_dev, 1);
3149 }
3150
3151 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3152 {
3153         return qede_common_dev_init(eth_dev, 0);
3154 }
3155
3156 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3157 {
3158 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3159         struct qede_dev *qdev = eth_dev->data->dev_private;
3160         struct ecore_dev *edev = &qdev->edev;
3161
3162         PMD_INIT_FUNC_TRACE(edev);
3163 #endif
3164
3165         /* only uninitialize in the primary process */
3166         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3167                 return 0;
3168
3169         /* safe to close dev here */
3170         qede_dev_close(eth_dev);
3171
3172         eth_dev->dev_ops = NULL;
3173         eth_dev->rx_pkt_burst = NULL;
3174         eth_dev->tx_pkt_burst = NULL;
3175
3176         if (eth_dev->data->mac_addrs)
3177                 rte_free(eth_dev->data->mac_addrs);
3178
3179         eth_dev->data->mac_addrs = NULL;
3180
3181         return 0;
3182 }
3183
3184 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3185 {
3186         return qede_dev_common_uninit(eth_dev);
3187 }
3188
3189 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3190 {
3191         return qede_dev_common_uninit(eth_dev);
3192 }
3193
3194 static const struct rte_pci_id pci_id_qedevf_map[] = {
3195 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3196         {
3197                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3198         },
3199         {
3200                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3201         },
3202         {
3203                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3204         },
3205         {.vendor_id = 0,}
3206 };
3207
3208 static const struct rte_pci_id pci_id_qede_map[] = {
3209 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3210         {
3211                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3212         },
3213         {
3214                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3215         },
3216         {
3217                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3218         },
3219         {
3220                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3221         },
3222         {
3223                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3224         },
3225         {
3226                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3227         },
3228         {
3229                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3230         },
3231         {
3232                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3233         },
3234         {
3235                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3236         },
3237         {
3238                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3239         },
3240         {.vendor_id = 0,}
3241 };
3242
3243 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3244         struct rte_pci_device *pci_dev)
3245 {
3246         return rte_eth_dev_pci_generic_probe(pci_dev,
3247                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3248 }
3249
3250 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3251 {
3252         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3253 }
3254
3255 static struct rte_pci_driver rte_qedevf_pmd = {
3256         .id_table = pci_id_qedevf_map,
3257         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3258         .probe = qedevf_eth_dev_pci_probe,
3259         .remove = qedevf_eth_dev_pci_remove,
3260 };
3261
3262 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3263         struct rte_pci_device *pci_dev)
3264 {
3265         return rte_eth_dev_pci_generic_probe(pci_dev,
3266                 sizeof(struct qede_dev), qede_eth_dev_init);
3267 }
3268
3269 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3270 {
3271         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3272 }
3273
3274 static struct rte_pci_driver rte_qede_pmd = {
3275         .id_table = pci_id_qede_map,
3276         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3277         .probe = qede_eth_dev_pci_probe,
3278         .remove = qede_eth_dev_pci_remove,
3279 };
3280
3281 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3282 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3283 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3284 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3285 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3286 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3287
3288 RTE_INIT(qede_init_log);
3289 static void
3290 qede_init_log(void)
3291 {
3292         qede_logtype_init = rte_log_register("pmd.qede.init");
3293         if (qede_logtype_init >= 0)
3294                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3295         qede_logtype_driver = rte_log_register("pmd.qede.driver");
3296         if (qede_logtype_driver >= 0)
3297                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3298 }