2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static int64_t timer_period = 1;
17 /* VXLAN tunnel classification mapping */
18 const struct _qede_vxlan_tunn_types {
19 uint16_t rte_filter_type;
20 enum ecore_filter_ucast_type qede_type;
21 enum ecore_tunn_clss qede_tunn_clss;
23 } qede_tunn_types[] = {
25 ETH_TUNNEL_FILTER_OMAC,
27 ECORE_TUNN_CLSS_MAC_VLAN,
31 ETH_TUNNEL_FILTER_TENID,
33 ECORE_TUNN_CLSS_MAC_VNI,
37 ETH_TUNNEL_FILTER_IMAC,
38 ECORE_FILTER_INNER_MAC,
39 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
43 ETH_TUNNEL_FILTER_IVLAN,
44 ECORE_FILTER_INNER_VLAN,
45 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
50 ECORE_FILTER_MAC_VNI_PAIR,
51 ECORE_TUNN_CLSS_MAC_VNI,
55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
58 "outer-mac and inner-mac"
61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
64 "outer-mac and inner-vlan"
67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
68 ECORE_FILTER_INNER_MAC_VNI_PAIR,
69 ECORE_TUNN_CLSS_INNER_MAC_VNI,
73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
80 ECORE_FILTER_INNER_PAIR,
81 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
82 "inner-mac and inner-vlan",
85 ETH_TUNNEL_FILTER_OIP,
91 ETH_TUNNEL_FILTER_IIP,
97 RTE_TUNNEL_FILTER_IMAC_IVLAN,
103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
109 RTE_TUNNEL_FILTER_IMAC_TENID,
115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
122 struct rte_qede_xstats_name_off {
123 char name[RTE_ETH_XSTATS_NAME_SIZE];
127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
129 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
130 {"rx_multicast_bytes",
131 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
132 {"rx_broadcast_bytes",
133 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
134 {"rx_unicast_packets",
135 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
136 {"rx_multicast_packets",
137 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
138 {"rx_broadcast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
142 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
143 {"tx_multicast_bytes",
144 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
145 {"tx_broadcast_bytes",
146 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
147 {"tx_unicast_packets",
148 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
149 {"tx_multicast_packets",
150 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
151 {"tx_broadcast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
154 {"rx_64_byte_packets",
155 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
156 {"rx_65_to_127_byte_packets",
157 offsetof(struct ecore_eth_stats_common,
158 rx_65_to_127_byte_packets)},
159 {"rx_128_to_255_byte_packets",
160 offsetof(struct ecore_eth_stats_common,
161 rx_128_to_255_byte_packets)},
162 {"rx_256_to_511_byte_packets",
163 offsetof(struct ecore_eth_stats_common,
164 rx_256_to_511_byte_packets)},
165 {"rx_512_to_1023_byte_packets",
166 offsetof(struct ecore_eth_stats_common,
167 rx_512_to_1023_byte_packets)},
168 {"rx_1024_to_1518_byte_packets",
169 offsetof(struct ecore_eth_stats_common,
170 rx_1024_to_1518_byte_packets)},
171 {"tx_64_byte_packets",
172 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
173 {"tx_65_to_127_byte_packets",
174 offsetof(struct ecore_eth_stats_common,
175 tx_65_to_127_byte_packets)},
176 {"tx_128_to_255_byte_packets",
177 offsetof(struct ecore_eth_stats_common,
178 tx_128_to_255_byte_packets)},
179 {"tx_256_to_511_byte_packets",
180 offsetof(struct ecore_eth_stats_common,
181 tx_256_to_511_byte_packets)},
182 {"tx_512_to_1023_byte_packets",
183 offsetof(struct ecore_eth_stats_common,
184 tx_512_to_1023_byte_packets)},
185 {"tx_1024_to_1518_byte_packets",
186 offsetof(struct ecore_eth_stats_common,
187 tx_1024_to_1518_byte_packets)},
189 {"rx_mac_crtl_frames",
190 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
191 {"tx_mac_control_frames",
192 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
194 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
196 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
197 {"rx_priority_flow_control_frames",
198 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
199 {"tx_priority_flow_control_frames",
200 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
203 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
205 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
206 {"rx_carrier_errors",
207 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
208 {"rx_oversize_packet_errors",
209 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
211 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
212 {"rx_undersize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
214 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
215 {"rx_host_buffer_not_available",
216 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
217 /* Number of packets discarded because they are bigger than MTU */
218 {"rx_packet_too_big_discards",
219 offsetof(struct ecore_eth_stats_common,
220 packet_too_big_discard)},
221 {"rx_ttl_zero_discards",
222 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
223 {"rx_multi_function_tag_filter_discards",
224 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
225 {"rx_mac_filter_discards",
226 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
227 {"rx_hw_buffer_truncates",
228 offsetof(struct ecore_eth_stats_common, brb_truncates)},
229 {"rx_hw_buffer_discards",
230 offsetof(struct ecore_eth_stats_common, brb_discards)},
231 {"tx_error_drop_packets",
232 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
234 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
235 {"rx_mac_unicast_packets",
236 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
237 {"rx_mac_multicast_packets",
238 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
239 {"rx_mac_broadcast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
242 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
243 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
244 {"tx_mac_unicast_packets",
245 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
246 {"tx_mac_multicast_packets",
247 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
248 {"tx_mac_broadcast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
251 {"lro_coalesced_packets",
252 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
253 {"lro_coalesced_events",
254 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
256 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
257 {"lro_not_coalesced_packets",
258 offsetof(struct ecore_eth_stats_common,
259 tpa_not_coalesced_pkts)},
260 {"lro_coalesced_bytes",
261 offsetof(struct ecore_eth_stats_common,
262 tpa_coalesced_bytes)},
265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
266 {"rx_1519_to_1522_byte_packets",
267 offsetof(struct ecore_eth_stats, bb) +
268 offsetof(struct ecore_eth_stats_bb,
269 rx_1519_to_1522_byte_packets)},
270 {"rx_1519_to_2047_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_2047_byte_packets)},
274 {"rx_2048_to_4095_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_2048_to_4095_byte_packets)},
278 {"rx_4096_to_9216_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_4096_to_9216_byte_packets)},
282 {"rx_9217_to_16383_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_9217_to_16383_byte_packets)},
287 {"tx_1519_to_2047_byte_packets",
288 offsetof(struct ecore_eth_stats, bb) +
289 offsetof(struct ecore_eth_stats_bb,
290 tx_1519_to_2047_byte_packets)},
291 {"tx_2048_to_4095_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_2048_to_4095_byte_packets)},
295 {"tx_4096_to_9216_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_4096_to_9216_byte_packets)},
299 {"tx_9217_to_16383_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_9217_to_16383_byte_packets)},
304 {"tx_lpi_entry_count",
305 offsetof(struct ecore_eth_stats, bb) +
306 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
307 {"tx_total_collisions",
308 offsetof(struct ecore_eth_stats, bb) +
309 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
313 {"rx_1519_to_max_byte_packets",
314 offsetof(struct ecore_eth_stats, ah) +
315 offsetof(struct ecore_eth_stats_ah,
316 rx_1519_to_max_byte_packets)},
317 {"tx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 tx_1519_to_max_byte_packets)},
323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
325 offsetof(struct qede_rx_queue, rx_segs)},
327 offsetof(struct qede_rx_queue, rx_hw_errors)},
328 {"rx_q_allocation_errors",
329 offsetof(struct qede_rx_queue, rx_alloc_errors)}
332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
334 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
338 qede_interrupt_handler(void *param)
340 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
341 struct qede_dev *qdev = eth_dev->data->dev_private;
342 struct ecore_dev *edev = &qdev->edev;
344 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
345 if (rte_intr_enable(eth_dev->intr_handle))
346 DP_ERR(edev, "rte_intr_enable failed\n");
350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
352 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
357 static void qede_print_adapter_info(struct qede_dev *qdev)
359 struct ecore_dev *edev = &qdev->edev;
360 struct qed_dev_info *info = &qdev->dev_info.common;
361 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
362 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
364 DP_INFO(edev, "*********************************\n");
365 DP_INFO(edev, " DPDK version:%s\n", rte_version());
366 DP_INFO(edev, " Chip details : %s %c%d\n",
367 ECORE_IS_BB(edev) ? "BB" : "AH",
368 'A' + edev->chip_rev,
369 (int)edev->chip_metal);
370 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
371 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
372 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
373 ver_str, QEDE_PMD_VERSION);
374 DP_INFO(edev, " Driver version : %s\n", drv_ver);
375 DP_INFO(edev, " Firmware version : %s\n", ver_str);
377 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
379 (info->mfw_rev >> 24) & 0xff,
380 (info->mfw_rev >> 16) & 0xff,
381 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
382 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
383 DP_INFO(edev, " Firmware file : %s\n", fw_file);
384 DP_INFO(edev, "*********************************\n");
389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
391 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
392 struct ecore_sp_vport_start_params params;
393 struct ecore_hwfn *p_hwfn;
397 memset(¶ms, 0, sizeof(params));
400 /* @DPDK - Disable FW placement */
401 params.zero_placement_offset = 1;
402 for_each_hwfn(edev, i) {
403 p_hwfn = &edev->hwfns[i];
404 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
405 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
406 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
407 if (rc != ECORE_SUCCESS) {
408 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
412 ecore_reset_vport_stats(edev);
413 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
419 qede_stop_vport(struct ecore_dev *edev)
421 struct ecore_hwfn *p_hwfn;
427 for_each_hwfn(edev, i) {
428 p_hwfn = &edev->hwfns[i];
429 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
431 if (rc != ECORE_SUCCESS) {
432 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
440 /* Activate or deactivate vport via vport-update */
441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
443 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
444 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
445 struct ecore_sp_vport_update_params params;
446 struct ecore_hwfn *p_hwfn;
450 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
452 params.update_vport_active_rx_flg = 1;
453 params.update_vport_active_tx_flg = 1;
454 params.vport_active_rx_flg = flg;
455 params.vport_active_tx_flg = flg;
456 for_each_hwfn(edev, i) {
457 p_hwfn = &edev->hwfns[i];
458 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
459 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
460 ECORE_SPQ_MODE_EBLOCK, NULL);
461 if (rc != ECORE_SUCCESS) {
462 DP_ERR(edev, "Failed to update vport\n");
466 DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
471 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
472 uint16_t mtu, bool enable)
474 /* Enable LRO in split mode */
475 sge_tpa_params->tpa_ipv4_en_flg = enable;
476 sge_tpa_params->tpa_ipv6_en_flg = enable;
477 sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
478 sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
479 /* set if tpa enable changes */
480 sge_tpa_params->update_tpa_en_flg = 1;
481 /* set if tpa parameters should be handled */
482 sge_tpa_params->update_tpa_param_flg = enable;
484 sge_tpa_params->max_buffers_per_cqe = 20;
485 /* Enable TPA in split mode. In this mode each TPA segment
486 * starts on the new BD, so there is one BD per segment.
488 sge_tpa_params->tpa_pkt_split_flg = 1;
489 sge_tpa_params->tpa_hdr_data_split_flg = 0;
490 sge_tpa_params->tpa_gro_consistent_flg = 0;
491 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
492 sge_tpa_params->tpa_max_size = 0x7FFF;
493 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
494 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
497 /* Enable/disable LRO via vport-update */
498 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
500 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
501 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
502 struct ecore_sp_vport_update_params params;
503 struct ecore_sge_tpa_params tpa_params;
504 struct ecore_hwfn *p_hwfn;
508 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
509 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
510 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
512 params.sge_tpa_params = &tpa_params;
513 for_each_hwfn(edev, i) {
514 p_hwfn = &edev->hwfns[i];
515 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
516 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
517 ECORE_SPQ_MODE_EBLOCK, NULL);
518 if (rc != ECORE_SUCCESS) {
519 DP_ERR(edev, "Failed to update LRO\n");
524 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
529 /* Update MTU via vport-update without doing port restart.
530 * The vport must be deactivated before calling this API.
532 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
534 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
535 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
536 struct ecore_sp_vport_update_params params;
537 struct ecore_hwfn *p_hwfn;
541 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
545 for_each_hwfn(edev, i) {
546 p_hwfn = &edev->hwfns[i];
547 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
548 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
549 ECORE_SPQ_MODE_EBLOCK, NULL);
550 if (rc != ECORE_SUCCESS) {
551 DP_ERR(edev, "Failed to update MTU\n");
555 DP_INFO(edev, "MTU updated to %u\n", mtu);
560 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
562 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
563 ucast->is_rx_filter = true;
564 ucast->is_tx_filter = true;
565 /* ucast->assert_on_error = true; - For debug */
569 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
570 enum qed_filter_rx_mode_type type)
572 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
573 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
574 struct ecore_filter_accept_flags flags;
576 memset(&flags, 0, sizeof(flags));
578 flags.update_rx_mode_config = 1;
579 flags.update_tx_mode_config = 1;
580 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
581 ECORE_ACCEPT_MCAST_MATCHED |
584 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
585 ECORE_ACCEPT_MCAST_MATCHED |
588 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
589 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
591 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
592 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
594 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
595 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
596 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
597 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
598 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
599 ECORE_ACCEPT_MCAST_UNMATCHED;
602 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
603 ECORE_SPQ_MODE_CB, NULL);
605 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
606 uint8_t clss, bool mode, bool mask)
608 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
609 p_tunn->vxlan.b_update_mode = mode;
610 p_tunn->vxlan.b_mode_enabled = mask;
611 p_tunn->b_update_rx_cls = true;
612 p_tunn->b_update_tx_cls = true;
613 p_tunn->vxlan.tun_cls = clss;
617 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
620 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
621 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
622 struct qede_ucast_entry *tmp = NULL;
623 struct qede_ucast_entry *u;
624 struct ether_addr *mac_addr;
626 mac_addr = (struct ether_addr *)ucast->mac;
628 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
629 if ((memcmp(mac_addr, &tmp->mac,
630 ETHER_ADDR_LEN) == 0) &&
631 ucast->vni == tmp->vni &&
632 ucast->vlan == tmp->vlan) {
633 DP_ERR(edev, "Unicast MAC is already added"
634 " with vlan = %u, vni = %u\n",
635 ucast->vlan, ucast->vni);
639 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
640 RTE_CACHE_LINE_SIZE);
642 DP_ERR(edev, "Did not allocate memory for ucast\n");
645 ether_addr_copy(mac_addr, &u->mac);
646 u->vlan = ucast->vlan;
648 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
651 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
652 if ((memcmp(mac_addr, &tmp->mac,
653 ETHER_ADDR_LEN) == 0) &&
654 ucast->vlan == tmp->vlan &&
655 ucast->vni == tmp->vni)
659 DP_INFO(edev, "Unicast MAC is not found\n");
662 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
670 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
673 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
674 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
675 struct ether_addr *mac_addr;
676 struct qede_mcast_entry *tmp = NULL;
677 struct qede_mcast_entry *m;
679 mac_addr = (struct ether_addr *)mcast->mac;
681 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
682 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
684 "Multicast MAC is already added\n");
688 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
689 RTE_CACHE_LINE_SIZE);
692 "Did not allocate memory for mcast\n");
695 ether_addr_copy(mac_addr, &m->mac);
696 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
699 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
700 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
704 DP_INFO(edev, "Multicast mac is not found\n");
707 SLIST_REMOVE(&qdev->mc_list_head, tmp,
708 qede_mcast_entry, list);
715 static enum _ecore_status_t
716 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
719 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
720 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
721 enum _ecore_status_t rc;
722 struct ecore_filter_mcast mcast;
723 struct qede_mcast_entry *tmp;
727 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
729 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
731 "Mcast filter table limit exceeded, "
732 "Please enable mcast promisc mode\n");
736 rc = qede_mcast_filter(eth_dev, ucast, add);
738 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
739 memset(&mcast, 0, sizeof(mcast));
740 mcast.num_mc_addrs = qdev->num_mc_addr;
741 mcast.opcode = ECORE_FILTER_ADD;
742 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
743 ether_addr_copy(&tmp->mac,
744 (struct ether_addr *)&mcast.mac[j]);
747 rc = ecore_filter_mcast_cmd(edev, &mcast,
748 ECORE_SPQ_MODE_CB, NULL);
750 if (rc != ECORE_SUCCESS) {
751 DP_ERR(edev, "Failed to add multicast filter"
752 " rc = %d, op = %d\n", rc, add);
754 } else { /* Unicast */
756 if (qdev->num_uc_addr >=
757 qdev->dev_info.num_mac_filters) {
759 "Ucast filter table limit exceeded,"
760 " Please enable promisc mode\n");
764 rc = qede_ucast_filter(eth_dev, ucast, add);
766 rc = ecore_filter_ucast_cmd(edev, ucast,
767 ECORE_SPQ_MODE_CB, NULL);
768 if (rc != ECORE_SUCCESS) {
769 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
778 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
779 __rte_unused uint32_t index, __rte_unused uint32_t pool)
781 struct ecore_filter_ucast ucast;
784 qede_set_ucast_cmn_params(&ucast);
785 ucast.type = ECORE_FILTER_MAC;
786 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
787 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
792 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
794 struct qede_dev *qdev = eth_dev->data->dev_private;
795 struct ecore_dev *edev = &qdev->edev;
796 struct ecore_filter_ucast ucast;
798 PMD_INIT_FUNC_TRACE(edev);
800 if (index >= qdev->dev_info.num_mac_filters) {
801 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
802 index, qdev->dev_info.num_mac_filters);
806 qede_set_ucast_cmn_params(&ucast);
807 ucast.opcode = ECORE_FILTER_REMOVE;
808 ucast.type = ECORE_FILTER_MAC;
810 /* Use the index maintained by rte */
811 ether_addr_copy(ð_dev->data->mac_addrs[index],
812 (struct ether_addr *)&ucast.mac);
814 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
818 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
820 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
821 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
823 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
824 mac_addr->addr_bytes)) {
825 DP_ERR(edev, "Setting MAC address is not allowed\n");
826 ether_addr_copy(&qdev->primary_mac,
827 ð_dev->data->mac_addrs[0]);
831 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
834 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
836 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
837 struct ecore_sp_vport_update_params params;
838 struct ecore_hwfn *p_hwfn;
842 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
844 params.update_accept_any_vlan_flg = 1;
845 params.accept_any_vlan = flg;
846 for_each_hwfn(edev, i) {
847 p_hwfn = &edev->hwfns[i];
848 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
849 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
850 ECORE_SPQ_MODE_EBLOCK, NULL);
851 if (rc != ECORE_SUCCESS) {
852 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
857 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
860 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
862 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
863 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
864 struct ecore_sp_vport_update_params params;
865 struct ecore_hwfn *p_hwfn;
869 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
871 params.update_inner_vlan_removal_flg = 1;
872 params.inner_vlan_removal_flg = flg;
873 for_each_hwfn(edev, i) {
874 p_hwfn = &edev->hwfns[i];
875 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
876 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
877 ECORE_SPQ_MODE_EBLOCK, NULL);
878 if (rc != ECORE_SUCCESS) {
879 DP_ERR(edev, "Failed to update vport\n");
884 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
888 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
889 uint16_t vlan_id, int on)
891 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
892 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
893 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
894 struct qede_vlan_entry *tmp = NULL;
895 struct qede_vlan_entry *vlan;
896 struct ecore_filter_ucast ucast;
900 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
901 DP_ERR(edev, "Reached max VLAN filter limit"
902 " enabling accept_any_vlan\n");
903 qede_config_accept_any_vlan(qdev, true);
907 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
908 if (tmp->vid == vlan_id) {
909 DP_ERR(edev, "VLAN %u already configured\n",
915 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
916 RTE_CACHE_LINE_SIZE);
919 DP_ERR(edev, "Did not allocate memory for VLAN\n");
923 qede_set_ucast_cmn_params(&ucast);
924 ucast.opcode = ECORE_FILTER_ADD;
925 ucast.type = ECORE_FILTER_VLAN;
926 ucast.vlan = vlan_id;
927 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
930 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
935 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
936 qdev->configured_vlans++;
937 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
938 vlan_id, qdev->configured_vlans);
941 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
942 if (tmp->vid == vlan_id)
947 if (qdev->configured_vlans == 0) {
949 "No VLAN filters configured yet\n");
953 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
957 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
959 qede_set_ucast_cmn_params(&ucast);
960 ucast.opcode = ECORE_FILTER_REMOVE;
961 ucast.type = ECORE_FILTER_VLAN;
962 ucast.vlan = vlan_id;
963 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
966 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
969 qdev->configured_vlans--;
970 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
971 vlan_id, qdev->configured_vlans);
978 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
980 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
981 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
982 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
984 if (mask & ETH_VLAN_STRIP_MASK) {
985 if (rxmode->hw_vlan_strip)
986 (void)qede_vlan_stripping(eth_dev, 1);
988 (void)qede_vlan_stripping(eth_dev, 0);
991 if (mask & ETH_VLAN_FILTER_MASK) {
992 /* VLAN filtering kicks in when a VLAN is added */
993 if (rxmode->hw_vlan_filter) {
994 qede_vlan_filter_set(eth_dev, 0, 1);
996 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
998 " Please remove existing VLAN filters"
999 " before disabling VLAN filtering\n");
1000 /* Signal app that VLAN filtering is still
1003 rxmode->hw_vlan_filter = true;
1005 qede_vlan_filter_set(eth_dev, 0, 0);
1010 if (mask & ETH_VLAN_EXTEND_MASK)
1011 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1012 " and classification is based on outer tag only\n");
1014 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1015 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1018 static void qede_prandom_bytes(uint32_t *buff)
1022 srand((unsigned int)time(NULL));
1023 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1027 int qede_config_rss(struct rte_eth_dev *eth_dev)
1029 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1030 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1031 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1033 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1034 struct rte_eth_rss_reta_entry64 reta_conf[2];
1035 struct rte_eth_rss_conf rss_conf;
1036 uint32_t i, id, pos, q;
1038 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1039 if (!rss_conf.rss_key) {
1040 DP_INFO(edev, "Applying driver default key\n");
1041 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1042 qede_prandom_bytes(&def_rss_key[0]);
1043 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1046 /* Configure RSS hash */
1047 if (qede_rss_hash_update(eth_dev, &rss_conf))
1050 /* Configure default RETA */
1051 memset(reta_conf, 0, sizeof(reta_conf));
1052 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1053 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1055 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1056 id = i / RTE_RETA_GROUP_SIZE;
1057 pos = i % RTE_RETA_GROUP_SIZE;
1058 q = i % QEDE_RSS_COUNT(qdev);
1059 reta_conf[id].reta[pos] = q;
1061 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1062 ECORE_RSS_IND_TABLE_SIZE))
1068 static void qede_fastpath_start(struct ecore_dev *edev)
1070 struct ecore_hwfn *p_hwfn;
1073 for_each_hwfn(edev, i) {
1074 p_hwfn = &edev->hwfns[i];
1075 ecore_hw_start_fastpath(p_hwfn);
1079 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1081 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1082 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1084 PMD_INIT_FUNC_TRACE(edev);
1086 /* Update MTU only if it has changed */
1087 if (qdev->mtu != qdev->new_mtu) {
1088 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1090 qdev->mtu = qdev->new_mtu;
1091 /* If MTU has changed then update TPA too */
1092 if (qdev->enable_lro)
1093 if (qede_enable_tpa(eth_dev, true))
1098 if (qede_start_queues(eth_dev))
1101 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1102 * enabling RSS. Hence RSS configuration is deferred upto this point.
1103 * Also, we would like to retain similar behavior in PF case, so we
1104 * don't do PF/VF specific check here.
1106 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1107 if (qede_config_rss(eth_dev))
1111 if (qede_activate_vport(eth_dev, true))
1114 /* Bring-up the link */
1115 qede_dev_set_link_state(eth_dev, true);
1117 /* Start/resume traffic */
1118 qede_fastpath_start(edev);
1120 DP_INFO(edev, "Device started\n");
1124 DP_ERR(edev, "Device start fails\n");
1125 return -1; /* common error code is < 0 */
1128 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1130 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1131 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1133 PMD_INIT_FUNC_TRACE(edev);
1136 if (qede_activate_vport(eth_dev, false))
1139 if (qdev->enable_lro)
1140 qede_enable_tpa(eth_dev, false);
1142 /* TODO: Do we need disable LRO or RSS */
1144 qede_stop_queues(eth_dev);
1146 /* Disable traffic */
1147 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1149 /* Bring the link down */
1150 qede_dev_set_link_state(eth_dev, false);
1152 DP_INFO(edev, "Device is stopped\n");
1155 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1157 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1158 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1159 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1161 PMD_INIT_FUNC_TRACE(edev);
1163 /* Check requirements for 100G mode */
1164 if (ECORE_IS_CMT(edev)) {
1165 if (eth_dev->data->nb_rx_queues < 2 ||
1166 eth_dev->data->nb_tx_queues < 2) {
1167 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1171 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1172 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1174 "100G mode needs even no. of RX/TX queues\n");
1179 /* Sanity checks and throw warnings */
1180 if (rxmode->enable_scatter)
1181 eth_dev->data->scattered_rx = 1;
1183 if (!rxmode->hw_strip_crc)
1184 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1186 if (!rxmode->hw_ip_checksum)
1187 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1189 if (rxmode->header_split)
1190 DP_INFO(edev, "Header split enable is not supported\n");
1191 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1193 DP_ERR(edev, "Unsupported multi-queue mode\n");
1196 /* Flow director mode check */
1197 if (qede_check_fdir_support(eth_dev))
1200 /* Deallocate resources if held previously. It is needed only if the
1201 * queue count has been changed from previous configuration. If its
1202 * going to change then it means RX/TX queue setup will be called
1203 * again and the fastpath pointers will be reinitialized there.
1205 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1206 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1207 qede_dealloc_fp_resc(eth_dev);
1208 /* Proceed with updated queue count */
1209 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1210 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1211 if (qede_alloc_fp_resc(qdev))
1215 /* VF's MTU has to be set using vport-start where as
1216 * PF's MTU can be updated via vport-update.
1219 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1222 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1226 qdev->mtu = rxmode->max_rx_pkt_len;
1227 qdev->new_mtu = qdev->mtu;
1229 /* Configure TPA parameters */
1230 if (rxmode->enable_lro) {
1231 if (qede_enable_tpa(eth_dev, true))
1233 /* Enable scatter mode for LRO */
1234 if (!rxmode->enable_scatter)
1235 eth_dev->data->scattered_rx = 1;
1237 qdev->enable_lro = rxmode->enable_lro;
1239 /* Enable VLAN offloads by default */
1240 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1241 ETH_VLAN_FILTER_MASK |
1242 ETH_VLAN_EXTEND_MASK);
1244 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1245 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1250 /* Info about HW descriptor ring limitations */
1251 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1252 .nb_max = 0x8000, /* 32K */
1254 .nb_align = 128 /* lowest common multiple */
1257 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1258 .nb_max = 0x8000, /* 32K */
1261 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1262 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1266 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1267 struct rte_eth_dev_info *dev_info)
1269 struct qede_dev *qdev = eth_dev->data->dev_private;
1270 struct ecore_dev *edev = &qdev->edev;
1271 struct qed_link_output link;
1272 uint32_t speed_cap = 0;
1274 PMD_INIT_FUNC_TRACE(edev);
1276 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1277 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1278 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1279 dev_info->rx_desc_lim = qede_rx_desc_lim;
1280 dev_info->tx_desc_lim = qede_tx_desc_lim;
1283 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1284 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1286 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1287 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1288 dev_info->max_tx_queues = dev_info->max_rx_queues;
1290 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1291 dev_info->max_vfs = 0;
1292 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1293 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1294 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1296 dev_info->default_txconf = (struct rte_eth_txconf) {
1297 .txq_flags = QEDE_TXQ_FLAGS,
1300 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
1301 DEV_RX_OFFLOAD_IPV4_CKSUM |
1302 DEV_RX_OFFLOAD_UDP_CKSUM |
1303 DEV_RX_OFFLOAD_TCP_CKSUM |
1304 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1305 DEV_RX_OFFLOAD_TCP_LRO);
1307 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1308 DEV_TX_OFFLOAD_IPV4_CKSUM |
1309 DEV_TX_OFFLOAD_UDP_CKSUM |
1310 DEV_TX_OFFLOAD_TCP_CKSUM |
1311 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1312 DEV_TX_OFFLOAD_TCP_TSO |
1313 DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1315 memset(&link, 0, sizeof(struct qed_link_output));
1316 qdev->ops->common->get_link(edev, &link);
1317 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1318 speed_cap |= ETH_LINK_SPEED_1G;
1319 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1320 speed_cap |= ETH_LINK_SPEED_10G;
1321 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1322 speed_cap |= ETH_LINK_SPEED_25G;
1323 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1324 speed_cap |= ETH_LINK_SPEED_40G;
1325 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1326 speed_cap |= ETH_LINK_SPEED_50G;
1327 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1328 speed_cap |= ETH_LINK_SPEED_100G;
1329 dev_info->speed_capa = speed_cap;
1332 /* return 0 means link status changed, -1 means not changed */
1334 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1336 struct qede_dev *qdev = eth_dev->data->dev_private;
1337 struct ecore_dev *edev = &qdev->edev;
1338 uint16_t link_duplex;
1339 struct qed_link_output link;
1340 struct rte_eth_link *curr = ð_dev->data->dev_link;
1342 memset(&link, 0, sizeof(struct qed_link_output));
1343 qdev->ops->common->get_link(edev, &link);
1346 curr->link_speed = link.speed;
1349 switch (link.duplex) {
1350 case QEDE_DUPLEX_HALF:
1351 link_duplex = ETH_LINK_HALF_DUPLEX;
1353 case QEDE_DUPLEX_FULL:
1354 link_duplex = ETH_LINK_FULL_DUPLEX;
1356 case QEDE_DUPLEX_UNKNOWN:
1360 curr->link_duplex = link_duplex;
1363 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1366 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1367 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1369 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1370 curr->link_speed, curr->link_duplex,
1371 curr->link_autoneg, curr->link_status);
1373 /* return 0 means link status changed, -1 means not changed */
1374 return ((curr->link_status == link.link_up) ? -1 : 0);
1377 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1379 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1380 struct qede_dev *qdev = eth_dev->data->dev_private;
1381 struct ecore_dev *edev = &qdev->edev;
1383 PMD_INIT_FUNC_TRACE(edev);
1386 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1388 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1389 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1391 qed_configure_filter_rx_mode(eth_dev, type);
1394 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1396 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1397 struct qede_dev *qdev = eth_dev->data->dev_private;
1398 struct ecore_dev *edev = &qdev->edev;
1400 PMD_INIT_FUNC_TRACE(edev);
1403 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1404 qed_configure_filter_rx_mode(eth_dev,
1405 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1407 qed_configure_filter_rx_mode(eth_dev,
1408 QED_FILTER_RX_MODE_TYPE_REGULAR);
1411 static void qede_poll_sp_sb_cb(void *param)
1413 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1414 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1415 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1418 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1419 qede_interrupt_action(&edev->hwfns[1]);
1421 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1425 DP_ERR(edev, "Unable to start periodic"
1426 " timer rc %d\n", rc);
1427 assert(false && "Unable to start periodic timer");
1431 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1433 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1434 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1435 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1437 PMD_INIT_FUNC_TRACE(edev);
1439 /* dev_stop() shall cleanup fp resources in hw but without releasing
1440 * dma memories and sw structures so that dev_start() can be called
1441 * by the app without reconfiguration. However, in dev_close() we
1442 * can release all the resources and device can be brought up newly
1444 if (eth_dev->data->dev_started)
1445 qede_dev_stop(eth_dev);
1447 qede_stop_vport(edev);
1448 qede_fdir_dealloc_resc(eth_dev);
1449 qede_dealloc_fp_resc(eth_dev);
1451 eth_dev->data->nb_rx_queues = 0;
1452 eth_dev->data->nb_tx_queues = 0;
1454 qdev->ops->common->slowpath_stop(edev);
1455 qdev->ops->common->remove(edev);
1456 rte_intr_disable(&pci_dev->intr_handle);
1457 rte_intr_callback_unregister(&pci_dev->intr_handle,
1458 qede_interrupt_handler, (void *)eth_dev);
1459 if (ECORE_IS_CMT(edev))
1460 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1464 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1466 struct qede_dev *qdev = eth_dev->data->dev_private;
1467 struct ecore_dev *edev = &qdev->edev;
1468 struct ecore_eth_stats stats;
1469 unsigned int i = 0, j = 0, qid;
1470 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1471 struct qede_tx_queue *txq;
1473 ecore_get_vport_stats(edev, &stats);
1476 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1477 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1479 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1480 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1482 eth_stats->ierrors = stats.common.rx_crc_errors +
1483 stats.common.rx_align_errors +
1484 stats.common.rx_carrier_errors +
1485 stats.common.rx_oversize_packets +
1486 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1488 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1490 eth_stats->imissed = stats.common.mftag_filter_discards +
1491 stats.common.mac_filter_discards +
1492 stats.common.no_buff_discards +
1493 stats.common.brb_truncates + stats.common.brb_discards;
1496 eth_stats->opackets = stats.common.tx_ucast_pkts +
1497 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1499 eth_stats->obytes = stats.common.tx_ucast_bytes +
1500 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1502 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1505 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1506 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1507 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1508 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1509 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1510 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1511 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1512 "Not all the queue stats will be displayed. Set"
1513 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1514 " appropriately and retry.\n");
1517 eth_stats->q_ipackets[i] =
1519 ((char *)(qdev->fp_array[qid].rxq)) +
1520 offsetof(struct qede_rx_queue,
1522 eth_stats->q_errors[i] =
1524 ((char *)(qdev->fp_array[qid].rxq)) +
1525 offsetof(struct qede_rx_queue,
1528 ((char *)(qdev->fp_array[qid].rxq)) +
1529 offsetof(struct qede_rx_queue,
1532 if (i == rxq_stat_cntrs)
1537 txq = qdev->fp_array[qid].txq;
1538 eth_stats->q_opackets[j] =
1539 *((uint64_t *)(uintptr_t)
1540 (((uint64_t)(uintptr_t)(txq)) +
1541 offsetof(struct qede_tx_queue,
1544 if (j == txq_stat_cntrs)
1552 qede_get_xstats_count(struct qede_dev *qdev) {
1553 if (ECORE_IS_BB(&qdev->edev))
1554 return RTE_DIM(qede_xstats_strings) +
1555 RTE_DIM(qede_bb_xstats_strings) +
1556 (RTE_DIM(qede_rxq_xstats_strings) *
1557 RTE_MIN(QEDE_RSS_COUNT(qdev),
1558 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1560 return RTE_DIM(qede_xstats_strings) +
1561 RTE_DIM(qede_ah_xstats_strings) +
1562 (RTE_DIM(qede_rxq_xstats_strings) *
1563 RTE_MIN(QEDE_RSS_COUNT(qdev),
1564 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1568 qede_get_xstats_names(struct rte_eth_dev *dev,
1569 struct rte_eth_xstat_name *xstats_names,
1570 __rte_unused unsigned int limit)
1572 struct qede_dev *qdev = dev->data->dev_private;
1573 struct ecore_dev *edev = &qdev->edev;
1574 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1575 unsigned int i, qid, stat_idx = 0;
1576 unsigned int rxq_stat_cntrs;
1578 if (xstats_names != NULL) {
1579 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1580 snprintf(xstats_names[stat_idx].name,
1581 sizeof(xstats_names[stat_idx].name),
1583 qede_xstats_strings[i].name);
1587 if (ECORE_IS_BB(edev)) {
1588 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1589 snprintf(xstats_names[stat_idx].name,
1590 sizeof(xstats_names[stat_idx].name),
1592 qede_bb_xstats_strings[i].name);
1596 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1597 snprintf(xstats_names[stat_idx].name,
1598 sizeof(xstats_names[stat_idx].name),
1600 qede_ah_xstats_strings[i].name);
1605 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1606 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1607 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1608 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1609 snprintf(xstats_names[stat_idx].name,
1610 sizeof(xstats_names[stat_idx].name),
1612 qede_rxq_xstats_strings[i].name, qid,
1613 qede_rxq_xstats_strings[i].name + 4);
1623 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1626 struct qede_dev *qdev = dev->data->dev_private;
1627 struct ecore_dev *edev = &qdev->edev;
1628 struct ecore_eth_stats stats;
1629 const unsigned int num = qede_get_xstats_count(qdev);
1630 unsigned int i, qid, stat_idx = 0;
1631 unsigned int rxq_stat_cntrs;
1636 ecore_get_vport_stats(edev, &stats);
1638 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1639 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1640 qede_xstats_strings[i].offset);
1641 xstats[stat_idx].id = stat_idx;
1645 if (ECORE_IS_BB(edev)) {
1646 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1647 xstats[stat_idx].value =
1648 *(uint64_t *)(((char *)&stats) +
1649 qede_bb_xstats_strings[i].offset);
1650 xstats[stat_idx].id = stat_idx;
1654 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1655 xstats[stat_idx].value =
1656 *(uint64_t *)(((char *)&stats) +
1657 qede_ah_xstats_strings[i].offset);
1658 xstats[stat_idx].id = stat_idx;
1663 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1664 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1665 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1667 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1668 xstats[stat_idx].value = *(uint64_t *)(
1669 ((char *)(qdev->fp_array[qid].rxq)) +
1670 qede_rxq_xstats_strings[i].offset);
1671 xstats[stat_idx].id = stat_idx;
1681 qede_reset_xstats(struct rte_eth_dev *dev)
1683 struct qede_dev *qdev = dev->data->dev_private;
1684 struct ecore_dev *edev = &qdev->edev;
1686 ecore_reset_vport_stats(edev);
1689 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1691 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1692 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1693 struct qed_link_params link_params;
1696 DP_INFO(edev, "setting link state %d\n", link_up);
1697 memset(&link_params, 0, sizeof(link_params));
1698 link_params.link_up = link_up;
1699 rc = qdev->ops->common->set_link(edev, &link_params);
1700 if (rc != ECORE_SUCCESS)
1701 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1706 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1708 return qede_dev_set_link_state(eth_dev, true);
1711 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1713 return qede_dev_set_link_state(eth_dev, false);
1716 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1718 struct qede_dev *qdev = eth_dev->data->dev_private;
1719 struct ecore_dev *edev = &qdev->edev;
1721 ecore_reset_vport_stats(edev);
1724 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1726 enum qed_filter_rx_mode_type type =
1727 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1729 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1730 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1732 qed_configure_filter_rx_mode(eth_dev, type);
1735 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1737 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1738 qed_configure_filter_rx_mode(eth_dev,
1739 QED_FILTER_RX_MODE_TYPE_PROMISC);
1741 qed_configure_filter_rx_mode(eth_dev,
1742 QED_FILTER_RX_MODE_TYPE_REGULAR);
1745 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1746 struct rte_eth_fc_conf *fc_conf)
1748 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1749 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1750 struct qed_link_output current_link;
1751 struct qed_link_params params;
1753 memset(¤t_link, 0, sizeof(current_link));
1754 qdev->ops->common->get_link(edev, ¤t_link);
1756 memset(¶ms, 0, sizeof(params));
1757 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1758 if (fc_conf->autoneg) {
1759 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1760 DP_ERR(edev, "Autoneg not supported\n");
1763 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1766 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1767 if (fc_conf->mode == RTE_FC_FULL)
1768 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1769 QED_LINK_PAUSE_RX_ENABLE);
1770 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1771 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1772 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1773 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1775 params.link_up = true;
1776 (void)qdev->ops->common->set_link(edev, ¶ms);
1781 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1782 struct rte_eth_fc_conf *fc_conf)
1784 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1785 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1786 struct qed_link_output current_link;
1788 memset(¤t_link, 0, sizeof(current_link));
1789 qdev->ops->common->get_link(edev, ¤t_link);
1791 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1792 fc_conf->autoneg = true;
1794 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1795 QED_LINK_PAUSE_TX_ENABLE))
1796 fc_conf->mode = RTE_FC_FULL;
1797 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1798 fc_conf->mode = RTE_FC_RX_PAUSE;
1799 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1800 fc_conf->mode = RTE_FC_TX_PAUSE;
1802 fc_conf->mode = RTE_FC_NONE;
1807 static const uint32_t *
1808 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1810 static const uint32_t ptypes[] = {
1816 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1822 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1825 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1826 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1827 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1828 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1829 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1830 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1831 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
1832 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
1835 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1836 struct rte_eth_rss_conf *rss_conf)
1838 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1839 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1840 struct ecore_sp_vport_update_params vport_update_params;
1841 struct ecore_rss_params rss_params;
1842 struct ecore_hwfn *p_hwfn;
1843 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1844 uint64_t hf = rss_conf->rss_hf;
1845 uint8_t len = rss_conf->rss_key_len;
1850 memset(&vport_update_params, 0, sizeof(vport_update_params));
1851 memset(&rss_params, 0, sizeof(rss_params));
1853 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1854 (unsigned long)hf, len, key);
1858 DP_INFO(edev, "Enabling rss\n");
1861 qede_init_rss_caps(&rss_params.rss_caps, hf);
1862 rss_params.update_rss_capabilities = 1;
1866 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1867 DP_ERR(edev, "RSS key length exceeds limit\n");
1870 DP_INFO(edev, "Applying user supplied hash key\n");
1871 rss_params.update_rss_key = 1;
1872 memcpy(&rss_params.rss_key, key, len);
1874 rss_params.rss_enable = 1;
1877 rss_params.update_rss_config = 1;
1878 /* tbl_size has to be set with capabilities */
1879 rss_params.rss_table_size_log = 7;
1880 vport_update_params.vport_id = 0;
1881 /* pass the L2 handles instead of qids */
1882 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1883 idx = qdev->rss_ind_table[i];
1884 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1886 vport_update_params.rss_params = &rss_params;
1888 for_each_hwfn(edev, i) {
1889 p_hwfn = &edev->hwfns[i];
1890 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1891 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1892 ECORE_SPQ_MODE_EBLOCK, NULL);
1894 DP_ERR(edev, "vport-update for RSS failed\n");
1898 qdev->rss_enable = rss_params.rss_enable;
1900 /* Update local structure for hash query */
1901 qdev->rss_conf.rss_hf = hf;
1902 qdev->rss_conf.rss_key_len = len;
1903 if (qdev->rss_enable) {
1904 if (qdev->rss_conf.rss_key == NULL) {
1905 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1906 if (qdev->rss_conf.rss_key == NULL) {
1907 DP_ERR(edev, "No memory to store RSS key\n");
1912 DP_INFO(edev, "Storing RSS key\n");
1913 memcpy(qdev->rss_conf.rss_key, key, len);
1915 } else if (!qdev->rss_enable && len == 0) {
1916 if (qdev->rss_conf.rss_key) {
1917 free(qdev->rss_conf.rss_key);
1918 qdev->rss_conf.rss_key = NULL;
1919 DP_INFO(edev, "Free RSS key\n");
1926 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1927 struct rte_eth_rss_conf *rss_conf)
1929 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1931 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1932 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1934 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1935 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1936 rss_conf->rss_key_len);
1940 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1941 struct ecore_rss_params *rss)
1944 bool rss_mode = 1; /* enable */
1945 struct ecore_queue_cid *cid;
1946 struct ecore_rss_params *t_rss;
1948 /* In regular scenario, we'd simply need to take input handlers.
1949 * But in CMT, we'd have to split the handlers according to the
1950 * engine they were configured on. We'd then have to understand
1951 * whether RSS is really required, since 2-queues on CMT doesn't
1955 /* CMT should be round-robin */
1956 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1957 cid = rss->rss_ind_table[i];
1959 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1964 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
1968 t_rss->update_rss_ind_table = 1;
1969 t_rss->rss_table_size_log = 7;
1970 t_rss->update_rss_config = 1;
1972 /* Make sure RSS is actually required */
1973 for_each_hwfn(edev, fn) {
1974 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
1976 if (rss[fn].rss_ind_table[i] !=
1977 rss[fn].rss_ind_table[0])
1981 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
1983 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1990 t_rss->rss_enable = rss_mode;
1995 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1996 struct rte_eth_rss_reta_entry64 *reta_conf,
1999 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2000 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2001 struct ecore_sp_vport_update_params vport_update_params;
2002 struct ecore_rss_params *params;
2003 struct ecore_hwfn *p_hwfn;
2004 uint16_t i, idx, shift;
2008 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2009 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2014 memset(&vport_update_params, 0, sizeof(vport_update_params));
2015 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2016 RTE_CACHE_LINE_SIZE);
2017 if (params == NULL) {
2018 DP_ERR(edev, "failed to allocate memory\n");
2022 for (i = 0; i < reta_size; i++) {
2023 idx = i / RTE_RETA_GROUP_SIZE;
2024 shift = i % RTE_RETA_GROUP_SIZE;
2025 if (reta_conf[idx].mask & (1ULL << shift)) {
2026 entry = reta_conf[idx].reta[shift];
2027 /* Pass rxq handles to ecore */
2028 params->rss_ind_table[i] =
2029 qdev->fp_array[entry].rxq->handle;
2030 /* Update the local copy for RETA query command */
2031 qdev->rss_ind_table[i] = entry;
2035 params->update_rss_ind_table = 1;
2036 params->rss_table_size_log = 7;
2037 params->update_rss_config = 1;
2039 /* Fix up RETA for CMT mode device */
2040 if (ECORE_IS_CMT(edev))
2041 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2043 vport_update_params.vport_id = 0;
2044 /* Use the current value of rss_enable */
2045 params->rss_enable = qdev->rss_enable;
2046 vport_update_params.rss_params = params;
2048 for_each_hwfn(edev, i) {
2049 p_hwfn = &edev->hwfns[i];
2050 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2051 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2052 ECORE_SPQ_MODE_EBLOCK, NULL);
2054 DP_ERR(edev, "vport-update for RSS failed\n");
2064 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2065 struct rte_eth_rss_reta_entry64 *reta_conf,
2068 struct qede_dev *qdev = eth_dev->data->dev_private;
2069 struct ecore_dev *edev = &qdev->edev;
2070 uint16_t i, idx, shift;
2073 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2074 DP_ERR(edev, "reta_size %d is not supported\n",
2079 for (i = 0; i < reta_size; i++) {
2080 idx = i / RTE_RETA_GROUP_SIZE;
2081 shift = i % RTE_RETA_GROUP_SIZE;
2082 if (reta_conf[idx].mask & (1ULL << shift)) {
2083 entry = qdev->rss_ind_table[i];
2084 reta_conf[idx].reta[shift] = entry;
2093 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2095 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2096 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2097 struct rte_eth_dev_info dev_info = {0};
2098 struct qede_fastpath *fp;
2099 uint32_t frame_size;
2100 uint16_t rx_buf_size;
2104 PMD_INIT_FUNC_TRACE(edev);
2105 qede_dev_info_get(dev, &dev_info);
2106 frame_size = mtu + QEDE_ETH_OVERHEAD;
2107 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2108 DP_ERR(edev, "MTU %u out of range\n", mtu);
2111 if (!dev->data->scattered_rx &&
2112 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2113 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2114 dev->data->min_rx_buf_size);
2117 /* Temporarily replace I/O functions with dummy ones. It cannot
2118 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2120 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2121 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2125 /* Fix up RX buf size for all queues of the port */
2127 fp = &qdev->fp_array[i];
2128 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2129 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2130 if (dev->data->scattered_rx)
2131 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2133 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2134 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2135 fp->rxq->rx_buf_size = rx_buf_size;
2136 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2138 qede_dev_start(dev);
2139 if (frame_size > ETHER_MAX_LEN)
2140 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2142 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2143 /* update max frame size */
2144 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2146 dev->rx_pkt_burst = qede_recv_pkts;
2147 dev->tx_pkt_burst = qede_xmit_pkts;
2153 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2154 struct rte_eth_udp_tunnel *tunnel_udp,
2157 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2158 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2159 struct ecore_tunnel_info tunn; /* @DPDK */
2160 struct ecore_hwfn *p_hwfn;
2163 PMD_INIT_FUNC_TRACE(edev);
2165 memset(&tunn, 0, sizeof(tunn));
2166 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2167 tunn.vxlan_port.b_update_port = true;
2168 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
2169 QEDE_VXLAN_DEF_PORT;
2170 for_each_hwfn(edev, i) {
2171 p_hwfn = &edev->hwfns[i];
2172 struct ecore_ptt *p_ptt = IS_PF(edev) ?
2173 ecore_ptt_acquire(p_hwfn) : NULL;
2174 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2175 ECORE_SPQ_MODE_CB, NULL);
2176 if (rc != ECORE_SUCCESS) {
2177 DP_ERR(edev, "Unable to config UDP port %u\n",
2178 tunn.vxlan_port.port);
2180 ecore_ptt_release(p_hwfn, p_ptt);
2190 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2191 struct rte_eth_udp_tunnel *tunnel_udp)
2193 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2197 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2198 struct rte_eth_udp_tunnel *tunnel_udp)
2200 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2203 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2204 uint32_t *clss, char *str)
2207 *clss = MAX_ECORE_TUNN_CLSS;
2209 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2210 if (filter == qede_tunn_types[j].rte_filter_type) {
2211 *type = qede_tunn_types[j].qede_type;
2212 *clss = qede_tunn_types[j].qede_tunn_clss;
2213 strcpy(str, qede_tunn_types[j].string);
2220 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2221 const struct rte_eth_tunnel_filter_conf *conf,
2224 /* Init commmon ucast params first */
2225 qede_set_ucast_cmn_params(ucast);
2227 /* Copy out the required fields based on classification type */
2231 case ECORE_FILTER_VNI:
2232 ucast->vni = conf->tenant_id;
2234 case ECORE_FILTER_INNER_VLAN:
2235 ucast->vlan = conf->inner_vlan;
2237 case ECORE_FILTER_MAC:
2238 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2241 case ECORE_FILTER_INNER_MAC:
2242 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2245 case ECORE_FILTER_MAC_VNI_PAIR:
2246 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2248 ucast->vni = conf->tenant_id;
2250 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2251 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2253 ucast->vni = conf->tenant_id;
2255 case ECORE_FILTER_INNER_PAIR:
2256 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2258 ucast->vlan = conf->inner_vlan;
2264 return ECORE_SUCCESS;
2267 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2268 enum rte_filter_op filter_op,
2269 const struct rte_eth_tunnel_filter_conf *conf)
2271 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2272 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2273 struct ecore_tunnel_info tunn;
2274 struct ecore_hwfn *p_hwfn;
2275 enum ecore_filter_ucast_type type;
2276 enum ecore_tunn_clss clss;
2277 struct ecore_filter_ucast ucast;
2279 uint16_t filter_type;
2282 PMD_INIT_FUNC_TRACE(edev);
2284 filter_type = conf->filter_type | qdev->vxlan_filter_type;
2285 /* First determine if the given filter classification is supported */
2286 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2287 if (clss == MAX_ECORE_TUNN_CLSS) {
2288 DP_ERR(edev, "Wrong filter type\n");
2291 /* Init tunnel ucast params */
2292 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2293 if (rc != ECORE_SUCCESS) {
2294 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2298 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2299 str, filter_op, ucast.type);
2300 switch (filter_op) {
2301 case RTE_ETH_FILTER_ADD:
2302 ucast.opcode = ECORE_FILTER_ADD;
2304 /* Skip MAC/VLAN if filter is based on VNI */
2305 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2306 rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2308 /* Enable accept anyvlan */
2309 qede_config_accept_any_vlan(qdev, true);
2312 rc = qede_ucast_filter(eth_dev, &ucast, 1);
2314 rc = ecore_filter_ucast_cmd(edev, &ucast,
2315 ECORE_SPQ_MODE_CB, NULL);
2318 if (rc != ECORE_SUCCESS)
2321 qdev->vxlan_filter_type = filter_type;
2323 DP_INFO(edev, "Enabling VXLAN tunneling\n");
2324 qede_set_cmn_tunn_param(&tunn, clss, true, true);
2325 for_each_hwfn(edev, i) {
2326 p_hwfn = &edev->hwfns[i];
2327 struct ecore_ptt *p_ptt = IS_PF(edev) ?
2328 ecore_ptt_acquire(p_hwfn) : NULL;
2329 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
2330 &tunn, ECORE_SPQ_MODE_CB, NULL);
2331 if (rc != ECORE_SUCCESS) {
2332 DP_ERR(edev, "Failed to update tunn_clss %u\n",
2333 tunn.vxlan.tun_cls);
2335 ecore_ptt_release(p_hwfn, p_ptt);
2338 qdev->num_tunn_filters++; /* Filter added successfully */
2340 case RTE_ETH_FILTER_DELETE:
2341 ucast.opcode = ECORE_FILTER_REMOVE;
2343 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2344 rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2346 rc = qede_ucast_filter(eth_dev, &ucast, 0);
2348 rc = ecore_filter_ucast_cmd(edev, &ucast,
2349 ECORE_SPQ_MODE_CB, NULL);
2351 if (rc != ECORE_SUCCESS)
2354 qdev->vxlan_filter_type = filter_type;
2355 qdev->num_tunn_filters--;
2357 /* Disable VXLAN if VXLAN filters become 0 */
2358 if (qdev->num_tunn_filters == 0) {
2359 DP_INFO(edev, "Disabling VXLAN tunneling\n");
2361 /* Use 0 as tunnel mode */
2362 qede_set_cmn_tunn_param(&tunn, clss, false, true);
2363 for_each_hwfn(edev, i) {
2364 p_hwfn = &edev->hwfns[i];
2365 struct ecore_ptt *p_ptt = IS_PF(edev) ?
2366 ecore_ptt_acquire(p_hwfn) : NULL;
2367 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
2368 &tunn, ECORE_SPQ_MODE_CB, NULL);
2369 if (rc != ECORE_SUCCESS) {
2371 "Failed to update tunn_clss %u\n",
2372 tunn.vxlan.tun_cls);
2374 ecore_ptt_release(p_hwfn,
2382 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2385 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
2390 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2391 enum rte_filter_type filter_type,
2392 enum rte_filter_op filter_op,
2395 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2396 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2397 struct rte_eth_tunnel_filter_conf *filter_conf =
2398 (struct rte_eth_tunnel_filter_conf *)arg;
2400 switch (filter_type) {
2401 case RTE_ETH_FILTER_TUNNEL:
2402 switch (filter_conf->tunnel_type) {
2403 case RTE_TUNNEL_TYPE_VXLAN:
2405 "Packet steering to the specified Rx queue"
2406 " is not supported with VXLAN tunneling");
2407 return(qede_vxlan_tunn_config(eth_dev, filter_op,
2409 /* Place holders for future tunneling support */
2410 case RTE_TUNNEL_TYPE_GENEVE:
2411 case RTE_TUNNEL_TYPE_TEREDO:
2412 case RTE_TUNNEL_TYPE_NVGRE:
2413 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2414 case RTE_L2_TUNNEL_TYPE_E_TAG:
2415 DP_ERR(edev, "Unsupported tunnel type %d\n",
2416 filter_conf->tunnel_type);
2418 case RTE_TUNNEL_TYPE_NONE:
2423 case RTE_ETH_FILTER_FDIR:
2424 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2425 case RTE_ETH_FILTER_NTUPLE:
2426 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2427 case RTE_ETH_FILTER_MACVLAN:
2428 case RTE_ETH_FILTER_ETHERTYPE:
2429 case RTE_ETH_FILTER_FLEXIBLE:
2430 case RTE_ETH_FILTER_SYN:
2431 case RTE_ETH_FILTER_HASH:
2432 case RTE_ETH_FILTER_L2_TUNNEL:
2433 case RTE_ETH_FILTER_MAX:
2435 DP_ERR(edev, "Unsupported filter type %d\n",
2443 static const struct eth_dev_ops qede_eth_dev_ops = {
2444 .dev_configure = qede_dev_configure,
2445 .dev_infos_get = qede_dev_info_get,
2446 .rx_queue_setup = qede_rx_queue_setup,
2447 .rx_queue_release = qede_rx_queue_release,
2448 .tx_queue_setup = qede_tx_queue_setup,
2449 .tx_queue_release = qede_tx_queue_release,
2450 .dev_start = qede_dev_start,
2451 .dev_set_link_up = qede_dev_set_link_up,
2452 .dev_set_link_down = qede_dev_set_link_down,
2453 .link_update = qede_link_update,
2454 .promiscuous_enable = qede_promiscuous_enable,
2455 .promiscuous_disable = qede_promiscuous_disable,
2456 .allmulticast_enable = qede_allmulticast_enable,
2457 .allmulticast_disable = qede_allmulticast_disable,
2458 .dev_stop = qede_dev_stop,
2459 .dev_close = qede_dev_close,
2460 .stats_get = qede_get_stats,
2461 .stats_reset = qede_reset_stats,
2462 .xstats_get = qede_get_xstats,
2463 .xstats_reset = qede_reset_xstats,
2464 .xstats_get_names = qede_get_xstats_names,
2465 .mac_addr_add = qede_mac_addr_add,
2466 .mac_addr_remove = qede_mac_addr_remove,
2467 .mac_addr_set = qede_mac_addr_set,
2468 .vlan_offload_set = qede_vlan_offload_set,
2469 .vlan_filter_set = qede_vlan_filter_set,
2470 .flow_ctrl_set = qede_flow_ctrl_set,
2471 .flow_ctrl_get = qede_flow_ctrl_get,
2472 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2473 .rss_hash_update = qede_rss_hash_update,
2474 .rss_hash_conf_get = qede_rss_hash_conf_get,
2475 .reta_update = qede_rss_reta_update,
2476 .reta_query = qede_rss_reta_query,
2477 .mtu_set = qede_set_mtu,
2478 .filter_ctrl = qede_dev_filter_ctrl,
2479 .udp_tunnel_port_add = qede_udp_dst_port_add,
2480 .udp_tunnel_port_del = qede_udp_dst_port_del,
2483 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2484 .dev_configure = qede_dev_configure,
2485 .dev_infos_get = qede_dev_info_get,
2486 .rx_queue_setup = qede_rx_queue_setup,
2487 .rx_queue_release = qede_rx_queue_release,
2488 .tx_queue_setup = qede_tx_queue_setup,
2489 .tx_queue_release = qede_tx_queue_release,
2490 .dev_start = qede_dev_start,
2491 .dev_set_link_up = qede_dev_set_link_up,
2492 .dev_set_link_down = qede_dev_set_link_down,
2493 .link_update = qede_link_update,
2494 .promiscuous_enable = qede_promiscuous_enable,
2495 .promiscuous_disable = qede_promiscuous_disable,
2496 .allmulticast_enable = qede_allmulticast_enable,
2497 .allmulticast_disable = qede_allmulticast_disable,
2498 .dev_stop = qede_dev_stop,
2499 .dev_close = qede_dev_close,
2500 .stats_get = qede_get_stats,
2501 .stats_reset = qede_reset_stats,
2502 .xstats_get = qede_get_xstats,
2503 .xstats_reset = qede_reset_xstats,
2504 .xstats_get_names = qede_get_xstats_names,
2505 .vlan_offload_set = qede_vlan_offload_set,
2506 .vlan_filter_set = qede_vlan_filter_set,
2507 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2508 .rss_hash_update = qede_rss_hash_update,
2509 .rss_hash_conf_get = qede_rss_hash_conf_get,
2510 .reta_update = qede_rss_reta_update,
2511 .reta_query = qede_rss_reta_query,
2512 .mtu_set = qede_set_mtu,
2515 static void qede_update_pf_params(struct ecore_dev *edev)
2517 struct ecore_pf_params pf_params;
2519 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2520 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2521 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2522 qed_ops->common->update_pf_params(edev, &pf_params);
2525 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2527 struct rte_pci_device *pci_dev;
2528 struct rte_pci_addr pci_addr;
2529 struct qede_dev *adapter;
2530 struct ecore_dev *edev;
2531 struct qed_dev_eth_info dev_info;
2532 struct qed_slowpath_params params;
2533 static bool do_once = true;
2534 uint8_t bulletin_change;
2535 uint8_t vf_mac[ETHER_ADDR_LEN];
2536 uint8_t is_mac_forced;
2538 /* Fix up ecore debug level */
2539 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2540 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2543 /* Extract key data structures */
2544 adapter = eth_dev->data->dev_private;
2545 edev = &adapter->edev;
2546 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2547 pci_addr = pci_dev->addr;
2549 PMD_INIT_FUNC_TRACE(edev);
2551 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2552 pci_addr.bus, pci_addr.devid, pci_addr.function,
2553 eth_dev->data->port_id);
2555 eth_dev->rx_pkt_burst = qede_recv_pkts;
2556 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2557 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2559 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2560 DP_ERR(edev, "Skipping device init from secondary process\n");
2564 rte_eth_copy_pci_info(eth_dev, pci_dev);
2567 edev->vendor_id = pci_dev->id.vendor_id;
2568 edev->device_id = pci_dev->id.device_id;
2570 qed_ops = qed_get_eth_ops();
2572 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2576 DP_INFO(edev, "Starting qede probe\n");
2577 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2580 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2583 qede_update_pf_params(edev);
2584 rte_intr_callback_register(&pci_dev->intr_handle,
2585 qede_interrupt_handler, (void *)eth_dev);
2586 if (rte_intr_enable(&pci_dev->intr_handle)) {
2587 DP_ERR(edev, "rte_intr_enable() failed\n");
2591 /* Start the Slowpath-process */
2592 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2593 params.int_mode = ECORE_INT_MODE_MSIX;
2594 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2595 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2596 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2597 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2598 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2599 QEDE_PMD_DRV_VER_STR_SIZE);
2601 /* For CMT mode device do periodic polling for slowpath events.
2602 * This is required since uio device uses only one MSI-x
2603 * interrupt vector but we need one for each engine.
2605 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2606 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2610 DP_ERR(edev, "Unable to start periodic"
2611 " timer rc %d\n", rc);
2616 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2618 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2619 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2624 rc = qed_ops->fill_dev_info(edev, &dev_info);
2626 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2627 qed_ops->common->slowpath_stop(edev);
2628 qed_ops->common->remove(edev);
2629 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2634 qede_alloc_etherdev(adapter, &dev_info);
2636 adapter->ops->common->set_name(edev, edev->name);
2639 adapter->dev_info.num_mac_filters =
2640 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2643 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2644 (uint32_t *)&adapter->dev_info.num_mac_filters);
2646 /* Allocate memory for storing MAC addr */
2647 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2649 adapter->dev_info.num_mac_filters),
2650 RTE_CACHE_LINE_SIZE);
2652 if (eth_dev->data->mac_addrs == NULL) {
2653 DP_ERR(edev, "Failed to allocate MAC address\n");
2654 qed_ops->common->slowpath_stop(edev);
2655 qed_ops->common->remove(edev);
2656 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2662 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2663 hw_info.hw_mac_addr,
2664 ð_dev->data->mac_addrs[0]);
2665 ether_addr_copy(ð_dev->data->mac_addrs[0],
2666 &adapter->primary_mac);
2668 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2670 if (bulletin_change) {
2672 ecore_vf_bulletin_get_forced_mac(
2673 ECORE_LEADING_HWFN(edev),
2676 if (is_mac_exist && is_mac_forced) {
2677 DP_INFO(edev, "VF macaddr received from PF\n");
2678 ether_addr_copy((struct ether_addr *)&vf_mac,
2679 ð_dev->data->mac_addrs[0]);
2680 ether_addr_copy(ð_dev->data->mac_addrs[0],
2681 &adapter->primary_mac);
2683 DP_ERR(edev, "No VF macaddr assigned\n");
2688 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2691 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2692 qede_print_adapter_info(adapter);
2697 adapter->num_tx_queues = 0;
2698 adapter->num_rx_queues = 0;
2699 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2700 SLIST_INIT(&adapter->vlan_list_head);
2701 SLIST_INIT(&adapter->uc_list_head);
2702 adapter->mtu = ETHER_MTU;
2703 adapter->new_mtu = ETHER_MTU;
2705 if (qede_start_vport(adapter, adapter->mtu))
2708 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2709 adapter->primary_mac.addr_bytes[0],
2710 adapter->primary_mac.addr_bytes[1],
2711 adapter->primary_mac.addr_bytes[2],
2712 adapter->primary_mac.addr_bytes[3],
2713 adapter->primary_mac.addr_bytes[4],
2714 adapter->primary_mac.addr_bytes[5]);
2716 DP_INFO(edev, "Device initialized\n");
2721 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2723 return qede_common_dev_init(eth_dev, 1);
2726 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2728 return qede_common_dev_init(eth_dev, 0);
2731 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2733 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2734 struct qede_dev *qdev = eth_dev->data->dev_private;
2735 struct ecore_dev *edev = &qdev->edev;
2737 PMD_INIT_FUNC_TRACE(edev);
2740 /* only uninitialize in the primary process */
2741 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2744 /* safe to close dev here */
2745 qede_dev_close(eth_dev);
2747 eth_dev->dev_ops = NULL;
2748 eth_dev->rx_pkt_burst = NULL;
2749 eth_dev->tx_pkt_burst = NULL;
2751 if (eth_dev->data->mac_addrs)
2752 rte_free(eth_dev->data->mac_addrs);
2754 eth_dev->data->mac_addrs = NULL;
2759 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2761 return qede_dev_common_uninit(eth_dev);
2764 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2766 return qede_dev_common_uninit(eth_dev);
2769 static const struct rte_pci_id pci_id_qedevf_map[] = {
2770 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2772 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2775 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2778 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2783 static const struct rte_pci_id pci_id_qede_map[] = {
2784 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2786 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2789 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2792 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2795 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2798 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2801 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2804 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2807 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2810 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2813 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2818 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2819 struct rte_pci_device *pci_dev)
2821 return rte_eth_dev_pci_generic_probe(pci_dev,
2822 sizeof(struct qede_dev), qedevf_eth_dev_init);
2825 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2827 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2830 static struct rte_pci_driver rte_qedevf_pmd = {
2831 .id_table = pci_id_qedevf_map,
2832 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2833 .probe = qedevf_eth_dev_pci_probe,
2834 .remove = qedevf_eth_dev_pci_remove,
2837 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2838 struct rte_pci_device *pci_dev)
2840 return rte_eth_dev_pci_generic_probe(pci_dev,
2841 sizeof(struct qede_dev), qede_eth_dev_init);
2844 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2846 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2849 static struct rte_pci_driver rte_qede_pmd = {
2850 .id_table = pci_id_qede_map,
2851 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2852 .probe = qede_eth_dev_pci_probe,
2853 .remove = qede_eth_dev_pci_remove,
2856 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2857 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2858 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2859 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2860 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2861 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");