2 * Copyright (c) 2016 - 2018 Cavium Inc.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #ifndef _QEDE_ETHDEV_H_
11 #define _QEDE_ETHDEV_H_
13 #include <sys/queue.h>
15 #include <rte_ether.h>
16 #include <rte_ethdev_driver.h>
17 #include <rte_ethdev_pci.h>
22 #include "base/bcm_osal.h"
23 #include "base/ecore.h"
24 #include "base/ecore_dev_api.h"
25 #include "base/ecore_l2_api.h"
26 #include "base/ecore_vf_api.h"
27 #include "base/ecore_hsi_common.h"
28 #include "base/ecore_int_api.h"
29 #include "base/ecore_chain.h"
30 #include "base/ecore_status.h"
31 #include "base/ecore_hsi_eth.h"
32 #include "base/ecore_iov_api.h"
33 #include "base/ecore_cxt.h"
34 #include "base/nvm_cfg.h"
35 #include "base/ecore_sp_commands.h"
36 #include "base/ecore_l2.h"
37 #include "base/ecore_vf.h"
39 #include "qede_logs.h"
41 #include "qede_rxtx.h"
43 #define qede_stringify1(x...) #x
44 #define qede_stringify(x...) qede_stringify1(x)
47 #define QEDE_PMD_VER_PREFIX "QEDE PMD"
48 #define QEDE_PMD_VERSION_MAJOR 2
49 #define QEDE_PMD_VERSION_MINOR 8
50 #define QEDE_PMD_VERSION_REVISION 0
51 #define QEDE_PMD_VERSION_PATCH 1
53 #define QEDE_PMD_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \
54 qede_stringify(QEDE_PMD_VERSION_MINOR) "." \
55 qede_stringify(QEDE_PMD_VERSION_REVISION) "." \
56 qede_stringify(QEDE_PMD_VERSION_PATCH)
58 #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE
59 #define QEDE_PMD_VER_PREFIX "QEDE PMD"
62 #define QEDE_RSS_INDIR_INITED (1 << 0)
63 #define QEDE_RSS_KEY_INITED (1 << 1)
64 #define QEDE_RSS_CAPS_INITED (1 << 2)
66 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
67 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
68 (edev)->dev_info.num_tc)
70 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues)
71 #define QEDE_RSS_COUNT(qdev) ((qdev)->num_rx_queues)
72 #define QEDE_TSS_COUNT(qdev) ((qdev)->num_tx_queues)
74 #define QEDE_DUPLEX_FULL 1
75 #define QEDE_DUPLEX_HALF 2
76 #define QEDE_DUPLEX_UNKNOWN 0xff
78 #define QEDE_SUPPORTED_AUTONEG (1 << 6)
79 #define QEDE_SUPPORTED_PAUSE (1 << 13)
81 #define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private)
83 #define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev)
85 #define QEDE_INIT(eth_dev) { \
86 struct qede_dev *qdev = eth_dev->data->dev_private; \
87 struct ecore_dev *edev = &qdev->edev; \
90 /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
91 #define PCI_VENDOR_ID_QLOGIC 0x1077
93 #define CHIP_NUM_57980E 0x1634
94 #define CHIP_NUM_57980S 0x1629
95 #define CHIP_NUM_VF 0x1630
96 #define CHIP_NUM_57980S_40 0x1634
97 #define CHIP_NUM_57980S_25 0x1656
98 #define CHIP_NUM_57980S_IOV 0x1664
99 #define CHIP_NUM_57980S_100 0x1644
100 #define CHIP_NUM_57980S_50 0x1654
101 #define CHIP_NUM_AH_50G 0x8070
102 #define CHIP_NUM_AH_10G 0x8071
103 #define CHIP_NUM_AH_40G 0x8072
104 #define CHIP_NUM_AH_25G 0x8073
105 #define CHIP_NUM_AH_IOV 0x8090
107 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E
108 #define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S
109 #define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF
110 #define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40
111 #define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
112 #define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
113 #define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
114 #define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50
115 #define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
116 #define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
117 #define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
118 #define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G
119 #define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV
123 extern char fw_file[];
125 /* Number of PF connections - 32 RX + 32 TX */
126 #define QEDE_PF_NUM_CONNS (64)
128 /* Maximum number of flowdir filters */
129 #define QEDE_RFS_MAX_FLTR (256)
131 #define QEDE_MAX_MCAST_FILTERS (64)
133 enum qed_filter_rx_mode_type {
134 QED_FILTER_RX_MODE_TYPE_REGULAR,
135 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC,
136 QED_FILTER_RX_MODE_TYPE_PROMISC,
139 struct qede_vlan_entry {
140 SLIST_ENTRY(qede_vlan_entry) list;
144 struct qede_mcast_entry {
145 struct ether_addr mac;
146 SLIST_ENTRY(qede_mcast_entry) list;
149 struct qede_ucast_entry {
150 struct ether_addr mac;
153 SLIST_ENTRY(qede_ucast_entry) list;
156 struct qede_fdir_entry {
157 uint32_t soft_id; /* unused for now */
158 uint16_t pkt_len; /* actual packet length to match */
159 uint16_t rx_queue; /* queue to be steered to */
160 const struct rte_memzone *mz; /* mz used to hold L2 frame */
161 SLIST_ENTRY(qede_fdir_entry) list;
164 struct qede_fdir_info {
165 struct ecore_arfs_config_params arfs;
166 uint16_t filter_count;
167 SLIST_HEAD(fdir_list_head, qede_fdir_entry)fdir_list_head;
170 /* IANA assigned default UDP ports for encapsulation protocols */
171 #define QEDE_VXLAN_DEF_PORT (4789)
172 #define QEDE_GENEVE_DEF_PORT (6081)
174 struct qede_tunn_params {
176 uint16_t num_filters;
177 uint16_t filter_type;
182 * Structure to store private data for each port.
185 struct ecore_dev edev;
186 const struct qed_eth_ops *ops;
187 struct qed_dev_eth_info dev_info;
188 struct ecore_sb_info *sb_array;
189 struct qede_fastpath *fp_array;
191 bool enable_tx_switching;
193 struct rte_eth_rss_conf rss_conf;
194 uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
198 uint8_t num_rx_queues;
199 uint8_t num_tx_queues;
200 SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head;
201 uint16_t configured_vlans;
202 bool accept_any_vlan;
203 struct ether_addr primary_mac;
204 SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head;
205 uint16_t num_mc_addr;
206 SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head;
207 uint16_t num_uc_addr;
209 struct qede_tunn_params vxlan;
210 struct qede_tunn_params geneve;
211 struct qede_tunn_params ipgre;
212 struct qede_fdir_info fdir_info;
214 char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
216 int vlan_offload_mask;
220 /* Non-static functions */
221 int qede_config_rss(struct rte_eth_dev *eth_dev);
223 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
224 struct rte_eth_rss_conf *rss_conf);
226 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
227 struct rte_eth_rss_reta_entry64 *reta_conf,
230 int qed_fill_eth_dev_info(struct ecore_dev *edev,
231 struct qed_dev_eth_info *info);
232 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);
234 int qede_link_update(struct rte_eth_dev *eth_dev,
235 __rte_unused int wait_to_complete);
237 int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
238 enum rte_filter_op op, void *arg);
240 int qede_fdir_filter_conf(struct rte_eth_dev *eth_dev,
241 enum rte_filter_op filter_op, void *arg);
243 int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
244 enum rte_filter_op filter_op, void *arg);
246 int qede_check_fdir_support(struct rte_eth_dev *eth_dev);
248 uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
249 struct rte_eth_fdir_filter *fdir,
251 struct ecore_arfs_config_params *params);
253 void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);
255 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg);
257 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);
259 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg);
261 #endif /* _QEDE_ETHDEV_H_ */