1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 #include <rte_string_fns.h>
12 #include "eal_firmware.h"
14 #include "qede_ethdev.h"
15 /* ######### DEBUG ###########*/
16 #include "qede_debug.h"
19 #define QEDE_ALARM_TIMEOUT_US 100000
21 /* Global variable to hold absolute path of fw file */
22 char qede_fw_file[PATH_MAX];
24 static const char * const QEDE_DEFAULT_FIRMWARE =
25 "/lib/firmware/qed/qed_init_values-8.40.33.0.bin";
28 qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)
32 for (i = 0; i < edev->num_hwfns; i++) {
33 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
34 p_hwfn->pf_params = *params;
38 static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)
40 edev->regview = pci_dev->mem_resource[0].addr;
41 edev->doorbells = pci_dev->mem_resource[2].addr;
42 edev->db_size = pci_dev->mem_resource[2].len;
43 edev->pci_dev = pci_dev;
47 qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,
48 uint32_t dp_module, uint8_t dp_level, bool is_vf)
50 struct ecore_hw_prepare_params hw_prepare_params;
53 ecore_init_struct(edev);
54 edev->drv_type = DRV_ID_DRV_TYPE_LINUX;
55 /* Protocol type is always fixed to PROTOCOL_ETH */
60 ecore_init_dp(edev, dp_module, dp_level, NULL);
61 qed_init_pci(edev, pci_dev);
63 memset(&hw_prepare_params, 0, sizeof(hw_prepare_params));
66 hw_prepare_params.acquire_retry_cnt = ECORE_VF_ACQUIRE_THRESH;
68 hw_prepare_params.personality = ECORE_PCI_ETH;
69 hw_prepare_params.drv_resc_alloc = false;
70 hw_prepare_params.chk_reg_fifo = false;
71 hw_prepare_params.initiate_pf_flr = true;
72 hw_prepare_params.allow_mdump = false;
73 hw_prepare_params.b_en_pacing = false;
74 hw_prepare_params.epoch = OSAL_GET_EPOCH(ECORE_LEADING_HWFN(edev));
75 rc = ecore_hw_prepare(edev, &hw_prepare_params);
77 DP_ERR(edev, "hw prepare failed\n");
84 static int qed_nic_setup(struct ecore_dev *edev)
88 rc = ecore_resc_alloc(edev);
92 DP_INFO(edev, "Allocated qed resources\n");
93 ecore_resc_setup(edev);
98 #ifdef CONFIG_ECORE_ZIPPED_FW
99 static int qed_alloc_stream_mem(struct ecore_dev *edev)
103 for_each_hwfn(edev, i) {
104 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
106 p_hwfn->stream = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
107 sizeof(*p_hwfn->stream));
115 static void qed_free_stream_mem(struct ecore_dev *edev)
119 for_each_hwfn(edev, i) {
120 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
125 OSAL_FREE(p_hwfn->p_dev, p_hwfn->stream);
130 #ifdef CONFIG_ECORE_BINARY_FW
131 static int qed_load_firmware_data(struct ecore_dev *edev)
133 const char *fw = RTE_LIBRTE_QEDE_FW;
138 if (strcmp(fw, "") == 0)
139 strcpy(qede_fw_file, QEDE_DEFAULT_FIRMWARE);
141 strcpy(qede_fw_file, fw);
143 if (rte_firmware_read(qede_fw_file, &buf, &bufsz) < 0) {
144 DP_ERR(edev, "Can't read firmware data: %s\n", qede_fw_file);
148 edev->firmware = rte_zmalloc("qede_fw", bufsz, RTE_CACHE_LINE_SIZE);
149 if (!edev->firmware) {
150 DP_ERR(edev, "Can't allocate memory for firmware\n");
155 memcpy(edev->firmware, buf, bufsz);
156 edev->fw_len = bufsz;
157 if (edev->fw_len < 104) {
158 DP_ERR(edev, "Invalid fw size: %" PRIu64 "\n",
170 static void qed_handle_bulletin_change(struct ecore_hwfn *hwfn)
172 uint8_t mac[ETH_ALEN], is_mac_exist, is_mac_forced;
174 is_mac_exist = ecore_vf_bulletin_get_forced_mac(hwfn, mac,
176 if (is_mac_exist && is_mac_forced)
177 rte_memcpy(hwfn->hw_info.hw_mac_addr, mac, ETH_ALEN);
179 /* Always update link configuration according to bulletin */
180 qed_link_update(hwfn);
183 static void qede_vf_task(void *arg)
185 struct ecore_hwfn *p_hwfn = arg;
188 /* Read the bulletin board, and re-schedule the task */
189 ecore_vf_read_bulletin(p_hwfn, &change);
191 qed_handle_bulletin_change(p_hwfn);
193 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task, p_hwfn);
196 static void qed_start_iov_task(struct ecore_dev *edev)
198 struct ecore_hwfn *p_hwfn;
201 for_each_hwfn(edev, i) {
202 p_hwfn = &edev->hwfns[i];
204 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task,
209 static void qed_stop_iov_task(struct ecore_dev *edev)
211 struct ecore_hwfn *p_hwfn;
214 for_each_hwfn(edev, i) {
215 p_hwfn = &edev->hwfns[i];
217 rte_eal_alarm_cancel(qed_iov_pf_task, p_hwfn);
219 rte_eal_alarm_cancel(qede_vf_task, p_hwfn);
222 static int qed_slowpath_start(struct ecore_dev *edev,
223 struct qed_slowpath_params *params)
225 struct ecore_drv_load_params drv_load_params;
226 struct ecore_hw_init_params hw_init_params;
227 struct ecore_mcp_drv_version drv_version;
228 const uint8_t *data = NULL;
229 struct ecore_hwfn *hwfn;
230 struct ecore_ptt *p_ptt;
234 #ifdef CONFIG_ECORE_BINARY_FW
235 rc = qed_load_firmware_data(edev);
237 DP_ERR(edev, "Failed to find fw file %s\n",
242 hwfn = ECORE_LEADING_HWFN(edev);
243 if (edev->num_hwfns == 1) { /* skip aRFS for 100G device */
244 p_ptt = ecore_ptt_acquire(hwfn);
246 ECORE_LEADING_HWFN(edev)->p_arfs_ptt = p_ptt;
248 DP_ERR(edev, "Failed to acquire PTT for flowdir\n");
255 rc = qed_nic_setup(edev);
259 /* set int_coalescing_mode */
260 edev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE;
262 #ifdef CONFIG_ECORE_ZIPPED_FW
264 /* Allocate stream for unzipping */
265 rc = qed_alloc_stream_mem(edev);
267 DP_ERR(edev, "Failed to allocate stream memory\n");
273 qed_start_iov_task(edev);
275 #ifdef CONFIG_ECORE_BINARY_FW
277 data = (const uint8_t *)edev->firmware + sizeof(u32);
279 /* ############### DEBUG ################## */
280 qed_dbg_pf_init(edev);
285 /* Start the slowpath */
286 memset(&hw_init_params, 0, sizeof(hw_init_params));
287 hw_init_params.b_hw_start = true;
288 hw_init_params.int_mode = params->int_mode;
289 hw_init_params.allow_npar_tx_switch = true;
290 hw_init_params.bin_fw_data = data;
292 memset(&drv_load_params, 0, sizeof(drv_load_params));
293 drv_load_params.mfw_timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
294 drv_load_params.avoid_eng_reset = false;
295 drv_load_params.override_force_load = ECORE_OVERRIDE_FORCE_LOAD_ALWAYS;
296 hw_init_params.avoid_eng_affin = false;
297 hw_init_params.p_drv_load_params = &drv_load_params;
299 rc = ecore_hw_init(edev, &hw_init_params);
301 DP_ERR(edev, "ecore_hw_init failed\n");
305 DP_INFO(edev, "HW inited and function started\n");
308 hwfn = ECORE_LEADING_HWFN(edev);
309 drv_version.version = (params->drv_major << 24) |
310 (params->drv_minor << 16) |
311 (params->drv_rev << 8) | (params->drv_eng);
312 strlcpy((char *)drv_version.name, (const char *)params->name,
313 sizeof(drv_version.name));
314 rc = ecore_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
317 DP_ERR(edev, "Failed sending drv version command\n");
322 ecore_reset_vport_stats(edev);
329 qed_stop_iov_task(edev);
330 #ifdef CONFIG_ECORE_ZIPPED_FW
331 qed_free_stream_mem(edev);
334 ecore_resc_free(edev);
336 #ifdef CONFIG_ECORE_BINARY_FW
339 rte_free(edev->firmware);
340 edev->firmware = NULL;
343 qed_stop_iov_task(edev);
349 qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
351 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(edev);
352 struct ecore_ptt *ptt = NULL;
353 struct ecore_tunnel_info *tun = &edev->tunnel;
355 memset(dev_info, 0, sizeof(struct qed_dev_info));
357 if (tun->vxlan.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
358 tun->vxlan.b_mode_enabled)
359 dev_info->vxlan_enable = true;
361 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
362 tun->l2_gre.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
363 tun->ip_gre.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN)
364 dev_info->gre_enable = true;
366 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
367 tun->l2_geneve.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
368 tun->ip_geneve.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN)
369 dev_info->geneve_enable = true;
371 dev_info->num_hwfns = edev->num_hwfns;
372 dev_info->is_mf_default = IS_MF_DEFAULT(&edev->hwfns[0]);
373 dev_info->mtu = ECORE_LEADING_HWFN(edev)->hw_info.mtu;
374 dev_info->dev_type = edev->type;
376 rte_memcpy(&dev_info->hw_mac, &edev->hwfns[0].hw_info.hw_mac_addr,
379 dev_info->fw_major = FW_MAJOR_VERSION;
380 dev_info->fw_minor = FW_MINOR_VERSION;
381 dev_info->fw_rev = FW_REVISION_VERSION;
382 dev_info->fw_eng = FW_ENGINEERING_VERSION;
385 dev_info->b_inter_pf_switch =
386 OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);
387 if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))
388 dev_info->b_arfs_capable = true;
389 dev_info->tx_switching = false;
391 dev_info->smart_an = ecore_mcp_is_smart_an_supported(p_hwfn);
393 ptt = ecore_ptt_acquire(ECORE_LEADING_HWFN(edev));
395 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
396 &dev_info->mfw_rev, NULL);
398 ecore_mcp_get_mbi_ver(ECORE_LEADING_HWFN(edev), ptt,
399 &dev_info->mbi_version);
401 ecore_mcp_get_flash_size(ECORE_LEADING_HWFN(edev), ptt,
402 &dev_info->flash_size);
404 /* Workaround to allow PHY-read commands for
407 if (ECORE_IS_BB_B0(edev))
408 dev_info->flash_size = 0xffffffff;
410 ecore_ptt_release(ECORE_LEADING_HWFN(edev), ptt);
413 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
414 &dev_info->mfw_rev, NULL);
421 qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info)
426 memset(info, 0, sizeof(*info));
428 info->num_tc = 1 /* @@@TBD aelior MULTI_COS */;
431 int max_vf_vlan_filters = 0;
433 info->num_queues = 0;
434 for_each_hwfn(edev, i)
436 FEAT_NUM(&edev->hwfns[i], ECORE_PF_L2_QUE);
438 if (IS_ECORE_SRIOV(edev))
439 max_vf_vlan_filters = edev->p_iov_info->total_vfs *
440 ECORE_ETH_VF_NUM_VLAN_FILTERS;
441 info->num_vlan_filters = RESC_NUM(&edev->hwfns[0], ECORE_VLAN) -
444 rte_memcpy(&info->port_mac, &edev->hwfns[0].hw_info.hw_mac_addr,
447 ecore_vf_get_num_rxqs(ECORE_LEADING_HWFN(edev),
449 if (ECORE_IS_CMT(edev)) {
450 ecore_vf_get_num_rxqs(&edev->hwfns[1], &queues);
451 info->num_queues += queues;
454 ecore_vf_get_num_vlan_filters(&edev->hwfns[0],
455 (u8 *)&info->num_vlan_filters);
457 ecore_vf_get_port_mac(&edev->hwfns[0],
458 (uint8_t *)&info->port_mac);
460 info->is_legacy = ecore_vf_get_pre_fp_hsi(&edev->hwfns[0]);
463 qed_fill_dev_info(edev, &info->common);
466 memset(&info->common.hw_mac, 0, RTE_ETHER_ADDR_LEN);
471 static void qed_set_name(struct ecore_dev *edev, char name[NAME_SIZE])
475 rte_memcpy(edev->name, name, NAME_SIZE);
476 for_each_hwfn(edev, i) {
477 snprintf(edev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
482 qed_sb_init(struct ecore_dev *edev, struct ecore_sb_info *sb_info,
483 void *sb_virt_addr, dma_addr_t sb_phy_addr, uint16_t sb_id)
485 struct ecore_hwfn *p_hwfn;
488 uint8_t n_hwfns = edev->num_hwfns;
491 hwfn_index = sb_id % n_hwfns;
492 p_hwfn = &edev->hwfns[hwfn_index];
493 rel_sb_id = sb_id / n_hwfns;
495 DP_INFO(edev, "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
496 hwfn_index, rel_sb_id, sb_id);
498 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
499 sb_virt_addr, sb_phy_addr, rel_sb_id);
504 static void qed_fill_link(struct ecore_hwfn *hwfn,
505 __rte_unused struct ecore_ptt *ptt,
506 struct qed_link_output *if_link)
508 struct ecore_mcp_link_params params;
509 struct ecore_mcp_link_state link;
510 struct ecore_mcp_link_capabilities link_caps;
513 memset(if_link, 0, sizeof(*if_link));
515 /* Prepare source inputs */
516 if (IS_PF(hwfn->p_dev)) {
517 rte_memcpy(¶ms, ecore_mcp_get_link_params(hwfn),
519 rte_memcpy(&link, ecore_mcp_get_link_state(hwfn), sizeof(link));
520 rte_memcpy(&link_caps, ecore_mcp_get_link_capabilities(hwfn),
523 ecore_vf_read_bulletin(hwfn, &change);
524 ecore_vf_get_link_params(hwfn, ¶ms);
525 ecore_vf_get_link_state(hwfn, &link);
526 ecore_vf_get_link_caps(hwfn, &link_caps);
529 /* Set the link parameters to pass to protocol driver */
531 if_link->link_up = true;
534 if_link->speed = link.speed;
536 if_link->duplex = QEDE_DUPLEX_FULL;
538 /* Fill up the native advertised speed cap mask */
539 if_link->adv_speed = params.speed.advertised_speeds;
541 if (params.speed.autoneg)
542 if_link->supported_caps |= QEDE_SUPPORTED_AUTONEG;
544 if (params.pause.autoneg || params.pause.forced_rx ||
545 params.pause.forced_tx)
546 if_link->supported_caps |= QEDE_SUPPORTED_PAUSE;
548 if (params.pause.autoneg)
549 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
551 if (params.pause.forced_rx)
552 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
554 if (params.pause.forced_tx)
555 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
557 if (link_caps.default_eee == ECORE_MCP_EEE_UNSUPPORTED) {
558 if_link->eee_supported = false;
560 if_link->eee_supported = true;
561 if_link->eee_active = link.eee_active;
562 if_link->sup_caps = link_caps.eee_speed_caps;
563 /* MFW clears adv_caps on eee disable; use configured value */
564 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
566 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
567 if_link->eee.enable = params.eee.enable;
568 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
569 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
574 qed_get_current_link(struct ecore_dev *edev, struct qed_link_output *if_link)
576 struct ecore_hwfn *hwfn;
577 struct ecore_ptt *ptt;
579 hwfn = &edev->hwfns[0];
581 ptt = ecore_ptt_acquire(hwfn);
583 qed_fill_link(hwfn, ptt, if_link);
584 ecore_ptt_release(hwfn, ptt);
586 DP_NOTICE(hwfn, true, "Failed to fill link; No PTT\n");
589 qed_fill_link(hwfn, NULL, if_link);
593 static int qed_set_link(struct ecore_dev *edev, struct qed_link_params *params)
595 struct ecore_hwfn *hwfn;
596 struct ecore_ptt *ptt;
597 struct ecore_mcp_link_params *link_params;
603 /* The link should be set only once per PF */
604 hwfn = &edev->hwfns[0];
606 ptt = ecore_ptt_acquire(hwfn);
610 link_params = ecore_mcp_get_link_params(hwfn);
611 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
612 link_params->speed.autoneg = params->autoneg;
614 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
615 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
616 link_params->pause.autoneg = true;
618 link_params->pause.autoneg = false;
619 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
620 link_params->pause.forced_rx = true;
622 link_params->pause.forced_rx = false;
623 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
624 link_params->pause.forced_tx = true;
626 link_params->pause.forced_tx = false;
629 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
630 memcpy(&link_params->eee, ¶ms->eee,
631 sizeof(link_params->eee));
633 rc = ecore_mcp_set_link(hwfn, ptt, params->link_up);
635 ecore_ptt_release(hwfn, ptt);
640 void qed_link_update(struct ecore_hwfn *hwfn)
642 struct ecore_dev *edev = hwfn->p_dev;
643 struct qede_dev *qdev = (struct qede_dev *)edev;
644 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
647 rc = qede_link_update(dev, 0);
648 qed_inform_vf_link_state(hwfn);
651 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
654 static int qed_drain(struct ecore_dev *edev)
656 struct ecore_hwfn *hwfn;
657 struct ecore_ptt *ptt;
663 for_each_hwfn(edev, i) {
664 hwfn = &edev->hwfns[i];
665 ptt = ecore_ptt_acquire(hwfn);
667 DP_ERR(hwfn, "Failed to drain NIG; No PTT\n");
670 rc = ecore_mcp_drain(hwfn, ptt);
673 ecore_ptt_release(hwfn, ptt);
679 static int qed_nic_stop(struct ecore_dev *edev)
683 rc = ecore_hw_stop(edev);
684 for (i = 0; i < edev->num_hwfns; i++) {
685 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
687 if (p_hwfn->b_sp_dpc_enabled)
688 p_hwfn->b_sp_dpc_enabled = false;
693 static int qed_slowpath_stop(struct ecore_dev *edev)
695 #ifdef CONFIG_QED_SRIOV
703 #ifdef CONFIG_ECORE_ZIPPED_FW
704 qed_free_stream_mem(edev);
707 #ifdef CONFIG_QED_SRIOV
708 if (IS_QED_ETH_IF(edev))
709 qed_sriov_disable(edev, true);
715 ecore_resc_free(edev);
716 qed_stop_iov_task(edev);
721 static void qed_remove(struct ecore_dev *edev)
726 ecore_hw_remove(edev);
729 static int qed_send_drv_state(struct ecore_dev *edev, bool active)
731 struct ecore_hwfn *hwfn = ECORE_LEADING_HWFN(edev);
732 struct ecore_ptt *ptt;
735 ptt = ecore_ptt_acquire(hwfn);
739 status = ecore_mcp_ov_update_driver_state(hwfn, ptt, active ?
740 ECORE_OV_DRIVER_STATE_ACTIVE :
741 ECORE_OV_DRIVER_STATE_DISABLED);
743 ecore_ptt_release(hwfn, ptt);
748 static int qed_get_sb_info(struct ecore_dev *edev, struct ecore_sb_info *sb,
749 u16 qid, struct ecore_sb_info_dbg *sb_dbg)
751 struct ecore_hwfn *hwfn = &edev->hwfns[qid % edev->num_hwfns];
752 struct ecore_ptt *ptt;
758 ptt = ecore_ptt_acquire(hwfn);
760 DP_ERR(hwfn, "Can't acquire PTT\n");
764 memset(sb_dbg, 0, sizeof(*sb_dbg));
765 rc = ecore_int_get_sb_dbg(hwfn, ptt, sb, sb_dbg);
767 ecore_ptt_release(hwfn, ptt);
771 const struct qed_common_ops qed_common_ops_pass = {
772 INIT_STRUCT_FIELD(probe, &qed_probe),
773 INIT_STRUCT_FIELD(update_pf_params, &qed_update_pf_params),
774 INIT_STRUCT_FIELD(slowpath_start, &qed_slowpath_start),
775 INIT_STRUCT_FIELD(set_name, &qed_set_name),
776 INIT_STRUCT_FIELD(chain_alloc, &ecore_chain_alloc),
777 INIT_STRUCT_FIELD(chain_free, &ecore_chain_free),
778 INIT_STRUCT_FIELD(sb_init, &qed_sb_init),
779 INIT_STRUCT_FIELD(get_sb_info, &qed_get_sb_info),
780 INIT_STRUCT_FIELD(get_link, &qed_get_current_link),
781 INIT_STRUCT_FIELD(set_link, &qed_set_link),
782 INIT_STRUCT_FIELD(drain, &qed_drain),
783 INIT_STRUCT_FIELD(slowpath_stop, &qed_slowpath_stop),
784 INIT_STRUCT_FIELD(remove, &qed_remove),
785 INIT_STRUCT_FIELD(send_drv_state, &qed_send_drv_state),
786 /* ############### DEBUG ####################*/
788 INIT_STRUCT_FIELD(dbg_get_debug_engine, &qed_get_debug_engine),
789 INIT_STRUCT_FIELD(dbg_set_debug_engine, &qed_set_debug_engine),
791 INIT_STRUCT_FIELD(dbg_protection_override,
792 &qed_dbg_protection_override),
793 INIT_STRUCT_FIELD(dbg_protection_override_size,
794 &qed_dbg_protection_override_size),
796 INIT_STRUCT_FIELD(dbg_grc, &qed_dbg_grc),
797 INIT_STRUCT_FIELD(dbg_grc_size, &qed_dbg_grc_size),
799 INIT_STRUCT_FIELD(dbg_idle_chk, &qed_dbg_idle_chk),
800 INIT_STRUCT_FIELD(dbg_idle_chk_size, &qed_dbg_idle_chk_size),
802 INIT_STRUCT_FIELD(dbg_mcp_trace, &qed_dbg_mcp_trace),
803 INIT_STRUCT_FIELD(dbg_mcp_trace_size, &qed_dbg_mcp_trace_size),
805 INIT_STRUCT_FIELD(dbg_fw_asserts, &qed_dbg_fw_asserts),
806 INIT_STRUCT_FIELD(dbg_fw_asserts_size, &qed_dbg_fw_asserts_size),
808 INIT_STRUCT_FIELD(dbg_ilt, &qed_dbg_ilt),
809 INIT_STRUCT_FIELD(dbg_ilt_size, &qed_dbg_ilt_size),
811 INIT_STRUCT_FIELD(dbg_reg_fifo_size, &qed_dbg_reg_fifo_size),
812 INIT_STRUCT_FIELD(dbg_reg_fifo, &qed_dbg_reg_fifo),
814 INIT_STRUCT_FIELD(dbg_igu_fifo_size, &qed_dbg_igu_fifo_size),
815 INIT_STRUCT_FIELD(dbg_igu_fifo, &qed_dbg_igu_fifo),
818 const struct qed_eth_ops qed_eth_ops_pass = {
819 INIT_STRUCT_FIELD(common, &qed_common_ops_pass),
820 INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info),
821 INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure),
824 const struct qed_eth_ops *qed_get_eth_ops(void)
826 return &qed_eth_ops_pass;